Semiconductor memory device, method for manufacturing semiconductor memory device, semiconductor integrated circuit, and semiconductor memory integrated circuit

Abstract

To provide a semiconductor storage device that has a structure capable of providing any one of a plurality of current characteristics without changing a transistor width.SOLUTION: A semiconductor storage device includes: a semiconductor region that has an active region for a memory transistor, and a plurality of recesses for trench isolation; insulation regions provided in the respective recesses; a gate electrode extending in a direction from one of a first insulation region and a second insulation region adjacent to each other among the insulation regions to the other, and passing above the active region; and a gate insulating film provided between the gate electrode and the active region. The active region is provided between the first insulation region and the second insulation region, at least one of these insulation regions having an adjacent portion and a remote portion. The remote portion is adjacent to the adjacent portion under the gate electrode. The adjacent portion is provided between the remote portion and the active region while being adjacent to the active region under the gate electrode, and has a thickness smaller than that of the remote portion.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device, a method for manufacturing a semiconductor memory device, a semiconductor integrated circuit, and a semiconductor memory integrated circuit. [Background technology]

[0002] Patent Document 1 discloses a mask ROM, which reduces the number of memory transistors to be ion-implanted for ROM coding in order to suppress lattice defects occurring inside the substrate and to facilitate coding. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-249696 Summary of the Invention [Problem to be solved by the invention]

[0004] Mask ROMs are broadly classified into NAND and NOR types. In NAND mask ROMs, the threshold of a specific transistor is lowered by ion implantation to create a depletion transistor. In NOR mask ROMs, the threshold of a specific transistor is raised by ion implantation to create a high-threshold enhancement transistor. In NOR mask ROMs, a selected word line applies a voltage to the gate electrode of a memory transistor. A read circuit detects whether the memory transistor is in one of two states (high threshold or low threshold).

[0005] These programming methods change the current characteristics of transistors depending on the implanted dopant concentration. However, the implanted dopants can be rearranged by dopant diffusion due to heat applied in the manufacturing process following the ion implantation process. In NOR-type mask ROMs, this dopant rearrangement occurs from the inside of the substrate to the surface, changing the current characteristics of the transistors. This characteristic change can cause the coding content of the memory transistor to be incorrectly transmitted to the read circuit. This possibility is unavoidable when using threshold shifting by the ion implantation process to code the memory transistors.

[0006] The present invention aims to provide a semiconductor memory device having a structure capable of providing any one of a plurality of current characteristics without changing the transistor width, a method for manufacturing a semiconductor memory device, a semiconductor integrated circuit including a current source circuit and a bias source, and a semiconductor memory integrated circuit including the semiconductor integrated circuit and the semiconductor memory device. [Means for solving the problem]

[0007] A semiconductor memory device according to a first aspect of the present invention includes a semiconductor region having a first active region for a first memory transistor and a plurality of recesses for trench isolation, a plurality of insulating regions provided in each of the recesses of the semiconductor region, a first gate electrode extending in a first direction from one of the first insulating region and the second insulating region adjacent to each other in the insulating region to pass over the first active region, and a first gate insulating film provided between the first gate electrode and the first active region, wherein the first active region of the semiconductor region is provided between the first insulating region and the second insulating region, At least one of the first insulating region and the second insulating region has an adjacent portion and a remote portion, the adjacent portion is adjacent to the first active region below the first gate electrode, the remote portion is adjacent to the adjacent portion below the first gate electrode, the adjacent portion is provided between the remote portion and the first active region, and the adjacent portion has a thickness smaller than a thickness of the remote portion, the semiconductor region has a first conductive region and a second conductive region provided between the first insulating region and the second insulating region, and the first conductive region, the first active region, and the second conductive region are arranged in a second direction intersecting the first direction.

[0008] In the semiconductor memory device according to the first aspect, the adjacent portion under the first gate electrode has a thickness smaller than that of the remote portion, so that the gate insulating film and gate electrode are provided not only on the top surface of the first active region but also along the side surface of the first active region. The gate insulating film and gate electrode on the side surface of the first active region enable the side surface of the first active region to operate as an additional transistor without ion implantation for ROM coding. It is possible to provide transistor structures each having a plurality of current driving capacities without changing the transistor width.

[0009] In a semiconductor memory device according to a second aspect of the present invention, the semiconductor region further includes a second active region for a second memory transistor provided between the first insulating region and the second insulating region, and the semiconductor memory device includes a second gate electrode extending in the first direction on the second active region and passing over the second active region, and a second gate insulating film provided between the second gate electrode and the second active region, the semiconductor region has a third conductive region provided between the first insulating region and the second insulating region, the first conductive region, the second conductive region, and the third conductive region have a conductivity type different from that of the first active region, the second conductive region, the first active region, the first conductive region, the second active region, and the third conductive region are arranged in order in the second direction, the second conductive region and the third conductive region are connected to a reference potential line, and the first conductive region is shared by the first memory transistor and the second memory transistor and is also connected to a metal wiring layer.

[0010] According to the semiconductor memory device of the second aspect, the first memory transistor and the second memory transistor can exhibit the following three types of current characteristics depending on whether or not there is an adjacent portion, specifically, current characteristics based on an additional transistor on one side, an additional transistor on both sides, or no additional transistor.

[0011] In a semiconductor memory device according to a third aspect of the present invention, in the first insulating region, the adjacent portion has a thickness smaller than the thickness of the remote portion, and the second insulating region is thicker than the adjacent portion of the first insulating region under the first gate electrode.

[0012] In the semiconductor memory device according to the third aspect, the additional transistor is provided in the first insulating region, and the second insulating region has a thickness greater than the adjacent portion of the first insulating region.

[0013] In the semiconductor memory device according to a fourth aspect of the present invention, in each of the first insulating region and the second insulating region, the adjacent portion has a thickness smaller than a thickness of the remote portion.

[0014] In the semiconductor memory device according to the fourth aspect, additional transistors are provided in both the first insulating region and the second insulating region.

[0015] In a semiconductor memory device according to a fifth aspect of the present invention, the insulating region includes a third insulating region adjacent to the second insulating region, and the first insulating region, the second insulating region, and the third insulating region are arranged in the first direction, in that order, and the semiconductor region further includes a third active region for a third memory transistor, and the first gate electrode extends in the first direction and passes over the third active region. The semiconductor memory device further includes a third gate insulating film provided between the first gate electrode and the third active region, and the third insulating region has an adjacent portion and a remote portion, and in the third insulating region, the adjacent portion is adjacent to the first active region below the first gate electrode and the remote portion is adjacent to the adjacent portion below the first gate electrode, and the adjacent portion is provided between the remote portion and the first active region, and under the first gate electrode, the adjacent portion of the third insulating region has a thickness smaller than a thickness of the remote portion of the third insulating region, and the second insulating region is thicker than the adjacent portion of the third insulating region under the first gate electrode.

[0016] In the semiconductor memory device according to the fifth aspect, the third memory transistor has a structure in which an additional transistor is provided in the third insulating region rather than the second insulating region, which makes it possible to provide a structure in which no adjacent portion is provided between the second memory transistor and the third memory transistor.

[0017] In a semiconductor memory device according to a sixth aspect of the present invention, the insulating region includes a fourth insulating region adjacent to the first insulating region, the semiconductor region further includes a fourth active region for a fourth memory transistor provided between the first insulating region and the fourth insulating region, the first gate electrode extends in the first direction and passes over the fourth active region, the semiconductor memory device further includes a fourth gate insulating film provided between the first gate electrode and the fourth active region, the first insulating region has a further adjacent portion adjacent to the fourth active region below the first gate electrode, the remote portion of the first insulating region is provided below the first gate electrode between the adjacent portion and the further adjacent portion of the first insulating region, the further adjacent portion is provided between the remote portion and the fourth active region, and the further adjacent portion has a thickness below the first gate electrode that is smaller than a thickness of the remote portion of the first insulating region.

[0018] In a semiconductor memory device according to a sixth aspect, a fourth memory transistor adjacent to a first memory transistor shares a word select line connected to its gate electrode with the first memory transistor, and the fourth memory transistor can be provided with an additional transistor in the first isolation region, regardless of whether the first memory transistor has an additional transistor associated with the first isolation region.

[0019] In a semiconductor memory device according to a seventh aspect of the present invention, the adjacent portion has either a structure that crosses the first gate electrode in a direction from one of the first conductive region and the second conductive region to the other, or a structure that extends from one of the first conductive region and the second conductive region and terminates directly below the first gate electrode.

[0020] In a semiconductor memory device according to a seventh aspect, the adjacent portion can be provided in at least a portion directly below the first gate electrode, and has a structure that crosses the first gate electrode in a direction from the source region to the drain region of the first memory transistor, or a structure that extends from the source region of the first memory transistor and terminates directly below the first gate electrode.

[0021] A method for manufacturing a semiconductor memory device according to an eighth aspect of the present invention includes: preparing a substrate product having a semiconductor region having a plurality of recesses for trench isolation and a plurality of insulating regions respectively provided in the recesses of the semiconductor region, the semiconductor region having an active region provided between a first insulating region and a second insulating region adjacent to each other among the insulating regions; forming a mask having an opening on a main surface of the substrate product; removing an insulator from the insulating region of the substrate product using the mask; after removing the insulator, forming a gate insulating film in the active region; and forming a gate insulating film on the gate insulating region. and after forming a film, forming a gate electrode on the insulating region and the active region, the opening being located on at least one of a first boundary between the active region and the first insulating region and a second boundary between the active region and the second insulating region, removing the insulator from the substrate product partially removing the insulating region at the opening in the mask to partially expose a side surface of the active region, the gate insulating film being provided on the side surface, and the gate electrode crossing the active region in a direction from one of the first insulating region and the second insulating region to the other and extending on the gate insulating film on the side surface.

[0022] According to the manufacturing method of the eighth aspect, the portion of the insulating region removed using the opening has a thickness smaller than the thickness of the insulating region outside the opening, so that the gate insulating film and gate electrode extend not only on the top surface of the active region but also along the side surface of the active region, enabling the side surface of the first active region to function as an additional transistor. This makes it possible to provide a transistor structure with multiple current driving capabilities without applying ion implantation to the transistor for changing the threshold value.

[0023] In the method for manufacturing a semiconductor memory device according to a ninth aspect of the present invention, the mask covers the second boundary.

[0024] According to the manufacturing method of the ninth aspect, an additional transistor is provided on one side of the active region.

[0025] In the manufacturing method according to a tenth aspect of the present invention, the opening of the mask is located on the first boundary and the second boundary.

[0026] According to the manufacturing method of the tenth aspect, additional transistors are provided on both sides of the active region.

[0027] A semiconductor integrated circuit according to an eleventh aspect of the present invention is a semiconductor integrated circuit including a current source circuit and a bias source, wherein the current source circuit includes at least one transistor, the transistor including a semiconductor region having a plurality of recesses for trench isolation, a plurality of insulating regions including a first insulating region and a second insulating region adjacent to each other and provided in each of the recesses of the semiconductor region, an active region for the transistor provided between the first insulating region and the second insulating region, a gate electrode extending in a first direction from one side to the other in the first insulating region and the second insulating region and passing over the active region, and a gate insulating film provided between the gate electrode and the active region, one of the semiconductor regions has an adjacent portion and a remote portion, the adjacent portion adjacent to the active region below the gate electrode, the adjacent portion adjacent to the remote portion below the gate electrode, the adjacent portion being provided between the remote portion and the active region below the gate electrode, the adjacent portion having a thickness smaller than a thickness of the remote portion, the semiconductor region having a first conductive region provided between the first insulating region and the second insulating region, and a second conductive region provided between the first insulating region and the second insulating region, the first conductive region, the active region, and the second conductive region being arranged in a second direction intersecting the first direction, and the bias source is connected to the gate electrode and configured to apply a voltage to the gate electrode.

[0028] According to the semiconductor integrated circuit of the eleventh aspect, the transistor can exhibit one of the following current characteristics depending on whether or not there is an adjacent portion, specifically the current characteristics of an additional transistor on one side or an additional transistor on both sides.

[0029] A semiconductor memory integrated circuit according to a twelfth aspect includes the semiconductor integrated circuit according to the eleventh aspect, A semiconductor memory device according to any one of the first to seventh aspects, and a read circuit configured to read the first memory transistor of the semiconductor memory device, the read circuit being connected to the semiconductor memory device and configured to compare a current from the first memory transistor with a current from the current source circuit of the semiconductor integrated circuit.

[0030] According to the semiconductor memory integrated circuit of the twelfth aspect of the present invention, the read circuit of the semiconductor memory device can determine the difference in current characteristics of the first memory transistors by using the semiconductor integrated circuit including the current source circuit. [Effects of the Invention]

[0031] According to the above aspects, an object is to provide a semiconductor memory device having a structure capable of providing any one of a plurality of current characteristics without changing the transistor width, a method for manufacturing a semiconductor memory device, a semiconductor integrated circuit including a current source circuit and a bias source, and a semiconductor memory integrated circuit including the semiconductor integrated circuit and the semiconductor memory device. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a diagram schematically showing a semiconductor memory integrated circuit according to the present embodiment. [Figure 2] FIG. 2 is a diagram showing a part of a semiconductor memory device according to an embodiment of the present invention. [Figure 3] Fig. 3(a) is a plan view showing a transistor located in the area T3 (area T3R) in Fig. 2. Fig. 3(b) is a drawing showing a cross section taken along line IIIb-IIIb shown in Fig. 3(a), and Fig. 3(c) is a drawing showing a cross section taken along line IIIc-IIIc shown in Fig. 3(a). [Figure 4] Fig. 4(a) is a plan view showing a transistor located in the area of ​​T4 in Fig. 2, Fig. 4(b) is a cross-sectional view taken along line IVb-IVb shown in Fig. 4(a), and Fig. 4(c) is an enlarged view showing a step for an additional transistor. [Figure 5] 5(a) is a plan view showing a transistor located in the area of ​​T5 in FIG. 2, and FIG. 5(b) is a drawing showing a cross section taken along the line Vb-Vb shown in FIG. 5(a). [Figure 6] FIG. 6 is a diagram showing three types of saturation current characteristics (IDS1, IDS2, IDS3) of transistors. [Figure 7] 7(a) is a diagram showing the arrangement of three types of memory transistors in an array of a semiconductor memory device according to one embodiment of the present invention, and FIG. 7(b) is a diagram showing a schematic diagram of the current characteristic distribution of three types of memory transistors, "None," "Either," and "Both," in an array of a semiconductor memory device according to one embodiment of the present invention. [Figure 8] FIG. 8 is a circuit diagram showing an example of a read circuit of the semiconductor memory integrated circuit according to this embodiment. [Figure 9] FIG. 9 is a circuit diagram showing an example of a semiconductor integrated circuit for a current source according to this embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of a semiconductor integrated circuit for a current source according to this embodiment. [Figure 11] 11(a), 11(b), and 11(c) are cross-sectional views showing major steps in a method for fabricating a semiconductor integrated circuit according to one embodiment of the present invention. [Figure 12] 12(a), 12(b), and 12(c) are cross-sectional views showing major steps in a method for fabricating a semiconductor integrated circuit according to one embodiment of the present invention. [Figure 13] 13(a), 13(b), and 13(c) are cross-sectional views showing major steps in a method for fabricating a semiconductor integrated circuit according to another embodiment of the present invention. [Figure 14] 14(a), 14(b), and 14(c) are cross-sectional views showing major steps in a method for fabricating a semiconductor integrated circuit according to one embodiment of the present invention. [Figure 15]FIG. 15 is a plan view showing the main steps in a method for fabricating a semiconductor integrated circuit according to one embodiment of the present invention. [Figure 16] 16(a), 16(b), and 16(c) are cross-sectional views showing major steps in a method for fabricating a semiconductor integrated circuit according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] Hereinafter, each embodiment for carrying out the present invention will be described with reference to the drawings. In the following description, the same or similar parts will be designated by the same or similar reference numerals to avoid redundant description.

[0034] 1 is a diagram schematically illustrating a semiconductor memory integrated circuit according to this embodiment. The semiconductor memory integrated circuit 11 includes a semiconductor memory device 13, a read circuit 15, a reference circuit 16, a current source circuit 17, a word decoder circuit 19, a bit decoder circuit 21, and a bit selection circuit 23.

[0035] The semiconductor memory device 13 includes a plurality of memory transistors, which are generally arranged to form a one-dimensional or two-dimensional array. For example, in a two-dimensional transistor array, a plurality of memory transistors are arranged in the X direction of a coordinate system CS shown in FIG. 1, with each gate electrode connected to a word line WL, forming a one-dimensional subarray. A plurality of subarrays are arranged in the Y direction of the coordinate system CS shown in FIG. 1, with corresponding drain electrodes in each subarray connected to a respective bit line BL, forming a two-dimensional array. The semiconductor memory device 13 can be referred to as, for example, a NOR-type mask ROM.

[0036] In the semiconductor memory device 13, a word decoder circuit 19 is connected to a plurality of word lines WL and selects one word line WLS from the plurality of word lines WL in accordance with a memory address (specifically, an X address XAD). When a certain word line WLS is selected, all memory transistors connected to that word line WLS are made conductive.

[0037] The bit selection transistors BLT in the bit selection circuit 23 are connected to a plurality of bit lines BL. The bit decoder circuit 21 selects the bit selection transistors BLT in the bit selection circuit 23. As a result, one or a plurality of bit lines BTS (e.g., 8 (1 byte) or 16 (1 word)) are selected from the plurality of bit lines BL according to a memory address (specifically, a Y address YAD). When a certain bit line BTS is selected, any one of the memory transistors connected to the bit line BTS is connected to a selected word line WL. The transistor MT selected in this manner is located at the intersection of the selected single word line WLS and the selected bit line BTS.

[0038] All bit lines BL are connected to one or more read circuits 15 via bit selection transistors BLT in the bit selection circuit 23, and the read circuits 15 are configured to read the memory transistors of the semiconductor memory device 13. Specifically, the read circuits 15 detect the memory contents of the selected memory transistors and output the detection results. In this embodiment, the read circuits 15 are connected to a current source circuit 17 in a reference circuit 16 of the semiconductor integrated circuit. The read circuits 15 use the current source circuit 17 to detect the memory contents of the selected memory transistors, and are configured to compare the current from the memory transistors with the current from the current source circuit 17 to determine the difference in current characteristics of the memory transistors. However, the semiconductor memory integrated circuit 11 of the present disclosure is not limited to this.

[0039] As will be understood from the following explanation, the selected memory transistor MT exhibits three types of current characteristics depending on its structure.

[0040] FIG. 2 is a plan view showing a portion of the semiconductor memory device 13. Referring to FIG. 2, the coordinate system CS of FIG. 1 is shown to indicate the orientation of the semiconductor memory device 13. In FIG. 2, gate electrodes 37 and element isolation insulating regions 33 are depicted with solid lines, and contact plugs 41a (contact holes) to conductive semiconductor regions 31, recesses 30 for additional transistors, and metal layers for bit lines BL are depicted with dashed lines. This metal layer is partially depicted to avoid cluttering the drawing. In the transistor array shown in FIG. 2, specifically, transistors having one of the three structures—T3 (T3R), T4, and T5—for transistors exhibiting three types of current characteristics are located at each intersection of the bit lines BL and word lines WL shown in FIG. 1.

[0041] FIG. 3(a) is a plan view showing a transistor positioned in the T3 structure in FIG. 2 (the T3R structure is a left-right inversion of the T3 structure). FIG. 3(b) is a drawing showing a cross section taken along line IIIb-IIIb shown in FIG. 3(a), and FIG. 3(c) is a drawing showing a cross section taken along line IIIc-IIIc shown in FIG. 3(a). FIG. 4(a) is a plan view showing a transistor positioned in the T4 structure in FIG. 2, and FIG. 4(b) is a drawing showing a cross section taken along line IVb-IVb shown in FIG. 4(a). FIG. 5(a) is a plan view showing a transistor positioned in the T5 structure in FIG. 2, and FIG. 5(b) is a drawing showing a cross section taken along line Vb-Vb shown in FIG. 5(a).

[0042] 2, 3(a) to 3(c), 4(a), 4(b), 5(a), and 5(b), the semiconductor memory device 13 includes a semiconductor region 31 (e.g., a silicon region), multiple insulating regions 33, multiple gate electrodes 37 for memory transistors, and a gate insulating film 39 for the memory transistors. The semiconductor region 31 includes multiple active regions 35 for the memory transistors. The semiconductor region 31 may include a silicon-based semiconductor such as silicon, silicon germanium, or silicon carbide, and may be provided by, for example, a semiconductor substrate or semiconductor wafer. The insulating region 33 may include a silicon-based inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride. The gate insulating film 39 may include, for example, silicon oxide, or a high-dielectric-constant insulating film such as silicon oxynitride.

[0043] As shown in FIGS. 3(a) to 3(c), 4(a) to 4(b), and 5(a) to 5(b), the semiconductor region 31 has an active region 35 for a memory transistor and multiple recesses 28 for shallow trench isolation. Multiple insulating regions 33 are provided in each of the recesses 28 of the semiconductor region 31. Each active region 35 is provided between two adjacent insulating regions 33. A gate electrode 37 extends from one of the two adjacent insulating regions 33 to the other in a first direction Ax1 and passes over the active region 35. A gate insulating film 39 is provided between each gate electrode 37 and each active region 35.

[0044] The semiconductor region 31 has a first conductive region 40a and a second conductive region 40b, which are provided between two adjacent insulating regions 33. The first conductive region 40a and the second conductive region 40b have a conductivity type (e.g., n-type) different from the conductivity type (e.g., p-type) of the active region 35. The first conductive region 40a, the active region 35, and the second conductive region 40b are arranged in a second direction Ax2 that intersects (e.g., is perpendicular to) the first direction Ax1. The active region 35 is located between the first conductive region 40a and the second conductive region 40b and is adjacent to the first conductive region 40a and the second conductive region 40b.

[0045] 3(c), the semiconductor memory device 13 includes an interlayer insulating film 41 provided on the gate electrode 37 and the insulating region 33, and a metal wiring layer 43 extending on the interlayer insulating film 41. The metal wiring layer 43 is connected to the second conductive region 40b via a contact plug 41a (contact hole) in the interlayer insulating film 41. The interlayer insulating film 41 and the metal wiring layer 43 are covered with a protective insulating film 45. The interlayer insulating film 41 includes a silicon-based inorganic insulator (e.g., silicon oxide, silicon nitride, or silicon oxynitride), and the protective insulating film 45 can include a silicon-based inorganic insulator.

[0046] 3(a) to 3(c), the active region 35 is provided between the first insulating region 32 and the second insulating region 34, which are adjacent to each other, of the insulating region 33. The first conductive region 40a and the second conductive region 40b of the semiconductor region 31 are provided between the first insulating region 32 and the second insulating region 34. One of the first insulating region 32 and the second insulating region 34 (in this embodiment, the first insulating region 32) has an adjacent portion 32a and a remote portion 32b. In the first insulating region 32, the adjacent portion 32a is adjacent to the active region 35 below the gate electrode 37, and the remote portion 32b is adjacent to the adjacent portion 32a below the gate electrode 37. The adjacent portion 32a is provided between the remote portion 32b and the active region 35. The adjacent portion 32a partially has a thickness Ta that is smaller than the thickness Tb of the remote portion 32b. A part of the adjacent portion 32a is recessed compared to the remote portion 32b and the active region 35, forming a recess 30. The thickness of the second insulating region 34 is greater than the thickness Ta of the adjacent portion 32a across the bottom surface of the gate electrode 37 of the transistor and is substantially the same as the thickness Tb of the remote portion 32b.

[0047] 3(b), the active region 35 has a top surface 35a and a first side surface 35b. The top surface 35a extends along a gate insulating film 39a. The first side surface 35b extends in a third direction Ax3 that intersects with the first direction Ax1 and the second direction Ax3 directly below the gate electrode 37. The gate insulating film 39 includes a gate insulating film 39a on the top surface 35a and a gate insulating film 39b provided on the first side surface 35b.

[0048] In this semiconductor memory device 13, the adjacent portion 32a under the gate electrode 37 has a thickness Tb that is smaller than the thickness Tb of the remote portion 32b. Therefore, the gate insulating film 39 and gate electrode 37 are provided not only on the top surface 35a of the active region 35 but also along the side surface 35b of the active region 35. The gate electrode 37 is provided on the gate insulating film 39a on the top surface 35a of the active region 35, thereby enabling the top surface 35a of the active region 35 to function as a channel for the main transistor. Furthermore, the gate insulating film 39b and gate electrode 37 on the side surface 35b of the active region 35 enable the side surface 35b of the active region 35 to function as a channel for the additional transistor. This structure can provide the transistor with the current driving capabilities from the main transistor and one additional transistor without changing the transistor width.

[0049] Furthermore, in this semiconductor memory device 13, an additional transistor is provided in the first insulating region 32, but no additional transistor is provided in the second insulating region 34. The second insulating region 34 is provided with a thickness Tb that is greater than the thickness of the adjacent portion 32a of the first insulating region 32, so that the second insulating region 34 extends along the active region 35 and the gate electrode directly below the gate electrode 37, enabling element isolation.

[0050] In this semiconductor memory device 13, an insulating gap fill for trench isolation is provided in the lower portion of the recess 28 in the semiconductor region 31, and a conductor of the gate electrode 37 is provided on the first side surface 35b relating to the upper portion of the recess 28 in the semiconductor region 31. This conductor is separated from the active region 35 by the gate insulating film 39a and the gate insulating film 39b.

[0051] 4(a) and 4(b), the active region 35 is provided between adjacent third and fourth insulating regions 42 and 44 of the insulating region 33. The first and second conductive regions 40a and 40b of the semiconductor region 31 are provided between the third and fourth insulating regions 42 and 44.

[0052] The third insulating region 42 has an adjacent portion 42a and a remote portion 42b. The adjacent portion 42a is adjacent to the active region 35 below the gate electrode 37, and the remote portion 42b is adjacent to the adjacent portion 42a below the gate electrode 37. The adjacent portion 42a is provided between the remote portion 42b and the active region 35. The adjacent portion 42a partially has a thickness Ta that is smaller than the thickness Tb of the remote portion 42b. A part of the adjacent portion 42a is recessed relative to the remote portion 42b and the active region 35, forming a recess 30.

[0053] The fourth insulating region 44 also has an adjacent portion 44a and a remote portion 44b. The adjacent portion 44a is adjacent to the active region 35 below the gate electrode 37, and the remote portion 44b is adjacent to the adjacent portion 44a below the gate electrode 37. The adjacent portion 44a is provided between the remote portion 44b and the active region 35. The adjacent portion 44a partially has a thickness Ta that is smaller than the thickness Tb of the remote portion 44b. A part of the adjacent portion 44a is recessed relative to the remote portion 44b and the active region 35 to form a recess 30.

[0054] In this semiconductor memory device 13, the adjacent portions 42a, 44a under the gate electrode 37 have a thickness Ta that is smaller than the thickness Tb of the remote portions 42b, 44b. Therefore, the gate insulating film 39 and gate electrode 37 are provided not only on the top surface 35a of the active region 35 but also along both side surfaces 35b, 35c of the active region 35. The gate electrode 37 is provided on the gate insulating film 39a on the top surface 35a of the active region 35, so that the top surface 35a of the active region 35 functions as a channel for the main transistor. Furthermore, the gate electrode 37 extends through the gate insulating films 39b, 39c on the side surfaces 35b, 35c of the active region 35. This extension allows each of the side surfaces 35b, 35c of the active region 35 to function as a channel for an additional transistor.

[0055] Furthermore, in this semiconductor memory device 13, an additional transistor is provided in the third insulating region 42, and an additional transistor is also provided in the fourth insulating region 42. The current driving capability of the main transistor and the two additional transistors can be provided to the transistor without changing the width of the transistor. Since the remote portions 42b, 44b of the third insulating region 42 and the fourth insulating region 34 are provided with a large thickness Tb, the remote portions 42b, 44b extend along the gate electrode 37 immediately below the gate electrode 37, enabling element isolation.

[0056] 4(b), the active region 35 has, in addition to an upper surface 35a, a first side surface 35b and a second side surface 35c extending in the third direction Ax3 directly below the gate electrode 37. The gate insulating film 39 includes, in addition to the gate insulating film 39a on the upper surface 35a, gate insulating films 39b and 39c provided on the first side surface 35b and the second side surface 35c, respectively.

[0057] According to this semiconductor memory device 13, an insulating gap fill for trench isolation is provided in the lower portion of the recess 28 in the semiconductor region 31. Also, a conductor for the gate electrode 37 is provided on the first side surface 35b and the second side surface 35c in the upper portion of the recess 28 in the semiconductor region 31. This conductor is separated from the active region 35 by the gate insulating films 39a, 39b, and 39c.

[0058] 3(a) and 4(a), the adjacent portions (32a, 42a, 44a) of the insulating region 33 may have a structure in which they cross the gate electrode 37 in a direction from one of the first conductive region 40a and the second conductive region 40b to the other. In this structure, when the gate electrode 37 is selected, inversion layers are generated at the interfaces between the side surfaces 35b and 35c of the gate electrode 37 and the gate insulating film (39b and 39c) in the active region 35. These inversion layers are always generated near the source region of the active region 35, regardless of whether the memory transistor operates in the saturation region or the non-saturation region of the IV characteristic.

[0059] If possible, the adjacent portions (32a, 42a, 44a) of the insulating region 33 may have a structure in which they extend from either the first conductive region 40a or the second conductive region 40b and terminate immediately below the gate electrode 37, or terminate before reaching the drain region. According to this semiconductor memory device 13, as described above, the adjacent portions (32a, 42a, 44a) may be provided in at least a portion immediately below the gate electrode 37.

[0060] For example, the adjacent portions (32a, 42a, 44a) can extend from the source region of the memory transistor and terminate before reaching the drain region, which allows the additional transistor to operate well.

[0061] FIG. 4(c) is an enlarged view showing the step for the additional transistor. The size of the step ST can be, for example, 10 to 100 nm. The gate insulating film 39b on the side surface 35b of the active region 35 is thinner than the gate insulating film 39a near the boundary between the gate insulating film 39b and the gate insulating film 39a (near the corner CN). This partial thinning of the gate insulating film 39b changes the current characteristics of the additional transistor. Furthermore, at the depth BT near the bottom of the recess 30, the p-type dopant concentration in the active region 35 decreases. This reduction in the dopant concentration lowers the threshold of the additional transistor, thereby changing the current characteristics. Furthermore, because the gate electrode 37 is formed to surround the CN portion, the electric field from the gate electrode is concentrated in the CN portion, lowering the threshold of the additional transistor and changing the current characteristics. These three effects occur in the CN portion, lowering the threshold and increasing the saturation current of the transistor having the recess 30.

[0062] 5(a) and 5(b), two T5 areas for memory transistors are shown. The active region 35 for each of the areas T5 is provided between adjacent fifth and sixth insulating regions 52 and 54 of the insulating region 33. The first, second, and third conductive regions 40a, 40b, and 40c of the semiconductor region 31 are provided between the fifth and sixth insulating regions 52 and 54.

[0063] The fifth insulating region 52 and the sixth insulating region 54 do not have adjacent portions such as the adjacent portions 42a, 44a of the third insulating region 42 and the fourth insulating region 34. The fifth insulating region 52 and the sixth insulating region 54 are provided with a thickness Tb directly below the gate electrode 37 that is greater than the adjacent portions 42a, 44a, for example, the same as the thickness Tb of the remote portions 42b, 44b of the third insulating region 42 and the fourth insulating region 34.

[0064] The third conductive region 40c, like the first conductive region 40a and the second conductive region 40b, has a conductivity type different from that of the active region 35. In addition, the first conductive region 40a, the second conductive region 40b, and the third conductive region 40c have electrical conductivities greater than that of the active region 35.

[0065] The second conductive region 40b, the active region 35 for one memory transistor, the first conductive region 40a, the active region 35 for the other memory transistor, and the third conductive region 40c are arranged in this order in the second direction Ax2. In this embodiment, the second conductive region 40b and the third conductive region 40c are connected to a reference potential line (e.g., a ground line). The first conductive region 40a is shared by two memory transistors and is connected to a metal wiring layer 43 (bit line) via a contact plug 41a (contact hole).

[0066] As shown in Figures 3(a) to 3(c), 4(a) to 4(b), and 5(a) to 5(b), according to the semiconductor memory device 13, the memory transistor can exhibit three types of current characteristics depending on the presence or absence of adjacent portions (32a, 42a, 44b) in the adjacent insulating regions 33 that define the width of the active region 35, specifically, current characteristics based on an additional transistor on one side, an additional transistor on both sides, and no additional transistor.

[0067] In conventional ROM memory arrays, adjacent transistors without additional transistors have been arranged to share a drain region. Referring to Figure 5, a combination of adjacent transistors that share a drain region is shown, and the combination in Figure 5 is referred to as D(T5, T5). This notation, D(T5, T5), also applies to other combinations as an arrangement representing D(upper Tr, lower Tr). Here, the "upper Tr" and "lower Tr" in D(upper Tr, lower Tr) are interchangeable. Referring again to Figure 2, the three types of memory transistors can be arranged in various ways in a two-dimensional memory array.

[0068] The combinations of adjacent transistors that share a drain region are shown below. D(T3, T3) D(T3, T3R) D (T3, T4) D(T3, T5) D(T3R, T3R) D(T3R, T4) D(T3R, T5) D(T4, T4) D (T4, T5) In addition, in conventional ROM memory arrays, adjacent transistors without additional transistors have been arranged to share a word line. This combination is referred to as W(T5, T5), following the notation above. This notation, W(T5, T5), also applies to other combinations as an arrangement representing W(left Tr, right Tr). Here, the "left Tr" and "right Tr" in W(left Tr, right Tr) are not interchangeable.

[0069] The combinations of adjacent transistors that share a word line are shown below. W(T3, T3) W(T3, T4) W(T3, T5) W (T3R, T3) W (T3R, T3R) W (T3R, T4) W (T3R, T5) W(T4, T3) W (T4, T3R) W (T4, T5) W(T5, T3) W (T5, T3R) W (T5, T4) If necessary, the following combinations can be used: W(T3, T3R) W(T4, T4) In this structure, the insulating region 33 located between the active regions 35 of two transistors is arranged in the order of an adjacent portion, a remote portion and a further adjacent portion directly below the gate electrode 37 .

[0070] In these combinations, an additional transistor belonging to two adjacent transistors is provided in an insulating region 33 between the two adjacent transistors that share a gate electrode 37. The insulating region 33 has an element isolation structure in which, directly below the gate electrode 37, an adjacent portion (32a, 42a, 44a), a remote portion (32b, 42b, 44b), and an adjacent portion (32a, 42a, 44a) are arranged in this order from one of the two adjacent transistors to the other.

[0071] Figure 6 shows the current characteristics of three types of transistors (IDS1, IDS2, and IDS3). In the current characteristics graph, the vertical axis represents the drain saturation current (normalized value) per unit width (1 μm) of the active region, and the horizontal axis represents the width of the active region on a logarithmic scale.

[0072] Each of the current characteristics (IDS1 to IDS3) represents a current characteristic based on a structure with additional transistors. Current characteristic (IDS1) represents a current characteristic based on a structure with additional transistors on both sides, current characteristic (IDS2) represents a current characteristic based on a structure with an additional transistor on one side, and current characteristic (IDS3) represents a current characteristic based on a structure without additional transistors. At a horizontal scale of 0.3 μm, the current value (normalized value) of current characteristic (IDS3) is approximately 650 μA / μm, the current value (normalized value) of current characteristic (IDS2) is approximately 680 μA / μm, and the current value (normalized value) of current characteristic (IDS1) is approximately 720 μA / μm. The current difference (difference in normalized values) between current characteristic (IDS1) and current characteristic (IDS2) is 40 μA / μm, and the current difference (difference in normalized values) between current characteristic (IDS2) and current characteristic (IDS3) is 30 μA / μm.

[0073] For a transistor with an active region width of 0.3 μm, the difference in drain saturation current between the two additional transistors is approximately 10 μA. The difference in current between the one additional transistor is approximately 10 μA.

[0074] 7(a) shows an exemplary arrangement of three types of memory transistors in an array of the semiconductor memory device 13. "None," "Either," and "Both" marked on the gate electrode 37 indicate whether the transistor of the gate electrode 37 has an additional transistor or not. "None" indicates a transistor that does not have an additional transistor, "Either" indicates a transistor that has an additional transistor on one side, and "Both" indicates a transistor that has an additional transistor on both sides.

[0075] 7(b) shows a schematic diagram of the characteristic distribution of three types of memory transistors, "None," "Either," and "Both," in the array of the semiconductor memory device 13. In FIG. 7(b), the vertical axis shows the typical current when a memory transistor with an active region width of 0.3 μm is conducting, and the horizontal axis shows the frequency of each individual transistor.

[0076] An example of a method for reading (or determining) the memory contents of a memory transistor of a semiconductor memory device 13 will be described. To read the ternary memory contents of a memory transistor, the read circuit 15 shown in FIG. 1 is used. In FIG. 7(b), a certain detection level (e.g., DET1) is used to distinguish a memory transistor "None" from a memory transistor "Either." A certain detection level (e.g., DET2) can be used to distinguish a memory transistor "Either" from a memory transistor "Both."

[0077] 8 is a circuit diagram showing an example of a read circuit 15 of the semiconductor memory integrated circuit according to this embodiment. The read circuit 15 includes a detection circuit 51 and one or more reference circuits 53. The detection circuit 51 is connected to the bit line BL of the semiconductor memory device 13 via the bit selection transistor BLT in the bit selection circuit 23. The detection circuit 51 is connected to the reference circuit 53. The reference circuit 53 generates two reference levels (DET1, DET2) that determine whether the current characteristic of the selected memory transistor is "None," "Either," or "Both," and provides signals representing the reference levels (DET1, DET2) to the detection circuit 51.

[0078] The detection circuit 51 includes a feedback circuit 55a that determines the potential level of the bit line BL and detects changes in the potential level to control the bit line BL; a load circuit 55b that receives a current from a selected memory transistor MT; and comparison circuits 55c and 55d that form a current mirror circuit with the load circuit 55b and compare the mirror current received from the current mirror circuit CM1 with reference currents (reference levels DET1 and DET2) from the reference circuit 53. The readout circuit 15 further includes logic gates 55e and 55f, which are connected to the outputs of the comparison circuits 55c and 55d of the detection circuit 51, respectively. The logic gates 55e and 55f receive signals from the outputs of the comparison circuits 55c and 55d, respectively, and convert the detection result of the detection circuit 51 into a logic level digital signal. The logic gates 55e and 55f can be, for example, CMOS inverters.

[0079] Specifically, feedback circuit 55a detects a change in the potential level of the bit line and connects the bit line BL to load circuit 55b. Load circuit 55b receives a current from a selected memory transistor ("MT" in the memory array of FIG. 1). Comparator circuit 55c configures current mirror circuit CM1 with load circuit 55b and compares the mirror current received via current mirror circuit CM1 with a reference current (reference level DET1) from reference circuit 53. Comparator circuit 55d configures current mirror circuit CM2 with load circuit 55b and compares the mirror current received via current mirror circuit CM2 with a reference current (reference level DET2) from reference circuit 53.

[0080] The semiconductor memory integrated circuit 11 according to this embodiment includes a DET1 reference circuit 57a and a DET2 reference circuit 57b that generate two reference levels (DET1 and DET2). Each of the DET1 reference circuit 57a and the DET2 reference circuit 57b includes a current source circuit 57c, a feedback circuit 57d, and a current mirror circuit 57e that are equivalent to the feedback circuit 55a and the current mirror circuit CM1 of the detection circuit 51.

[0081] In the DET1 reference circuit 57a, the current source circuit 57c is set to generate the reference current (reference level DET1) shown in FIG. 7. The reference current from the current source circuit 57c is provided to the current mirror circuit 57e (CM3) via the feedback circuit 57d. The DET1 reference circuit 57a forms a current mirror circuit CM4 with the transistors in the comparison circuit 55c, and mirrors a current related to the reference current (reference level DET1) to the comparison circuit 55c for determination in the comparison circuit 55c. The comparison circuit 55c compares this mirror current with the mirror current from the memory transistor.

[0082] Similarly, in the DET2 reference circuit 57b, the current source circuit 57c is set to generate the reference current (reference level DET2) shown in FIG. 7. The reference current from the current source circuit 57c is provided to the current mirror circuit 57e (CM5) via the feedback circuit 57d. The DET2 reference circuit 57b forms a current mirror circuit CM6 with the transistors in the comparison circuit 55d, and mirrors a current related to the reference current (reference level DET2) to the comparison circuit 55d for determination in the comparison circuit 55d. The comparison circuit 55d compares this mirror current with the mirror current from the memory transistor.

[0083] The read circuit 15 provides the read result of the memory transistor as follows. The type of memory transistor, the output value of logic gate 55e, and the output value of logic gate 55f. "Both": H level, H level. "Either": H level, L level. "None": L level, L level. At an active region width of 0.35 μm or less, the saturation current of the "None" type transistor without any additional transistor is the smallest.

[0084] FIG. 9 shows an example of a circuit diagram of a semiconductor integrated circuit for a current source according to this embodiment. A current source circuit 61 can be used for the current source circuit 57c. The current source circuit 61 includes at least one of a "Both" type and an "Either" type transistor, and can further include one or more "None" type transistors, if necessary. When the current source circuit 61 includes a "Both" type transistor, the current source circuit 61 can be provided with one or more "Both" type transistors. When the current source circuit 61 includes an "Either" type transistor, the current source circuit 61 can be provided with one or more "Either" type transistors.

[0085] Referring to FIG. 9, specifically, the current source circuit 61 includes one "Both" type current source transistor 65a, one "Either" type current source transistor 65b, and one "None" type current source transistor 65c.

[0086] In the current source circuit 61, the drain regions or source regions of adjacent current source transistors (65a, 65b, 65c) are shared. The source regions of the current source transistors (65a, 65b, 65c) are connected to a ground line via, for example, a metal wiring layer 67a, and the drain regions of the current source transistors (65a, 65b, 65c) are connected to a metal wiring layer 67b.

[0087] The current source circuit 61 includes a switch group 63 including a plurality of switches. The switch group 63 generates a signal to select one or more of the current source transistors 65 a, 65 b, and 65 c, and the current source circuit 61 generates a current from the selected current source transistors (65 a, 65 b, 65 c). Specifically, the switches of the switch group 63 are connected to the gate electrodes of the current source transistors (65 a, 65 b, 65 c), and the switches of the switch group 63 determine which of the current source transistors (65 a, 65 b, 65 c) are to be turned on and which are to be turned off. Each switch in the switch group 63 may be a fixed switch that uses metal wiring formed during the manufacturing process, or may be a selectable switch that operates in response to an external control signal CNTL1 to the switch group 63. Such a switch may be configured by a transistor.

[0088] In this embodiment, the metal wiring layer 67b is connected to the power supply line VD via a load circuit 68 outside the current source circuit 61. The load circuit 68 operates to generate a voltage value corresponding to the current flowing through the current source circuit 61. This voltage value is provided to an amplifier 69. The amplifier 69 can be, for example, an operational amplifier, which is connected to form, for example, a voltage buffer circuit (voltage follower).

[0089] FIG. 10 shows another example of a circuit diagram of a semiconductor integrated circuit for a current source according to this embodiment. A current source circuit 71 can be used for the current source circuit 57c. The current source circuit 71 includes at least one of a "Both" type and an "Either" type transistor, and can further include one or more "None" type transistors, if necessary. When the current source circuit 71 includes a "Both" type transistor, the current source circuit 61 can be provided with one or more "Both" type transistors. When the current source circuit 61 includes an "Either" type transistor, the current source circuit 61 can be provided with one or more "Either" type transistors.

[0090] Referring to FIG. 10, the exemplary circuit includes one "Both" type current source transistor 75a, one "Either" type current source transistor 75b, and one "None" type current source transistor 75c.

[0091] In the current source circuit 71, the gate electrodes of the current source transistors (75a, 75b, 75c) are shared. The source regions of the current source transistors (75a, 75b, 75c) are connected to a ground line, for example, via a metal wiring layer 77a, and the drain regions of the current source transistors (75a, 75b, 75c) are connected to a common metal wiring layer 77e via respective metal wiring layers 77b, 77c, 77d and selectors 79b, 79c, 79d. The gate electrodes 37 of the current source transistors (75a, 75b, 75c) are connected to a bias source 78, which applies an appropriate voltage to the gate electrodes 37 of the current source transistors (75a, 75b, 75c) to control the conduction and non-conduction of the current source transistors (75a, 75b, 75c) as needed. Each of the selectors 79b, 79c, 79d can be, for example, a transistor. The current source circuit 71 includes a switch group 73 including a plurality of switches for selecting selectors 79b, 79c, and 79d, and the switch group 73 provides signals for selecting one or more of the current source transistors 75a, 75b, and 75c to these current source transistors (75a, 75b, and 75c). Specifically, the switches of the switch group 73 are connected to the gates of the transistors of the selectors 79b, 79c, and 79d connected to the current source transistors 75a, 75b, and 75c, respectively.

[0092] The switches of the switch group 73 specify which current source transistors (75a, 75b, 75c) are to be selected and which are to be unselected, via selectors 79b, 79c, 79d. The individual switches in the switch group 73 may be fixed switches that utilize metal wiring formed in the manufacturing process, or may be selectable in response to an external control signal CNTL1 to the switch group 73.

[0093] In this embodiment, the metal wiring layer 77e is connected to the power supply line VD via a load circuit 68 outside the current source circuit 71. The load circuit 68 operates to generate a voltage value corresponding to the current flowing through the current source circuit 71. This voltage value is provided to an amplifier 69.

[0094] The current source circuits 61 and 71 shown in Figures 9 and 10 can be used for current sources and voltage sources of analog circuits. Such analog circuits can include, for example, an A / D converter and a D / A converter. The readout circuit 15 of the semiconductor memory integrated circuit 11 can use the current source circuits 61 and 71.

[0095] Next, the main steps in the method for fabricating the semiconductor memory device 13 will be described with reference to Figures 11(a), 11(b), 11(c), 12(a), 12(b), 12(c), 13(a), 13(b), 13(c), 14(a), 14(b), 14(c), 15, 16(a), 16(b), and 16(c). In the following description, for ease of understanding, reference numerals from the previous description may be used.

[0096] As shown in FIG. 11(a), a semiconductor substrate 81 such as a silicon wafer is prepared. The silicon wafer may have, for example, a p-type conductive semiconductor region 80. An insulating film such as a silicon oxide film 82a, a silicon nitride film 82b, and a resist film 82c are sequentially formed on the semiconductor substrate 81. The silicon oxide film 82a may be generated, for example, by oxidizing the semiconductor substrate 81. The silicon nitride film 82b may be deposited by vapor deposition. The resist film 82c may be applied. The silicon oxide film 82a may be, for example, 10 nm thick, the silicon nitride film 82b may be, for example, 100 nm thick, and the resist film 82c may be, for example, 700 nm thick.

[0097] As shown in FIG. 11(b), the resist film 82c is exposed to light to form a pattern, forming a mask 83. The mask 83 has openings 83a at positions where recesses 28 for trenches should be formed. Next, the silicon oxide film 82a, the silicon nitride film 82b, and the semiconductor substrate 81 are etched using the mask 83 to form the recesses 28 in the semiconductor substrate 81. The etching can be performed by anisotropic dry etching. The depth of the recesses 28 can be, for example, 0.2 μm. The width of the openings of the recesses 28 can be, for example, 0.3 μm. After etching, the mask 83 is removed.

[0098] 11(c), after removing the mask 83, the semiconductor substrate 81 is cleaned by treatment with hydrofluoric acid. Overhangs 82d are formed on the silicon oxide film 82a.

[0099] If necessary, as shown in FIG. 12( a ), after removing the mask 83 , the semiconductor substrate 81 exposed in the recess 28 is thermally oxidized to cover the surface of the recess 28 with a silicon oxide film 84 .

[0100] 12(b), after the surface of the recess 28 is thermally oxidized, silicon oxide 85 is deposited in the recess 28 and on the silicon nitride film 82b by chemical vapor deposition, thereby filling the recess 28 with the silicon oxide 85. The deposited silicon oxide 85 becomes an integral silicon oxide film that fills the recess 28 from the silicon nitride film 82b.

[0101] 12(c), after depositing the silicon oxide 85, the deposited silicon oxide 85 and (if necessary) the upper part of the silicon nitride film 82b are polished and removed by a chemical mechanical polishing (CMP) method to produce a substrate product SP1. By this removal, the irregularities on the surface of the deposited silicon oxide 85 are planarized, and the surface of the substrate product SP1 is almost flat.

[0102] 13(a), after polishing, the silicon nitride film 82b remains on the semiconductor substrate 81, and the upper surface of the polished silicon oxide 85 is flush with the upper surface of the silicon nitride film 82b. The silicon nitride film 82b will be removed in a later step. To prevent protruding portions of the polished silicon oxide 85 from remaining after the removal of the silicon nitride film 82b, the polished silicon oxide 85 that appears in the openings of the silicon nitride film 82b is pre-etched before the silicon nitride film 82b is removed.

[0103] 13(b), insulating portions for the insulating regions 33 (32, 34) are formed after preliminary etching of the silicon oxide 85 in the recesses 28. After this, the silicon nitride film 82b is removed by etching.

[0104] Through these steps, a substrate product SP0 was prepared. In this embodiment, this preparation was performed by fabricating the substrate product SP0 from a semiconductor substrate 81. The substrate product SP0 has a semiconductor region 31 having a plurality of recesses 28 for shallow trench isolation (STI), and a plurality of insulating regions 33 provided in each of the recesses 28 of the semiconductor region 31. The semiconductor region 31 has an active region 35, and the active region 35 is provided between a first insulating region 32 and a second insulating region 34 adjacent to each other within the insulating region 33.

[0105] As shown in FIG. 13(c), a dopant for adjusting the threshold voltage of the memory transistor is introduced into the active region 35 of the substrate product SP0. The dopant can be, for example, a p-type dopant, specifically boron. The introduction of the dopant can be performed, for example, by ion implantation (I / I). Specifically, after forming a thin oxide film on the surface of the substrate product SP0 by thermal oxidation, a resist mask 86 is formed on the substrate product SP0 by photolithography. The dopant introduction area is defined by the formed mask 86. Ion implantation of the p-type dopant is performed in the opening 86a of the mask 86. After the ion implantation, the mask 86 is removed. In this embodiment, the ion implantation is performed on the active regions 35 of all memory transistors.

[0106] 14(a), after the ion implantation, a resist mask 87 is formed on the main surface of the substrate product SP0 by photolithography. The mask 87 has an opening 87a, which is located on the boundary (either BDY1 or BDY2) between the insulating region 33 and the active region 35 where an additional transistor is to be formed in the active region 35.

[0107] 15 is a plan view showing a mask 87 formed on the main surface of the substrate product SP0. The mask 87 has three types of openings 87a, 87b, and 87c. The opening 87a is located on a boundary BDY1 between the insulating region for the first insulating region 32 and the active region 35. The opening 87b is located on a boundary BDY2 between the insulating region for the second insulating region 34 and the active region 35. The opening 87c is located on the boundary BDY1 and the boundary BDY2. Therefore, the openings (87a, 87b, and 87c) of the mask 87 can be located on at least one of the boundary BDY1 and the boundary BDY2.

[0108] As shown in FIG. 14(b), a mask 87 is used to selectively remove the insulating region 33 (32), e.g., silicon oxide, exposed in the openings (87a, 87b, 87c) relative to the semiconductor region 31 (active region 35). This removal can be performed, for example, by reactive ion etching. This etching removes the insulating region 33 exposed in the openings (87a, 87b, 87c) to form a recess 30. As a result, the etched insulating region 33 is provided with an adjacent portion 32a and a remote portion 32b. The recess 30 partially exposes a side surface 35b of the active region 35.

[0109] 14(c), after forming the recess 30 in the substrate product SP0 by partially removing the insulator in the insulating region 33, a gate insulating film 39 is formed in the active region 35. Specifically, the gate insulating film 39 is made of, for example, silicon oxide, and this silicon oxide is formed by thermally oxidizing the top surface 35a of the active region 35 and all of the side surfaces 35b (35c) of the active region 35.

[0110] 16(a), after forming a gate insulating film 39, a gate electrode 37 is formed on the active region 35 and insulating region 33 (32, 34) by polysilicon deposition, photolithography, and etching. The formed gate electrode 37 extends on the upper surface of the active region 35 and is also provided on all side surfaces 35b (35c) of the active region 35. The gate electrode 37 crosses the active region 35 in a direction from one of the first insulating region 32 and the second insulating region 34 to the other and extends on the formed gate insulating film 39 on all side surfaces 35b (35c).

[0111] According to this manufacturing method, the areas of the insulating region 33 removed using the openings (87a, 87b, 87c) of the mask 87 have a thickness smaller than the thickness of the insulating region 33 outside the openings (87a, 87b, 87c), so that the gate electrode 37 and the gate insulating film 39 extend not only along the top surface 35a of the active region 35 but also along at least one of the formed side surfaces 35b and / or side surfaces 35c of the active region 35, enabling the formed side surfaces 35b and / or side surfaces 35c to function as additional transistors. According to this manufacturing method, additional transistors can be formed on one and / or both sides of the active region 35 using photolithography and anisotropic etching.

[0112] 16(b), after the gate electrode 37 is formed, an interlayer insulating film 41 is grown on the substrate product by chemical vapor deposition. The interlayer insulating film 41 can be made of, for example, a silicon-based inorganic insulator.

[0113] 16(c), after forming the interlayer insulating film 41, photolithography and etching are used to form contact openings in the interlayer insulating film 41. Next, a metallization step is carried out to form a metal wiring layer 43.

[0114] As described above, according to the embodiments, an object is to provide a semiconductor memory device having a structure that can provide any one of a plurality of current characteristics without changing the transistor width, a method for manufacturing a semiconductor memory device, a semiconductor integrated circuit including a current source circuit and a bias source, and a semiconductor memory integrated circuit including the semiconductor integrated circuit and the semiconductor memory device.

[0115] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0116] 11...Semiconductor memory integrated circuit, 13...Semiconductor memory device, 15...Readout circuit, 16...Semiconductor integrated circuit, 17...Current source circuit, 19...Word decoder circuit, 21...Bit decoder circuit, 23...Bit selection circuit, 28...Depression, 30...Recess, 31...Semiconductor region, 32, 33, 34, 42, 44, 52, 54...Insulating region, 32a, 34a, 42a...Adjacent portion, 32b, 34b, 44b...Remote portion, 35...Active region, 35a...Top surface, 35b, 35c...Side surface, 37...Gate electrode, 39, 39a, 39b, 39c···Gate insulating film, 40a, 40b, 40c··Conductive region, 41··Interlayer insulating film, 41a··Contact plug, 43··Metal wiring layer, 45··Protective insulating film, 51··Detection circuit, 53··Reference circuit, 55a, 57d··Feedback circuit, 55b··Load circuit, 55c, 55d··Comparator circuit, 55e, 55f··Logic gate, 57a, 57b··Reference circuit, 57c··Current source circuit, 57e··Current mirror circuit, 61, 71··Current source circuit, 63, 73··Switch group, 65a, 65b, 65c, 75 a, 75b, 75c... Current source transistor, 67a, 67b, 77a, 77b, 77e... Metal wiring layer, 68... Load circuit, 69... Amplifier, 78... Bias source, 79b... Selector, 80... Semiconductor region, 81... Semiconductor substrate, 82a... Silicon oxide film, 82b... Silicon nitride film, 82c... Resist film, 82d... Overhang, 83... Mask, 83a... Opening, 84... Silicon oxide film, 85... Silicon oxide, 86... Mask, 86a... Opening, 87... Mask, 87a, 87b, 87c... Opening , Ax1, Ax2, Ax3...direction, BDY1, BDY2...boundary, BL...bit line, BTS...selected bit line, BLT...bit select transistor, CM1, CM2, CM3, CM4, CM5, CM6...current mirror circuit, CNTL1...external control signal, CS...coordinate system, DET1, DET2...reference level, MT...transistor, SP0...substrate product, SP1...substrate product, VD...power supply line, WL...word line, WLS...selected word line, XAD...X address, YAD...Y address.

Claims

1. a semiconductor region having a first active region for a first memory transistor and a plurality of recesses for trench isolation; a plurality of insulating regions provided in each of the recesses in the semiconductor region; a first gate electrode extending in a first direction from one of the first insulating region and the second insulating region adjacent to each other among the insulating regions to the other and passing over the first active region; a first gate insulating film provided between the first gate electrode and the first active region; Including, the first active region of the semiconductor region is provided between the first insulating region and the second insulating region; one of the first insulating region and the second insulating region has an adjacent portion and a remote portion, and the other of the first insulating region and the second insulating region is thicker than the adjacent portion under the first gate electrode; the adjacent portion is adjacent to the first active region under the first gate electrode; the remote portion is adjacent to the adjacent portion under the first gate electrode; the adjacent portion is disposed between the remote portion and the first active area; the adjacent portion has a thickness that is less than a thickness of the remote portion; the first gate insulating film has an upper surface portion extending along an upper surface of the first active region, a side surface portion extending along a side surface of the first active region, and a corner portion at a boundary between the upper surface portion and the side surface portion; the semiconductor region has a first conductive region and a second conductive region provided between the first insulating region and the second insulating region, the first conductive region, the first active region, and the second conductive region are arranged in a second direction intersecting the first direction; Semiconductor memory device.

2. the semiconductor region further includes a second active region for a second memory transistor provided between the first insulating region and the second insulating region; The semiconductor memory device includes: a second gate electrode extending in the first direction above the second active region and passing over the second active region; a second gate insulating film provided between the second gate electrode and the second active region; Including, the semiconductor region has a third conductive region provided between the first insulating region and the second insulating region; the first conductive region, the second conductive region, and the third conductive region have a conductivity type different from a conductivity type of the first active region; the second conductive region, the first active region, the first conductive region, the second active region, and the third conductive region are sequentially arranged in the second direction; the second conductive region and the third conductive region are connected to a reference potential line; the first conductive region is shared by the first memory transistor and the second memory transistor, and is connected to a metal wiring layer; 2. The semiconductor memory device according to claim 1.

3. In the first insulating region, the adjacent portion has a thickness that is less than a thickness of the remote portion; the second insulating region is thicker under the first gate electrode than the adjacent portion of the first insulating region; 3. The semiconductor memory device according to claim 1.

4. the first insulating region and the second insulating region, the adjacent portion being disposed to sandwich the second active region, and the remote portion being disposed to sandwich the adjacent portion and the second active region; On either side of the second active area, the adjacent portions have a thickness that is less than a thickness of the remote portions.

3. The semiconductor memory device according to claim 2.

5. the insulating region includes a third insulating region adjacent to the second insulating region; the first insulating region, the second insulating region, and the third insulating region are arranged in the first direction, the semiconductor region further includes a third active region for a third memory transistor; the first gate electrode extends in the first direction and passes over the third active region; The semiconductor memory device includes: a third gate insulating film provided between the first gate electrode and the third active region; the third insulating region has an adjacent portion and a remote portion; In the third insulating region, the adjacent portion is adjacent to the third active region below the first gate electrode, and the remote portion is adjacent to the adjacent portion below the first gate electrode, and the adjacent portion is provided between the remote portion and the third active region; beneath the first gate electrode, the adjacent portion of the third insulating region has a thickness that is less than a thickness of the remote portion of the third insulating region; the second insulating region is thicker under the first gate electrode than the adjacent portion of the third insulating region; 5. The semiconductor memory device according to claim 1.

6. the insulating region includes a fourth insulating region adjacent to the first insulating region; the semiconductor region further includes a fourth active region for a fourth memory transistor provided between the first insulating region and the fourth insulating region; the first gate electrode extends in the first direction and passes over the fourth active region; the semiconductor memory device further includes a fourth gate insulating film provided between the first gate electrode and the fourth active region; the first insulating region has a further adjacent portion adjacent the fourth active region beneath the first gate electrode; the remote portion of the first insulating region is located between the adjacent portion and the further adjacent portion of the first insulating region under the first gate electrode; the further adjacent portion is disposed between the remote portion and the fourth active area; and beneath the first gate electrode, the further adjacent portion has a thickness that is less than a thickness of the remote portion of the first insulating region.

6. The semiconductor memory device according to claim 4 or 5.

7. the adjacent portion has either a structure crossing the first gate electrode in a direction from one of the first conductive region and the second conductive region to the other, or a structure extending from one of the first conductive region and the second conductive region and terminating directly below the first gate electrode.

7. The semiconductor memory device according to claim 1.

8. preparing a substrate product having a semiconductor region having a plurality of recesses for trench isolation and a plurality of insulating regions respectively provided in the recesses of the semiconductor region, the semiconductor region having an active region provided between a first insulating region and a second insulating region adjacent to each other among the insulating regions; forming a mask having an opening on a major surface of the substrate product; removing the insulator from the insulating region of the substrate product using the mask; forming a gate insulating film on the active region after removing the insulator; forming a gate electrode on the insulating region and the active region after forming the gate insulating film; Including, the opening is located on one of a first boundary between the active region and the first insulating region and a second boundary between the active region and the second insulating region; removing the insulator from the substrate product includes partially removing the insulating region at the opening in the mask to partially expose a side surface of the active region; one of the first insulating region and the second insulating region has an adjacent portion and a remote portion according to the opening in the mask, and the other of the first insulating region and the second insulating region is thicker than the adjacent portion under the gate electrode; the gate insulating film has an upper surface portion extending along an upper surface of the active region, a side surface portion extending along the side surface of the active region, and a corner portion at a boundary between the upper surface portion and the side surface portion; the gate electrode crosses the active region in a direction from one of the first insulating region and the second insulating region to the other and extends on the gate insulating film on the side surface; A method for manufacturing a semiconductor memory device.

9. the mask covers the second boundary; 9. A method for manufacturing a semiconductor memory device according to claim 8.

10. the opening of the mask is located on the first boundary and the second boundary.

9. A method for manufacturing a semiconductor memory device according to claim 8.

11. A semiconductor integrated circuit including a current source circuit and a bias source, the current source circuit includes at least one transistor; The transistor is a semiconductor region having a plurality of recesses for trench isolation; a plurality of insulating regions, each of which includes a first insulating region and a second insulating region adjacent to each other, provided in each of the recesses of the semiconductor region; an active region for the transistor disposed between the first insulating region and the second insulating region; a gate electrode extending in a first direction from one of the first insulating region and the second insulating region to the other and passing over the active region; a gate insulating film provided between the gate electrode and the active region; Including, one of the first insulating region and the second insulating region has an adjacent portion and a remote portion; the gate insulating film has an upper surface portion extending along an upper surface of the active region, a side surface portion extending along a side surface of the active region, and a corner portion at a boundary between the upper surface portion and the side surface portion; one of the first insulating region and the second insulating region has an adjacent portion and a remote portion; the other of the first insulating region and the second insulating region is thicker under the gate electrode than the adjacent portion; the adjacent portion is adjacent to the active region under the gate electrode; the adjacent portion is adjacent to the remote portion under the gate electrode; the adjacent portion is disposed beneath the gate electrode between the remote portion and the active region; the adjacent portion has a thickness that is less than a thickness of the remote portion; the semiconductor region has a first conductive region provided between the first insulating region and the second insulating region, and a second conductive region provided between the first insulating region and the second insulating region; the first conductive region, the active region, and the second conductive region are arranged in a second direction intersecting the first direction; the bias source is connected to the gate electrode and configured to apply a voltage to the gate electrode; Semiconductor integrated circuit.

12. A semiconductor memory integrated circuit, comprising: a semiconductor integrated circuit according to claim 11; A semiconductor memory device according to any one of claims 1 to 7; a read circuit configured to read the first memory transistor of the semiconductor memory device; Including, the read circuit is connected to the semiconductor memory device and configured to compare a current from the first memory transistor with a current from the current source circuit of the semiconductor integrated circuit; Semiconductor memory integrated circuit.

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