Semiconductor device, light detection system, light emitting system, and mobile object

Abstract

To reduce crosstalk generated in a functional layer.SOLUTION: A semiconductor device includes: a substrate having a principal surface; an upper electrode disposed on the substrate; a first lower electrode and a second lower electrode that are disposed between the substrate and the upper electrode; an isolation region disposed between the first lower electrode and the second lower electrode; a functional layer for performing light emission or photoelectric conversion; and an interlayer disposed at least on the first lower electrode. The semiconductor device further includes a first insulator part that is disposed between the first lower electrode and the second lower electrode and has a first part disposed at a position separated more from the principal surface than the interlayer's top surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a light detection system, a light emitting system, and a moving object. [Background technology]

[0002] There is known a photoelectric conversion device in which pixels each having two electrodes and a photoelectric conversion layer as a photoelectric conversion unit are arranged. Patent Document 1 discloses a photoelectric conversion device having a configuration in which an insulating member arranged on one electrode is covered with a photoelectric conversion layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-033978 Summary of the Invention [Problem to be solved by the invention]

[0004] As a result of investigations by the present inventors, it has been found that the configuration of Patent Document 1 may not provide sufficient electrical isolation between adjacent pixels. Therefore, an object of the present invention is to reduce crosstalk that occurs in functional layers such as photoelectric conversion layers. [Means for solving the problem]

[0005] One aspect of the present invention is a semiconductor device comprising: a substrate having a main surface; an upper electrode arranged on the substrate; a first lower electrode arranged between the substrate and the upper electrode; a second lower electrode arranged between the substrate and the upper electrode; a separation region arranged between the first lower electrode and the second lower electrode; a functional layer arranged between the first lower electrode and the upper electrode and between the second lower electrode and the upper electrode, the functional layer performing light emission or photoelectric conversion; and an interface layer having a portion arranged between the first lower electrode and the functional layer and a portion arranged between the second lower electrode and the functional layer, the first insulator portion being arranged between the first lower electrode and the second lower electrode and having a first portion positioned farther from the main surface than the upper surface of the portion of the interface layer arranged between the first lower electrode and the functional layer.

[0006] Another aspect of the present invention is a semiconductor device comprising: a substrate having a main surface; an upper electrode arranged on the substrate; a first lower electrode arranged between the substrate and the upper electrode; a second lower electrode arranged between the substrate and the upper electrode; a separation region arranged between the first lower electrode and the second lower electrode; functional layers arranged between the first lower electrode and the upper electrode and between the second lower electrode and the upper electrode, the functional layers performing light emission or photoelectric conversion; an interface layer arranged at least between an upper surface of the first lower electrode and the functional layer; and a first insulator portion, wherein the interface layer is located between the first lower electrode and the first insulator portion. [Effects of the Invention]

[0007] The present invention can reduce crosstalk that occurs in a functional layer such as a photoelectric conversion layer. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] 1A is a schematic cross-sectional view showing the semiconductor device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view showing a modified example of the semiconductor device according to the first embodiment. [Figure 3]10(a) is a schematic cross-sectional view showing a semiconductor device according to a second embodiment, and FIG. 10(b) is a schematic cross-sectional view showing a modified example of the semiconductor device according to the second embodiment. [Figure 4] 10(a) is a schematic cross-sectional view showing a semiconductor device according to a third embodiment, and (b) is a schematic cross-sectional view showing a modified example of the semiconductor device according to the third embodiment. [Figure 5] 10A is a schematic cross-sectional view showing a semiconductor device according to a fourth embodiment, FIG. 10B is a schematic cross-sectional view showing a modified example of the semiconductor device according to the fourth embodiment, and FIG. 10C is a schematic cross-sectional view showing a modified example of the semiconductor device according to the fourth embodiment. [Figure 6] 10A is a schematic cross-sectional view showing a semiconductor device according to a fifth embodiment, FIG. 10B is a schematic cross-sectional view showing a modified example of the semiconductor device according to the fifth embodiment, and FIG. 10C is a schematic cross-sectional view showing a modified example of the semiconductor device according to the fifth embodiment. [Figure 7] 1A is a schematic plan view showing the semiconductor device according to the first embodiment, FIG. 1B is a schematic plan view showing the semiconductor device according to the third embodiment, and FIG. 1C is a schematic plan view showing a modified example of the semiconductor device according to the third embodiment. [Figure 8] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 1 is a block diagram illustrating an example of an electronic device. [Figure 11] FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] The semiconductor device according to the present invention will be described below with reference to the drawings. Each embodiment shows an example of the present invention, and the values, shapes, materials, components, arrangement and connection of the components, etc. do not limit the present invention. For example, each embodiment uses a photoelectric conversion device as the semiconductor device, but the present invention can also be applied to a light-emitting device. Furthermore, while each embodiment describes transistors, semiconductor regions, etc., the conductivity type thereof can be changed as appropriate.

[0010] In the drawings, components with the same reference numerals are considered to be equivalent components and will not be described again. Furthermore, the reference numerals may be omitted for repeating patterns or components that can be understood as being the same.

[0011] (First embodiment) In this embodiment, a photoelectric conversion device will be used as the semiconductor device according to the present invention. FIG. 1 is a cross-sectional schematic diagram showing three unit cells 120 of the photoelectric conversion device. Here, FIG. 1 is a cross-section taken along a plane including the Z direction (upward) and the X direction. The unit cells 120 are also referred to as pixels or subpixels. Each unit cell 120 has an equivalent circuit configuration. Here, when the semiconductor device is a photoelectric conversion device, the unit cell 120 has at least one photoelectric conversion element. When the semiconductor device is a light-emitting device, the unit cell 120 has at least one light-emitting element. The photoelectric conversion element and the light-emitting element are configured by appropriately selecting materials for the functional layers described below. The circuit configuration of the unit cells of the photoelectric conversion device and the light-emitting device is set appropriately. Next, the photoelectric conversion device of FIG. 1 will be described in detail.

[0012] In FIG. 1 , substrate 100 has a principal surface P1. The material of substrate 100 may be glass, ceramic, or the like, and in this embodiment, it is a semiconductor substrate made of single crystal silicon. Substrate 100 has transistor 101 and element isolation portion 113. Transistor 101 includes source / drain region 102, gate insulating film 103, gate electrode 104, and source / drain region 105. Gate electrode 104 is disposed on principal surface P1. Gate insulating film 103 is located between gate electrode 104 and principal surface P1. Source / drain region 102 and source / drain region 105 are disposed inside substrate 100.

[0013] A wiring structure 106 is disposed on the main surface P1 of the substrate 100. The wiring structure 106 includes a contact plug 107, a wiring layer 108, a via plug 109, a wiring layer 110, a via plug 111, and an insulating film 112. The insulating film 112 may be a multilayer film, although not shown in detail in FIG. 1. These members may be made of common semiconductor materials.

[0014] An upper electrode 134 is disposed on the substrate 100. In this embodiment, the upper electrode 134 is provided continuously across three unit cells 120. The upper and lower surfaces of the upper electrode 134 are flat. The lower electrode 131 can also be said to be included in the wiring structure 106. The lower electrode 131 is disposed between the substrate 100 and the upper electrode 134. At least one lower electrode 131 is included in each unit cell 120. In this embodiment, a configuration is shown in which one lower electrode 131 is disposed for each unit cell 120. Separation regions 130 are disposed between the multiple lower electrodes 131. The separation regions 130 may be the insulating films 112 of the wiring structure 106. The functional layers 133 are disposed between each lower electrode 131 and the upper electrode 134. The functional layers 133 emit light or perform photoelectric conversion. When the functional layer 133 emits light, the lower electrode 131 can supply the functional layer 133 with a control signal for controlling light emission / non-emission and light emission intensity. When the functional layer 133 performs photoelectric conversion, the lower electrode 131 can read out a signal based on the charge generated by the photoelectric conversion. In this embodiment, the functional layer 133 is described as performing photoelectric conversion. An interface layer 132 is disposed between the functional layer 133 and multiple lower electrodes 131. FIG. 1 shows three interface layers separated from each other. Here, it can be said that the interface layer 132 has, for example, a portion disposed between the functional layer 133 and one lower electrode 131 and a portion disposed between the functional layer 133 and another lower electrode 131. The interface layer 132 is a layer that ensures electrical insulation between the lower electrode 131 and the functional layer 133 with respect to some carriers. The interface layer 132 is also a layer that ensures conduction between the lower electrode 131 and the functional layer 133 with respect to other carriers. The interface layer 132 can also be considered a carrier injection blocking layer. The interface layer 132 can also function as an adhesion layer, and can suppress film peeling that occurs due to poor wettability between the lower electrode 131 and the functional layer 133. In areas where the interface layer 132 is not present, an insulator portion 135 can be formed at the interface between the lower electrode 131 and the functional layer 133, or between the separation region 130 and the functional layer 133.The interface layer 132 can be a layer that blocks electrons and conducts only holes (electron blocking interface layer) for the electrode that collects holes (positive electrode), and a layer that blocks holes and conducts only electrons (hole blocking interface layer) for the electrode that collects electrons (negative electrode).

[0015] In FIG. 1 , an insulating layer 136, a color filter layer 137, a planarization layer 138, and a microlens layer 139 are arranged in this order on the upper electrode 134 along the Z direction. The insulating layer 136 can function as a protective layer or a sealing layer. The color filter layer 137 has color filters corresponding to multiple colors. For example, one unit cell 120 includes one color filter. The planarization layer 138 is arranged on the color filter layer 137 and has a flat upper surface. The microlens layer 139 has multiple microlenses. For example, one unit cell 120 includes one microlens.

[0016] The semiconductor device of this embodiment has an insulator portion 135 disposed between two lower electrodes 131. The insulator portion 135 will be described with reference to Figures 1 and 2(a). In this embodiment, the insulator portion 135 is a void that contains, for example, air or an insulating gas.

[0017] FIG. 2(a) is an enlarged cross-sectional view of a portion of the wiring structure 106 in FIG. 1, extending from the color filter layer 137. The insulator portion 135 has a portion 201 located farther from the main surface P1 than the upper surface of the interface layer 132 disposed on the lower electrode 131. The insulator portion 135 also has a portion 201 surrounded by the functional layer 133 in a cross-sectional view perpendicular to the main surface P1. The positional relationship between the insulator portion 135, the interface layer 132, and the lower electrode 131 will now be described. Heights H1, H2, and H3 are measured along the Z direction from the main surface P1. Here, height H1 includes the upper surface 131T of the lower electrode 131, the lower surface 132B of the interface layer 132, and the lower surface 135B of the insulator portion 135. Height H2 includes the upper surface 132T of the interface layer 132. Height H3 includes the upper surface 135T of the insulator portion 135. Here, the portion 201 of the insulator portion 135 is disposed at a position farther from the main surface P1 than the upper surface 132T of the interface layer 132. In other words, the portion 201 is located between the heights H2 and H3. Such an insulator portion 135 can reduce the electric field strength in the direction of the adjacent unit cell 120 when a voltage is applied between the upper electrode 134 and the lower electrode 131. This is because the portion 201 weakens the electric field E1 indicated by the dotted line in FIG. 2(a). Therefore, it becomes possible to selectively and effectively collect only the carriers generated on the lower electrode 131.

[0018] Furthermore, the insulator portion 135 has a portion 202. The portion 202 is located closer to the principal surface P1 than the upper surface 132T of the interface layer 132. The portion 202 is located between heights H1 and H2. In a cross section perpendicular to the principal surface P1, the portion 202 is located between two interface layers 132 along a direction parallel to the principal surface P1 (e.g., the X direction). The insulator portion 135 separates the interface layers 132 of adjacent lower electrodes 131 so that they are not continuous. This configuration can reduce the intrusion of carriers from adjacent unit cells 120 through the interface layer 132, even when the electrical conductivity of the interface layer 132 is high. The interface layer 132 can block carrier injection in the film thickness direction, i.e., the Z direction in FIG. 2(a), but carriers can move freely horizontally of the interface layer 132, i.e., the X direction in FIG. 2(a), if the electrical conductivity of the interface layer 132 is high. That is, if the electrical conductivity of the interface layer 132 is high, leakage current between unit cells and crosstalk between unit cells may occur.

[0019] In this embodiment, a portion of the functional layer 133 can also be said to be surrounded by the insulator portion 135 in a plan view on a plane parallel to the principal surface P1. The portion of the functional layer 133 is a portion located on the lower electrode 131 between heights H2 and H3. This configuration can reduce crosstalk between one unit cell 120 and an adjacent unit cell 120.

[0020] Furthermore, if materials that greatly differ in refractive index are selected as materials for the functional layer 133 and the insulator portion 135, light that reaches the side surface of the insulator portion 135 can be reflected by the insulator portion 135 and collected on the lower electrode 131. In other words, by selecting the materials for the insulator portion 135 and the functional layer 133, the functional layer 133 surrounded by the insulator portion 135 can function as a light guide portion.

[0021] FIG. 7( a) is a schematic plan view illustrating the planar positional relationship between the lower electrode 131, the interface layer 132, and the insulator portion 135. The lower electrode 131 and the interface layer 132 are rectangular, with the interface layer 132 being larger than the lower electrode 131. The lower electrode 131 is enclosed by the outer edge of the interface layer 132. The insulator portion 135 is disposed at the boundary of the unit cells 120. When the unit cells 120 are arranged two-dimensionally, the insulator portion 135 has a lattice shape and surrounds each lower electrode 131. The outer edges of the lower electrode 131 and the insulator portion 135 may be located at the same position. In this embodiment, the outer edge of the insulator portion 135 is located at a distance from the outer edge of the lower electrode 131, taking into account manufacturing variations in the lower electrode 131 and the insulator portion 135. The distance can be set between 0.01 μm and 5.0 μm depending on the size of the unit cells 120. To reduce crosstalk, it is preferable to reduce this separation distance, preferably 0.01 μm or more and 0.1 μm or less. Furthermore, if the area of ​​the insulator portion 135 is large, the contact area between the functional layer 133 and the interface layer 132 decreases, which may cause peeling of the functional layer 133. It is preferable to set the area ratio of the insulator portion 135 and the functional layer 133 to the area of ​​the unit cell 120, taking into consideration the materials of the functional layer 133 and the interface layer 132. The size of the insulator portion 135 is in the range of 0.1 nm to 20 μm. The insulator portion 135 may be thinner than the functional layer 133. When the functional layer 133 is composed of quantum dots, the size of the insulator portion 135 may be approximately the same as that of nanoparticles (with an average particle diameter of 0.5 nm or more and less than 100 nm). Also, as shown in FIG. 7(a), the insulator portion 135 is shown as one lattice-like region and has a continuous shape, but it may be partially cut and exist intermittently.

[0022] FIG. 2(b) is a cross-sectional view showing a modified example of the semiconductor device of this embodiment. In FIG. 2(b), the insulator portion 135 has a narrower width and a portion 203. First, in FIG. 2(a), the insulator portion 135 has a width W1. However, in FIG. 2(b), the insulator portion 135 has a width W2, which is smaller than the width W1. Here, the widths W1 and W2 are the maximum widths of the respective insulator portions 135. The narrow width of the insulator portion 135 increases the area of ​​the functional layer 133, thereby improving sensitivity. Next, the portion 203 of the insulator portion 135 is located closer to the main surface P1 than the height H1 and is located between the height H1 and the main surface P1. The presence of the portion 203 enables electrical isolation between the unit cells 120. Note that the depth of the portion 203 from the height H1 can be changed as appropriate.

[0023] (Materials for the semiconductor device of the first embodiment) The materials of the semiconductor device of the first embodiment will be described. First, the functional layer 133 will be described. The functional layer 133 in this embodiment is a photoelectric conversion film. Its material may be an inorganic material or an organic material. For example, the photoelectric conversion film can be made of amorphous silicon, an organic semiconductor, or quantum dots, which are an aggregate of nanoparticles of a compound semiconductor material. Suitable organic semiconductors include, for example, fullerene (C60), coumarin 6 (C6), rhodamine 6G (R6G), quinacridone, phthalocyanine, and naphthalocyanine. In this embodiment, quantum dots, which are an aggregate of nanoparticles of a compound semiconductor material, will be used as an example.

[0024] The quantum dots constituting the functional layer 133 are made of nanoparticles (with an average particle diameter of 0.5 nm or more and less than 100 nm). Examples of nanoparticle materials include common semiconductor crystals, such as Group IV semiconductors, III-V and II-VI compound semiconductors, and compound semiconductors consisting of a combination of three or more of Group II, III, IV, V, and VI elements. Specific examples include semiconductor materials with relatively narrow band gaps, such as PbS, PbSe, PbTe, InN, InAs, InP, InSb, InAs, InGaAs, CdS, CdSe, CdTe, Ge, CuInS, CuInSe, CuInGaSe, and Si. These are also called semiconductor quantum dots. Quantum dots may contain at least one of these semiconductor quantum dot materials. Quantum dots may have a core-shell structure, with a semiconductor quantum dot material as the core and the semiconductor quantum dot material covered with a coating compound. Among the above, the semiconductor quantum dot material is preferably PbS or PbSe because of the ease of quantum dot synthesis. The average particle size of the quantum dots is preferably 2 nm to 15 nm. A transmission electron microscope is used to measure the particle size of the quantum dots. If the average particle size of the quantum dots is 15 nm or less, it is possible to control the band gap due to the quantum size effect. By setting the average particle size of the quantum dots to 2 nm or more, it is possible to easily control the crystal growth of the quantum dots during synthesis. There are no particular limitations on the manufacturing method of the functional layer 133, which is composed of an aggregate of nanoparticles as quantum dots. The film thickness of the functional layer 133 is not particularly limited, but is preferably 10 nm or more, and more preferably 50 nm or more, from the viewpoint of obtaining high electrical conductivity. Furthermore, from the viewpoint of ease of manufacturing, the film thickness of the functional layer 133 is preferably 800 nm or less.

[0025] Next, the material of the interface layer 132 will be described. In this embodiment, the interface layer 132 is also an effective film for suppressing peeling of the functional layer 133, which occurs due to poor wettability between the lower electrode 131 and the functional layer 133, or between the separation region 130 and the functional layer 133. In the portion without the interface layer 132, an insulator portion 135 can be provided at the interface between the lower electrode 131 and the functional layer 133, or between the separation region 130 and the functional layer 133. The interface layer 132 can be of two types: a layer that blocks electrons and conducts only holes (electron-blocking interface layer) and a layer that blocks holes and conducts only electrons (hole-blocking interface layer). For example, an electron-blocking interface layer can be provided for an electrode (positive electrode) that collects holes, and a hole-blocking interface layer can be provided for an electrode (negative electrode) that collects electrons. In the following description, the functional layer 133 is assumed to be a photoelectric conversion layer that performs photoelectric conversion.

[0026] The electron blocking interface layer will now be described. A material for the electron blocking interface layer is preferably one that can efficiently transport holes generated in the photoelectric conversion layer to the positive electrode. The material preferably has properties such as high hole mobility, high electrical conductivity, a small hole injection barrier between the positive electrode and the electron blocking interface layer, and a small hole injection barrier from the photoelectric conversion layer to the electron blocking interface layer. Furthermore, when light is introduced into the photoelectric conversion layer through the electron blocking interface layer, a highly transparent material is preferably used as the material for the electron blocking interface layer. When visible light is introduced into the photoelectric conversion layer, a transparent electron blocking interface layer material is preferably one that has a transmittance of transmitted visible light of typically 60% or more, preferably 80% or more. From this perspective, examples of the electron blocking interface layer material include P-type semiconductor materials such as inorganic semiconductors such as molybdenum oxide (MoO3) and nickel oxide (NiO2). On the other hand, the function required of the hole-blocking interface layer is to block holes separated from the photoelectric conversion layer and transport electrons to the negative electrode. Therefore, in the above description of the hole-blocking interface layer, the positive electrode is replaced with the negative electrode, the P-type semiconductor with an N-type semiconductor, and the holes with electrons. It is also possible to effectively utilize a configuration in which light is irradiated from the negative electrode side or light reflected from the negative electrode side, in which case high transmittance is also required. From this perspective, suitable examples of hole-blocking interface layer materials include N-type semiconductor materials such as inorganic semiconductors such as titanium oxide (TiO2) and zinc oxide (ZnO), and N-type semiconductor materials such as fullerene C60.

[0027] The interface layer 132 is formed to a thickness of approximately 1 nm to 100 nm. The injection of charges into the interface layer 132 can be controlled by applying an electric field in the film thickness direction, but charges can move freely in the direction horizontal to the film thickness. If the electrical conductivity of the interface layer 132 as a film is high, this can occur as leakage current or crosstalk between unit cells.

[0028] Next, the materials for the lower electrode 131 and the upper electrode 134 will be described. The lower electrode 131 and the upper electrode 134 can be formed from any conductive material. Examples of materials for the electrodes include metals such as platinum, gold, silver, aluminum, chromium, nickel, copper, titanium, and magnesium, alloys thereof, metal oxides such as indium oxide and tin oxide, and composite oxides thereof (e.g., ITO and IZO). Examples of materials for the electrodes include conductive particles such as carbon black, fullerene, carbon nanotubes, and graphene, or conductive composite materials in which these particles are dispersed in a matrix such as a polymer binder. The electrode materials may be used alone or in any combination and ratio of two or more. In a photoelectric conversion device or a light-emitting device, at least one pair (two) of electrodes is provided, and a functional layer 133 is provided between the pair of electrodes. In this case, it is preferable that at least one of the pair of electrodes is transparent. This is because the electrode transmits light absorbed by the functional layer 133 or transmits light emitted by the functional layer 133. The electrode has the function of collecting electrons and holes generated inside the functional layer 133. Therefore, it is preferable to use, as the constituent material of the electrode, a constituent material suitable for collecting electrons and holes from among the materials described above. Examples of electrode materials suitable for collecting holes include materials with a high work function such as Au and ITO. On the other hand, examples of electrode materials suitable for collecting electrons include materials with a low work function such as Al. There are no particular limitations on the thickness of the electrode, and it is determined appropriately taking into account the material used and the required conductivity, transparency, etc., but it is usually about 10 nm to 10 μm.

[0029] The material of the insulator portion 135 will now be described. The insulator portion 135 is made of a material that maintains electrical insulation. Furthermore, the material of the insulator portion 135 preferably has a lower density than the surrounding material to reduce the optical refractive index. By using a material with a low refractive index, the insulator portion 135 can function as a wall of the light guide portion. The insulator portion 135 preferably contains an insulating gas or air, but it may also be a vaporized functional layer. For example, it may contain vaporized nanoparticles or a vaporized solvent that dispersed the nanoparticles. The insulator portion 135 may be a vacuum or may be filled with a gas such as nitrogen, water vapor, helium, neon, argon, krypton, xenon, or radon. Alternatively, the insulator portion 135 may be filled with an insulating liquid such as an organic solvent, an electrolyte, or an ionic liquid. The insulator portion 135 may also be a mixture of these.

[0030] (Method for manufacturing the semiconductor device according to the first embodiment) A method for manufacturing a semiconductor device according to the first embodiment will now be described. Figures 8(a) to 8(d) are cross-sectional views showing the method for manufacturing a semiconductor device. In Figures 8(a) to 8(d), the same reference numerals as those used for the processed components in Figure 1 may be used for the components before processing.

[0031] The process shown in FIG. 8(a) will be described. First, a substrate 100 on which a wiring structure 106 is formed is prepared. Then, a film that will become an interface layer 132 is formed on the wiring structure 106. First, the process of preparing the substrate 100 on which the wiring structure 106 is formed will be described. An element isolation region 113 and a transistor 101 are formed in the substrate 100, which is a semiconductor substrate. The element isolation region 113 has, for example, an STI (Shallow Trench Isolation) structure. The transistor 101 is, for example, an N-type MOS transistor, and is composed of a gate electrode 104, a gate insulating film 103, a source / drain region 102, and a source / drain region 105. The source / drain regions 102 and 105 are composed of N-type semiconductor regions.

[0032] Next, a wiring structure 106 is formed on the substrate 100. The contact plugs 107, via plugs 109, and via plugs 111 are made of a material selected from metals such as Al, Cu, W, Ti, and TiN, and in this embodiment, may have a layered structure of titanium, titanium nitride, and tungsten. The wiring layers 108 and 110 are made of a material selected from metals such as Al, Cu, W, Ti, and TiN, and in this embodiment, may have a layered structure of tantalum and copper. The insulating film 112 is made of a film such as silicon oxide or silicon nitride. Next, a lower electrode 131 made of copper or aluminum is formed on the via plug 111. The lower electrode 131 is formed to a thickness of approximately 10 nm to 500 nm. The insulating film 112 may be formed after the lower electrode 131 is formed. In this case, a planarization process is performed so that the upper surfaces of the insulating film 112 and the lower electrode 131 are flush with each other at a height H1. The planarization process is performed by etching or CMP (Chemical Mechanical Polishing). A general semiconductor process can be applied to the manufacturing method of these.

[0033] Thereafter, a film that will become the interface layer 132 is formed on the insulating film 112 and the lower electrode 131. The film that will become the interface layer 132 is made of the above-mentioned material and is formed, for example, by vapor deposition or sputtering. The film that will become the interface layer 132 is deposited to a thickness of approximately 1 nm to 100 nm. If the film thickness of the interface layer 132 is thin, the voltage applied to the functional layer 133 can be reduced. However, if the film thickness of the interface layer 132 is thick, the passage of electrons or holes due to the tunneling effect can be reduced and film defects such as pinholes can be avoided. For example, by making the film thickness of the interface layer 132 thicker than the unevenness of the surface of the lower electrode 131, defects in the interface layer 132 can be reduced. The film thickness of the interface layer 132 can be appropriately set taking these points into consideration. In this way, the configuration shown in FIG. 8(a) is completed.

[0034] 8(b), a portion of the interface layer 132 is removed. A resist mask is formed by photolithography on the film that will become the interface layer 132, and the resist mask is used to perform etching until a portion of the surface of the insulating film 112 is exposed, thereby removing the interface layer 132.

[0035] Next, as shown in FIG. 8( c), a functional layer 133 is formed. Specifically, quantum dots, which are an aggregate of compound semiconductor nanoparticles, are deposited on the entire surface to form the functional layer 133. The functional layer 133 is formed so as to cover the insulating film 112 and the interface layer 132 that constitute the separation region 130. The functional layer 133 is formed on the lower electrode 131 and the separation region 130 other than the lower electrode 131, but is formed on the interface layer 132 on the lower electrode 131 and part of the separation region 130. Because the interface layer 132 has been removed above the separation region 130, part of the functional layer 133 is not provided. In such regions without the functional layer 133, an insulator portion 135 is formed, as described above.

[0036] Here, a method for forming the insulator portion 135 will be described in detail. As described above, the insulator portion 135 can be formed by removing the interface layer 132. Regarding the method for removing the interface layer 132, for example, in a structure having a convex portion, if the interface layer 132 is formed using a vapor deposition method or a sputtering method, it is possible to form a portion on the side surface of the convex portion where the interface layer 132 is thin or where the interface layer 132 is not deposited. Furthermore, after the interface layer 132 is formed, a resist mask is formed by photolithography, and the interface layer 132 is etched using this resist mask, whereby the interface layer 132 can be removed.

[0037] The insulator portion 135 can also be formed by performing heat treatment on the functional layer 133. Furthermore, the insulator portion 135 can also be formed by performing heat treatment when forming the color filter layer 137, rather than on the functional layer 133. This is a method that utilizes the deformation of the functional layer 133 when heated. For example, if the functional layer 133 is made of a quantum dot material composed of an aggregate of nanoparticles, the linear expansion coefficient is approximately 1x10 -4 / K. The linear expansion coefficient of silicon in the substrate 100 is approximately 4×10 -6 / K, the linear expansion coefficient of the functional layer 133 is 25 times larger. By performing a heat treatment with the functional layer 133 formed on the substrate 100, the deformation of the functional layer 133 can be utilized to form the insulator portion 135.

[0038] Thereafter, the upper electrode 134 is formed. More specifically, ITO, IZO, ZnO, or the like is deposited on the functional layer 133 to form the upper electrode 134. Then, an insulating layer 136, a color filter layer 137, a planarizing layer 138, and a microlens layer 139 are formed in this order. These can be manufactured using methods commonly used for manufacturing semiconductor devices. In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0039] As described above, according to this embodiment, when a voltage is applied between the upper electrode 134 and the lower electrode 131, the electric field spreading to adjacent unit cells 120 can be alleviated. Furthermore, according to this embodiment, it is possible to selectively and effectively collect only carriers generated on the lower electrode 131. Furthermore, by having a configuration in which a portion of the interface layer 132 between adjacent lower electrodes 131 is removed, crosstalk due to carriers generated in adjacent unit cells 120 can be reduced. By providing the insulator portion 135 in a portion of the functional layer 133 between adjacent lower electrodes 131, crosstalk due to carriers generated in adjacent unit cells 120 can be reduced. Thus, the semiconductor device of this embodiment can reduce crosstalk. Furthermore, when the difference in refractive index between the functional layer 133 and the insulator portion 135 is large, light reaching the side surface of the insulator portion 135 can be reflected by the insulator portion 135 and collected on the lower electrode 131, thereby improving sensitivity.

[0040] (Second embodiment) A cross-sectional view of the semiconductor device of this embodiment is shown in Figure 3(a). Figure 3(a) is a cross-sectional view corresponding to Figure 2(a). Portions of the semiconductor device of this embodiment not shown in Figure 3(a) have the same configuration as in Figure 1. The following description will focus on the differences from the first embodiment.

[0041] The configuration in FIG. 3(a) differs from the configuration in FIG. 2(a) in that the widths of the insulator portions 135 are different and two insulator portions 135 are disposed between two lower electrodes 131. In addition, in FIG. 3(a), it can also be said that two insulator portions 135 are provided for one lower electrode 131. Specifically, one insulator portion 135 is disposed on each end of one lower electrode 131. With such a configuration, crosstalk between adjacent unit cells 120 can be reduced, as in FIG. 2(a).

[0042] A modified example of this embodiment is shown in Figure 3(b). This differs from the configuration of Figure 3(a) in that the insulator portion 135 has the portion 203 shown in Figure 2(b). This configuration also makes it possible to reduce crosstalk between adjacent unit cells 120, as in Figure 2(b).

[0043] (Third embodiment) FIG. 4(a) shows a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 4(a) is a schematic cross-sectional view corresponding to FIG. 2(a). Portions of the semiconductor device of this embodiment not shown in FIG. 4(a) have the same configuration as FIG. 2(a) and are similarly configured as shown in FIG. 1. In this embodiment, the structure of the isolation region 130 differs from that of the first embodiment. Specifically, the isolation region 130 of this embodiment is disposed between two lower electrodes 131 and on a portion of the lower electrode 131. The upper surface 130T of the isolation region 130 is located farther from the main surface P1 than the upper surface 131T of the lower electrode 131. In FIG. 4(a), the upper surface 131T of the lower electrode 131 is located at height H1, the upper surface 132T of the interface layer 132 is located at height H6, and the upper surface 135T of the insulator portion 135 is located at height H6. The upper surface 130T of the isolation region 130 is located at height H5, which is between heights H1 and H6. That is, the lower electrode 131 and the isolation region 130 form unevenness on the upper surface.

[0044] The interface layer 132 is provided along the surface whose upper surface is uneven due to the lower electrode 131 and the separation region 130. The interface layer 132 can also be described as a film of uniform thickness, a film that follows the shape of the base, a conformal film, etc. The unevenness of the upper surface 132T of the interface layer 132 improves adhesion between the functional layer 133 and the interface layer 132 due to an anchor effect. In addition, the thickness of the functional layer 133 located on the lower electrode 131 can be increased, which can improve sensitivity.

[0045] The insulator portion 135 is disposed between the two lower electrodes 131 and has a portion 201 located above the upper surface 132T of the interface layer 132 disposed on the lower electrode 131. Even with the structure of Fig. 4(a), crosstalk can be reduced in the same way as in the first embodiment.

[0046] The insulator portion 135 is provided on the lower electrode 131. An interface layer 132 is disposed between the insulator portion 135 and the lower electrode 131. By disposing the insulator portion 135 on the interface layer 132 disposed on the lower electrode 131, it is possible to reduce the spread of the electric field and reduce crosstalk.

[0047] The positional relationship of each component in the configuration of FIG. 4(a) will be described. The upper surface 131T of the lower electrode 131 is located at height H1, and the upper surface 130T of the separation region 130 and the lower surface 132B of the interface layer 132 are located at height H5. The upper surface 135T of the insulator portion 135 and the upper surface 132T of the interface layer 132 are located at height H6. Height H5 is located between heights H6 and H1. The lower electrode 131, insulator portion 135, and interface layer 132 of FIG. 4(a) have a planar layout as shown in FIG. 7(b). The insulator portion 135 surrounds the lower electrode 131, and the interface layer 132 has a lattice pattern. Note that the insulator portion 135 is shown as a single region surrounding the lower electrode 131 and has a continuous shape, but it may be partially cut off and present intermittently.

[0048] Next, a modified example of this embodiment will be described using FIG. 4(b). The insulator portion 135 in FIG. 4(b) has a structure including both a portion 401 and a portion 402 corresponding to the insulator portion 135 shown in FIG. 4(a). The portion 401 is located between two lower electrodes 131, is located closer to the main surface P1 than the lower surface 132B of the interface layer 132 located in the isolation region 130, and is located farther from the main surface P1 than the upper surface 132T of the interface layer 132 located in the isolation region 130. This configuration also enables crosstalk reduction. In other words, crosstalk reduction is possible by a configuration including at least one of the portion 401 and the portion 402. The lower electrode 131, the insulator portion 135, and the interface layer 132 in FIG. 4(b) have a planar layout as shown in FIG. 7(c). The insulator portion 135, which is portion 402, surrounds the lower electrode 131, the insulator portion 135, which is portion 401, extends across multiple unit cells 120 in the Y direction, and the interface layer 132 is ladder-shaped. Note that a portion of the insulator portion 135 is shown as one region along the Y direction and has a continuous shape, but it may be partially cut and exist intermittently. Also, a portion of the insulator portion 135 is shown as one region surrounding the lower electrode 131 and has a continuous shape, but it may be partially cut and exist intermittently.

[0049] (Fourth embodiment) FIG. 5(a) shows a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 5(a) is a schematic cross-sectional view corresponding to FIG. 4(a). Portions of the semiconductor device of this embodiment not shown in FIG. 5(a) have the same configuration as FIG. 1, as in FIG. 4(a). In this embodiment, the isolation region 130 and the lower electrode 131 form an uneven surface, as in the fourth embodiment. However, unlike the fourth embodiment, in which the isolation region 130 forms the convex portion, the lower electrode 131 forms the convex portion. Specifically, the upper surface 130T of the isolation region 130 and the lower surface 131B of the lower electrode 131 are located at height H501, and the upper surface 131T of the lower electrode 131 is located at height H502. The lower surface 132B of the interface layer 132, located above the isolation region 130, is located at height H501, and the portion located above the lower electrode 131 is located at height H502. The upper surface 132T of the interface layer 132 located above the lower electrode 131 is located at height H503.

[0050] The insulator portion 135 is disposed on the isolation region 130 and on the side surface of the lower electrode 131. The interface layer 132 is located between the insulator portion 135 and the lower electrode 131. That is, the insulator portion 135 is disposed along the side surface of the lower electrode 131, more specifically, along the interface layer 132 along the side surface of the lower electrode 131. The insulator portion 135 has a longitudinal shape in a direction along the side surface of the lower electrode 131, for example, in the Z direction. The insulator portion 135 can reduce the electric field that spreads from the side surface of the lower electrode 131 to adjacent unit cells 120 via the interface layer 132, thereby reducing crosstalk. Furthermore, even if there is a defect in the interface layer 132 on the side surface of the lower electrode 131, the insulator portion 135 covers the side surface of the interface layer 132, thereby reducing leakage from the lower electrode 131 to the functional layer 133. In this embodiment, the width of the insulator portion 135 is about 10 nm to 1 μm, and the height of the insulator portion 135 is about 10 nm to 1 μm.

[0051] 9(a) and 9(b) are cross-sectional views illustrating the method for manufacturing the semiconductor device of this embodiment. In the following description, the same steps as those in the manufacturing method described in the first embodiment will not be described.

[0052] First, in the step shown in FIG. 9(a), a wiring structure 106 is formed on a substrate 100 on which elements such as transistors are formed. Then, a lower electrode 131 is formed on the upper surface of an insulating film 112. An interface layer 132 is formed with a uniform thickness to cover the uneven portion formed by the isolation region 130 and the lower electrode 131. The thickness of the lower electrode 131 may be 10 nm or more and 10 μm or less. Here, by forming the lower electrode 131 to a thickness of 10 nm or more and 500 nm or less, unevenness is reduced and the formation of the interface layer 132 becomes easier. In this embodiment, the thickness is selected from the range of 100 nm or more and 500 nm or less.

[0053] Next, as shown in FIG. 9( b), a functional layer 133 is formed on the interface layer 132. The functional layer 133 is formed on the lower electrode 131 and on the separation region 130. An insulator portion 135 may be formed on the side of the lower electrode 131, across the interface layer 132. The insulator portion 135 may be formed by utilizing the characteristic that the interface layer 132 is less likely to form on the side of the lower electrode 131. Alternatively, the insulator portion 135 may be formed by a heat treatment. In the structure with the concave and convex portions of this embodiment, the thickness of the functional layer 133 disposed on the portions other than the concave portion of the lower electrode 131 is greater than that of the functional layer 133 disposed on the convex portion of the lower electrode 131. In such a structure in which the thickness of the functional layer 133 varies, the functional layer 133 undergoes large deformation due to thermal expansion and contraction, making it easy to form the insulator portion 135. The size of the insulator portion 135 can be adjusted by adjusting the deformation amount of the functional layer 133 upon heating and the height of the lower electrode 131. The width of the insulator portion 135 can be reduced by setting the heat treatment conditions so that the amount of deformation of the functional layer 133 during heating is reduced. The width of the insulator portion 135 can be increased by setting the heat treatment conditions so that the amount of deformation of the functional layer 133 during heating is increased.

[0054] Furthermore, the amount of deformation of the functional layer 133 when heated also depends on the film thickness of the functional layer 133. By reducing the film thickness of the functional layer 133, the width of the insulator portion 135 can be reduced, and by increasing the film thickness of the functional layer 133, the width of the insulator portion 135 can be increased. In other words, the width of the insulator portion 135 can be appropriately set depending on the film thickness and arrangement of the lower electrode 131 and the separation region 130. Furthermore, the height of the insulator portion 135 depends on the length of the side surface of the lower electrode 131, and by reducing the height of the lower electrode 131, the height of the insulator portion 135 can be reduced. If the height of the lower electrode 131 is high, the height of the insulator portion 135 also increases.

[0055] The insulator portion 135 may be formed by other methods as described in the first embodiment. Thereafter, the manufacturing method described in the first embodiment is carried out to form the semiconductor device of this embodiment.

[0056] Next, a modified example of the semiconductor device of this embodiment will be described. FIG. 5(b) is a cross-sectional view showing a modified example of the semiconductor device of this embodiment. FIG. 5(b) is a cross-sectional view corresponding to FIG. 5(a). Portions of the semiconductor device of this embodiment not shown in FIG. 5(b) have the same configuration as FIG. 1, as in FIG. 5(a). The insulator portion 135 of FIG. 5(b) includes a portion 504 corresponding to the insulator portion 135 shown in FIG. 5(a) and a portion 505 having a longitudinal shape along the X direction between the two portions 504. The portion 505 is disposed between the interface layer 132 on the separation region 130 between the two lower electrodes 131 and the functional layer 133. The portion 505 is configured so that the portion 504 of a unit cell is continuous and integrated with the portion 504 of an adjacent unit cell. The presence of the portion 505 reduces leakage from the functional layer 133 to the wiring structure 106. Furthermore, by making the refractive index of the portion 505 lower than that of the functional layer 133, leakage light that is not absorbed by the functional layer 133 is reflected at the interface between the portion 505 and the functional layer 133, thereby suppressing noise and malfunctions caused by light entering the substrate 100 from the wiring structure 106. Furthermore, the insulator portion 135 can absorb thermal deformation of the functional layer 133 due to temperature changes in the usage environment, thereby improving reliability.

[0057] Next, a modified example of the semiconductor device of this embodiment will be described. FIG. 5(c) is a cross-sectional view showing a modified example of the semiconductor device of this embodiment. FIG. 5(c) is a cross-sectional view corresponding to FIG. 5(b). Portions of the semiconductor device of this embodiment not shown in FIG. 5(c) are assumed to have the same configuration as FIG. 1, as in FIG. 5(b). Here, the portion 504 of the insulator portion 135 in FIG. 5(c) is located at a height H506, where its upper surface 504T is higher than the height H503. In other words, the portion 504 is located farther from the main surface P1 than the upper surface 132T of the interface layer 132 located on the lower electrode 131. This configuration enables separation down to the functional layer 133, further reducing crosstalk. In FIG. 5(c), the insulator portion 135 includes the portion 505, but it may also include only the portion 504, as in FIG. 5(a).

[0058] According to this embodiment, because the lower electrode 131 is a convex portion, the film thickness of the functional layer 133 above the lower electrode 131 is thinner than the film thickness of the functional layer 133 above the separation region 130. The thinner film thickness of the functional layer 133 concentrates the voltage applied between the lower electrode 131 and the upper electrode 134, strengthening the electric field. This allows carriers generated on the lower electrode 131 to be selectively and quickly collected. By disposing the insulator portion 135 on the side of the lower electrode 131, the electric field strength toward the adjacent unit cell 120 can be reduced. Even if the electrical conductivity of the interface layer 132 or the functional layer 133 is high, crosstalk can be reduced without collecting carriers generated in the adjacent unit cell 120. Furthermore, even if a defect occurs in the interface layer 132 disposed on the side of the lower electrode 131, the insulator portion 135 prevents the lower electrode 131 and the functional layer 133 from coming into direct contact with each other, thereby reducing leakage current to the functional layer 133.

[0059] (Fifth embodiment) FIG. 6(a) shows a schematic cross-sectional view of the semiconductor device of this embodiment. FIG. 6(a) is a schematic cross-sectional view corresponding to FIG. 4(a). Portions of the semiconductor device of this embodiment not shown in FIG. 6(a) have the same configuration as FIG. 1, as in FIG. 4(a). In FIG. 6(a), the isolation region 130 forms a convex portion, as in FIG. 4(a), but the difference is that the isolation region 130 is not disposed on the lower electrode 131. This configuration also makes it possible to reduce crosstalk to adjacent unit cells 120.

[0060] A modified example of the semiconductor device of this embodiment will be described with reference to FIG. 6(b). FIG. 6(b) is a schematic cross-sectional view corresponding to FIG. 6(a). Portions of the semiconductor device of this embodiment not shown in FIG. 6(b) have the same configuration as in FIG. 6(a) and are configured as shown in FIG. 1. The insulator portion 135 of FIG. 6(b) has both a portion 601 corresponding to the insulator portion 135 shown in FIG. 6(a) and a portion 602 corresponding to the portion 401 shown in FIG. 4(c). Even with this structure, crosstalk can be reduced.

[0061] A modified example of the semiconductor device of this embodiment will be described with reference to FIG. 6(c). FIG. 6(c) is a cross-sectional view corresponding to FIG. 6(a). Portions of the semiconductor device of this embodiment not shown in FIG. 6(c) have the same configuration as FIG. 1, as in FIG. 6(a). The insulator portion 135 in FIG. 6(c) is disposed on the isolation region 130. The interface layer 132 is not formed on the upper surface 130T of the isolation region 130, which constitutes the convex portion, so the insulator portion 135 is in contact with the isolation region 130. The insulator portion 135 is disposed above the upper surface of the interface layer 132 disposed on the lower electrode 131. The interface layer 132 is also disposed between the insulator portion 135 and the lower electrode 131. This configuration also makes it possible to reduce crosstalk.

[0062] (Sixth embodiment) The semiconductor device as described above can be applied to a light detection system or a light emission system. When the semiconductor device is applied to a light detection system, the functional layer performs photoelectric conversion. In this case, the semiconductor device can also be called a photoelectric conversion device or an imaging device. When the semiconductor device is applied to a light detection system, the functional layer performs photoelectric conversion. In this case, the semiconductor device can also be called a photoelectric conversion device or an imaging device. The light detection system includes the semiconductor device and a signal processing unit that processes signals acquired by the semiconductor device. Furthermore, when the semiconductor device is applied to a light emission system, the functional layer emits light in response to an electrical signal. In this case, the semiconductor device can also be called a light emitting device or a display device. The light emission system includes the semiconductor device and a control unit that supplies a control signal to cause the semiconductor device to emit light.

[0063] The light detection system and the light emission system may be, for example, electronic devices. Examples of the electronic devices include cameras, computers, lighting, lighting fixtures, mobile terminals, displays, and in-vehicle display devices. In this embodiment, the light detection system refers to the imaging part of a camera, and the light emission system refers to the display part of a camera.

[0064] An example in which the semiconductor device is applied to a camera will be described using FIG. 10 . The semiconductor device is applied to at least one of an image capture device 1005 and a display device 1012. The lens unit 1001 is an imaging optical system that forms an optical image of a subject on the image capture device 1005, and includes a focus lens, a variable magnification lens, an aperture, etc. The drive of the focus lens position, variable magnification lens position, aperture opening diameter, etc. in the lens unit 1001 is controlled by the control unit 1009 via the lens drive unit 1002. The shutter 1003 is a mechanical shutter disposed between the lens unit 1001 and the image capture device 1005. The drive of the shutter 1003 is controlled by the control unit 1009 via the shutter drive unit 1004. The image capture device 1005 converts the optical image formed by the lens unit 1001 through multiple pixels into an image signal. The signal processing unit 1006 performs signal processing such as A / D conversion, demosaic processing, white balance adjustment processing, and encoding processing on the image signal output from the image capture device 1005. The control unit 1009 has, for example, memory (ROM, RAM) and a microprocessor (CPU), and realizes various functions of the camera by loading a program stored in the ROM into the RAM and having the CPU execute the program to control each unit. The functions realized by the control unit 1009 include autofocus (AF) and autoexposure (AE).

[0065] The memory unit 1008 is used by the control unit 1009 and signal processing unit 1006 to temporarily store image data and as a work area. The medium I / F unit 1010 is an interface for reading and writing to a recording medium 1011, which is, for example, a removable memory card. The display device 1012 displays captured images and various information about the camera. The display device 1012 is controlled by the control unit 1009 and displays images and various information. The operation unit 1007 is a user interface that includes a power switch, release button, menu button, etc., allowing the user to give instructions and make settings to the camera.

[0066] Next, the operation of the camera during shooting will be described. When the power is turned on, the camera enters a shooting standby state. The control unit 1009 starts video shooting processing and display processing to operate the display device 1012 as an electronic viewfinder. When a shooting preparation command (for example, half-pressing the release button on the operation unit 1007) is input in the shooting standby state, the control unit 1009 starts focus detection processing.

[0067] Then, the control unit 1009 determines the amount and direction of movement of the focus lens of the lens unit 1001 from the obtained defocus amount and direction, and drives the focus lens via the lens driving unit 1002 to adjust the focus of the imaging optical system. After driving, focus detection based on the contrast evaluation value may be further performed as necessary to fine-tune the focus lens position.

[0068] Thereafter, when an instruction to start shooting is input (for example, by fully pressing the release button), the control unit 1009 executes a shooting operation for recording, and the obtained image data is processed by the signal processing unit 1006 and stored in the memory unit 1008. The control unit 1009 then records the image data stored in the memory unit 1008 on the recording medium 1011 via the medium control I / F unit 1010. At this time, the control unit 1009 may also drive the display device 1012 to display the shot image. The control unit 1009 may also output the image data from an external I / F unit (not shown) to an external device such as a computer.

[0069] In this way, the semiconductor device of each embodiment can be mounted on a camera. In the present embodiment, a camera having both a light detection system and a light emission system is exemplified, but it may have only one of them.

[0070] Seventh embodiment 11(a) and 11(b) show an example in which the above-described semiconductor device is applied to an imaging system for a vehicle-mounted camera. In this embodiment, an imaging device 2010 corresponds to the above-described semiconductor device.

[0071] The imaging system 2000 includes an image processing unit 2030 that performs image processing on multiple pieces of image data acquired by the imaging device 2010, and a parallax calculation unit 2040 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the imaging system 2000. The imaging system 2000 also includes a distance measurement unit 2050 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 2060 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 2040 and the distance measurement unit 2050 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information includes information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 2060 may determine the possibility of a collision using any of these pieces of distance information. The distance information acquisition means may be realized by dedicated hardware or a software module. It may also be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0072] The imaging system 2000 is connected to a vehicle information acquisition device 2310 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 2000 is also connected to a control ECU 2410, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 2060. The imaging system 2000 is also connected to an alarm device 2420 that issues an alarm to the driver based on the determination result of the collision determination unit 2060. For example, if the collision determination unit 2060 determines that a collision is highly likely, the control ECU 2410 performs vehicle control to avoid a collision and mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The alarm device 2420 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, or vibrating the seat belt or steering wheel. The imaging system 2000 functions as a control unit that controls the operation of the vehicle as described above.

[0073] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 2000. Fig. 11(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 2510). A vehicle information acquisition device 2310, which serves as imaging control means, sends instructions to the imaging system 2000 or the imaging device 2010. This configuration can further improve the accuracy of distance measurement.

[0074] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0075] The moving object may also have a light emitting device using the semiconductor device described above, such as a lamp such as a tail lamp or an in-vehicle display device, and a control unit.

[0076] In the above-described embodiment, the substrate of the semiconductor device is a transistor using a single-crystal silicon wafer. However, the present invention is not limited to this, and the substrate may be a thin-film transistor having an active layer on an insulating surface of the substrate. Examples of semiconductor substrates include single-crystal silicon, amorphous silicon, non-single-crystal silicon such as microcrystalline silicon, and non-single-crystal oxide semiconductors such as indium zinc oxide and indium gallium zinc oxide. The transistor may be a thin-film transistor, also known as a TFT element.

[0077] It should be noted that the above-described embodiments are merely examples of specific implementations of the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. The present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0078] 100 boards 106 Wiring structure 130 Separation area 131 Lower electrode 132 Interface layer 133 Functional Layer 134 Upper electrode 135 Insulator section

Claims

1. a substrate having a major surface; an upper electrode disposed on a major surface of the substrate; a first lower electrode disposed between the substrate and the upper electrode; a second lower electrode disposed between the substrate and the upper electrode; an isolation region disposed between the substrate and the upper electrode; functional layers that are arranged between the first lower electrode and the upper electrode, between the second lower electrode and the upper electrode, and between the separation region and the upper electrode, and that perform light emission or photoelectric conversion; an interface layer having a portion disposed between the first lower electrode and the functional layer and a portion disposed between the second lower electrode and the functional layer, the functional layer includes a first insulator portion disposed between the first lower electrode and the second lower electrode and having a first portion disposed at a position farther from the main surface than an upper surface of a portion of the interface layer disposed between the first lower electrode and the functional layer; the first insulator portion is a gap, and the isolation region is not a gap; the separation region is disposed in a region between the first lower electrode and the second lower electrode in a plan view with respect to the principal surface, and the functional layer is continuously disposed in the region between the first lower electrode and the second lower electrode; A semiconductor device characterized in that the first insulator portion has a second portion located closer to the main surface than the upper surface of a portion of the interface layer arranged between the first lower electrode and the functional layer.

2. The semiconductor device according to claim 1 , wherein the functional layer is disposed between the first lower electrode and the second lower electrode.

3. a substrate having a major surface; an upper electrode disposed on a major surface of the substrate; a first lower electrode disposed between the substrate and the upper electrode; a second lower electrode disposed between the substrate and the upper electrode; an isolation region disposed between the substrate and the upper electrode; functional layers that are arranged between the first lower electrode and the upper electrode, between the second lower electrode and the upper electrode, and between the separation region and the upper electrode, and that perform light emission or photoelectric conversion; an interface layer having a portion disposed between the first lower electrode and the functional layer and a portion disposed between the second lower electrode and the functional layer, the functional layer includes a first insulator portion disposed between the first lower electrode and the second lower electrode and having a first portion disposed at a position farther from the main surface than an upper surface of a portion of the interface layer disposed between the first lower electrode and the functional layer; the first insulator portion is a gap, and the isolation region is not a gap; the separation region is disposed in a region between the first lower electrode and the second lower electrode in a plan view with respect to the principal surface, and the functional layer is continuously disposed in the region between the first lower electrode and the second lower electrode; The semiconductor device is characterized in that the isolation region is disposed between the first lower electrode and the second lower electrode.

4. 4. The semiconductor device according to claim 3, wherein the first insulator portion has a second portion located closer to the main surface than the upper surface of a portion of the interface layer arranged between the first lower electrode and the functional layer.

5. 5. The semiconductor device according to claim 1, wherein the first insulator portion has a third portion located closer to the main surface than an upper surface of the first lower electrode.

6. 4. The semiconductor device according to claim 1, wherein the first insulating portion is in contact with a side surface of the first lower electrode.

7. A semiconductor device as described in any one of claims 1 to 6, characterized in that the functional layer further has a second insulator portion, the second insulator portion being arranged between the first insulator portion and the second lower electrode, being located above the upper surface of the portion of the interface layer arranged between the first lower electrode and the functional layer, and having a first portion surrounded by the functional layer in a planar view along a plane parallel to the main surface.

8. 8. The semiconductor device according to claim 7, wherein the second insulating portion is a gap.

9. 4. The semiconductor device according to claim 1, wherein the distance between the upper surface of the isolation region and the main surface is the same as the distance between the upper surface of the first lower electrode and the main surface.

10. 4. The semiconductor device according to claim 1, wherein a distance between an upper surface of the isolation region and the main surface is greater than a distance between an upper surface of the first lower electrode and the main surface.

11. 3. The semiconductor device according to claim 1, wherein a distance between an upper surface of the first lower electrode and the main surface is greater than a distance between an upper surface of the isolation region and the main surface.

12. a substrate having a major surface; an upper electrode disposed on a major surface of the substrate; a first lower electrode disposed between the substrate and the upper electrode; a second lower electrode disposed between the substrate and the upper electrode; an isolation region disposed between the substrate and the upper electrode; functional layers that are disposed between the first lower electrode and the upper electrode, between the second lower electrode and the upper electrode, and between the separation region and the upper electrode, and that perform light emission or photoelectric conversion; a semiconductor device having at least an interface layer disposed between an upper surface of the first lower electrode and the functional layer, the functional layer has a first insulator portion, the first insulator portion is a gap, and the isolation region is not a gap; the interface layer is located between the first lower electrode and the first insulator portion, the separation region is disposed in a region between the first lower electrode and the second lower electrode in a plan view with respect to the principal surface, and the functional layer is continuously disposed in the region between the first lower electrode and the second lower electrode; A semiconductor device characterized in that the first insulator portion has a second portion located closer to the main surface than the upper surface of a portion of the interface layer arranged between the first lower electrode and the functional layer.

13. The semiconductor device according to claim 12 , wherein the functional layer is disposed between the first lower electrode and the second lower electrode.

14. a substrate having a major surface; an upper electrode disposed on a major surface of the substrate; a first lower electrode disposed between the substrate and the upper electrode; a second lower electrode disposed between the substrate and the upper electrode; an isolation region disposed between the substrate and the upper electrode; functional layers that are disposed between the first lower electrode and the upper electrode, between the second lower electrode and the upper electrode, and between the separation region and the upper electrode, and that perform light emission or photoelectric conversion; a semiconductor device having at least an interface layer disposed between an upper surface of the first lower electrode and the functional layer, the functional layer has a first insulator portion, the first insulator portion is a gap, and the isolation region is not a gap; the interface layer is located between the first lower electrode and the first insulator portion, In a plan view of the main surface, the separation region is disposed in a region between the first lower electrode and the second lower electrode, and the functional layer is continuously disposed in the region between the first lower electrode and the second lower electrode. The semiconductor device is characterized in that the isolation region is disposed between the first lower electrode and the second lower electrode.

15. 15. The semiconductor device according to claim 14, wherein a distance between an upper surface of the isolation region and the main surface is greater than a distance between an upper surface of the first lower electrode and the main surface.

16. 14. The semiconductor device according to claim 12, wherein a distance between an upper surface of the first lower electrode and the main surface is greater than a distance between an upper surface of the isolation region and the main surface.

17. a distance between an upper surface of the second lower electrode and the main surface is greater than a distance between an upper surface of the isolation region and the main surface; the interface layer is continuously disposed from the top surface of the first lower electrode to the side surface of the first lower electrode, the top surface of the isolation region, the side surface of the second lower electrode, and the top surface of the second lower electrode; 17. The semiconductor device according to claim 16, wherein the first insulator portion is in contact with the interface layer and is arranged along a side surface of the first lower electrode, a side surface of the second lower electrode, and an upper surface of the isolation region.

18. 16. The semiconductor device according to claim 15, wherein the first insulator portion is disposed on the first lower electrode in a plan view relative to the main surface.

19. the interface layer is disposed between the top surface of the separation region and the functional layer; 16. The semiconductor device according to claim 15, wherein a distance between an upper surface of the interface layer disposed in the isolation region and the main surface is smaller than a distance between an upper surface of the first insulator portion and the main surface.

20. a portion of the isolation region is located on a portion of the first bottom electrode and a portion of the second bottom electrode; 16. The semiconductor device according to claim 15, wherein the interface layer is disposed between the first insulator and an upper surface of the first lower electrode, and between the first insulator and a portion of the isolation region.

21. 21. The semiconductor device according to claim 1, wherein the gap contains a vacuum, air, or a vaporized portion of the constituent elements of the functional layer.

22. 22. The semiconductor device according to claim 1, wherein the interface layer is a carrier injection blocking layer capable of restricting one-way transfer of charges between the first lower electrode and the functional layer.

23. 23. The semiconductor device according to claim 1, wherein the substrate has a transistor electrically connected to the first lower electrode.

24. 24. The semiconductor device according to claim 1, wherein the functional layer is a photoelectric conversion layer made of an organic material.

25. 25. The semiconductor device according to claim 1, wherein the functional layer is a photoelectric conversion layer made of quantum dots including an aggregate of a plurality of nanoparticles.

26. 26. The semiconductor device according to claim 25, wherein the aggregate of the plurality of nanoparticles contains any one of PbS, PbSe, PbTe, InP, InAs, CdS, CdSe, and CdTe.

27. 27. The semiconductor device according to claim 1, The functional layer performs photoelectric conversion, a signal processing unit that processes a signal acquired by the semiconductor device.

28. 28. The semiconductor device according to claim 1, The functional layer performs photoelectric conversion, a signal processing unit that processes the signal acquired by the semiconductor device.

29. 24. The semiconductor device according to claim 1, wherein the functional layer is made of an organic material and emits light.

30. a semiconductor device according to claim 29; a control unit that supplies a control signal for causing the semiconductor device to emit light.

31. a semiconductor device according to claim 29; a control unit that supplies a control signal for causing the semiconductor device to emit light.

Images