Isolation amplifier and abnormal condition detection device

Abstract

To provide an isolation amplifier and an anomaly state detection device that convey the occurrence of an abnormal state quickly.SOLUTION: An isolation amplifier 1 includes: a primary circuit 10 provided with a ΔΣADC for converting an input signal into a digital signal and an encoder; an abnormality detection circuit for detecting abnormality having occurred to the input signal; an isolation unit for conveying the output of the encoder and a detection signal to a secondary circuit 20 in the insulated state; and an abnormal input detection output circuit provided in the secondary circuit, having a decoder and a low-pass filter receiving the output and the detection signal of the encoder and performing decode processing, and changing the output signal on the basis of an output circuit for generating an output signal and the detection signal. The input signal and the output signal are a pair of differential signals. The abnormal input detection output circuit inputs the detection signal from the isolation unit without passing through the low-pass filter, and changes the levels of both of the differential signals being the output signals by the same predetermined level during the period in which an abnormality occurs due to the detection signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] An embodiment of the present invention relates to an isolation amplifier and an abnormal state detection device. [Background technology]

[0002] Isolation amplifiers have traditionally been used as devices that provide both electrical isolation and signal transmission. Isolation amplifiers are widely used in a variety of applications, including industrial, communications, consumer, and automotive fields. For example, they are used for data transmission between a motor driven by a high power supply voltage and current and the MPU (microprocessor unit) that controls the motor. For example, isolation amplifiers are used to realize current sensors and voltage sensors that detect high voltages and currents in the target circuit.

[0003] However, an abnormality may occur in the circuit being detected, causing an excessive input to the isolation amplifier. In this case, from the perspective of protecting the entire system, the isolation amplifier must notify the occurrence of the abnormality in a short time. However, the transmission speed of the data transmission path of the isolation amplifier is relatively slow, and it takes a relatively long time to notify the abnormality, such as an excessive input.

[0004] One possible solution is to provide a transmission path separate from the isolation amplifier's normal data transmission path to transmit the abnormal state, but this would require a new dedicated pin for the transmission path. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-160096 Summary of the Invention [Problem to be solved by the invention]

[0006] The embodiments aim to provide an isolation amplifier and an abnormal state detection device that can transmit the occurrence of an abnormal state at high speed. [Means for solving the problem]

[0007] An isolation amplifier according to an embodiment includes a primary circuit having an analog-to-digital conversion circuit that converts an input signal provided from a device to be detected into a digital signal and an encoder that encodes and outputs the output of the analog-to-digital conversion circuit; an abnormality detection circuit that is provided in the primary circuit and detects an abnormality that occurs in the input signal and generates a detection signal; an isolation unit that transmits the output of the encoder and the detection signal to the secondary circuit while isolating the primary circuit from the secondary circuit; an output circuit that is provided in the secondary circuit and includes a decoder that receives the output of the encoder and the detection signal transmitted by the isolation unit and performs a decoding process corresponding to the encoding process, and generates an output signal corresponding to the input signal; and an abnormal input detection output circuit that, based on the detection signal, changes the output signal of the output circuit in accordance with a predetermined rule to produce the output signal of the secondary circuit, wherein the output circuit includes a digital-to-analog conversion circuit that converts the output of the decoder into an analog signal, and a low-pass filter that limits the high frequencies of the output of the digital-to-analog conversion circuit to generate the output signal, the input signal and the output signal being a pair of differential signals, and the abnormal input detection output circuit inputs the detection signal transmitted from the isolation unit without passing through the low-pass filter, detects that an abnormality has occurred from the input detection signal, and changes the levels of both of the pair of differential signals, which are the output signals, by the same predetermined level during the period in which the detection signal indicates that an abnormality has occurred. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. [Figure 2] FIG. 3 is a block diagram showing a specific example of the configuration of an isolation section 30. [Figure 3] FIG. 3 is a block diagram showing a specific example of the configuration of an isolation section 30. [Figure 4] FIG. 3 is a block diagram showing a specific example of the configuration of an isolation section 30. [Figure 5] 2 is a circuit diagram showing an example of a specific configuration of the converting circuit 50 shown in FIG. 1. FIG. [Figure 6] FIG. 2 is a circuit diagram showing an example of a specific configuration of an LPF 23 and an abnormal input detection output circuit 26. [Figure 7] It shows waveforms of input / output, etc., with time on the horizontal axis and voltage on the vertical axis. [Figure 8] FIG. [Figure 9] FIG. 10 is a block diagram showing a second embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram showing an example of a specific configuration of the abnormal input detection output circuit 27 of FIG. 9. [Figure 11] It shows waveforms of input / output, etc., with time on the horizontal axis and voltage on the vertical axis. [Figure 12] FIG. 10 is a block diagram showing a third embodiment of the present invention. [Figure 13] 13 is a circuit diagram showing an example of a specific configuration of a mixer 62 and an external circuit 80 in FIG. 12. [Figure 14] 10 is a timing chart for explaining the operation of the third embodiment. [Figure 15] FIG. 10 is a block diagram showing an example of a specific configuration of a mixer employed in a fourth embodiment of the present invention. [Figure 16] 10 is a timing chart for explaining the operation of the fourth embodiment. [Figure 17] FIG. 13 is a block diagram showing an example of a specific configuration of a mixer employed in a fifth embodiment of the present invention. [Figure 18] 10 is a timing chart for explaining the operation of the fifth embodiment. [Figure 19] FIG. 13 is a block diagram showing an example of a specific configuration of a mixer employed in a sixth embodiment of the present invention. [Figure 20]10 is a timing chart for explaining the operation of the sixth embodiment. [Figure 21] FIG. 13 is a block diagram showing an example of a specific configuration of a mixer employed in a seventh embodiment of the present invention. [Figure 22] 13 is a timing chart for explaining the operation of the seventh embodiment. [Figure 23] FIG. 13 is a block diagram showing an example of a specific configuration of a mixer employed in an eighth embodiment of the present invention. [Figure 24] FIG. 24 is a circuit diagram showing an example of a specific configuration of a pulse detector 87 in FIG. 23. [Figure 25] 4 is a timing chart for explaining generation of a clock MCLK and output data MDAT in the isolation amplifier 8. [Figure 26] 4 is a timing chart for explaining the operation of the pulse detector 87. [Figure 27] Compatible with analog output isolation amplifiers. [Figure 28] FIG. 13 is a block diagram showing a ninth embodiment. [Figure 29] FIG. 22 is a block diagram showing a tenth embodiment. [Figure 30] FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] (First embodiment) Fig. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. The semiconductor integrated circuit in Fig. 1 constitutes an isolation amplifier. In this embodiment, the normal data transmission path of the isolation amplifier is used to change the output data in response to the occurrence of an abnormality, thereby enabling the occurrence of an abnormality to be transmitted at high speed.

[0011] 1, the detection target is assumed to be the motor 55 or the motor drive circuit 56 that drives the motor 55, and an example of detecting an abnormality in voltage or current generated therein will be described, but the detection target is not limited to this. For example, this embodiment can also be applied to a case where a generator is used as the detection target and an abnormality in the power of a sensor for vibration or heat generated in the generator is detected.

[0012] In FIG. 1, isolation amplifier 1 includes a primary circuit 10, a secondary circuit 20, and an isolation unit 30. Primary circuit 10 outputs a digital value corresponding to the voltage, current, etc. generated in a detection target such as a motor to isolation unit 30. Isolation unit 30 transmits the output of primary circuit 10 to secondary circuit 20 while electrically isolating primary circuit 10 from secondary circuit 20. Secondary circuit 20 receives the digital value transmitted via isolation unit 30 and restores the value of the voltage or current generated in the detection target. The output of isolation amplifier 1 is supplied to control circuit 52, which is configured by an MCU (microcontroller unit) or the like, via differential to single-phase conversion circuit 50 and abnormality detection circuit 51, allowing control circuit 52 to grasp the state of the detection target.

[0013] The primary circuit 10 includes, for example, a ΔΣ ADC 11, an encoder 12, a clock generator 13, a reference voltage generator 14, and a comparator 15. The primary circuit 10 and the secondary circuit 20 are supplied with independent power supplies. In FIG. 1, the primary circuit 10 is supplied with a power supply voltage VDD1 and a ground voltage GND1, and the secondary circuit 20 is supplied with a power supply voltage VDD2 and a ground voltage GND2.

[0014] A signal corresponding to a voltage value, a current value, or the like generated in the detection target is input to the primary circuit 10 as a differential input VIN, which is a pair of input differential signals VIN+ and VIN-. These input differential signals VIN+ and VIN- are provided to a ΔΣADC 11. A clock generator 13 generates a clock and provides it to the ΔΣADC 11. A reference voltage generator 14 generates a reference voltage and provides it to the ΔΣADC 11. Using the reference voltage from the reference voltage generator 14, the ΔΣADC 11 converts the input differential signals VIN+ and VIN- into digital signals in synchronization with the clock signal generated by the clock generator 13 and outputs the digital signals to the encoder 12. The encoder 12 encodes the digital signals converted by the ΔΣADC 11 and outputs the encoded digital signals to the isolation unit 30.

[0015] Resistors R1 and R2 are connected in series between the power supply line supplied with power supply voltage VDD1 and the ground line supplied with ground voltage GND2. The voltage appearing at the connection point between resistors R1 and R2 is supplied as detection voltage VREF to the negative input terminal of comparator 15. An input differential signal VIN+ is supplied to the positive input terminal of comparator 15. When the input differential signal VIN+ exceeds the detection voltage VREF, comparator 15 outputs a high-level (H-level) detection signal. By appropriately setting the resistance values ​​of resistors R1 and R2, comparator 15 can be configured to output an H-level detection signal when the input differential signal VIN+ is excessively high. In other words, the detection signal from comparator 15 indicates whether an abnormality, such as excessive input, has occurred in the differential input VIN when the input differential signals VIN+ and VIN- are fixed to a voltage such as ground. Comparator 15 outputs the detection signal to isolation section 30.

[0016] In the following explanation, it is assumed that an H level detection signal is generated when an abnormality is detected, and that the detection signal is low level (L level) when no abnormality is detected, but conversely, the detection of an abnormality may be indicated by an L level, and normal (usual) conditions may be indicated by an H level.

[0017] 2 to 4 are block diagrams showing specific configuration examples of the isolation section 30. Fig. 2 shows an optical coupling system, Fig. 3 shows a magnetic coupling system, and Fig. 4 shows a capacitive coupling system.

[0018] 2, a digital signal is supplied from the encoder 12 to a driver 31. A light-emitting element 32a and a current source 33 are connected in series between a power supply line and a ground line. The driver 31 drives the light-emitting element 32a using the input digital signal. As a result, the light-emitting element 32a is driven by the driver 31 to pass a current and emits light in an amount corresponding to the current that has passed.

[0019] The current source 33 is also supplied with a detection signal from the comparator 15. In response to the H-level detection signal, the current source 33 causes a predetermined amount of current to flow through the light-emitting element 32 a. The current from the current source 33 is set to a current greater than the amount of current generated in the light-emitting element 32 a by driving the driver 31.

[0020] Light from the light-emitting element 32a is received by the photodetector element 32b. The light-emitting element 32a and the photodetector element 32b are electrically insulated from each other. The photodetector element 32b generates a current corresponding to the amount of light emitted by the light-emitting element 32a. A transimpedance amplifier (TIA) 34 converts the current generated by the photodetector element 32b into a voltage. The output voltage of the transimpedance amplifier 34 is supplied to the positive input terminals of comparators 35 and 36.

[0021] The comparator 35 compares the reference voltage VREF1 supplied to its negative input terminal with the output voltage of the transimpedance amplifier 34, and outputs a digital signal of H level if the output voltage of the transimpedance amplifier 34 is large, and a digital signal of low level (L level) if the output voltage is small. That is, the output of the comparator 35 is a digital signal corresponding to the digital signal from the encoder 12.

[0022] The comparator 36 compares the reference voltage VREF2 supplied to its negative input terminal with the output voltage of the transimpedance amplifier 34. The reference voltage VREF2 is set to a voltage that is greater than the reference voltage VREF1 and higher than the voltage generated by driving the driver 31. The comparator 36 outputs a digital signal that is H level if the output voltage of the transimpedance amplifier 34 is greater than the reference voltage VREF2, and L level if it is smaller. In other words, the output of the comparator 36 is a pulse signal that corresponds to the detection signal from the comparator 15.

[0023] 3 shows an isolation unit 40 that can be used as the isolation unit 30. The isolation unit 40 is composed of drivers 41a and 41b, primary and secondary coils 42a and 42b, and receivers 43a and 43b. The driver 41a and the receiver 43a are electrically insulated by the primary and secondary coil 42a, and the driver 41b and the receiver 43b are electrically insulated by the primary and secondary coil 42b. Although not shown, two pairs of coils may be provided, providing double insulation.

[0024] The driver 41a drives the primary and secondary coils 42a with the digital signal from the encoder 12. The receiver 43a extracts the voltage generated by the mutual induction between the primary and secondary coils 42a. Thus, the output of the receiver 43a becomes a digital signal corresponding to the digital signal from the encoder 12.

[0025] Furthermore, the driver 41b drives the primary and secondary coils 42b in response to the detection signal from the comparator 15. The receiver 43b extracts the voltage generated by the mutual induction between the primary and secondary coils 42b. Thus, the output of the receiver 43b becomes a pulse signal corresponding to the detection signal from the comparator 15.

[0026] 4 shows an isolation section 45 that can be used as the isolation section 30. The isolation section 45 is composed of drivers 46a and 46b, coupling capacitors 47a and 47b, and receivers 48a and 48b. The driver 46a and the receiver 48a are electrically isolated by the coupling capacitor 47a, and the driver 46b and the receiver 48b are electrically isolated by the coupling capacitor 47b. Although not shown, two pairs of coupling capacitors may be provided to provide double insulation.

[0027] The driver 46a applies the digital signal from the encoder 12 to a coupling capacitor 47a. The receiver 48a extracts the output of the driver 46a via the coupling capacitor 47a. Thus, the output of the receiver 48a is a digital signal corresponding to the digital signal from the encoder 12.

[0028] Driver 46b also applies the detection signal from comparator 15 to coupling capacitor 47b. Receiver 48b extracts the output of driver 46b via coupling capacitor 47b. Thus, the output of receiver 48b becomes a pulse signal corresponding to the detection signal from comparator 15.

[0029] 1, the output of the isolation unit 30 is supplied to a secondary circuit 20. The secondary circuit 20 includes a decoder 21, a 1-bit DAC 22, an LPF (low pass filter) 23, a clock recovery circuit 24, a reference voltage generator 25, and an abnormal input detection output circuit 26.

[0030] The output (digital signal) of the isolation unit 30 based on the output of the encoder 12 is provided to the decoder 21 and the clock recovery circuit 24. The clock recovery circuit 24 recovers a clock from the input digital signal and outputs it to the decoder 21. In addition, the reference voltage generator 25 generates a reference voltage and outputs it to the decoder 21. The decoder 21 uses the clock and reference voltage from the clock recovery circuit 24 to perform a decoding process that restores the signal encoded by the encoder 12 to the signal before encoding. The decoder 21 outputs the decoded digital signal to the 1-bit DAC 22.

[0031] The 1-bit DAC 22 converts the digital signal decoded by the decoder 21 into an analog signal and outputs it to the LPF 23. The LPF 23 removes unnecessary frequency components contained in the analog signal output from the 1-bit DAC 22 and outputs a differential output VOUT consisting of a pair of output differential signals VOUT+, VOUT- from its output terminal. The output differential signals VOUT+, VOUT- are input to the differential to single-phase conversion circuit 50 as differential signals AIN+, AIN- (hereinafter, referred to as differential signals AIN when there is no need to distinguish between them). The decoder 21, the 1-bit DAC 22, and the LPF 23 form an output circuit.

[0032] The differential to single-phase conversion circuit 50 converts the differential signals AIN+, AIN- into a single-phase output. For example, the differential to single-phase conversion circuit 50 calculates the difference between the differential signals AIN+, AIN-, converts the differential signals AIN+, AIN- into a single-phase output AOUT, and outputs it to the ADC1 terminal of the control circuit 52. The differential to single-phase conversion circuit 50 also adds the differential signals AIN+, AIN- together and outputs a voltage that is (half) the addition result to the abnormality detection circuit 51.

[0033] FIG. 5 is a circuit diagram showing an example of a specific configuration of the converting circuit 50 shown in FIG.

[0034] The differential signal AIN+ is supplied to the non-inverting input terminal of the operational amplifier OP1a. The inverting input terminal of the operational amplifier OP1a is connected to the output terminal via a resistor R22a and to a node r via a resistor R21a. The operational amplifier OP1a and the resistors R21a and R22a form a non-inverting amplifier.

[0035] The differential signal AIN- is supplied to the non-inverting input terminal of the operational amplifier OP1b. The inverting input terminal of the operational amplifier OP1b is connected to the output terminal via a resistor R22b and to a node r via a resistor R21b. The operational amplifier OP1b and the resistors R21b and R22b form a non-inverting amplifier.

[0036] The output terminal of the operational amplifier OP1a is connected to the inverting input terminal of the operational amplifier OP2 via a resistor R23a, and the output terminal of the operational amplifier OP1b is connected to the non-inverting input terminal of the operational amplifier OP2 via a resistor R23b. The inverting input terminal of the operational amplifier OP2 is connected to the output terminal via a resistor R24a, and the non-inverting input terminal of the operational amplifier OP2 is connected to the reference potential point via a resistor R24b. The operational amplifier OP2 and the resistors R23a, R23b, R24a, and R24b form a differential amplifier.

[0037] The differential signal AIN+ is amplified by a non-inverting amplifier formed by an operational amplifier OP1a and is provided to the inverting input terminal of an operational amplifier OP2 that forms a differential amplifier. The differential signal AIN- is amplified by a non-inverting amplifier formed by an operational amplifier OP1b and is provided to the non-inverting input terminal of the operational amplifier OP2. The differential signals AIN+ and AIN- are differentially amplified by the operational amplifier OP2, and a single-phase output AOUT corresponding to the difference between the differential signals AIN+ and AIN- is obtained from the output terminal of the operational amplifier OP2. This single-phase output AOUT is provided to the ADC1 terminal of the control circuit 52.

[0038] The voltage of the differential signal AIN+ appearing at the inverting input terminal of the operational amplifier OP1a and the differential signal AIN- appearing at the inverting input terminal of the operational amplifier OP1b is divided by resistors R21a and R21b. By making the resistance values ​​of the resistors R21a and R21b the same, a voltage that is half the sum of the differential signals AIN+ and AIN- appears at node r. This voltage is supplied to the abnormality detection circuit 51.

[0039] 1, the abnormality detection circuit 51 can be configured with, for example, a comparator. A reference voltage Vref is also applied to the abnormality detection circuit 51. The abnormality detection circuit 51 compares the reference voltage Vref with a voltage based on the addition result from the differential to single-phase conversion circuit 50, and outputs an abnormality detection result indicating whether an abnormality such as an excessive input has occurred to the ADC2 terminal of the control circuit 52.

[0040] The control circuit 52 is configured by, for example, an MCU. The control circuit 52 obtains values ​​of voltage, current, etc. generated in the detection target from the single-phase output AOUT input to the ADC1 terminal. The control circuit 52 also detects an abnormality, such as an excessive input, generated in the detection target from the abnormality detection result input to the ADC2 terminal.

[0041] The isolation amplifier 1 converts a signal to be transmitted in the primary circuit 10 into a digital signal, and then converts the transmitted digital signal back into an analog signal in the secondary circuit 20. This requires filtering by the LPF 23 after D / A conversion. However, the filtering by the LPF 23 inherently causes a relatively long predetermined delay time. Due to the signal delay caused by the LPF 23, it takes a relatively long time for the control circuit 52 to recognize an abnormal state such as an excessive input.

[0042] Therefore, in this embodiment, an abnormal input detection output circuit 26 is provided. When an H-level detection signal indicating the occurrence of an abnormal state such as an excessive input is given, the abnormal input detection output circuit 26 changes the output of the LPF 23 at the timing of this detection signal, thereby making it possible to notify the control circuit 52 of the occurrence of an excessive input or the like in a short time.

[0043] (Abnormal input detection output circuit) FIG. 6 is a circuit diagram showing an example of a specific configuration of the LPF 23 and the abnormal input detection output circuit 26.

[0044] The LPF 23 has an LPF section 23b that filters the positive input VINP from the 1-bit DAC 22, and an LPF section 23a that filters the negative input VINN from the 1-bit DAC 22. The LPF section 23b is a second-order active filter composed of resistors R1P and R2P, capacitors C1P and C2P, and an operational amplifier 23P. The LPF section 23a is a second-order active filter composed of resistors R1N and R2N, capacitors C1N and C2N, and an operational amplifier 23N.

[0045] The positive input VINP is input to the non-inverting input terminal in+ of the operational amplifier 23P via resistors R1P and R2P. The non-inverting input terminal in+ of the operational amplifier 23P is connected to the ground line (gnd) via a capacitor C1P, and the output terminal is connected to the inverting input terminal in- and to the connection point of the resistors R1P and R2P via a capacitor C2P. The LPF unit 23b band-limits the high frequencies of the positive input VINP and then outputs the output differential signal VOUT+.

[0046] Meanwhile, the negative input VINN is input to the non-inverting input terminal in+ of an operational amplifier 23N via resistors R1N and R2N. The non-inverting input terminal in+ of the operational amplifier 23N is connected to the ground line (gnd) via a capacitor C1N, and the output terminal is connected to the inverting input terminal in- and to the connection point of the resistors R1N and R2N via a capacitor C2N. The LPF unit 23a band-limits the high frequencies of the negative input VINN and then outputs the output differential signal VOUT-.

[0047] In this embodiment, the non-inverting input terminal in+ of the operational amplifier 23P is connected to a node b of the abnormal input detection output circuit 26, and the non-inverting input terminal in+ of the operational amplifier 23N is connected to a node a of the abnormal input detection output circuit 26. The abnormal input detection output circuit 26 is composed of a constant voltage generating circuit V0, current sources I0 and I1, resistors R3 and R4, and switches S0 and S1.

[0048] The negative terminal of constant voltage generating circuit V0 is connected to the ground line (GND), and the positive terminal is connected to node a via current source I0 and switch S0. Resistor R3 is connected in parallel to the current path of current source I0. The positive terminal of constant voltage generating circuit V0 is also connected to node b via current source I1 and switch S1. Resistor R4 is connected in parallel to the current path of current source I1.

[0049] The abnormal input detection output circuit 26 receives a detection signal from the isolation unit 30 and controls the switches S0 and S1 to turn on and off based on this detection signal. That is, when the detection signal is at an L level, which does not indicate the detection of an excessive input or the like, both switches S0 and S1 are off, and when the detection signal is at an H level, which indicates the detection of an excessive input or the like, both switches S0 and S1 are on.

[0050] When switch S0 is on, a voltage Vcm1 determined by the voltage generated by constant voltage generating circuit V0, the current generated by current source I0, and the resistance value of resistor R3 is applied to node a. This voltage Vcm1 sets the voltage at the non-inverting input terminal in+ of operational amplifier 23N, and the common-mode level of output differential signal VOUT- becomes Vcm1.

[0051] Similarly, when switch S1 is on, a voltage Vcm2 determined by the voltage generated by constant voltage generating circuit V0, the current generated by current source I1, and the resistance value of resistor R4 is applied to node b. This voltage Vcm2 sets the voltage at the non-inverting input terminal in+ of operational amplifier 23P, and the common-mode level of output differential signal VOUT+ becomes Vcm2. Note that the following explanation will be given assuming Vcm1 = Vcm2 = Vcm.

[0052] The detection signal from comparator 15 becomes H level immediately after the input differential signal VIN+ or the differential input VIN becomes excessively large, and nodes a and b of abnormal input detection output circuit 26 change to voltage Vcm immediately after the input differential signal VIN+ or the differential input VIN becomes excessively large. Therefore, immediately after the input differential signal VIN+ or the differential input VIN becomes excessively large, before the output differential signals VOUT+ and VOUT- corresponding to the excessive input of the input differential signals VIN+ and VIN- are output from LPF 23, the common-mode level of the output differential signals VOUT+ and VOUT- from LPF 23 shifts to Vcm. In other words, the common-mode level, which is a predetermined level (e.g., 0 V) ​​under normal conditions, changes to Vcm.

[0053] In a normal state where no abnormal conditions such as excessive input are occurring in the output differential signals VOUT+ and VOUT-, the sum of the output differential signals VOUT+ and VOUT- will be at a certain level. In contrast, when an abnormal condition such as excessive input is occurring in the output differential signals VOUT+ and VOUT-, the sum of the output differential signals VOUT+ and VOUT- will be at a level corresponding to the voltage Vcm. Therefore, it is possible to determine whether an abnormal condition such as excessive input is occurring based on the sum of the output differential signals VOUT+ and VOUT-.

[0054] (action) Next, the operation of the embodiment configured as described above will be described with reference to the waveform diagram of FIG. 7. FIG. 7 shows input / output waveforms, with time on the horizontal axis and voltage on the vertical axis. In the upper part of FIG. 7, the dashed line indicates the differential input VIN, which is the difference voltage between the input differential signals VIN+ and VIN-, and the solid line indicates the differential output VOUT, which is the difference voltage between the output differential signals VOUT+ and VOUT-. In the middle part of FIG. 7, the solid line indicates the output differential signal VOUT+, and the dashed line indicates the output differential signal VOUT-. In addition, the bottom part of FIG. 7 shows the results of detecting an abnormality in the control circuit.

[0055] Now, assume that the differential input VIN shown by the dashed line in the upper part of Figure 7 is input. Note that from here on, the explanation will be given assuming that the input differential signal VIN- is fixed to the ground voltage. The detection level in the upper part of Figure 7 indicates the judgment level for excessive input, and if the difference voltage VIN between the input differential signal VIN+ and the input differential signal VIN- is higher than the detection level, it is judged that an excessive input has occurred. In other words, the period during which the differential input VIN is higher than the detection level is the period during which an abnormality has occurred. Note that the detection voltage VREF corresponding to the detection level in Figure 7 is set by the power supply voltage VDD1 and resistors R1 and R2.

[0056] The input differential signals VIN+, VIN− input to the primary circuit 10 are converted into digital signals by the ΔΣADC 11, encoded by the encoder 12, and then supplied to the isolation unit 30. The isolation unit 30 transmits the output of the encoder 12 to the secondary circuit 20. The decoder 21 of the secondary circuit 20 decodes the input signal and provides it to the 1-bit DAC 22. The 1-bit DAC 22 converts the output of the decoder 21 back into an analog signal and outputs it to the LPF 23. The LPF 23 filters the high frequencies of the output of the 1-bit DAC 22, thereby outputting a differential output VOUT corresponding to the differential input VIN.

[0057] A delay occurs in the filtering process of the LPF 23. As a result, as shown in the upper part of FIG. 7, the differential output VOUT is output with a relatively long delay from the differential input VIN.

[0058] Now, assume that the differential input VIN goes into an excessive input state (abnormality occurrence period) exceeding the detection level shown in the upper part of FIG. 7. The comparator 15 outputs an H-level detection signal relatively quickly after the occurrence of this excessive input. The H-level period of the detection signal is the abnormality detection period by the primary circuit 10. The detection signal is supplied to the abnormal input detection output circuit 26 via the isolation unit 30, turning on the switches S0 and S1. As a result, the voltage Vcm is applied to the nodes a and b of the abnormal input detection output circuit 26, and the in-phase outputs of the LPF units 23a and 23b become the voltage Vcm.

[0059] The middle part of Figure 7 shows this state, with the common-mode levels of both output differential signals VOUT+ and VOUT- rising by the voltage Vcm. Immediately after the excessive input of the differential input VIN is resolved and the differential input VIN falls below the detection level shown in the upper part of Figure 7, the detection signal from the comparator 15 goes low. This detection signal is supplied to the abnormal input detection output circuit 26 via the isolation unit 30, and switches S0 and S1 are turned off. As a result, the common-mode outputs of the LPF units 23a and 23b return to the normal common-mode voltage.

[0060] The output differential signals VOUT+ and VOUT− from the LPF 23 are supplied to the downstream differential to single-phase conversion circuit 50. The differential to single-phase conversion circuit 50 calculates the difference between the output differential signals VOUT+ and VOUT− to determine an output corresponding to the differential input VIN, and outputs the output to the control circuit 52. This allows the control circuit 52 to grasp the voltage, current, etc. of the detection target from the differential output VOUT.

[0061] Furthermore, the differential to single-phase conversion circuit 50 calculates the sum of the output differential signal VOUT+ and the output differential signal VOUT- and outputs the sum to the abnormality detection circuit 51. The abnormality detection circuit 51 compares the voltage based on the sum result from the differential to single-phase conversion circuit 50 with the reference voltage Vref and outputs the comparison result. As shown in the lower part of Figure 7, under normal conditions, half the sum voltage of the output differential signal VOUT+ and the output differential signal VOUT- is a certain voltage (a voltage equivalent to the common-mode voltage under normal conditions). Under abnormal conditions, half the sum voltage of the output differential signal VOUT+ and the output differential signal VOUT- becomes voltage Vcm. In other words, the pulse waveform in the lower part of Figure 7 represents the detection result of the abnormality detection circuit 51, indicating the period of an abnormal state (abnormality detection period) such as excessive input. The abnormality detection circuit 51 outputs the abnormality detection result to the ADC2 terminal of the control circuit 52. The pulse waveform in the lower part of FIG. 7 shows the abnormality detection period that is slightly delayed from the abnormality occurrence period, and the isolation amplifier 1 is capable of transmitting the occurrence of an abnormality detected by the primary circuit 10 at high speed.

[0062] Furthermore, the output differential signal VOUT+ and the output differential signal VOUT- during the abnormality detection period are obtained by adding a known voltage from the abnormal input detection output circuit 26. Therefore, even during the abnormality detection period, the difference between the output differential signal VOUT+ and the output differential signal VOUT- corresponds to the differential input VIN, as shown in the upper part of Fig. 7. That is, in this embodiment, the output differential signals VOUT+ and VOUT- from the LPF 23 can be used to detect an abnormal period such as an excessive input, and can also be used to grasp the voltage, current, etc. of the detection target over the entire period, including the abnormality period.

[0063] As described above, in this embodiment, an abnormality in the differential input VIN is detected on the primary side and a detection signal is transmitted to the secondary side. Based on the detection signal, the secondary side shifts the common-mode level of the LPF output differential signals VOUT+ and VOUT- during the abnormality detection period. This allows the occurrence of an abnormality to be quickly transmitted to the downstream control circuit 52 via the LPF output without being subject to LPF processing delays.

[0064] (Variation) 8 is a circuit diagram showing a modified example. Fig. 8 shows another example of the configuration of the LPF 23 and the abnormal input detection output circuit 26. This modified example shows a configuration example in which a fully differential circuit is used as the LPF 23.

[0065] 8, a positive input VINP from a 1-bit DAC 22 is applied to the non-inverting input terminal of a fully differential amplifier OPA1 via a resistor R5P. A negative input VINN from the 1-bit DAC 22 is applied to the inverting input terminal of the fully differential amplifier OPA1 via a resistor R5N. A capacitor C3P is connected between the positive output terminal and the non-inverting input terminal of the fully differential amplifier OPA1, and a capacitor C3N is connected between the negative output terminal and the inverting input terminal of the fully differential amplifier OPA1. The fully differential amplifier OPA1, resistors R5P and R5N, and capacitors C3P and C3N form an LPF 23.

[0066] The positive input VINP and negative input VINN are filtered by the full differential amplifier OPA1, and an output differential signal VOUT+ is output from the positive output terminal of the full differential amplifier OPA1, and an output differential signal VOUT- is output from the negative output terminal.

[0067] Resistors R6P and R6N are connected in series between the positive and negative output terminals of the full differential amplifier OPA1, and the junction of the resistors R6P and R6N is connected to the inverting input terminal of the operational amplifier OPA2. A voltage generated by a voltage generating circuit 26a is supplied to the non-inverting input terminal of the operational amplifier OPA2. The operational amplifier OPA2 supplies a voltage based on the differential voltage between the two inputs to the full differential amplifier OPA1. The common-mode voltage of the full differential amplifier OPA1 operates to match the output voltage of the operational amplifier OPA2.

[0068] The negative terminal of constant voltage generating circuit V0 is connected to the ground line (gnd), and the positive terminal is connected to one terminal of switch SW1. The negative terminal of constant voltage generating circuit V1 is connected to the positive terminal of constant voltage generating circuit V0, and the positive terminal is connected to the other terminal of switch SW1. The constant voltage generating circuits V0 and V1 generate voltages V0 and V1, respectively.

[0069] The common terminal of switch SW1 is connected to the non-inverting input terminal of operational amplifier OPA2. Switch SW1 is controlled by a detection signal from isolation unit 30. In response to a detection signal indicating that no abnormality has occurred, switch SW1 applies voltage V0 generated by constant voltage generation circuit V0 to the non-inverting input terminal of operational amplifier OPA2, and in response to a detection signal indicating that an abnormality has occurred, switch SW1 applies the sum voltage (V0+V1) of the voltages generated by constant voltage generation circuits V0 and V1 to the non-inverting input terminal of operational amplifier OPA2.

[0070] 8 is a fully differential circuit, the common-mode voltage of the fully differential amplifier OPA1 is controlled by a detection signal to change the output differential signals VOUT+ and VOUT- of the LPF 23. Under normal conditions, the output of the operational amplifier OPA2 is fed back to the fully differential amplifier OPA1 so that the voltage at the connection point of resistors R6P and R6N matches the voltage V0.

[0071] Under normal circumstances, switch SW1 supplies voltage V0, which is generated by constant voltage generator circuit V0 in response to the detection signal, to the non-inverting input terminal of operational amplifier OPA2. As a result, the common-mode voltage of full differential amplifier OPA1 becomes V0. When an abnormality such as excessive input occurs and the detection signal becomes high level, switch SW1 supplies the sum of the voltages generated by constant voltage generator circuits V0 and V1, (V0+V1), to the non-inverting input terminal of operational amplifier OPA2. As a result, the common-mode voltage of full differential amplifier OPA1 becomes (V0+V1), and the output differential signals VOUT+ and VOUT- increase by V1.

[0072] In this way, even when the circuit of FIG. 8 is employed, the same effects as those of the first embodiment can be obtained.

[0073] (Second embodiment) Fig. 9 is a block diagram showing a second embodiment of the present invention. In Fig. 9, the same components as those in Fig. 1 are given the same reference numerals and their description will be omitted.

[0074] The isolation amplifier 2 of this embodiment modifies the output of the LPF 23 in a stage subsequent to the LPF 23 based on the detection signal transmitted from the primary circuit 10 to the secondary circuit 20, thereby quickly transmitting the occurrence of an abnormality to the control circuit 52 in the subsequent stage. Note that in this embodiment, the differential to single-phase conversion circuit 50 and the control circuit 52 are not shown. Also, in this embodiment, an arithmetic circuit 29 is employed instead of the abnormality detection circuit 51, as shown in FIG. 10.

[0075] The secondary circuit 28 of this embodiment differs from the secondary circuit 20 of FIG. 1 in that it employs an abnormal input detection output circuit 27 instead of the abnormal input detection output circuit 26. The abnormal input detection output circuit 27 receives the output of the LPF 23 and outputs output differential signals VOUT+, VOUT−. The abnormal input detection output circuit 27 also receives a detection signal indicating the detection result of an abnormality such as an excessive input from the primary circuit 10 via the isolation unit 30. When the detection signal indicates the occurrence of an abnormality, the abnormal input detection output circuit 27 generates an output to notify the occurrence of the abnormality instead of the differential output VOUT.

[0076] Fig. 10 is a circuit diagram showing an example of a specific configuration of the abnormal input detection output circuit 27 of Fig. 9. Fig. 10 shows only a part of the configuration of the secondary circuit 28 in Fig. 9.

[0077] 10, the abnormal input detection output circuit 27 is composed of two switches S2 and S3 controlled by a detection signal. The output differential signal VOUT+ is input from the LPF 23 to one input terminal of the switch S2, and an internal clock (internal CK) is input to the other input terminal. The output differential signal VOUT- is input from the LPF 23 to one input terminal of the switch S3, and the internal clock (internal CK) is input to the other input terminal. The internal CK is a recovered clock recovered by the clock recovery circuit 24.

[0078] When the detection signal is at an L level indicating no abnormality, the switches S2 and S3 select and output the output differential signal VOUT+ or VOUT− of the LPF 23. On the other hand, when the detection signal is at an H level indicating the occurrence of an abnormality, the switches S2 and S3 select and output the internal CK.

[0079] The output differential signals VOUT+ and VOUT- input to one input terminal of each of the switches S2 and S3 are differential signals, whereas the internal CK input to the other input terminal of each of the switches S2 and S3 is an in-phase signal. Therefore, in the circuit downstream of the secondary circuit 28, by providing the output of the abnormal input detection output circuit 27 to an arithmetic circuit 29 such as an AND circuit or an EXOR circuit, it is possible to determine which input terminal of the switches S2 and S3 has been selected and which signal has been output.

[0080] Next, the operation of the embodiment configured as described above will be described with reference to the waveform diagram of Fig. 11. Fig. 11 shows input / output waveforms, with time on the horizontal axis and voltage on the vertical axis. As with Fig. 7, in the upper part of Fig. 11, the dashed line indicates the differential input VIN, which is the difference voltage between input differential signals VIN+ and VIN-, and the solid line indicates the differential output VOUT, which is the difference voltage between output differential signals VOUT+ and VOUT-. In the middle part, the solid line indicates the output differential signal VOUT+ and the dashed line indicates the output differential signal VOUT-. In the lower part, the abnormality detection result input to control circuit 52 is shown.

[0081] The operation is the same as that of the first embodiment, from when a signal (VIN+, VIN−) corresponding to the input differential signals VIN+, VIN− is input to the 1-bit DAC 22 to when an analog signal is output from the 1-bit DAC 22. In addition, the operation is also the same as that of the first embodiment, from when a detection signal indicating the occurrence of an abnormality is output from the comparator 15 to when the detection signal is transmitted to the secondary circuit 28 via the isolation unit 30.

[0082] In this embodiment, the LPF 23 filters the high frequencies of the input signal and outputs filtered output differential signals VOUT+ and VOUT-. In the upper part of Fig. 11, the solid line indicates the difference VOUT between the output differential signals VOUT+ and VOUT-, and the dashed line indicates the difference VIN between the input differential signals VIN+ and VIN-. Note that the dotted line waveform shown connecting the curved portions of the differential output VOUT from the abnormal input detection output circuit 27 in Fig. 11 is the output (<internal signal (LPF)>) of the LPF 23, and has the same waveform as the waveform of the differential output VOUT during periods other than the period corresponding to the abnormality occurrence period.

[0083] 11, the detection signal input to the abnormal input detection output circuit 27 is at L level. In this case, the switches S2 and S3 of the abnormal input detection output circuit 27 select and output the output differential signals VOUT+ and VOUT− from the LPF 23.

[0084] Here, assume that the differential input VIN goes into an excessive input state (abnormality occurrence period) exceeding the detection level in the upper part of FIG. 11. Comparably shortly after the occurrence of this excessive input, the comparator 15 outputs a detection signal indicating the abnormality detection period by going high. The detection signal is supplied to the abnormal input detection output circuit 27 via the isolation unit 30, causing the switches S2 and S3 to select the internal CK. As a result, the output of the abnormal input detection output circuit 27 becomes the clock CK, as shown in the abnormality detection period in the middle part of FIG. 11.

[0085] When the differential input VIN becomes lower than the detection level in the upper part of FIG. 11, the detection signal becomes L level, and the switches S2 and S3 again output the output differential signals VOUT+ and VOUT− from the LPF 23 as they are (middle part of FIG. 11).

[0086] As shown in the upper part of Figure 11, the difference between the output differential signal VOUT+ and the output differential signal VOUT- is 0 V during the abnormality detection period. Therefore, the abnormality detection period can be determined by calculating the output differential signals VOUT+ and VOUT- rather than the difference between the output differential signals. The lower part of Figure 11 shows half the sum of the output differential signals VOUT+ and VOUT- from the abnormal input detection output circuit 27. As shown in Figure 11, under normal conditions, the sum voltage of the output differential signals VOUT+ and VOUT- is a certain voltage (the normal common-mode voltage). Under abnormal conditions, half the sum voltage of the output differential signals VOUT+ and VOUT- forms a pulse waveform synchronized with the internal CK. The period of this pulse waveform indicates the period of an abnormal state (abnormality detection period) such as an excessive input. The period of the pulse waveform in the lower part of Figure 11 indicates the abnormality detection period, which is slightly delayed from the abnormality occurrence period. This enables the isolation amplifier 2 to quickly transmit the occurrence of an abnormality detected by the primary circuit 10.

[0087] As in the first embodiment, in this embodiment, an abnormality in the differential input VIN is detected on the primary side and a detection signal is transmitted to the secondary side. On the secondary side, based on the detection signal, the output differential signals VOUT+ and VOUT- of the LPF are converted into in-phase signals during the abnormality detection period. This makes it possible to quickly transmit the occurrence of an abnormality to a downstream control circuit via the output of the LPF without being subject to processing delays of the LPF.

[0088] (Third embodiment) Fig. 12 is a block diagram showing a third embodiment of the present invention. In Fig. 12, the same components as those in Fig. 1 are given the same reference numerals and their description will be omitted.

[0089] In the first and second embodiments, an example was described in which the isolation amplifier outputs an analog signal as the differential output VOUT. This embodiment shows an example in which digital data is output from the isolation amplifier. Note that even in this case, low-pass filtering is required in the circuit downstream of the isolation amplifier, and signal delays occur due to the low-pass filter in a normal signal transmission path.

[0090] 12, the configurations of the primary circuit 10 and the isolation unit 30 of the isolation amplifier 3 are the same as those in Fig. 1. In this embodiment, the decoder 61 of the secondary circuit 60 decodes the differential signal transferred from the isolation unit 30 to generate output data DTI corresponding to the differential input VIN, and also generates the recovered clock CKI in the clock recovery circuit 24.

[0091] In this embodiment, an example will be described in which the clock CKI recovered by the clock recovery circuit 24 in the isolation amplifier 3 is used for data transmission, but an externally taken-in clock may also be used as the clock CKI.

[0092] In this embodiment, the output data DTI and clock CKI from the decoder 61 are not directly output as outputs of the isolation amplifier 3, but are instead provided to a mixer 62. A detection signal from the comparator 15 is provided as a detection signal FLTN to the mixer 62, which serves as an abnormal input detection output circuit, via the isolation unit 30. The decoder 61 and mixer 62 form an output circuit.

[0093] In this embodiment, as will be described later, the mixer 62 forcibly changes the logic of the output data DTI in response to an H-level detection signal FLTN, thereby transmitting the abnormality occurrence period to a downstream circuit. The downstream circuit detects this forced change and determines the abnormality occurrence period. The mixer 62 outputs output data DTO, which is obtained by changing the output data DTI in response to the detection signal FLTN, and also outputs the clock CKI as the clock CKO. The clock CKO and output data DTO are output as the clock MCLK and output data MDAT from the isolation amplifier 3 via buffers 63 and 64, respectively.

[0094] The clock MCLK and output data MDAT from the isolation amplifier 3 are provided to the FPGA 70. The FPGA 70 is composed of a latch 71, an LPF 72, and an MCU interface (I / F) 73. Note that in the following description, the term "latch" may refer to a D-type flip-flop. The clock MCLK is supplied to the latch 71 and the LPF 72 via a clock terminal CLK of the FPGA 70. The output data MDAT is input to the latch 71 via a data terminal DAT of the FPGA 70. The latch 71 captures the data MDAT in synchronization with the rising edge of the clock MCLK and outputs it to the LPF 72. The LPF 72 uses the clock MCLK to perform filtering to limit the high-pass frequency of the data and outputs the filtered data to the MCUI / F 73. The MCUI / F 73 outputs the data from the LPF 72 via an output terminal DIF to the DIF terminal of the control circuit 90. The control circuit 90 is composed of, for example, an MCU, captures the output data from the LPF 72, and restores data corresponding to the differential input VIN.

[0095] In this embodiment, the clock MCLK and output data MDAT from the isolation amplifier 3 are also supplied to an external circuit 80. The external circuit 80 uses the clock MCLK and output data MDAT to obtain a detection result FAULTN indicating the abnormality detection period. The external circuit 80 outputs the detection result FAULTN to an interrupt (INT) terminal of a control circuit 90. The control circuit 90 is configured to grasp the period during which the abnormality occurred based on the detection result FAULTN input to the INT terminal.

[0096] FIG. 13 is a circuit diagram showing an example of a specific configuration of the mixer 62 and the external circuit 80 in FIG.

[0097] 13, the mixer 62 is composed of a rising edge detector DT1, an inverter IN1, latches L1 and L2, and an AND circuit A1. The external circuit 80 is composed of a latch 81. The clock CKI from the decoder 61 is supplied to the latch L1, the rising edge detector DT1, and the inverter IN1, and is also supplied to the buffer 63. The output data DTI from the decoder 61 is supplied to the latch L2. The detection signal FLTN from the isolation unit 30 is supplied to the latch L1.

[0098] The rising edge detector DT1 detects the rising edge of the clock CKI and supplies a rising edge detection pulse to one input terminal of the AND circuit A1. The inverter IN1 inverts the clock CKI and supplies it to the clock terminal of the latch L2. The latch L1 receives the detection signal FLTN in response to the clock CKI and supplies it to the other input terminal of the AND circuit A1. The AND circuit A1 supplies the result of the AND operation of the two inputs to the S terminal of the latch L2. While an L level is supplied to the S terminal of the latch L2, it receives and outputs output data DTI at the timing of the falling edge of the clock CKI from the inverter IN1. Furthermore, while an H level is supplied to the S terminal of the latch L2, it outputs an H level. The output of the latch L2 passes through the buffer 64 and becomes the output (output data MDAT) of the isolation amplifier 3.

[0099] Since the latch L2 captures and outputs the output data DTI at the falling edge of the clock CKI, the output data MDAT is data whose logic changes while the clock MCLK is at level L. Also, the clock MCLK is at level H at the rising edge of the clock CKI immediately after the detection signal FLTN changes to level H.

[0100] The latch 81 of the external circuit 80 has a data terminal supplied with the clock MCLK and a clock terminal supplied with the output data MDAT. That is, the latch 81 takes in and outputs the clock MCLK at the rising edge of the output data MDAT.

[0101] Next, the operation of the embodiment configured as above will be described with reference to Fig. 14. Fig. 14 is a timing chart for explaining the operation of the third embodiment.

[0102] A decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with this clock CKI. CKI and DTI in Fig. 14 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 62 and buffers 63 and 64.

[0103] Assume now that the system is operating normally and no abnormalities such as excessive input have occurred. In this case, the detection signal FLTN is at L level, and the outputs of the latch L1 and AND circuit A1 in the mixer 62 are at L level. Therefore, the latch L2 captures and outputs the output data DTI in synchronization with the falling edge of the clock CKI. In this way, the output data MDAT, which is identical to the output data DTI, is output in synchronization with the clock MCLK. The output data MDAT switches data during the L level period of the clock MCLK.

[0104] Next, assume that an abnormality such as excessive input occurs, causing the detection signal FLTN to change to H level. FLTN in FIG. 14 shows this state. In this embodiment, in order to quickly transmit the abnormality detection result to the control circuit 90, the mixer 62 superimposes information about the abnormality detection result on the output data MDAT. In this case, the information about the abnormality detection result is superimposed using a portion of the data period of one clock so that the logic of the output data MDAT can be determined in a subsequent circuit.

[0105] That is, the rising edge detector DT1 detects the rising edge of the clock CKI to determine the superimposition timing and outputs a rising edge detection pulse (DT1 output in FIG. 14). The latch L1 latches the detection signal FLTN at the timing of the clock CKI and outputs it (L1 output in FIG. 14). The AND circuit A1 performs an AND operation on the rising edge detection pulse and the output of the latch L1. The A1 output in FIG. 14 indicates the result of the AND operation, and the AND circuit A1 outputs a pulse that is generated in synchronization with the rising timing of the clock CKI during the H level period of the detection signal FLTN.

[0106] Latch L2 forcibly changes the level of output data DTI to H level in synchronization with the rising edge of the output pulse from AND circuit A1. The output of latch L2 becomes output data DTO from mixer 62. Clock CKI becomes clock CKO from mixer 62 as is. These clock CKO and output data DTO are delayed by buffers 63 and 64, and then output to FPGA 70 as clock MCLK and output data MDAT. MCLK and MDAT in FIG. 14 indicate these outputs.

[0107] 14 indicates that the output data MDAT is forced to H level at the timing of the output pulse of the AND circuit A1. Even if the output data DTI is L level at the timing of the output pulse of the AND circuit A1, the output data MDAT changes to H level at the timing of the output pulse of the AND circuit A1. The example of FIG. 14 indicates that the data D1, D2, and D3 of the data D0, D1, ... are forced to change to H level.

[0108] The clock MCLK and output data MDAT from the isolation amplifier 3 are supplied to a latch 81 of an external circuit 80. The latch 81 takes in the clock MCLK at the rising edge of the output data MDAT and outputs it as a detection result FAULTN. If a forced level change is not performed, the data value of the output data MDAT switches while the clock MCLK is at L level. In contrast, by forcibly changing the level to H level midway through the data, it becomes possible to latch the H level of the clock at the rising edge of the output data MDAT. In this way, the detection result FAULTN shown in FAULTN in FIG. 14 can be obtained.

[0109] 14 indicates that the detection result FAULTN depends on the output data MDAT. For example, if the data D1 is originally at L level, the data D1 is forcibly changed to H level at the timing of the output pulse of the AND circuit A1. In this case, the H level of the clock MCLK is captured at the rising edge of the data D1. That is, the detection result FAULTN changes to H level at the timing when the data D1 is input to the external circuit 80.

[0110] However, if data D1 is originally at H level, data D1 does not rise at the timing of the output pulse of AND circuit A1, so the detection result FAULTN from latch 81 remains at L level. That is, the dashed line of FAULTN indicates that the detection result FAULTN may change to H level at the timing of any of data D1, D2, and D3. Similarly, when detection signal FLTN goes to L level, the detection result FAULTN takes in the L level of clock MCLK and outputs it at the timing of any of data D4, D5, ... rising. For example, if the original data D1 and D4 are L level and the original data D3 is H level, the detection result FAULTN goes to H level when data D1 is input to latch 81 and goes to L level when data D4 is input to latch 81.

[0111] The control circuit 90 determines that the high level period of the detection result FAULTN is an abnormality detection result. Furthermore, at the rising timing of the clock MCLK, the information of the data D0, D1, ... maintains the original information, and the control circuit 90 can reliably obtain data corresponding to the differential input VIN.

[0112] As described above, in this embodiment, a detection signal indicating the occurrence of an abnormality is acquired in the primary circuit 10 and transmitted to the secondary circuit 60. The secondary circuit 60 uses the transmitted detection signal to superimpose information indicating the period during which the abnormality was detected on the digital data, and extracts the superimposed information without filtering. This enables the abnormality detection result to be transmitted to downstream circuits at high speed.

[0113] (Fourth embodiment) Fig. 15 is a block diagram showing an example of a specific configuration of a mixer employed in the fourth embodiment of the present invention. In Fig. 15, the same components as those in Fig. 13 are assigned the same reference numerals, and their description will be omitted. Note that the isolation amplifier 4 of this embodiment differs from that of Fig. 12 only in that a mixer 100 is employed instead of the mixer 62, and description of the configuration other than the mixer 100 will be omitted.

[0114] In the third embodiment, the detection result FAULTN may not be obtained depending on the logic level of the transmitted output data MDAT. Therefore, in this embodiment, the detection result FAULTN can be reliably obtained by forcibly rewriting the data at the rising and falling timings of the detection signal FLTN.

[0115] 15, the clock CKI is supplied to inverters IN2 and IN3 and a rising edge detector DT1 that constitute the mixer 100, and is also supplied directly to a buffer 63. The output data DTI is supplied to a selector SE1. The detection signal FLTN is supplied to an inverter IN4, an AND circuit A2, and a latch L3.

[0116] Inverter IN2 inverts clock CKI and provides it to latch L3. Latch L3, in synchronization with the falling edge of clock CKI, captures detection signal FLTN and outputs it to latch L4 and AND circuit A4, and also inverts the captured detection signal FLTN and provides it to AND circuit A2. AND circuit A2 outputs the result of the AND operation of the two inputs to OR circuit OR1. Latch L4, in synchronization with the falling edge of clock CKI, captures the output of latch L3 and outputs it to AND circuit A3, and also inverts the captured output of latch L3 and outputs it to AND circuit A4.

[0117] The AND circuit A3 outputs the AND operation result of the two inputs to the AND circuit A5 and the OR circuit OR1. The OR circuit OR1 outputs the OR operation result of the two inputs as a selection signal to the selector SE1. The detection signal FLTN is inverted by the inverter IN4 and input to the selector SE1. The selector SE1 selects either the output data DTI or an inverted signal of the detection signal FLTN in accordance with the selection signal from the OR circuit OR1 and outputs the selected signal to the latch L5.

[0118] The AND circuit A5 outputs the AND operation result of the output of the rising edge detector DT1 and the output of the AND circuit A3 to the R terminal of the latch L5. The AND circuit A6 outputs the AND operation result of the output of the rising edge detector DT1 and the output of the AND circuit A4 to the S terminal of the latch L5. The latch L5 takes in and outputs the output of the selector SE1 in synchronization with the falling edge of the clock CKI from the inverter IN3, and outputs a high level in response to the high level output of the AND circuit A5, and a low level in response to the high level output of the AND circuit A6. The output of the latch L5 becomes the output (output data MDAT) of the isolation amplifier 4 via the buffer 64.

[0119] Next, the operation of the embodiment configured as above will be described with reference to Fig. 16. Fig. 16 is a timing chart for explaining the operation of the fourth embodiment.

[0120] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with this clock CKI. CKI and DTI in Fig. 16 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 100 and buffers 63 and 64.

[0121] Assume now that the mixer 100 is in a normal state with no abnormality such as excessive input. In this case, the detection signal FLTN is at L level. Therefore, the outputs of the latches L3 and L4, the AND circuits A2 to A6, and the OR circuit OR1 in the mixer 100 are all at L level. This causes the selector SE1 to select the output data DTI and output it to the latch L5. The latch L5 outputs the output of the selector SE1 to the buffer 64 in synchronization with the falling edge of the clock CKI. Thus, in this case, the clock MCLK and the output data MDAT correspond to the clock CKI and the output data DTI, respectively. Note that in this embodiment as well, the data value of the output data MDAT changes during the L level period of the clock MCLK.

[0122] Next, assume that an abnormality such as excessive input occurs and the detection signal FLTN changes to H level. FLTN in FIG. 16 shows this state. In this embodiment, too, when the detection signal FLTN changes to H level, the mixer 100 forcibly sets the output data MDAT to H level while the clock MCLK is at H level, as in the first embodiment. Furthermore, in this embodiment, when the detection signal FLTN changes to H level, the mixer 100 forcibly sets the output data to L level at a timing corresponding to this change, and when the detection signal FLTN changes to L level, the mixer 100 forcibly sets the output data to H level at a timing corresponding to this change.

[0123] That is, latch L3 captures and outputs the detection signal FLTN in synchronization with the falling edge of clock CKI (L3 output in FIG. 16). The AND circuit A2 performs an AND operation on the inverted signal of the output of latch L3 and the detection signal FLTN, and outputs a pulse (A2 output in FIG. 16) that becomes H level during the period from the rising edge of the detection signal FLTN to the falling edge of clock CKI to the OR circuit OR1.

[0124] Latch L4 outputs the output of latch L3 delayed by one clock to AND circuit A3, and also inverts the output and outputs it to AND circuit A4. The output of AND circuit A4 becomes H level for one clock period from the falling edge of clock CKI after detection signal FLTN becomes H level (A4 output in FIG. 16). Also, the output of AND circuit A3 becomes H level for one clock period from the falling edge of clock CKI after detection signal FLTN becomes L level (A3 output in FIG. 16).

[0125] The OR circuit OR1 performs an OR operation on the output of the AND circuit A2 and the output of the AND circuit A3, and outputs a pulse that is at an H level while the two inputs are at an H level (the OR1 output in FIG. 16). The selector SE1 selects and outputs the output data DTI while the selection signal from the OR circuit OR1 is at an L level, and selects and outputs the inverted signal of the detection signal FLTN while the selection signal is at an H level. That is, the output of the selector SE1 during the H level period of the selection signal is at an L level immediately after the rise of the detection signal FLTN, and is at an H level immediately after the fall of the detection signal FLTN.

[0126] The rising edge detector DT1 detects the rising edge of the clock CKI and outputs a rising edge detection pulse (DT1 output in FIG. 16). The AND circuit A6 outputs the result of an AND operation between the rising edge detection pulse from the rising edge detector DT1 and the output of the AND circuit A4 to the S terminal of the latch L5 (A6 output in FIG. 16). That is, the output of the AND circuit A6 is a rising edge detection pulse that is generated during the H level period of the output of the AND circuit A4, which goes to H level after the detection signal FLTN rises.

[0127] Furthermore, the AND circuit A5 outputs the AND operation result of the output of the rising edge detector DT1 and the output of the AND circuit A3 (A5 output in FIG. 16). That is, the output of the AND circuit A5 is a rising edge detection pulse generated during the H level period of the output of the AND circuit A3, which becomes H level after the detection signal FLTN falls.

[0128] Latch L5 selects and outputs the output of selector SE1 (output data DTI) while the outputs of AND circuits A5 and A6 are both at L level. Latch L5 outputs H level in response to a rising edge detection pulse from AND circuit A5 supplied to its R terminal, and outputs L level in response to a rising edge detection pulse from AND circuit A6 supplied to its S terminal.

[0129] As a result, as shown in Fig. 16, of the data D0, D1, ... of the output data MDAT, the data D2 is forced to the L level and the data D6 is forced to the H level. The clock MCLK and the output data MDAT are supplied to the FPGA 70. Due to the forced level change by the mixer 100, the output data MDAT processed in the FPGA 70 has lost the values ​​of the data D2 and D6, as shown in the FPGA in Fig. 16.

[0130] The latch 81 of the external circuit 80 takes in the clock MCLK at the rising edge of the output data MDAT and outputs it as the detection result FAULTN. As shown in Fig. 16, the detection result FAULTN goes high at the timing of the rising edge detection pulse after the detection signal FLTN goes high, and goes low at the timing of the rising edge detection pulse after the detection signal FLTN goes low.

[0131] In this way, the abnormality detection result can be transmitted to the control circuit 90 at high speed by the detection result FAULTN.

[0132] In this way, the present embodiment can also achieve the same effects as those of the third embodiment. In the present embodiment, the data value is forcibly changed at the timing when the detection signal FLTN changes, so that the detection result FAULTN indicating the abnormality detection result can be reliably obtained.

[0133] (Fifth embodiment) Fig. 17 is a block diagram showing an example of a specific configuration of a mixer employed in the fifth embodiment of the present invention. In Fig. 17, the same components as those in Fig. 13 are assigned the same reference numerals, and their description will be omitted. Note that the isolation amplifier 5 of this embodiment differs from that in Fig. 12 only in that a mixer 110 is employed instead of the mixer 62, and description of the configuration other than the mixer 110 will be omitted.

[0134] In the fourth embodiment, the output data MDAT was forcibly changed to an L or H level, resulting in data loss. This embodiment is intended to prevent this data loss. To achieve this, the mixer 110 of this embodiment changes the latter half of the data to an L level and then to an H level during the H level period of the clock MCLK at the rising edge of the detection signal FLTN. Also, the mixer 110 changes the latter half of the data to an L level and then to an H level during the L level period of the clock MCLK at the falling edge of the detection signal FLTN.

[0135] 17, the clock CKI is supplied to inverters IN5, IN6, and IN7 that make up the mixer 110, and is also supplied directly to a buffer 63. The output data DTI is supplied to a latch L6. The detection signal FLTN is supplied to a latch L7.

[0136] Inverters IN5-IN7 each invert the clock CKI and provide it to latches L8, L6, and L9. Latch L6 captures output data DTI in synchronization with the falling edge of clock CKI and outputs it to selector SE2. Latch L7 captures the detection signal FLTN in synchronization with clock CKI and outputs it to latch L8 and AND circuit A7, and also outputs an inverted signal of the detection signal FLTN to AND circuit A8. Latch L8 captures the output of latch L7 in synchronization with the falling edge of clock CKI and outputs it to delay circuit DE1. Delay circuit DE1 delays the output of latch L8 and provides a delayed output to AND circuit A8, and also inverts the delayed output and outputs it to AND circuit A7.

[0137] The AND circuit A7 outputs the AND operation result of the two inputs as a selection signal to the selector SE2, and also outputs the AND operation result to the delay circuit DE2. The delay circuit DE2 delays the output of the AND circuit A7 and then outputs it to the selector SE2. Based on the selection signal from the AND circuit A7, the selector SE2 selects the output of the latch L6 or the output of the delay circuit DE2 and outputs it to the selector SE3.

[0138] The AND circuit A8 outputs the AND operation result of the two inputs as a selection signal to the selector SE3, and also outputs the AND operation result to the latch L9. The latch L9 captures the output of the AND circuit A8 in synchronization with the falling edge of the clock CKI and outputs it to the selector SE3. The selector SE3 selects the output of the selector SE2 or the output of the latch L9 based on the selection signal from the AND circuit A8, and outputs it to the buffer 64.

[0139] Next, the operation of the embodiment configured as above will be described with reference to Fig. 18. Fig. 18 is a timing chart for explaining the operation of the fifth embodiment.

[0140] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with this clock CKI. CKI and DTI in Fig. 18 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 110 and buffers 63 and 64.

[0141] Assume now that the mixer 110 is operating normally and no abnormality such as excessive input has occurred. In this case, the detection signal FLTN is at L level. Therefore, the outputs of the latches L7, L8, and L9, the AND circuits A7 and A8, and the delay circuits DE1 and DE2 in the mixer 110 are all at L level. As a result, the selector SE2 selects the output of the latch L6, and the selector SE3 selects the output of the selector SE2. In this way, the output data DTI is supplied to the buffer 64 via the latch L6 and the selectors SE2 and SE3, and the buffer 64 outputs the output data MDAT corresponding to the output data DTI in synchronization with the clock MCLK.

[0142] Next, assume that an abnormality such as excessive input occurs and the detection signal FLTN changes to H level. FLTN in FIG. 18 shows this state. In this embodiment, as in the first embodiment, when the detection signal FLTN changes to H level, the mixer 110 forcibly sets the output data MDAT to H level during the H level period of the clock MCLK. Furthermore, in this embodiment, when the detection signal FLTN changes to H level, the mixer 110 forcibly sets the output data to L level and then to H level during the H level period of the clock MCLK in response to this change, and when the detection signal FLTN changes to L level, the mixer 110 forcibly sets the output data to L level and then to H level in response to this change and during the L level period of the clock MCLK.

[0143] That is, latch L7 captures the detection signal FLTN in synchronization with the rising edge of clock CKI and outputs it to latch L8 (L7 output in FIG. 18). Latch L8 captures the detection signal FLTN from latch L7 at the falling edge of clock CKI and outputs it to delay circuit DE1. Delay circuit DE1 delays and outputs the detection signal FLTN from latch L8 (DE1 output in FIG. 18). That is, the output of delay circuit DE1 becomes H level a predetermined period after the first falling edge of clock CKI after the rising edge of detection signal FLTN.

[0144] The AND circuit A7 outputs the result of an AND operation between the inverted signal of the output of the delay circuit DE1 and the output of the latch L7. As shown in the A7 output in Fig. 18, the output of the AND circuit A7 is a pulse that is at H level for a predetermined period (a width of at least half a clock period in Fig. 18) from the first falling edge of the clock CKI after the rising edge of the detection signal FLTN.

[0145] The delay circuit DE2 delays the output of the AND circuit A7 and provides the selector SE2 with an output (the DE2 output in FIG. 18). The delay time of the delay circuit DE2 is set to be longer than the period required for sampling the output data DTI from the rising edge of the clock CKI and shorter than half the clock period (the period during which the clock CKI is at H level). Therefore, while the output of the AND circuit A7 is at H level, the output of the selector SE2 is at L level immediately after the output of the AND circuit A7 goes to H level, and then goes to H level after the delay time of the delay circuit DE2 has elapsed after the output of the AND circuit A7 goes to H level.

[0146] The AND circuit A8 outputs the result of an AND operation between the inverted signal of the output of the latch L7 and the output of the delay circuit DE1 to the latch L9 and the selector SE2. As shown in the A8 output in Fig. 18, the output of the AND circuit A8 is a pulse that is at H level for a predetermined period (a width of at least half a clock period in Fig. 18) from the first falling edge of the clock CKI after the falling edge of the detection signal FLTN.

[0147] Latch L9 captures the output of AND circuit A8 in synchronization with the falling edge of clock CKI and provides it to selector SE3 (L9 output in FIG. 18). Selector SE3 selects the output of selector SE2 while the output of AND circuit A8 is at L level, and selects the output of latch L9 while it is at H level. Therefore, when the output of AND circuit A8 goes to H level, the output of selector SE3 is at L level immediately after the output of AND circuit A8 goes to H level, and goes to H level at the falling edge of the next clock CKI after the output of AND circuit A8 goes to H level. The output of selector SE3 is output as output data MDAT from isolation amplifier 5 via buffer 64.

[0148] 18, among the data D0, D1, ... of the output data MDAT, at the timing of data D2 corresponding to the rising edge of the detection signal FLTN, data D2 is forced to be at L level partway through and is returned to H level during the H level period of the clock MCLK.Furthermore, among the data D0, D1, ... of the output data MDAT, at the timing of data D5 corresponding to the falling edge of the detection signal FLTN, data D5 is forced to be at L level partway through and is returned to H level during the L level period of the clock MCLK.

[0149] The clock MCLK and output data MDAT are supplied to the FPGA 70. A latch 81 of the external circuit 80 captures the clock MCLK at the rising edge of the output data MDAT and outputs it as a detection result FAULTN. As shown in Fig. 18, the detection result FAULTN goes high about one clock after the detection signal FLTN goes high, and goes low about one and a half clocks after the detection signal FLTN goes low.

[0150] In this way, the detection result FAULTN can be used to quickly transmit the abnormality detection result to the control circuit 90. Furthermore, even if a forced level change occurs by the mixer 110, the output data MDAT processed in the FPGA 70 does not lose data, as shown in the FPGA of FIG.

[0151] In this way, the present embodiment can also achieve the same effects as those of the third embodiment. In the present embodiment, the data level is forcibly changed at the timing of change of the detection signal FLTN while the data value is maintained, so that the detection result FAULTN indicating the abnormality detection result can be reliably obtained without losing data.

[0152] (Sixth embodiment) FIG. 19 is a block diagram showing an example of a specific configuration of a mixer employed in a sixth embodiment of the present invention. In FIG. 19, the same components as those in FIG. 13 are designated by the same reference numerals, and their description will be omitted. The isolation amplifier 6 of this embodiment differs from that of FIG. 12 only in that a mixer 120 is employed instead of the mixer 62, and description of the configuration other than the mixer 120 will be omitted. In this embodiment, an FPGA 75 capable of processing at double data rate is employed instead of the FPGA 70. Furthermore, in this embodiment, an external circuit 82 is employed instead of the external circuit 80 of FIG. 12.

[0153] This embodiment utilizes a double data rate system that transmits data on both edges of the clock, and normally transmits data and an L level in one clock, and in the event of an abnormality such as excessive input, transmits data and an H level in one clock.

[0154] 19, clock CKI is supplied to inverter IN8, selector SE4, and double-edge detector DT2 that constitute mixer 120, and is also supplied directly to buffer 63. Output data DTI is supplied to selector SE4. Detection signal FLTN is supplied to latch L10. Inverter IN8 inverts clock CKI and supplies it to latch L10. Latch L10 takes in output data DTI in synchronization with the falling edge of clock CKI and outputs it to selector SE4.

[0155] The selector SE4 selects and outputs the output data DTI depending on the H level of the clock CKI, and selects and outputs the detection signal FLTN from the latch L10 depending on the L level of the clock CKI. The dual edge detector DT2 detects the rising and falling edges of the clock CKI and outputs an edge detection pulse to the latch L11. The latch L11 captures the output of the selector SE4 at the timing of the edge detection pulse and outputs it to the buffer 64.

[0156] Therefore, output data DTI is output from latch L11 in synchronization with the rising edge of clock CKI, and detection signal FLTN is output in synchronization with the falling edge of clock CKI. Note that the output of latch L11 is an L level output in synchronization with the falling edge of clock CKI during an L level period of detection signal FLTN when no abnormality such as excessive input occurs, and an H level output in synchronization with the falling edge of clock CKI during an H level period of detection signal FLTN when an abnormality such as excessive input occurs.

[0157] The clock MCLK and output data MDAT from the isolation amplifier 6 are supplied to the FPGA 75. The FPGA 75 has the same configuration as the FPGA 70 in FIG. 12 except that it can handle double data rate signals. The FPGA 75 samples the output data MDAT in synchronization with the rising edge of the clock MCLK to obtain data corresponding to the differential input VIN. The FPGA 75 performs low-pass filtering and other processes on the captured data before outputting it to the control circuit 90.

[0158] In this embodiment, the external circuit 82 is composed of inverters 83 to 85 and a latch 81. The inverter 83 inverts the output data MDAT and supplies it to the latch 81, and the inverter 84 inverts the clock MCLK and supplies it to the clock terminal of the latch 81. This causes the latch 81 to capture and output an inverted signal of the output data MDAT in synchronization with the falling edge of the clock MCLK. The output of the latch 81 is supplied to an inverter 85. The inverter 85 inverts the output of the latch 81 and outputs it to the INT terminal of the control circuit 90 as the detection result ALM.

[0159] Next, the operation of the embodiment configured as above will be described with reference to Fig. 20. Fig. 20 is a timing chart for explaining the operation of the sixth embodiment.

[0160] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with this clock CKI. CKI and DTI in Fig. 20 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 120 and buffers 63 and 64.

[0161] The double edge detector DT2 detects the rising and falling edges of the clock CKI and outputs edge detection pulses (Fig. 20 DT2 output). Using the edge detection pulses generated at the rising and falling edges of the clock CKI, the latch L11 captures and outputs the output of the selector SE4. Therefore, the output from the latch L11 is double data rate.

[0162] Assume now that the system is in a normal state where no abnormality such as excessive input has occurred. In this case, the detection signal FLTN is at L level. Therefore, the output of the latch L10 in the mixer 120 is at L level. The selector SE4 receives the output data DTI when the clock CKI is at H level and outputs it to L11, and receives the detection signal FLTN when the clock CKI is at L level and outputs it to L11. Therefore, in this case, the output of the latch L11 contains information about the output data DTI during the period synchronized with the clock CKI at H level, and is at L level during the period synchronized with the clock CKI at L level.

[0163] Next, assume that an abnormality such as excessive input occurs, causing the detection signal FLTN to change to H level. FLTN in FIG. 20 shows this state. The output of latch L10 changes to H level at the first falling edge of clock CKI after the detection signal FLTN changes to H level (L10 output in FIG. 20). This H-level output of latch L11 is output from selector SE4 in synchronization with the falling edge of clock CKI. Therefore, when the detection signal FLTN changes to H level, the output of latch L11 contains information about output data DTI during the period synchronized with the H level of clock CKI, and changes to H level during the period synchronized with the L level of clock CKI (SE4 output in FIG. 20). The output of latch L11 is output as output data MDAT from isolation amplifier 6 via buffer 64.

[0164] The clock MCLK and output data MDAT from the isolation amplifier 6 are supplied to the FPGA 75. The FPGA 75 obtains data corresponding to the differential input VIN by sampling the output data MDAT in synchronization with the rising edge of the clock MCLK.

[0165] An inverter 83 of the external circuit 82 inverts the output data MDAT and provides it to the latch 81. Furthermore, an inverter 84 inverts the clock MCLK and provides it to the clock terminal of the latch 81. As a result, the latch 81 captures and outputs the inverted signal of the output data MDAT in synchronization with the falling edge of the clock MCLK. Therefore, the latch 81 outputs a high level corresponding to the low level period of the detection signal FLTN, and outputs a low level corresponding to the high level period of the detection signal FLTN. The output of the latch 81 is inverted by an inverter 85 to become the detection result ALM. As shown by ALM in FIG. 20, the detection result ALM is a signal corresponding to the detection signal FLTN. The detection result ALM from the inverter 85 is supplied to the control circuit 90.

[0166] In this way, the detection result ALM can be used to quickly transmit the abnormality detection result to the control circuit 90. Furthermore, the output data MDAT processed in the FPGA 75 does not lose data, as shown in the FPGA of FIG.

[0167] In this way, the same effects as those of the fifth embodiment can be obtained in this embodiment as well.

[0168] (Seventh embodiment) Figure 21 is a block diagram showing an example of a specific configuration of a mixer employed in the seventh embodiment of the present invention. In Figure 21, the same components as those in Figure 13 are assigned the same reference numerals, and their description will be omitted. Note that the isolation amplifier 7 of this embodiment differs from that of Figure 12 only in that a mixer 130 is employed instead of the mixer 62, and description of the configuration other than the mixer 130 will be omitted. Note that in this embodiment, an external circuit 86 is employed instead of the external circuit 80 of Figure 12.

[0169] In the third to sixth embodiments, it has been explained that the clock CKI may be either a clock generated by the clock recovery circuit 24 or a clock taken in from outside the isolation amplifier, but in this embodiment, the clock CKI is the clock generated by the clock recovery circuit 24.

[0170] In the third to sixth embodiments, examples have been described in which the information of the detection signal FLTN is superimposed on the output data MDAT and transmitted. In this embodiment, the information of the detection signal FLTN is transmitted using a clock.

[0171] 21, a clock CKI is supplied to latches L12, L13, and L14 and a delay circuit DE3 that constitute a mixer 130. In this embodiment, the mixer 130 supplies the input clock CKI to a buffer 63 via the latch L13. Output data DTI is supplied to the latch L14. The latch L14 latches the output data DTI in synchronization with the clock CKI and outputs it to the buffer 64.

[0172] The detection signal FLTN is supplied to a latch L12. The latch L12 captures the detection signal FLTN in synchronization with the rising edge of the clock CKI and supplies it to the selector SE5 as a selection signal. The delay circuit DE3 delays the clock CKI by a predetermined delay time and outputs the delayed signal to the rising detector DT1 and the falling detector DT3. The rising detector DT1 detects the rising edge of the clock CKI delayed in the delay circuit DE3 and outputs an edge detection pulse to the selector SE5. The falling detector DT3 detects the falling edge of the clock CKI delayed in the delay circuit DE3 and outputs an edge detection pulse to the selector SE5.

[0173] The selector SE5 selects an edge detection pulse from the rising edge detector DT1 during the H level period of the detection signal FLTN from the latch L12 and supplies it to the R terminal of the latch L13, and selects an edge detection pulse from the falling edge detector DT3 during the L level period of the detection signal FLTN from the latch L12 and supplies it to the R terminal of the latch L13.

[0174] Latch L13 takes in and outputs an H level input (logical value "1") at the rising edge of clock CKI, and returns its output to L level when an edge detection pulse from selector SE5 is input to its R terminal. That is, during the L level period of the detection signal FLTN from latch L12, the output of L13 becomes H level at the rising edge of clock CKI and becomes a relatively short pulse output that turns L level at the timing of the edge detection pulse from rising edge detector DT1. Also, during the H level period of the detection signal FLTN from latch L12, the output of L13 becomes H level at the rising edge of clock CKI and becomes a relatively wide pulse output that turns L level at the timing of the edge detection pulse from falling edge detector DT3. The output of latch L13 is output as clock MCLK from isolation amplifier 7 via buffer 63.

[0175] The clock MCLK and output data MDAT from the isolation amplifier 7 are also provided to an external circuit 86. The external circuit 86 has a low-pass filter configured with a capacitor C11 and a resistor R11. One end of the resistor R11 is connected to the output end of the clock MCLK of the isolation amplifier 7, and the other end is connected to a reference potential point via the capacitor C11. The connection point between the capacitor C11 and the resistor R11 is connected to the ADC end of the control circuit 90.

[0176] The external circuit 86 calculates the average value of the voltage level of the clock MCLK, and supplies the calculated average value to the ADC terminal of the control circuit 90 as the detection result ALM.

[0177] Next, the operation of the embodiment configured as above will be described with reference to Fig. 22. Fig. 22 is a timing chart for explaining the operation of the seventh embodiment.

[0178] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with this clock CKI. CKI and DTI in Fig. 22 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 130 and buffers 63 and 64.

[0179] The output data DTI is supplied to the latch L14, which outputs the output data DTI to the buffer 64 in synchronization with the rising edge of the clock CKI. In this way, the output data MDAT (MDAT in FIG. 22) from the isolation amplifier 7 is information corresponding to the output data DTI, and is output in synchronization with the rising edge of the clock CKI.

[0180] The clock CKI is supplied to a latch L13. The latch L13 outputs an H level, which is a logical value of "1", at the rising edge of the clock CKI. The output of the latch L13 is output as the clock MCLK via a buffer 63. Therefore, the rising edge of the clock MCLK is synchronized with the rising edge of the clock CKI.

[0181] The clock CKI is also supplied to a delay circuit DE3. The delay circuit DE3 delays the clock CKI and then outputs the delayed signal to a rising edge detector DT1 and a falling edge detector DT3. The rising edge detector DT1 detects the rising edge of the delayed signal and outputs an edge detection pulse to the selector SE5, and the falling edge detector DT3 detects the falling edge of the delayed signal and outputs an edge detection pulse to the selector SE5. The output of the selector SE5 is supplied to the R terminal of the latch L13, and the output of the latch L13 goes low at the timing of the output pulse of the selector SE5.

[0182] Assume now that the system is operating normally, with no abnormalities such as excessive input occurring. In this case, the detection signal FLTN is at L level. Therefore, the selector SE5 selects the edge detection pulse from the rising edge detector DT1 and applies it to the latch L13. In this case, the output of the latch L13 outputs a relatively narrow pulse that goes H level at the rising edge of the clock CKI and goes L level at the rising edge of the clock CKI.

[0183] Next, suppose that an abnormality such as excessive input occurs, causing the detection signal FLTN to change to H level. FLTN in FIG. 22 shows this state. The output of latch L12 changes to H level at the first rising edge of clock CKI after the detection signal FLTN changes to H level (L12 output in FIG. 22). The edge detection pulse from rising edge detector DT1 is a pulse generated after the delay time of delay circuit DE3 from the rising edge of clock CKI (DT1 output in FIG. 22). In addition, the output of falling edge detector DT3 is a pulse generated at the falling edge of clock CKI after the delay time of delay circuit DE3 from the rising edge of clock CKI (DT3 output in FIG. 22).

[0184] The output of the latch L13 becomes a narrow pulse that goes high at the rising edge of the clock CKI during the period corresponding to the low level period of the detection signal FLTN and goes low at the timing of the edge detection pulse from the rising edge detector DT1. Also, the output of the latch L13 becomes a wide pulse that goes high at the rising edge of the clock CKI during the period corresponding to the high level period of the detection signal FLTN and goes low at the timing of the edge detection pulse from the falling edge detector DT3 (MCLK in FIG. 22).

[0185] The clock MCLK and the output data MDAT are supplied to the FPGA 70. As shown in the FPGA in Fig. 22, the output data MDAT is synchronized with the clock MCLK, and the output data MDAT can be processed in the FPGA 70.

[0186] The clock MCLK is also supplied to the external circuit 86. The clock MCLK is averaged by a low-pass filter formed by capacitors C11 and R11 of the external circuit 86. The external circuit 86 outputs this averaged clock MCLK to the control circuit 90 as the detection result ALM.

[0187] As shown in ALM in Fig. 22, by averaging the clock MCLK using the external circuit 86, the level of the detection result ALM becomes relatively low when the clock MCLK is narrow, and becomes relatively high when the clock MCLK is wide. The control circuit 90 obtains the abnormality detection result by comparing the level of the detection result ALM with the level shown by the dashed line in Fig. 22, for example.

[0188] In this way, the same effects as those of the fifth embodiment can be obtained in this embodiment as well.

[0189] (Eighth embodiment) Figure 23 is a block diagram showing an example of a specific configuration of a mixer employed in the eighth embodiment of the present invention. In Figure 23, the same components as those in Figure 13 are assigned the same reference numerals, and their description will be omitted. Note that the isolation amplifier 8 of this embodiment differs from that of Figure 13 only in that a mixer 140 is employed instead of the mixer 62, and description of the configuration other than the mixer 140 will be omitted. Note that in this embodiment, a pulse detector 87, which is an external circuit, is employed instead of the external circuit 80 of Figure 13.

[0190] This embodiment is an example in which information of the detection signal FLTN is superimposed on the invalid period of the output data MDAT and transmitted. In the FPGA 70 downstream of the isolation amplifier 8, the output data MDAT is sampled during the H level period of the clock MCLK. Therefore, in this embodiment, the information of the detection signal FLTN is superimposed using the invalid period of the output data MDAT corresponding to the L level period of the clock MCLK.

[0191] 23, clock CKI is supplied to inverter IN9 and latches L16 and L17 that constitute mixer 140, and is also supplied directly to buffer 63. Output data DTI is supplied to selector SE6. Detection signal FLTN is supplied to XOR circuit EX1. Inverter IN9 inverts clock CKI and supplies it to latch L15. Latch L15 takes in the output of XOR circuit EX1 at the timing of the inverted clock of clock CKI and outputs it to selector SE6 as a selection signal, as well as to XOR circuit EX1 and latch L16.

[0192] The XOR circuit EX1 performs an exclusive OR operation (hereinafter referred to as an XOR operation) on the detection signal FLTN and the output of the latch L15, and outputs the XOR operation result to L15. The output of the selector SE6 is given to the latch L17, which takes in the output of the selector SE6 at the rising edge of the clock CKI and outputs it to the selector SE6 and the XOR circuit EX2. The selector SE6 outputs output data DTI when the selection signal is at the L level, and outputs the output of the latch L17 when the selection signal is at the H level.

[0193] Latch L16 captures the output of latch L15 at the rising edge of clock CKI and outputs it to falling edge detector DT3. Falling edge detector DT3 detects the falling edge of the output of latch L15 and outputs an edge detection pulse to XOR circuit EX2. XOR circuit EX2 outputs the XOR operation result of the output of latch L17 and the output of falling edge detector DT3 to buffer 64.

[0194] With this configuration, as will be described later, during the invalid period of the output data MDAT corresponding to the rising and falling edges of the detection signal FLTN, a pulse is generated that inverts the level of the output data MDAT and returns it to its original level.

[0195] The clock MCLK and output data MDAT from the isolation amplifier 8 are supplied to the FPGA 70. The FPGA 70 obtains data corresponding to the differential input VIN by sampling the output data MDAT in synchronization with the rising edge of the clock MCLK.

[0196] In this embodiment, a pulse detector 87 is employed as an external circuit. The CLK terminal of the pulse detector 87 is supplied with the clock MCLK from the isolation amplifier 8, and the DAT terminal is supplied with the output data MDAT from the isolation amplifier 8. The pulse detector 87 detects pulses superimposed on the invalid period of the output data MDAT, and generates a detection result ALM indicating the detection of an abnormality and outputs it to the control circuit 90.

[0197] FIG. 24 is a circuit diagram showing an example of a specific configuration of the pulse detector 87 in FIG.

[0198] The clock MCLK and output data MDAT from the isolation amplifier 8 are also supplied to the pulse detector 87. That is, the clock MCLK is supplied to latches L18, L20, L21 and a delay circuit DE4. The output data MDAT is supplied to the latch L18 and the match circuit EX3. The latch L18 captures the output data MDAT at the rising edge of the clock MCLK and outputs it to the match circuit EX3. The match circuit EX3 performs a match operation, outputting a high level if the two inputs are the same logic (match) and a low level if they do not match, and outputs the match operation result to the AND circuit A9. The match operation result of the match circuit EX3 is also inverted and supplied to the latch L19.

[0199] The delay circuit DE4 delays the output data MDAT by a predetermined period and outputs it to the latch L19. The latch L19 takes in the inverted signal of the output of the match circuit EX3 while the output of the delay circuit DE4 is at H level and outputs it to the AND circuit A9, and outputs an L level (logical value "0") to the AND circuit A9 while the output of the delay circuit DE4 is at L level. The AND circuit A9 outputs the result of the AND operation of the two inputs to the OR circuit OR2 and the latch L20.

[0200] Latch L20 receives the output of AND circuit A9 at the rising edge of clock MCLK and outputs it to OR circuit OR2. OR circuit OR2 outputs the OR operation result of the two inputs to latch L21. Latch L21 receives the output of OR circuit OR2 at the rising edge of clock MCLK and outputs it. The output of latch L21 is supplied to control circuit 90 as detection result ALM. As will be described later, pulses included in the invalid period of output data MDAT are detected by pulse detector 87, and detection result ALM is determined according to these pulses.

[0201] Next, the operation of the embodiment configured as above will be described with reference to Figures 25 and 26. Figure 25 is a timing chart for explaining the generation of the clock MCLK and output data MDAT in the isolation amplifier 8, and Figure 26 is a timing chart for explaining the operation of the pulse detector 87.

[0202] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with this clock CKI. CKI and DTI in Fig. 25 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 140 and buffers 63 and 64.

[0203] Assume now that we are in a normal state where no abnormality such as excessive input has occurred. In this case, the detection signal FLTN is at L level. Therefore, the outputs of latches L15 and L16 are also at L level, and the output of XOR circuit EX1 remains at L level. Selector SE6 selects output data DTI and outputs it to latch L17. Latch L17 outputs the output data DTI to XOR circuit EX2 at the rising edge of clock CKI.

[0204] Since the output of L16 is at L level, the output of DT3 also becomes L level, and output data DTI is output from the XOR circuit EX2. The output of the XOR circuit EX2 is output as output data MDAT via the buffer 64. Thus, under normal circumstances, the clock CKI and output data DTI are output as they are as the clock MCLK and output data MDAT.

[0205] Next, suppose that an abnormality such as excessive input occurs and the detection signal FLTN changes to H level. FLTN in Figure 25 shows this state. When the detection signal FLTN changes from L level to H level, the output of the XOR circuit EX1 outputs an H level output. The output of the XOR circuit EX1 is captured by the latch L15 at the falling edge of the clock CKI and returned to the input terminal. Therefore, while the detection signal FLTN is at H level, the output of the XOR circuit EX1 changes at every falling edge of the clock CKI. As a result, the output of the latch L15 is also inverted at the falling edge of the clock CKI while the detection signal FLTN is at H level (L15 output in Figure 25).

[0206] Latch L17 takes in the output of selector SE6 at the rising edge of clock CKI and returns it to the input terminal of selector SE6. During the L level period of detection signal FLTN, selector SE6 outputs output data DTI as is, and during the H level period, selector SE6 outputs the output data DTI output by latch L17 one clock before. Therefore, as shown in the latch L17 output in Figure 25, during the detection signal FLTN period, latch L17 outputs the same data for two clock periods.

[0207] Latch L16 captures the output of latch L15 at the rising edge of clock CKI and outputs it to falling edge detector DT3. Therefore, the output of latch L16 is the output of latch L15 delayed by half a clock cycle (L16 output in Figure 25). Falling edge detector DT3 detects the falling edge of latch L16 and outputs an edge detection pulse (DT3 output in Figure 25). XOR circuit EX2 performs an XOR operation on the output of latch L17 and the output of falling edge detector DT3. When the output of latch L16 is at low level, XOR circuit EX2 outputs the data from latch L17 as is, and when the edge detection pulse from latch L16 is at high level, it outputs the inverted data from latch L17. MDAT in Figure 25 shows this, and the level of data D1 is inverted during the period corresponding to the high level of the edge detection pulse.

[0208] The clock MCLK and output data MDAT from the isolation amplifier 8 are supplied to the FPGA 70. As shown in the FPGA of Fig. 25, the FPGA 70 acquires the output data MDAT during the H level period of the clock MCLK.

[0209] The clock MCLK and output data MDAT from the isolation amplifier 8 are also supplied to the pulse detector 87. MCLK and MDAT in Fig. 26 show an example of the clock MCLK and output data MDAT supplied to the pulse detector 87. In the example of Fig. 26, the output data MDAT indicates whether the data value is "0" or "1" by an L level or an H level, and the protruding pulses in MDAT indicate pulse P1 corresponding to a change from L level to H level of the detection signal FLTN, which are added to the data by the mixer 140, and pulse P2 corresponding to a change from H level to L level of the detection signal FLTN.

[0210] The latch L18 of the pulse detector 87 captures the output data MDAT at the rising edge of the clock MCLK and outputs it to the coincidence circuit EX3. As shown in the L18 output in Figure 26, the latch L18 outputs the output data MDAT in synchronization with the rising edge of the clock MCLK.

[0211] The output data MDAT from the isolation amplifier 8 is supplied to the match circuit EX3, and the match circuit EX3 outputs to the AND circuit A9 a match operation result that is H level when the output of the latch L18 matches the input output data MDAT and L level when they do not match. The match operation result from the match circuit EX3 is also inverted and supplied to the latch L19.

[0212] The delay circuit DE4 delays the clock MCLK by a predetermined period and outputs the delayed signal to the latch L19 (DE4 output in FIG. 26). The latch L19 receives the inverted signal of the output from the coincidence circuit EX3 while the output of the delay circuit DE4 is at H level and outputs it to the AND circuit A9, and outputs an L level (logical value "0") to the AND circuit A9 while the output of the delay circuit DE4 is at L level.

[0213] As a result, the latch L19 outputs an output that is approximately the inverse of the output of the match circuit EX3, but which falls with a delay of the delay time of the delay circuit DE4 from the rising timing of the output of the match circuit EX3. Therefore, as shown in the L19 output in Figure 26, the output of latch L19 has a waveform with a H-level period that is slightly wider than the L-level period of the output of the match circuit EX3 at normal data switching timings. On the other hand, at timings corresponding to pulses P1 and P2, which are narrow pulses, the output of delay circuit DE4 goes to L level before rising in response to the rising of pulses P1 and P2, so changes in the waveform due to pulses P1 and P2 do not appear in the output of L19.

[0214] The AND circuit A9 performs an AND operation on the output of the match circuit EX3 and the output of the latch L19. As shown in the A9 output in Figure 26, the output of the AND circuit A9 is a narrow pulse waveform, corresponding to the waveform in which the H-level period of the output of the latch L19 is wider than the L-level period of the match circuit EX3. The output of the AND circuit A9 is also a pulse waveform with a wide H-level period, corresponding to the waveform of the output of the latch L19 in the periods corresponding to the pulses P1 and P2.

[0215] Latch L20 receives the output of AND circuit A9 at the rising edge of clock MCLK and outputs it to OR circuit OR2. The narrow pulse at the output of latch L19 occurs after the rising edge of clock MCLK and does not appear in the output of latch L20. On the other hand, the wide pulse at the output of latch L19 has an H-level period at the rising edge of clock MCLK, and the output of latch L20 has a pulse waveform with a width of one clock cycle corresponding to this wide pulse period (L20 output in Figure 26).

[0216] The OR circuit OR2 performs an OR operation on the output of the AND circuit A9 and the output of the latch L20 to obtain the output shown as OR2 output in FIG. 26. The output of the OR circuit OR2 is provided to the latch L21, which captures and outputs the output of the OR circuit OR2 at the rising edge of the clock MCLK. The output of the latch L21 is the detection result ALM corresponding to the period from pulse P1 to pulse P2, as shown as ALM in FIG. 26. The latch L21 outputs the detection result ALM to the control circuit 90.

[0217] In this way, the same effects as those of the third embodiment can be obtained in this embodiment as well.

[0218] (Ninth embodiment) 27 and 28 are block diagrams showing the ninth embodiment, in which Fig. 27 corresponds to an isolation amplifier with analog output, and Fig. 28 corresponds to an isolation amplifier with digital output.

[0219] In each of the above embodiments, the control circuit required two terminals: a data input terminal for inputting data corresponding to the differential input VIN, and an interrupt terminal for inputting the abnormality detection result. This embodiment makes it possible for the control circuit to take in the data corresponding to the differential input VIN and the abnormality detection result via a single terminal.

[0220] 27, an isolation amplifier 53 is the isolation amplifier 1 or 2 of the first or second embodiment. A differential to single-phase conversion circuit 50 adds output differential signals VOUT+ and VOUT− of the isolation amplifier 53 and outputs the addition result to terminal A of an abnormality detection circuit 51. The abnormality detection circuit 51 is configured with a comparator and compares the addition result A with a reference voltage Vref input to terminal B. The abnormality detection circuit 51 outputs an H level when the level at terminal A is equal to or higher than the level at terminal B, and outputs an L level when the level at terminal A is lower than the level at terminal B. In this embodiment, the abnormality detection circuit 51 outputs the comparison result to a selector 54 as a selection signal.

[0221] The selector 54 also receives the single-phase output AOUT from the differential to single-phase conversion circuit 50, selects and outputs the single-phase output AOUT in response to an L-level selection signal, and selects and outputs a predetermined maximum value in response to an H-level selection signal. The output of the selector 54 is output to the ADC1 terminal of the control circuit 91.

[0222] When a signal of a normal level is input to the ADC1 terminal, the control circuit 91 determines that the input signal is a single-phase output AOUT and processes it accordingly. On the other hand, when a signal of the maximum level that the control circuit 91 can handle is input to the ADC1 terminal, the control circuit 91 determines that the input signal is an abnormality detection result indicating the occurrence of an abnormality and processes it accordingly.

[0223] By adopting the configuration of FIG. 27 in this way, it is possible to transmit data and abnormality detection results to the control circuit through one terminal.

[0224] 28, an isolation amplifier 57, an FPGA 58, and an external circuit 59 are shown to represent the isolation amplifiers 3 to 8, FPGAs 70 and 75, and external circuits 80, 82, and 86 of the third to eighth embodiments, respectively. The external circuit 59 receives the clock MCLK and output data MDAT from the isolation amplifier 57. The external circuit 59 generates a detection result ALM based on the clock MCLK and the output data MDAT.

[0225] In this embodiment, the external circuit 59 outputs the detection result ALM as a selection signal to the selector 92. The selector 92 also receives filtered data from the output terminal DIF of the FPGA 58. The selector 92 selects and outputs data from the FPGA 58 in response to an L-level selection signal, and selects and outputs a predetermined singular value in response to an H-level selection signal. The singular value may be a negative maximum value, for example. The selector 92 outputs the selected output to the DIF terminal of the control circuit 93.

[0226] When a signal of a normal level is input to the DIF terminal, the control circuit 93 determines that the input signal is data from the FPGA 58 and performs processing accordingly. On the other hand, when a signal of a singular value is input to the DIF terminal, the control circuit 93 determines that the input signal is an abnormality detection result indicating the occurrence of an abnormality and performs processing accordingly.

[0227] By adopting the configuration of FIG. 28 in this way, it is possible to transmit data and abnormality detection results to the control circuit via a single terminal.

[0228] (Tenth embodiment) Fig. 29 is a block diagram showing a tenth embodiment. In Fig. 29, the same components as those in Fig. 12 are assigned the same reference numerals and their description will be omitted. The embodiment in Fig. 12 describes an example in which an internal clock (clock MCLK) generated in the secondary circuit 60 of the isolation amplifier 3 is used, but this embodiment shows an example in which an external clock generated externally is used as the clock MCLK.

[0229] The secondary circuit 151 of the isolation amplifier 150 in FIG. 29 differs from the secondary circuit 60 of the isolation amplifier 3 in that the clock recovery circuit 24 and buffer 63 are omitted. The isolation amplifier 150 receives an external clock MCLK as a clock MCLKIN via a clock input terminal. The decoder 61 of the secondary circuit 151 decodes the differential signal transferred from the isolation unit 30 using the clock MCLKIN to generate output data DTI corresponding to the differential input VIN. Similarly to the mixer 62 of the isolation amplifier 3, the mixer 62 of the secondary circuit 151 outputs output data DTO obtained by varying the output data DTI in accordance with the detection signal FLTN. Note that the mixer 62 of the secondary circuit 151 does not output a clock.

[0230] 29, the clock MCLK is generated by a clock generation circuit 156 provided in the FPGA 155. The FPGA 155 differs from the FPGA 70 in that the clock generation circuit 156 is added. The clock generation circuit 156 provides the generated clock MCLK to the latch 71 and also to the clock input terminal of the isolation amplifier 150.

[0231] This embodiment differs from the embodiment of FIG. 12 only in that an external clock is used instead of the built-in clock, and other configurations and operations are the same as those of the embodiment of FIG.

[0232] Although this embodiment has been described as being applied to the third embodiment in FIG. 12, it can be applied to the third to sixth, eighth and ninth embodiments, except for the seventh embodiment in which the clock is processed.

[0233] (Variation) Fig. 30 is a block diagram showing a modified example. In Fig. 30, the same components as those in Fig. 1 are given the same reference numerals and their explanations will be omitted.

[0234] 1, an example has been described in which the detection information is generated by external resistors R1 and R2 and the comparator 15, but a circuit for generating the detection information may also be built in. Figure 30 shows an example of this case.

[0235] The primary circuit 161 of the isolation amplifier 160 in FIG. 30 differs from the primary circuit 10 of the isolation amplifier 1 in that it employs an abnormality detection circuit 162 instead of the comparator 15. Furthermore, in this modification, the resistors R1 and R2 are omitted. The input differential signals VIN+ and VIN- are provided to the abnormality detection circuit 162. The abnormality detection circuit 162 detects the occurrence of an abnormality based on the input differential signals VIN+ and VIN-. For example, the abnormality detection circuit 162 may detect the occurrence of an abnormality by dividing the differential input VIN and comparing it with a predetermined detection voltage VREF. The abnormality detection circuit 162 outputs a detection signal indicating the presence or absence of an abnormality to the secondary circuit 20 via the isolation unit 30.

[0236] The other configurations, functions, and effects are the same as those of the first embodiment.

[0237] The present invention is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the invention. Furthermore, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed multiple constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, if the problem described in the "Problem to be Solved by the Invention" section can be solved and the effect described in the "Effect of the Invention" section can be obtained, the configuration from which these constituent elements are deleted can be extracted as an invention. [Explanation of symbols]

[0238] 1 to 8...isolation amplifier, 10...primary circuit, 11...ΔΣADC, 12...encoder, 13...clock generator, 14...reference voltage generator, 15...comparator, 20, 28, 60...secondary circuit, 21...decoder, 22...1-bit DAC, 23...LPF, 24...clock recovery circuit, 25...reference voltage generator, 26, 27...abnormal input detection output circuit, 30...isolation section, 50...differential to single-phase conversion circuit, 51...abnormal detection circuit, 52, 90...control circuit, 55...motor, 56...motor drive circuit, 61...decoder, 62, 100, 110, 120, 130, 140...mixer, 70, 75...FPGA, 72...LPF, 80, 82, 86...external circuit.

Claims

1. a primary circuit including an analog-to-digital conversion circuit that converts an input signal provided from a device to be detected into a digital signal, and an encoder that encodes and outputs the output of the analog-to-digital conversion circuit; an abnormality detection circuit provided in the primary circuit to detect an abnormality occurring in the input signal and generate a detection signal; an isolation unit that transmits the output of the encoder and the detection signal to the secondary circuit while isolating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, the output circuit including a decoder that receives the output of the encoder and the detection signal transmitted by the isolation unit, performs a decoding process corresponding to the encoding process, and generates an output signal corresponding to the input signal; an abnormal input detection output circuit provided in the secondary circuit, which changes the output signal of the output circuit in accordance with a predetermined rule based on the detection signal to produce the output signal of the secondary circuit; the output circuit includes a digital-to-analog conversion circuit that converts the output of the decoder into an analog signal, and a low-pass filter that limits the high frequency range of the output of the digital-to-analog conversion circuit to generate the output signal; the input signal and the output signal are a pair of differential signals, The abnormal input detection output circuit inputs the detection signal transmitted from the isolation unit without passing through the low-pass filter, detects that an abnormality has occurred from the input detection signal, and changes the levels of both of the pair of differential signals that are the output signals by the same predetermined level during the period in which the detection signal indicates that an abnormality has occurred.

2. an isolation amplifier according to claim 1; a detection circuit that detects the presence or absence of an abnormality in the input signal provided from the device to be detected from the output signal of the isolation amplifier, and outputs the abnormality detection result to a control circuit.

3. a processing circuit that outputs a signal that corresponds to the input signal and is included in the output signal of the isolation amplifier; an output of the processing circuit and a signal indicating that an abnormality has occurred in the input signal based on the abnormality detection result from the detection circuit, and a selector that outputs the selected signal to a common terminal of the control circuit.

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