Package substrate

Abstract

A package substrate according to an embodiment includes an insulating layer, a first outer circuit pattern disposed on an upper surface of the insulating layer, a second outer circuit pattern disposed on a lower surface of the insulating layer, a first connecting portion disposed on an upper surface of a 1-1 circuit pattern of the first outer circuit pattern, a first connection portion disposed on the first connecting portion, a first element disposed on the first connecting portion via the first connection portion, a second connecting portion disposed on a lower surface of a 2-1 circuit pattern of the second outer circuit pattern, a second element attached to the 2-1 circuit pattern via the second connection portion, and a second connecting portion disposed on a lower surface of a 2-2 circuit pattern of the second outer circuit pattern, wherein the first connecting portion is disposed with a first width and a first spacing, and the second connecting portion is disposed with a second width larger than the first width and a second spacing larger than the first spacing.

Description

[Technical Field]

[0001] The embodiment relates to a package substrate. [Background technology]

[0002] As electronic components become smaller, lighter, and more integrated, circuit line widths are becoming finer. In particular, as semiconductor chip design rules move toward nanometer-scale integration, the circuit line widths of package substrates or circuit boards on which semiconductor chips are mounted are becoming finer, down to a few micrometers or less.

[0003] Various processes have been proposed to increase the circuit integration density of circuit boards, i.e., to reduce the circuit line width. SAP (semi-additive process) and MSAP (modified semi-additive process) have been proposed to prevent loss of circuit line width during the etching step to form patterns after copper plating.

[0004] Since then, the Embedded Trace Substrate (ETS) method, which embeds copper foil in an insulating layer, has been used in the industry to realize finer circuit patterns. The ETS method embeds copper foil circuits in an insulating layer instead of forming them on the surface of the insulating layer, which eliminates circuit loss due to etching and is advantageous for finer circuit pitches.

[0005] Meanwhile, efforts have been made recently to develop improved 5th generation (5G) or pre-5G communication systems to meet the demand for wireless data traffic. 5G communication systems use ultra-high frequency (mmWave) bands (sub-6 GHz, 28 GHz, 38 GHz, or higher frequencies) to achieve high data transmission rates.

[0006] In order to mitigate the path loss of radio waves in the ultra-high frequency band and increase the transmission distance of radio waves, 5G communication systems are developing convergence technologies such as beamforming, massive MIMO, and array antennas. Considering that these frequency bands can be configured with hundreds of active antennas, the antenna system becomes relatively large.

[0007] Because these antennas and AP modules are patterned or mounted on a circuit board, low circuit board loss is crucial, which means that the multiple boards that make up an active antenna system—the antenna board, antenna feed board, transceiver board, and baseband board—must be integrated into one compact unit. Summary of the Invention [Problem to be solved by the invention]

[0008] In the embodiments, a package substrate with a new structure and a manufacturing method thereof are provided.

[0009] Furthermore, the embodiments aim to provide a package substrate that is easily adaptable to fine pitches and a method for manufacturing the same.

[0010] Also, the present invention provides a package substrate and a manufacturing method thereof that can minimize the occurrence of warpage by maintaining the balance between both sides of the circuit board.

[0011] Furthermore, the embodiments provide a package substrate and a manufacturing method thereof that can improve the reliability of the connection portion.

[0012] In addition, the present invention provides a circuit board including post bumps directly connected to elements embedded inside an insulating layer, and a package substrate including the same.

[0013] In addition, the embodiments provide a circuit board that is easily adaptable to fine pitches and a package substrate including the same.

[0014] Furthermore, the embodiments provide a circuit board and a package substrate including the same that can minimize the occurrence of warpage by maintaining balance between the top and bottom.

[0015] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0016] A package substrate according to an embodiment includes an insulating layer, a first outer circuit pattern disposed on an upper surface of the insulating layer, a second outer circuit pattern disposed on a lower surface of the insulating layer, a first connecting portion disposed on an upper surface of a 1-1 circuit pattern of the first outer circuit pattern, a first connection portion disposed on the first connecting portion, a first element disposed on the first connecting portion via the first connection portion, a second connecting portion disposed on a lower surface of a 2-1 circuit pattern of the second outer circuit pattern, a second element attached to the 2-1 circuit pattern via the second connection portion, and a second connecting portion disposed on a lower surface of a 2-2 circuit pattern of the second outer circuit pattern, wherein the first connecting portion is disposed with a first width and a first spacing, and the second connecting portion is disposed with a second width larger than the first width and a second spacing larger than the first spacing.

[0017] The insulating layer also includes a first solder resist disposed on the upper surface thereof and including a first opening exposing the first connecting portion, and a second solder resist disposed on the lower surface thereof and exposing the second connecting portion and the second connecting portion, and the first circuit pattern includes a 1-2 circuit pattern covered by the first solder resist.

[0018] It also includes a seed metal layer disposed between the 1-1 circuit pattern and the first connecting portion, and the seed metal layer includes a first portion disposed between the 1-1 circuit pattern and the first connecting portion and a second portion disposed between the 1-2 circuit pattern and the first solder resist.

[0019] The seed metal layer is a seed layer for the first circuit pattern, the second circuit pattern, and the first connection portion.

[0020] The device also includes a first molding layer disposed on the insulating layer and molding the first element, and a second molding layer disposed below the insulating layer and molding the second element, the second molding layer including an opening that exposes a lower surface of the second connecting portion.

[0021] The second connection portion includes a first post bump and a second post bump spaced apart from the first post bump and having a width different from that of the first post bump.

[0022] The upper surface of the first outer circuit pattern is located on the same plane as the upper surface of the insulating layer or is located lower than the upper surface of the insulating layer, and the side surface of the first outer circuit pattern is covered with the insulating layer.

[0023] The first molding layer also includes an open area, which exposes the first element.

[0024] In addition, the first outer circuit pattern protrudes above the upper surface of the insulating layer and is exposed through the open area of ​​the first molding layer, and the bottom surface of the first open area of ​​the first molding layer is positioned higher than the bottom surface of the first outer circuit pattern.

[0025] Additionally, the first open area of ​​the first molding layer includes a first portion adjacent to the first outer circuit pattern and a second portion other than the first portion, and the height of the first portion is different from the height of the second portion. [Effects of the Invention]

[0026] According to the embodiment, a first connection portion is formed on a first circuit pattern of a circuit board, rather than on an under bump metal (UBM) of a first device. The first connection portion may be formed by electroplating using a seed metal layer formed for electroplating the first circuit pattern as a seed layer. Accordingly, in the embodiment, the first connection portion is formed using the seed metal layer of the first circuit pattern, thereby improving the bonding strength between the seed metal layer, the first circuit pattern, and the first connection portion. Furthermore, in the embodiment, the first connection portion is formed on the first circuit pattern, thereby eliminating the need to control the embedding depth of the first circuit pattern having an ETS (Embedded Trace Substrate) structure. Furthermore, the embodiment may solve the non-contact or non-wet issue problem that occurs in the comparative example due to variations in the embedding depth of the first circuit pattern during assembly of the first device and the circuit board.

[0027] In addition, in the embodiment, since there is no need to control the embedding depth of the first circuit pattern, the spacing between the first connecting portions or the spacing between the first circuit patterns can be reduced, thereby enabling support for fine pitches.In addition, in the embodiment, the size width and spacing of the first connecting portions can be reduced, making it possible to utilize the present invention for fine bump products, thereby ensuring design freedom through space savings.

[0028] In addition, in the embodiment, the first connecting part is arranged on the upper side of the insulating layer, and the second connecting part is arranged on the lower side of the insulating layer, thereby making it possible to make the balance between the upper and lower parts of the package substrate uniform, thereby improving the warpage characteristics of the package substrate.

[0029] In addition, in the embodiment, the device and main board are attached using the first and second connecting parts, which eliminates the need to ensure the collapse height of the solder balls compared to solder ball bonding methods, thereby reducing product volume. In addition, in the embodiment, the device and main board are attached using the first and second connecting parts, which have higher thermal conductivity than solder balls. As a result, in the embodiment, the transfer characteristics of heat generated in the device and motherboard can be improved, thereby improving heat dissipation characteristics.

[0030] In addition, in the embodiment, first post bumps constituting second connecting portions are formed on the circuit board, and the main board is attached using the post bumps to manufacture the package substrate, thereby enabling fine pitches to be accommodated and maximizing the productivity of manufacturers.

[0031] In addition, in the embodiment, elements are mounted on both sides of the circuit board, and a molding part is disposed to mold the mounted elements. This makes it possible to maintain balance between the top and bottom of the printed circuit board compared to existing cross-sectional molding structures, thereby minimizing the occurrence of warpage of the circuit board.

[0032] In addition, according to the embodiment, by mounting elements on both sides of the circuit board, active elements or passive elements that are mounted in an existing upper package can all be mounted on the circuit board, thereby reducing the overall thickness of the package substrate.

[0033] In addition, according to this embodiment, the lower surface of the lower molding part to which the main board is attached is placed on the same plane as the lower surface of the device mounted on the lower part of the circuit board, thereby improving the connection reliability between the main board and the circuit board.

[0034] In addition, in the embodiment, a device embedded in a circuit board is connected to a main board using second post bumps constituting a second connecting portion. Thus, in the embodiment, a fine pitch can be accommodated by using a plurality of second post bumps corresponding to the pitch of the terminals of the embedded device. In the embodiment, the device and the main board are connected via the second post bumps, thereby improving heat dissipation characteristics. In the embodiment, the embedded device and the main board are connected via the second post bumps, thereby reducing the signal transmission distance between the embedded device and the main board, thereby improving noise characteristics and transmission speed.

[0035] Furthermore, according to this embodiment, the height of the first post bumps can be adjusted by the height of the element, which makes it easy to design the package.

[0036] In addition, according to the embodiment, a separate seed layer for electroplating the first and second post bumps constituting the second connection portion is not formed, and the post bumps are formed using the seed layer of the pad. This simplifies the manufacturing process because there is no need to form a separate seed layer for forming the post bumps, and it is possible to prevent cracks from occurring between the seed layers of the post bumps, thereby improving the reliability and durability of the product. [Brief explanation of the drawings]

[0037] [Figure 1] FIG. 10 is a diagram showing a package substrate according to a comparative example. [Figure 2] 1A and 1B are diagrams illustrating a package substrate of a first form according to a first embodiment. [Figure 3] FIG. 10 is a diagram showing a package substrate of a second type according to the first embodiment. [Figure 4] 10A and 10B are diagrams illustrating a package substrate of a third type according to the first embodiment. [Figure 5] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 6] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 7] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 8] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 9] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 10] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 11] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 12] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 13] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 14] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 15] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 16] FIG. 10 is a diagram showing a printed circuit board according to a second embodiment. [Figure 17a] FIG. 17 shows an open area of ​​the first molding layer of FIG. 16 according to the first embodiment. [Figure 17b] FIG. 17 shows an open area of ​​the first molding layer of FIG. 16 according to the first embodiment. [Figure 18] FIG. 17 shows an open area of ​​the first molding layer of FIG. 16 according to the second embodiment. [Figure 19] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 20] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 21] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 22] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 23]2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 24] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 25] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 26] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 27] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 28] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 29] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 30] FIG. 10 is a diagram showing a package substrate according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0038] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0039] However, the technical concept of the present invention is not limited to the several embodiments described, but may be realized in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0040] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention are interpreted as meanings that can be commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs, and commonly used terms such as predefined terms can be interpreted in consideration of the contextual meaning of the related art. Furthermore, the terms used in the embodiments of the present invention are intended to explain the embodiments and are not intended to limit the present invention.

[0041] In this specification, unless otherwise specified, the singular form can also include the plural form, and when it is stated as "A and (and) at least one (or more) of B and C," it can include one or more of all combinations of A, B, and C. Furthermore, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used.

[0042] Such terms are used only to distinguish a component from other components, and do not limit the essence, order, or procedure of the components. Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it includes not only the case where the component is directly coupled or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" between the other component and the other component or by another component.

[0043] Furthermore, when it is stated that something is formed or disposed "above (upper) or below (lower)" a component, the above (upper) or below (lower) includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components. Furthermore, when it is expressed as "above (upper) or below (lower)," it can mean not only the upper direction but also the lower direction based on one component.

[0044] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] FIG. 1 is a diagram showing a package substrate of a comparative example.

[0046] Referring to FIG. 1, the comparative example package substrate includes an insulating layer 10, a first circuit pattern 20, a second circuit pattern 25, a via 30, a first solder resist 40, a second solder resist 45, a first connection portion 50, a second connecting portion 55, an element 60, a UBM (Under Bump Metal) 65, and a connecting portion 70.

[0047] The comparative example package substrate includes a circuit board manufactured by the ETS method.

[0048] Therefore, the paging substrate includes an insulating layer 10 and circuit patterns disposed on both sides of the insulating layer 10, respectively.

[0049] In this case, the circuit pattern includes a first circuit pattern 20 disposed on one side of the insulating layer 10 and a second circuit pattern 25 disposed on the other side of the insulating layer 10. One of the first circuit pattern 20 and the second circuit pattern 25 has a structure embedded in the insulating layer 10.

[0050] A via 30 is formed in the insulating layer 10 to electrically connect the first circuit pattern 20 and the second circuit pattern 25 .

[0051] On the upper and lower surfaces of the insulating layer 10, a first solder resist 40 and a second solder resist 45 are disposed to protect the surface of the insulating layer 10 and the surface of the first circuit pattern 20 or the second circuit pattern 25.

[0052] The first solder resist 40 includes an opening (not shown) that exposes the upper surface of the first circuit pattern 20, and the second solder resist 45 includes an opening (not shown) that exposes the lower surface of the second circuit pattern 25.

[0053] Meanwhile, the package substrate of the comparative example includes a device 60 mounted on the first circuit pattern 20. At this time, an under bump metal (UBM) 65 is formed on the bottom surface of the device 60. In addition, a connecting portion 70 is formed under the under bump metal (UBM) 65. The connecting portion 70 is generally referred to as a copper filler (Cu pillar).

[0054] In the package substrate of the comparative example, the element 60 is mounted by forming the connecting portion 70 on the element 60 and then forming a first connection portion 50 between the first circuit pattern 20 and the connecting portion 70.

[0055] That is, the device mounting in the package substrate of the comparative example is performed by forming a connection part 70 on the UBM (Under Bump Metal) 65 of the device 60 instead of on the circuit board, and then soldering the connection part 70 of the device 60 to the first circuit pattern 20 of the circuit board through a device attachment process.

[0056] However, although the structure of the connecting portion included in the package substrate of this comparative example can reduce the thickness of the package, it places many restrictions on the device mounting space during design and has problems with weak warpage characteristics.

[0057] Specifically, the package substrate of the comparative example has a connecting portion 70 formed on the device 60. In this case, the connecting portion 70 is formed on only one side of the package substrate, and no corresponding connecting portion is formed on the other side. In other words, the package substrate of the comparative example has an asymmetric structure in which the connecting portion is disposed on only one side of the insulating layer 10, which causes a problem of poor warpage due to imbalance between the top and bottom of the package substrate.

[0058] In addition, in the package substrate of the comparative example, when soldering to the device, the contact area between the first circuit pattern 20 is small depending on the degree of embedding of the first circuit pattern 20, which may cause problems with the connection reliability with the first connection part 50.

[0059] Furthermore, in the comparative example package substrate, if the contact area between the first circuit pattern 20 and the first connection portion 50 is small, the possibility of cracks occurring due to thermal stress or physical damage increases, which may cause reliability problems.

[0060] As a result, the embodiment can provide a package substrate with a new structure that can solve the reliability problems of the package substrate of the comparative example.

[0061] FIG. 2 is a diagram showing a package substrate of a first type according to an embodiment.

[0062] Referring to FIG. 2, the first type of package substrate 100 includes an insulating layer 110, a first circuit pattern 120, a second circuit pattern 125, a via 130, a seed metal layer 140, a first solder resist 160, a second solder resist 165, a first connecting portion 170, a second connecting portion 175, a first connecting portion 180, and a second connecting portion 185.

[0063] The package substrate 100 of the first type includes a first element 200 and a second element 300, each having an underbump metal (UBM) 210 formed on its bottom surface.

[0064] Prior to describing FIG. 2, the package substrate according to the embodiment may have a multi-layer structure based on the insulating layer of the circuit board. That is, although the circuit board in FIG. 2 is illustrated as including a single insulating layer, this is not limited thereto. For example, the package substrate according to the embodiment may include a circuit board having a laminated structure of multiple insulating layers. For example, the insulating layer 110 of the package substrate 100 may have a multi-layer structure. When the insulating layer 110 has a multi-layer structure, the first circuit pattern 120 may be disposed on the upper surface of the uppermost insulating layer of the multi-layer structure, and the second circuit pattern 125 may be disposed on the lower surface of the lowermost insulating layer of the multi-layer structure. For example, the first circuit pattern 120 may be referred to as a first outer circuit pattern disposed on the uppermost side or first outermost side of the circuit board. The second circuit pattern 125 may be referred to as a second outer circuit pattern disposed on the lowermost side or second outermost side of the circuit board.

[0065] For the sake of convenience, the following description will be given assuming that the insulating layer 110 is formed as a single layer.

[0066] A circuit pattern may be disposed on the surface of the insulating layer 110 .

[0067] For example, a first circuit pattern 120 may be formed on an upper surface of the insulating layer 110. Also, a second circuit pattern 125 may be formed on a lower surface of the insulating layer 110.

[0068] The first circuit pattern 120 may be embedded in the insulating layer 110. For example, the first circuit pattern 120 may have an ETS (Embedded Trace Substrate) structure. For example, the side of the first circuit pattern 120 may be surrounded by the insulating layer 110. For example, the top surface of the first circuit pattern 120 may be flush with the top surface of the insulating layer 110 or may be lower than the top surface of the insulating layer 110. For example, the bottom surface of the first circuit pattern 120 may be lower than the top surface of the insulating layer 110.

[0069] The second circuit pattern 125 may be disposed to protrude below the lower surface of the insulating layer 110. That is, the upper surface of the second circuit pattern 125 may be in direct contact with the lower surface of the insulating layer 110. However, the embodiment is not limited thereto, and a seed metal layer (not shown) of the second circuit pattern 125 may be disposed between the upper surface of the second circuit pattern 125 and the lower surface of the insulating layer 110.

[0070] That is, the package substrate in the embodiment is manufactured using the ETS method, whereby the first circuit pattern 120 can have a structure embedded in the insulating layer 110, and the second circuit pattern 125 can have a structure protruding above the surface of the insulating layer 110.

[0071] The first circuit pattern 120 and the second circuit pattern 125 are wirings that transmit electrical signals and may be formed of a highly conductive metal material. To this end, the first circuit pattern 120 and the second circuit pattern 125 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit pattern 120 and the second circuit pattern 125 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern 120 and the second circuit pattern 125 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0072] Meanwhile, the first circuit pattern 120 and the second circuit pattern 125 are each configured as a plurality of patterns. For example, the first circuit pattern 120 can be referred to as a 1-1 circuit pattern connected to the first connecting portion 170. The first circuit pattern 120 can also include a 1-2 circuit pattern covered with the first solder resist 160. For example, the second circuit pattern 125 can include a 2-1 circuit pattern on which the second connecting portion 185 is disposed and the second element 300 is mounted. For example, the second circuit pattern 125 can include a 2-2 circuit pattern on which the second connecting portion 175 is disposed.

[0073] Vias 130 may be disposed within the insulating layer 110. The vias 130 may be disposed within the insulating layer 110, thereby electrically connecting circuit patterns disposed on different layers to each other.

[0074] That is, the via 130 may be disposed in the insulating layer 110 , and may have an upper surface connected to the lower surface of the first circuit pattern 120 and a lower surface connected to the upper surface of the second circuit pattern 125 .

[0075] The via 130 may be formed by filling the interior of a via hole (not shown) formed in the insulating layer 110 with a metal material.

[0076] The metal material forming the via 130 may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material may be performed using any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink-jetting, and dispensing.

[0077] A seed metal layer 140 is disposed on top of the insulating layer 110 .

[0078] The seed metal layer 140 may be a seed layer used to form the first circuit pattern 120 by electroplating. Also, the seed metal layer 140 may be a seed layer used to form the first connecting portion 170 (described later) by electroplating. That is, the seed metal layer 140 may be a seed layer for the first circuit pattern 120 and a seed layer for the first connecting portion 170.

[0079] That is, the seed metal layer 140 may be disposed between the first circuit pattern 120 and the first connecting portion 170. The first circuit pattern 120 may be formed by electroplating using the seed metal layer 140. The first connecting portion 170 may be formed by electroplating using the seed metal layer 140, which is the same seed layer as the first circuit pattern 120.

[0080] The seed metal layer 140 may be formed by a chemical copper plating process. The seed metal layer 140 may have a thin film form and may be formed on the upper surface of the insulating layer 110. However, the embodiment is not limited thereto, and the seed metal layer 140 may be a copper foil layer (not shown) included in a carrier board (not shown) used in manufacturing the circuit board.

[0081] In this case, the seed metal layer 140 includes a first portion disposed between the first circuit pattern 120 and the first connecting portion 170. The first portion of the seed metal layer 140 may have a lower surface and an upper surface having the same width. For example, the lower surface of the first portion of the seed metal layer 140 may have the same width as the upper surface of the first circuit pattern 120. For example, the upper surface of the first portion of the seed metal layer 140 may have the same width as the lower surface of the first connecting portion 170. As a result, the first circuit pattern 120, the first portion of the seed metal layer 140, and the first circuit pattern 120 may have a pillar shape and be formed to protrude from the inside to the outside of the insulating layer 110.

[0082] Meanwhile, the seed metal layer 140 may include a second portion disposed between the first circuit pattern 120 and the first solder resist 160. In this case, the width of a typical seed metal layer is the same as the width of the circuit pattern. This is because the seed metal layer is used to form the circuit pattern by electroplating and is removed once the electroplating process of the circuit pattern is completed. That is, the circuit pattern is disposed on the seed metal layer, and once the formation of the circuit pattern is completed, the seed metal layer in the area where the circuit pattern is not disposed is removed, resulting in the circuit pattern and the seed metal layer having the same width.

[0083] Alternatively, in the embodiment, the first connecting portion 170 is formed using the seed metal layer 140 after the first solder resist 160 is formed. Then, after the first connecting portion 170 is formed, the seed metal layer in the region where the first solder resist 160 and the first connecting portion 170 are not formed is removed. As a result, in the embodiment, the second portion of the seed metal layer 140 may have a width different from that of the second circuit pattern 125. That is, the lower surface of the second portion of the seed metal layer 140 directly contacts the first circuit pattern 120. And the upper surface of the second portion of the seed metal layer 140 directly contacts the first solder resist 160. In this case, the second portion of the seed metal layer 140 may have a width larger than that of the first circuit pattern 120 with which it is in contact. Also, the second portion of the seed metal layer 140 may have a width equal to or smaller than that of the first solder resist 160 with which it is in contact. For example, the second portion of the seed metal layer 140 may be formed to be larger than the width of the first circuit pattern 120 that it contacts and smaller than the width of the first solder resist 160 that it contacts.

[0084] As described above, in the embodiment, the first circuit pattern 120 and the first connecting portion 170 are formed using the seed metal layer 140. As a result, in the embodiment, a separate seed layer for forming the first connecting portion 170 and a process for removing the seed layer are not required, thereby simplifying the manufacturing process.

[0085] In addition, in the embodiment, the first connecting portion 170 is formed using the seed metal layer 140, thereby improving the bonding strength between the first circuit pattern 120 and the first connecting portion 170. That is, in the embodiment, the seed metal layer 140 is formed, and then an electroplating process is performed to form the first circuit pattern 120. As a result, the first connecting portion 170 is formed using the seed metal layer 140 as a seed layer. In the comparative example, an additional seed metal layer is formed on the first circuit pattern by performing a chemical copper plating process. The bonding strength of the seed metal layer formed by the additional process is lower than the bonding strength between the first circuit pattern 120 and the seed metal layer 140 in the embodiment. This is because, in the embodiment, the first circuit pattern 120 is formed after the seed metal layer 140 is formed, and has a thickness greater than that of the seed metal layer 140, whereas in the comparative example, the seed metal layer is formed after the circuit pattern is formed, and has a thickness less than that of the seed metal layer 140.

[0086] First connectors 170 are formed on the top surface of the first portion of the seed metal layer 140. The first connectors 170 may be formed in plurality on the seed metal layer 140 at regular intervals. The first connectors 170 may be copper pillars. The first connectors 170 may be connected to an under bump metal (UBM) 210 of the first element 200. Thus, the first connectors 170 may be formed on the seed metal layer 140 with a first width and a first spacing. The first width may be the same as the width and spacing of the first circuit patterns 120. For example, the first connectors 170 may be disposed on the top surface of the seed metal layer 140 with a first width of 10 μm or less and a first spacing of 10 μm or less.

[0087] The second connecting portion 175 may be formed below the lower surface of the second circuit pattern 125. The second connecting portion 175 may be disposed in an opening (not shown) of a second solder resist 165 formed on the lower surface of the insulating layer 110. The second connecting portion 175 may be formed to have a structure that protrudes below the lower surface of the second solder resist 165.

[0088] The second connecting portion 175 may be formed in a plurality of portions spaced apart from each other at regular intervals.

[0089] The second connecting portions 175 may be arranged to have a second width and a second spacing. For example, the second width may be larger than the first width of the first connecting portions 170. Furthermore, the second spacing may be larger than the first spacing of the first connecting portions 170.

[0090] A first connecting portion 180 may be disposed on an upper surface of the first connecting portion 170. A second connecting portion 185 may be disposed on a lower surface of the second circuit pattern 125.

[0091] The first connecting portion 180 and the second connecting portion 185 may have a circular or elliptical shape, but are not limited thereto.

[0092] The first connection portion 180 and the second connection portion 185 may include at least one of silver copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), bismuth (Bi), silver (Ag), and nickel (Ni). For example, the first connection portion 180 and the second connection portion 185 may be solder bumps. For example, the first connection portion 180 and the second connection portion 185 may be solder balls, which may melt at the temperature of a reflow process.

[0093] A first element 200 may be attached on the first connection part 180. Also, a second element 300 may be attached below the second connection part 185.

[0094] At this time, an under bump metal (UBM) 210 may be formed between the first connecting part 180 and the contact surface of the first element 200. That is, the under bump metal (UBM) 210 is formed on the lower surface of the first element 200. The first element 200 may be attached to the first connecting part 170 by performing a soldering process with the position of the under bump metal (UBM) 210 aligned on the first connecting part 180.

[0095] According to the embodiment, the first connection portion is formed on the first circuit pattern of the circuit board, rather than on the UBM (Under Bump Metal) of the first device. The first connection portion may be formed by electroplating using a seed metal layer formed for electroplating the first circuit pattern as a seed layer. Accordingly, in the embodiment, the first connection portion is formed using the seed metal layer of the first circuit pattern, thereby improving the bonding strength between the seed metal layer, the first circuit pattern, and the first connection portion. Furthermore, in the embodiment, the first connection portion is formed on the first circuit pattern, which eliminates the need to control the embedding depth of the first circuit pattern having an ETS (Embedded Trace Substrate) structure. Furthermore, the embodiment may solve the non-contact or non-wet issue problem that occurs in the comparative example due to variations in the embedding depth of the first circuit pattern during assembly of the first device and the circuit board.

[0096] In addition, in the embodiment, since there is no need to control the embedding depth of the first circuit pattern, the spacing between the first connecting portions or the spacing between the first circuit patterns can be reduced, thereby enabling fine pitches to be accommodated.In addition, in the embodiment, the size width and spacing of the first connecting portions can be reduced, making it possible to utilize the device for fine bump products, thereby securing space and ensuring design freedom.

[0097] In addition, in the embodiment, the first connecting part is arranged on the upper side of the insulating layer, and the second connecting part is arranged on the lower side of the insulating layer, thereby making it possible to make the balance between the upper and lower parts of the package substrate uniform, thereby improving the warpage characteristics of the package substrate.

[0098] In addition, in the embodiment, the device and main board are attached using the first and second connecting parts, which eliminates the need to ensure the collapse height of the solder balls compared to solder ball bonding methods, thereby reducing product volume. In addition, in the embodiment, the device and main board are attached using the first and second connecting parts, which have higher thermal conductivity than solder balls. As a result, in the embodiment, the transfer characteristics of heat generated in the device and motherboard can be improved, thereby improving heat dissipation characteristics.

[0099] FIG. 3 is a diagram showing a package substrate of a second type according to the embodiment.

[0100] Referring to FIG. 3, the package substrate may further include a molding layer compared to FIG.

[0101] That is, the second type package substrate 100B includes a first molding layer 190 and a second molding layer 195.

[0102] A first molding layer 190 may be formed on the top surface of the insulating layer 110 and the top surface of the first solder resist 160 .

[0103] The first molding layer 190 may be disposed to cover the components disposed on the upper side of the insulating layer 110. That is, the first molding layer 190 may be formed by embedding the seed metal layer 140, the first solder resist 160, the first connecting portion 170, the first connecting portion 180, the first element 200, and the UBM (Under Bump Metal) 210 disposed on the upper surface of the insulating layer 110.

[0104] As described above, the first molding layer 190 may be formed by embedding the first solder resist 160 therein.

[0105] The second molding layer 195 may be disposed to cover the components disposed below the insulating layer 110. That is, the second molding layer 195 may be formed by embedding the second connecting part 175, the second connecting part 185, and the second element 300 disposed below the lower surface of the insulating layer 110. However, the second molding layer 195 may include an opening (not shown) exposing the lower surface of the second connecting part 175.

[0106] FIG. 4 is a diagram showing a package substrate of a third embodiment according to the present invention.

[0107] Referring to FIG. 4, the package substrate may further include a lower substrate compared to FIG.

[0108] That is, the third type package substrate 100C may include a third connection part 410 and a lower substrate 400.

[0109] The third connecting portion 410 may be a solder ball and may be formed below the lower surface of the second connecting portion 175 exposed through the opening in the second molding layer 195.

[0110] A lower substrate 400 may be attached below the third connection part 410. The lower substrate 400 may be, but is not limited to, a main board.

[0111] For example, the lower substrate 400 may be any one of a plurality of substrates constituting an active antenna system in a 5G package substrate, i.e., an antenna substrate, an antenna feed substrate, a transceiver substrate, and a baseband substrate.

[0112] The method for manufacturing a package substrate according to the embodiment will be described below in the order of steps.

[0113] 5 to 15 are diagrams showing the manufacturing method of the manufacturing substrate shown in FIG. 4 in the order of steps.

[0114] Referring to FIG. 5, in this embodiment, a carrier board CB is first prepared as a base material for manufacturing a circuit board. The carrier board CB may include a carrier insulating layer CB1 and a carrier metal layer CB2 disposed on one side of the carrier insulating layer CB1. While the drawing shows the carrier metal layer CB2 disposed only on one side of the carrier insulating layer CB1, this is not limiting. That is, the carrier metal layer may be formed on both the upper and lower sides of the carrier insulating layer CB1, thereby enabling multiple circuit boards to be simultaneously manufactured on both sides of the carrier insulating layer CB1 in this embodiment.

[0115] 6, in this embodiment, a seed metal layer 140 is formed under the carrier metal layer CB2. The seed metal layer 140 may be formed by a chemical copper plating process, but is not limited thereto.

[0116] After the seed metal layer 140 is formed, in an embodiment, a first mask M1 is formed on the seed metal layer 140. Then, in an embodiment, the first mask M1 is exposed and developed to form an opening (not shown) in the first mask M1. The opening may be formed by exposing the lower surface of the seed metal layer 140 at a position where the first circuit pattern 120 is to be formed.

[0117] After the first mask M1 is formed, in this embodiment, electroplating is performed using the seed metal layer 140 as a seed layer to form a first circuit pattern 120 that fills the openings of the first mask M1.

[0118] Next, referring to FIG. 7, in an embodiment, the first mask M1 is removed, thereby forming an insulating layer 110 covering the first circuit pattern 120 under the seed metal layer 140.

[0119] After the insulating layer 110 is formed, in the embodiment, the via 130 is formed in the insulating layer 110. Also, in the embodiment, the second circuit pattern 125 connected to the via 130 is formed on the lower surface of the insulating layer 110.

[0120] The second circuit pattern 125 may be disposed to protrude below the lower surface of the insulating layer 110. That is, the upper surface of the second circuit pattern 125 may be in direct contact with the lower surface of the insulating layer 110. However, the embodiment is not limited thereto, and a seed metal layer (not shown) of the second circuit pattern 125 may be disposed between the upper surface of the second circuit pattern 125 and the lower surface of the insulating layer 110.

[0121] That is, the package substrate in the embodiment is manufactured using the ETS method, whereby the first circuit pattern 120 can have a structure embedded in the insulating layer 110, and the second circuit pattern 125 can have a structure protruding above the surface of the insulating layer 110.

[0122] That is, the via 130 may be disposed in the insulating layer 110, with an upper surface connected to a lower surface of the first circuit pattern 120 and a lower surface connected to an upper surface of the second circuit pattern 125. The via 130 may be formed by filling the inside of a via hole (not shown) formed in the insulating layer 110 with a metal material.

[0123] 8, in this embodiment, a second solder resist 165 is formed under the lower surface of the insulating layer 110. The second solder resist 165 may have openings that open portions of the lower surface of the second circuit pattern 125 that should be exposed.

[0124] 9, a second mask M2 is formed under the lower surface of the second solder resist 165. The second mask M2 may include an opening (not shown) that exposes the lower surface of the second circuit pattern 125 at a position where the second connection portion 175 will be formed through an exposure and development process.

[0125] When the openings of the second mask M2 are formed, the second connecting portions 175 are formed under the lower surface of the second circuit pattern 125 exposed through the openings.

[0126] 10, in an embodiment, a process of removing the second mask M2 and a process of removing the carrier board CB may be performed. After the process of removing the carrier board CB is performed, the top surface of the seed metal layer 140 used as a seed layer for the first circuit pattern 120 may be exposed.

[0127] 11, in an embodiment, a process of forming a first solder resist 160 on the seed metal layer 140 may be performed. The first solder resist 160 may include an opening portion (not shown) that opens an area to be exposed on the top surface of the seed metal layer 140.

[0128] 12, in an embodiment, a process of forming a third mask M3 on the first solder resist 160 and the seed metal layer 140 may be performed. The third mask M3 may include an opening (not shown) that exposes the top surface of the seed metal layer 140 at a position where the first connection portion 170 will be formed through an exposure and development process.

[0129] After the openings of the third mask M3 are formed, electroplating may be performed on the upper surface of the seed metal layer 140 exposed through the openings to form the first connector 170. The first connector 170 may be formed by electroplating using the seed metal layer 140 as a seed layer. The seed metal layer 140 is also used as a seed layer for the first circuit pattern 120 as described above, and in this embodiment, the seed metal layer 140 is used as a seed layer, and the first circuit pattern 120 and the first connector 170 are formed on both sides of the seed metal layer 140.

[0130] Next, referring to FIG. 13, in an embodiment, a process can be performed in which the third mask M3 is removed, thereby removing the seed metal layer 140 in areas where the first solder resist 160 and the first connecting portion 170 are not formed.

[0131] 14, in an embodiment, a process of attaching a first element 200 may be performed by disposing a first connection part 180 on the first connection part 170. In addition, in an embodiment, a process of attaching a second element 300 may be performed by disposing a second connection part 185 under the lower surface of the second circuit pattern 125 exposed through the opening of the second solder resist 165.

[0132] Next, referring to FIG. 15, in an embodiment, steps of forming a first molding layer 190 and a second molding layer 195 may be performed.

[0133] The first molding layer 190 may be formed on the upper surface of the insulating layer 110 and the upper surface of the first solder resist 160. The first molding layer 190 may be disposed to cover the components disposed on the upper side of the insulating layer 110. That is, the first molding layer 190 may be formed by embedding the seed metal layer 140, the first solder resist 160, the first connecting portion 170, the first connection portion 180, the first element 200, and the UBM (Under Bump Metal) 210, which are disposed on the upper surface of the insulating layer 110. As described above, the first molding layer 190 may be formed by embedding the first solder resist 160.

[0134] The second molding layer 195 may be disposed to cover the components disposed below the insulating layer 110. That is, the second molding layer 195 may be formed by embedding the second connecting part 175, the second connecting part 185, and the second element 300 disposed below the lower surface of the insulating layer 110. However, the second molding layer 195 may include an opening (not shown) exposing the lower surface of the second connecting part 175.

[0135] In addition, in this embodiment, a third connecting portion 410 may be formed under the lower surface of the second connecting portion 175, and a process of attaching the lower substrate 400 may be performed using the third connecting portion 410.

[0136] FIG. 16 is a diagram showing a circuit board according to the second embodiment.

[0137] The circuit board in the first embodiment was manufactured using the ETS process. In contrast, the circuit board in the second embodiment of FIG. 16 can be manufactured using either the MSAP (Modified Semi-Additive Process) or the SAP (Semi-Additive Process). This allows each of the circuit patterns arranged on the outermost side of the circuit board in the second embodiment to have a structure that protrudes above the surface of the insulating layer.

[0138] 16 , the circuit board according to the embodiment includes a first insulating layer 1101, a second insulating layer 1102, a third insulating layer 1103, a first circuit pattern 1111, a second circuit pattern 1112, a third circuit pattern 1113, a fourth circuit pattern 1114, a first via 1121, a second via 1122, a third via 1123, a first element C1, a second element C2, a third element C3, a first post bump 1150, a second post bump 1160, a first connecting portion 1141, a second connecting portion 1142, a first molding layer 1131, and a second molding layer 1133. The first post bump 1150 and the second post bump 1160 may correspond to the second connecting portion 175 of the first embodiment. For example, according to the second embodiment, the second connecting portion disposed on the bottom side of the circuit board may include a plurality of post bumps having different widths.

[0139] In the circuit board of the second embodiment, the first insulating layer 1101 may be a core substrate. The second insulating layer 1102 and the third insulating layer 1103 may be disposed above and below the first insulating layer 1101, respectively. In this regard, although the second embodiment shows a three-layer structure for the insulating layer, this is not limiting. For example, the number of insulating layers in the second embodiment may be one or two, or may be four or more.

[0140] Circuit patterns may be disposed on the surfaces of the first insulating layer 1101, the second insulating layer 1102, and the third insulating layer 1103. The circuit patterns may include a first circuit pattern 1111, a second circuit pattern 1112, a third circuit pattern 1113, and a fourth circuit pattern 1114.

[0141] The first circuit pattern 1111 may be disposed on the upper surface of the first insulating layer 1101. The second circuit pattern 1112 may be disposed on the lower surface of the first insulating layer 1101. The third circuit pattern 1113 may be disposed on the upper surface of the second insulating layer 1102. The fourth circuit pattern 1114 may be disposed on the lower surface of the third insulating layer 1103. The third circuit pattern 1113 may refer to a circuit pattern disposed on the upper surface of the uppermost insulating layer in the laminated structure of insulating layers of a circuit board. For example, the third circuit pattern 1113 may also be referred to as a first outer circuit pattern. The fourth circuit pattern 1114 may refer to a circuit pattern disposed on the lower surface of the lowermost insulating layer in the laminated structure of insulating layers of a circuit board. For example, the fourth circuit pattern 1114 may also be referred to as a second outer circuit pattern disposed on the lowermost insulating layer.

[0142] The third circuit pattern 1113 corresponding to the first outer circuit pattern may include a first pad 1113a on which the second component C2 is mounted. The fourth circuit pattern 1114 may include a second pad (not shown) on which the third component C3 is mounted. The fourth circuit pattern 1114 may also include a 4-1 pattern and a 4-2 pattern arranged to overlap the first terminal T1 of the first component C1 in the vertical direction. A first post bump 1150 (described below) may be arranged below the bottom surface of the 4-2 pattern of the fourth circuit pattern 1114, and the second post bump 1160 may be arranged below the 4-1 pattern of the fourth circuit pattern 1114.

[0143] In this case, the first pad 1113a may correspond to the first circuit pattern 120 on which elements are mounted on the circuit board of the first embodiment. For example, the first connector 170, which is disposed on the upper surface of the first circuit pattern 120 in the first embodiment, may be disposed on the upper surface of the first pad 1113a in the second embodiment.

[0144] Vias are disposed in each of the insulating layers. Specifically, vias may be formed in and through the first insulating layer 1101, the second insulating layer 1102, and the third insulating layer 1103.

[0145] Specifically, a first via 1121 is disposed in the first insulating layer 1101. The first via 1121 electrically connects a first circuit pattern 1111 disposed on the upper surface of the first insulating layer 1101 to a second circuit pattern 1112 disposed on the lower surface of the first insulating layer 1101.

[0146] A second via 1122 is disposed in the second insulating layer 1102. The second via 1122 electrically connects a third circuit pattern 1113 disposed on the upper surface of the second insulating layer 1102 to the first circuit pattern 1111 disposed on the upper surface of the first insulating layer 1101.

[0147] A third via 1123 is disposed in the third insulating layer 1103. The third via 1123 electrically connects a second circuit pattern 1112 disposed on the lower surface of the first insulating layer 1101 to a fourth circuit pattern 1114 disposed on the lower surface of the third insulating layer 1103.

[0148] A first element C1 is embedded in the first insulating layer 1101. The first element C1 may be embedded in the first insulating layer 1101, with at least a portion thereof exposed below the lower surface of the first insulating layer 1101. For example, the first element C1 includes a first terminal T1. The first terminal T1 of the first element C1 may be disposed to protrude below the lower surface of the first insulating layer 1101. As a result, at least a portion of the first terminal T1 of the first element C1 may be covered by the third insulating layer 1103.

[0149] For example, the top surface of the first terminal T1 of the first element C1 may be flush with the top surface of the second circuit pattern 1112.

[0150] As a result, the first terminal T1 of the first component C1 may be directly connected to the third via 1123 disposed in the third insulating layer 1103. As described above, by directly connecting the first terminal T1 of the first component C1 to the third via 1123 without a separate connection pad connected to the first terminal T1 of the first component C1, in this embodiment, the wiring length of the electrical signal transmitted through the first component C1 may be minimized, thereby improving the transmission speed and noise characteristics.

[0151] The first element C1 may be an electronic component such as a chip, which may be classified as an active element or a passive element. An active element is an element that actively utilizes nonlinear components, while a passive element is an element that has both linear and nonlinear characteristics but does not utilize nonlinear characteristics. The active element may include a transistor, an IC semiconductor chip, etc., while the passive element may include a capacitor, a resistor, and an inductor. The passive element may increase the signal processing speed of the semiconductor chip, which is an active element, or perform a filtering function.

[0152] A second element C2 is mounted on the second insulating layer 1102. Specifically, the second element C2 is mounted on a first pad 1113a of a third circuit pattern 1113 disposed on the upper surface of the second insulating layer 1102. The second insulating layer 1102 can also be considered a first outer insulating layer disposed on the first outermost or uppermost side of the multiple insulating layers. The second element C2 can be disposed on the first outer insulating layer.

[0153] Specifically, a first connection part 1141 is disposed on a first pad 1113a of the third circuit pattern 1113. The second component C2 is electrically connected to the first pad 1113a through the first connection part 1141. The first connection part 1141 may be a solder ball. The first connection part 1141 may include a solder containing a heterogeneous material. The solder may be made of at least one of SnCu, SnPb, and SnAgCu. The heterogeneous material may include one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

[0154] A first molding layer 1131 is disposed on the second insulating layer 1102. The first molding layer 1131 is disposed to cover the upper surface of the second insulating layer 1102. Preferably, the first molding layer 1131 is disposed to cover the entire upper surface of the second insulating layer 1102. For example, a portion of the upper surface of the second insulating layer 1102 contacts the third circuit pattern 1113. Furthermore, the remaining portion of the upper surface of the second insulating layer 1102 contacts the first molding layer 1131.

[0155] The first molding layer 1131 may be, but is not limited to, an epoxy molding compound (EMC).

[0156] The first molding layer 1131 includes an open region 1132. Preferably, the first molding layer 1131 includes the open region 1132 that opens the region where the second component C2 is to be disposed in the upper region of the second insulating layer 1102. The second component C2 may be mounted on the first pad 1113a of the third circuit pattern 1113 within the open region 1132 of the first molding layer 1131.

[0157] A third element C3 is mounted under the third insulating layer 1103. Specifically, the third element C3 is mounted on a second pad (not shown) of a fourth circuit pattern 1114 disposed on the lower surface of the third insulating layer 1103.

[0158] Specifically, a second connection part 1142 is disposed under the second pad of the fourth circuit pattern 1114. The third element C3 is electrically connected to the second pad through the second connection part 1142. The second connection part 1142 may be a solder ball. The second connection part 1142 may include a material with a different component than the solder.

[0159] A second molding layer 1133 is disposed under the third insulating layer 1103. The second molding layer 1133 is disposed to cover the lower surface of the third insulating layer 1103. The second molding layer 1133 may be, but is not limited to, an epoxy molding compound (EMC).

[0160] The second molding layer 1133 may be formed to expose the bottom surface of the third element C3. That is, the second molding layer 1133 may be disposed to cover the side and top surfaces of the third element C3. In this case, a terminal (not shown) of the third element C3 may be disposed on the top surface, and thus the second connection portion 1142 and the terminal of the third element C3 may be covered by the second molding layer 1133.

[0161] The second molding layer 1133 may be disposed under the third insulating layer 1103 with a certain thickness. In this case, the lower surface of the second molding layer 1133 may be flush with the lower surface of the third element C3. Therefore, the lower surface of the third element C3 may be exposed to the outside. As a result, heat generated in the third element C3 may be dissipated to the outside through the exposed portion.

[0162] Meanwhile, the lower surface of the second molding layer 1133 may be positioned lower than the lower surfaces of the first post bump 1150 and the second post bump 1160. In addition, the second molding layer 1133 is formed to expose the lower surfaces of the first post bump 1150 and the second post bump 1160. As a result, a seating portion, which is an open area of ​​the second molding layer 1133, may be formed on the lower surfaces of the first post bump 1150 and the second post bump 1160. As a result, solder balls for subsequent connection to a main board can be accurately positioned, thereby improving reliability.

[0163] A first post bump 1150 and a second post bump 1160 are disposed under the lower surface of the fourth circuit pattern 1114. The first post bump 1150 and the second post bump 1160 may be connection portions for connection to an external main board.

[0164] The first post bump 1150 and the second post bump 1160 may be formed using a plating seed layer (not shown) used to form the fourth circuit pattern 1114. As a result, in an embodiment, a separate seed layer for forming the first post bump 1150 and the second post bump 1160 may be omitted. As a result, the first post bump 1150 and the second post bump 1160 may be disposed in direct contact with the fourth circuit pattern 1114 disposed on the lower surface of the third insulating layer 1103.

[0165] That is, in this embodiment, a separate seed layer for electroplating is not formed between the first and second post bumps 150, 160 and the fourth circuit pattern 1114, but the first post bumps 1150 and the second post bumps 1160 are formed on the fourth circuit pattern 1114 using the seed layer formed on the fourth circuit pattern 1114. As a result, in this embodiment, a separate seed layer for the shape of the post bumps can be omitted, thereby simplifying the manufacturing process. Furthermore, in this embodiment, when a separate seed layer for electroplating of the post bumps is formed, the problem of cracks occurring between the separate seed layer and the post bumps can be solved, thereby improving the reliability and durability of the product.

[0166] That is, in the circuit board of the first embodiment, the second connection portion includes only one post bump, whereas in the circuit board of the second embodiment, the second connection portion includes a first post bump 1150 and a second post bump 1160 having different widths.

[0167] The first post bump 1150 may have a first width W1. For example, the first width W1 of the first post bump 1150 may be in the range of 150 μm to 300 μm. For example, the first width W1 of the first post bump 1150 may be in the range of 170 μm to 280 μm. For example, the first width W1 of the first post bump 1150 may be in the range of 200 μm to 250 μm. If the width of the first post bump 1150 is less than 150 μm, it may be impossible to stably support the main board 1200. Furthermore, if the width of the first post bump 1150 is greater than 300 μm, the volume of the circuit board in the longitudinal direction may increase.

[0168] The second post bumps 1160 may have a second width W2. For example, the second width W2 of the second post bumps 1160 may be in the range of 50 μm to 120 μm. For example, the second width W2 of the second post bumps 1160 may be in the range of 70 μm to 110 μm. For example, the second width W2 of the second post bumps 1160 may be in the range of 80 μm to 100 μm. If the width of the second post bumps 1160 is less than 50 μm, the adjacent second post bumps may not be able to stably support the main board. Furthermore, if the width of the second post bumps 1160 is greater than 120 μm, the longitudinal volume of the circuit board may increase.

[0169] In the embodiment, as described above, first post bumps 1150 and second post bumps 1160 having different widths are formed in the second connecting portion connected to the main board. That is, in the comparative example, only the first post bump is included in the second connecting portion, which increases the thickness of the circuit board in the longitudinal direction. In contrast, in the embodiment, not only the first post bump but also the second post bump are formed together with the first post bump, which allows for different support of the main board depending on the position, thereby reducing the volume of the circuit board in the longitudinal direction.

[0170] The second post bump 1160 may be a bump connected to the first element C1 embedded in the first insulating layer 1101.

[0171] For example, the second post bump 1160 may be a bump that is directly connected to the first terminal T1 of the first component C1 through the fourth circuit pattern 1114 and the third via 1123. For example, the second post bump 1160 may be a bump that is arranged to overlap the first component C1 in the vertical direction. For example, the second post bump 1160 may be arranged to overlap the first terminal T1 of the first component C1 in the vertical direction.

[0172] As described above, in the embodiment, the first component C1 and the main board are connected using the second post bumps 1160. Meanwhile, in the comparative example, the first component C1 and the main board are connected using solder balls. However, due to the characteristics of the solder balls, there is a limit to how fine pitches can be accommodated, so additional connecting wires must be used to secure space for the solder balls.

[0173] In contrast, in the embodiment, the first component C1 and the main board are connected using second post bumps 1160. Accordingly, in the embodiment, a fine pitch can be accommodated by using a plurality of second post bumps 1160 corresponding to the pitch of the first terminals T1 of the first component C1. Furthermore, in the embodiment, the first component C1 and the main board are connected via the second post bumps 1160, thereby improving heat dissipation characteristics compared to the comparative example. Furthermore, in the embodiment, the first component C1 and the main board are connected via the second post bumps, thereby reducing the signal transmission distance between the first component C1 and the main board, thereby improving characteristics and transmission speed.

[0174] The open area 1132 of the first molding layer 1131 according to the embodiment will be described in detail below.

[0175] 17 is a diagram showing an open area of ​​the first molding layer of FIG. 2 according to the first embodiment, and FIG. 18 is a diagram showing an open area of ​​the first molding layer of FIG. 2 according to the second embodiment.

[0176] In this case, the structure of the first molding layer described below would be similarly applicable to the first molding layer 190 shown in FIG.

[0177] The open region 1132 of the first molding layer 1131 may open the region of the upper region of the second insulating layer 1102 where the second element C2 is disposed.

[0178] In this case, the open region 1132 of the first molding layer 1131 may be formed to cover the top surface of the second insulating layer 1102 and expose the first pad 1113a.

[0179] Therefore, the top surface of the second insulating layer 1102 may be covered even in the open region 1132. That is, in a typical cavity, the top surface of the second insulating layer is exposed to ensure a mounting area for a device. In contrast, in this embodiment, the open region 1132 covers the top surface of the second insulating layer 1102 while selectively exposing the first pad 1113a, thereby improving reliability.

[0180] That is, the first molding layer 1131 includes a first portion that forms the open region 1132 and a second portion other than the first portion.

[0181] The first portion may be formed to expose the first pad 1113a on which the second element C2 is mounted.

[0182] The upper surface of the first portion may have steps. For example, the first portion of the first molding layer 1131 may have steps having different heights depending on the position. For example, the upper surface of the first portion of the first molding layer 1131 may have a uniform surface roughness. In this case, the surface roughness of the upper surface of the first portion of the first molding layer 1131 is not processed to have the desired roughness through an additional process, but is formed by placing a jig in place, thereby allowing the upper surface of the first portion to have a uniform surface roughness.

[0183] The first portion of the first molding layer 1131 may include a 1-1 portion corresponding to an edge region and a 1-2 portion corresponding to an inner region.

[0184] In this case, the upper surface S1 of the 1-1 portion of the first molding layer 1131 may have a different height from the upper surface S2 of the 1-2 portion of the first molding layer 1131.

[0185] For example, the top surface of the first portion of the first molding layer 1131 may change from the 1-1 portion to the 1-2 portion, i.e., the height of the top surface of the first portion of the first molding layer 1131 may decrease as it moves away from the inner wall of the open region 1132.

[0186] For example, the depth of the open region 1132 of the first molding layer 1131 may increase from the outside to the inside.

[0187] In this embodiment, since a square jig is used to form the open area 1132, the inner wall of the open area 1132 may be perpendicular to the upper surface of the second insulating layer 1102. Preferably, the upper and lower widths of the open area 1132 may be the same.

[0188] The 1-1 portion of the first molding layer 1131 may have a second height H2, and the 1-2 portion of the first molding layer 1131 may have a third height H3 that is smaller than the second height H2.

[0189] That is, the first pad 1113a may be formed to have a first height H1 on the upper surface of the second insulating layer 1102. The 1-1 portion of the first molding layer 1131 must expose the upper surface of the first pad 1113a, and thus the first pad 1113a may have a second height H2 that is smaller than the first height H1.

[0190] In addition, the 1-2 portion of the first molding layer 1131 may have a third height H3 that is smaller than the second height H2. In this case, the 1-2 portion having the third height H3 may be disposed closer to the first pad 1113a than the 1-1 portion having the second height H2.

[0191] 17, the respective top surfaces S1 and S2 of the 1-1 and 1-2 portions of the first molding layer 1131 may have the same height across the entire region. For example, the top surface S1 of the 1-1 portion of the first molding layer 1131 may be flat. For example, the top surfaces S1 of the 1-1 portion of the first element C1 may have the same height across the entire region. For example, the top surface S2 of the 1-2 portion of the first molding layer 1131 may be flat. For example, the top surfaces S2 of the 1-2 portions of the first element C1 may have the same height across the entire region.

[0192] Alternatively, as shown in FIG. 18, the heights of the upper surfaces S1 and S2 of the first molding layer 1131's portions 1-1 and 1-2 may vary from the outside to the inside.

[0193] Meanwhile, the second height H2 may be 195% or less of the first height H1. In this case, the first upper surface S1 of the 1-1 portion and the second upper surface S2 of the 1-2 portion of the first molding layer 1131 may have different heights depending on the position. Thus, the second height H2 may refer to the average height of the first upper surface S1. Alternatively, the second height H2 may refer to the largest height value among the heights of the first upper surface S1 depending on the position.

[0194] The upper surface S1 of the first portion may become lower from the outside to the inside. For example, the upper surface S1 of the first portion may have a maximum height at a portion closest to the inner wall. For example, the upper surface S1 of the first portion may have a minimum height at a portion adjacent to the upper surface S2 of the first portion.

[0195] Also, the upper surface S2 of the 1-2 portion may have a height smaller than the upper surface S1 of the 1-1 portion and may be located between the first pads 1113a.

[0196] In this case, the upper surface S2 of the 1-2 portion may have a height smaller than the upper surface S1 of the 1-1 portion. Furthermore, the upper surface S2 of the 1-2 portion may have a height that varies depending on the position. That is, the third height H3 of the upper surface S2 of the 1-2 portion may have a value that varies depending on the position.

[0197] Preferably, the height of the top surface S2 of the 1-2 portion may decrease from the outer side to the inner side. For example, the top surface S2 of the 1-2 portion may have a maximum height at a portion adjacent to the inner side of the first pad 1113a (or a portion adjacent to the top surface of the 1-1 portion). The top surface S2 of the 1-2 portion may have a minimum height at a central portion. That is, the cross section of the top surface S2 of the 1-2 portion may have a V-shape whose height gradually decreases from the outer side to the inner side. In addition, the cross section of the top surface S1 of the 1-1 portion may also have a V-shape whose height gradually decreases from the outer side to the inner side. As a result, in this embodiment, since the surface of the first pad 1113a is not exposed when the second component C2 is mounted, poor connection of the second component C2 can be prevented, thereby improving the reliability of the electrical connection between the first pad 1113a and the second component C2.

[0198] 19 to 29 are diagrams showing the manufacturing method of the circuit board shown in FIG. 16 in the order of steps.

[0199] Referring to FIG. 19, in an embodiment, a process for manufacturing an inner layer substrate can be performed first.

[0200] In order to manufacture an inner layer substrate, in the embodiment, a first insulating layer 1101 is prepared. Then, in the embodiment, a process of forming a first circuit pattern 1111 on an upper surface of the first insulating layer 1101 and forming a second circuit pattern 1112 on a lower surface of the first insulating layer 1101 can be performed. Also, in the embodiment, a process of forming a first via 1121 connecting the first circuit pattern 1111 and the second circuit pattern 1112 in the first insulating layer 1101 can be performed.

[0201] 20, in an embodiment, a process of forming a carrier board CB under the first insulating layer 1101 may be performed. Then, in an embodiment, a process of forming a cavity 1101a in the first insulating layer 1101 may be performed.

[0202] 21, in an embodiment, a process of embedding a first element C1 in a cavity 1101a formed in the first insulating layer 1101 may be performed. The first element C1 may be embedded in the first insulating layer 1101, with at least a portion thereof exposed below the lower surface of the first insulating layer 1101. For example, the first element C1 may include a first terminal T1. In this case, the first terminal T1 of the first element C1 may be disposed to protrude below the lower surface of the first insulating layer 1101. For example, the first terminal T1 of the first element C1 may be disposed within the carrier board CB. For example, the upper surface of the first terminal T1 of the first element C1 may be located on the same plane as the upper surface of the second circuit pattern 1112.

[0203] 22, in an embodiment, a step of forming the second insulating layer 1102 on an upper surface of the first insulating layer 1101 may be performed. The upper surface of the first element C1 may be covered by the formed second insulating layer 1102.

[0204] 23, in an embodiment, a step of removing the carrier board CB disposed on the lower surface of the first insulating layer 1101 may be performed. For example, in an embodiment, a step of removing the carrier board CB may be performed so as to expose the second circuit pattern 1112 protruding below the lower surface of the first insulating layer 1101 and the first terminal T1 of the first element C1.

[0205] 24, in an embodiment, a process of forming a third circuit pattern 1113 on an upper surface of the second insulating layer 1102 may be performed. Also, in an embodiment, a process of forming a second via 1122 connecting the first circuit pattern 1111 and the third circuit pattern 1113 in the second insulating layer 1102 may be performed. In this case, the third circuit pattern 1113 formed on the upper surface of the second insulating layer 1102 may include a first pad 1113a for mounting the second component C2.

[0206] In addition, in an embodiment, a process of forming a fourth circuit pattern 1114 on the lower surface of the third insulating layer 1103 may be performed. In an embodiment, a process of forming a third via 1123 connecting the second circuit pattern 1112 and the fourth circuit pattern 1114 in the third insulating layer 1103 may be performed. In this case, the third via 1123 may include a via directly connected to a first terminal T1 of a first component C1 embedded in the first insulating layer 1101. In addition, the fourth circuit pattern 1114 may include a second pad (not shown) for mounting a third component C3.

[0207] 25, in this embodiment, a process of disposing a mold chase MC on the second insulating layer 1102 may be performed. The mold chase MC may include a protrusion (not shown) disposed on a first pad 1113a connected to the second element C2 of a third circuit pattern 1113 disposed on the upper surface of the second insulating layer 1102. That is, the protrusion of the mold chase MC may be disposed on the first pad 1113a of the third circuit pattern 1113.

[0208] Next, referring to FIG. 26, in an embodiment, a process of forming a first molding layer 1131 can be performed while filling the remaining area of ​​the upper region of the second insulating layer 1102 except for the protrusion portion of the mold chase MC.

[0209] The first molding layer 1131 may have an open region 1132 corresponding to the protrusion of the mold chase MC. The first molding layer 1131 in the open region 1132 may be formed to fill a portion of the space between the protrusion and the upper surface of the second insulating layer 1102.

[0210] 27, in an embodiment, a first connection portion 1141 is disposed on a first pad 1113a exposed through an open area 1132 of the first molding layer 1131. Then, in an embodiment, a process of mounting a second element C2 on the first pad 1113a using the first connection portion 1141 can be performed.

[0211] In addition, in the embodiment, a second connection portion 1142 can be placed under the second pad of the fourth circuit pattern 1114 arranged on the underside of the third insulating layer 1103, and a process can be performed in which the third element C3 is mounted using the second connection portion 1142.

[0212] Specifically, the open region 1132 of the first molding layer 1131 may open a region where the second element C2 is disposed in an upper region of the second insulating layer 1102. In this case, the open region 1132 of the first molding layer 1131 may be formed to cover the upper surface of the second insulating layer 1102 and expose the first pad 1113a.

[0213] Therefore, the open region 1132 may also cover the top surface of the second insulating layer 1102. That is, in a typical cavity, the top surface of the second insulating layer is also exposed to ensure a mounting area for a device. In contrast, in this embodiment, the open region 1132 covers the top surface of the second insulating layer 1102 while selectively exposing the first pad 1113a, thereby improving reliability.

[0214] 28 and 29, in an embodiment, a process may be performed in which a first post bump 1150 and a second post bump 1160 constituting a second connector are formed under the lower surface of the fourth circuit pattern 1114. Also, in an embodiment, a process may be performed in which a second molding layer 1133 is formed under the third insulating layer 1103 to cover the third element C3 while exposing the lower surfaces of the first post bump 1150 and the second post bump 1160.

[0215] FIG. 30 is a diagram illustrating a package substrate according to an embodiment.

[0216] 30, in the package substrate in the embodiment, the third connection portion 1220 may be disposed below the first post bump 1150 and the second post bump 1160 of the circuit board shown in FIG.

[0217] In addition, a main board 1200 may be attached below the circuit board via the third connection part 1220. In this case, the main board 1200 may include, on its upper surface, pads directly connected to the first post bumps 1150 and pads directly connected to the second post bumps 1160.

[0218] The second post bump 1160 is disposed to vertically overlap the first component C1 embedded in the first insulating layer 1101 of the circuit board. That is, the second post bump 1160 may be directly connected to the first component C1 through the third via 1123 and the fourth circuit pattern 1114. Here, direct connection may mean that the signal line connected to the terminal T1 of the first component C1 is not provided horizontally but is directly connected to the second post bump 1160 vertically through the third via 1123 and the fourth circuit pattern 1114.

[0219] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0220] Furthermore, although the above description has focused on the embodiments, these are merely examples and are not intended to limit the scope of the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; a first outer circuit pattern at least partially embedded in the insulating layer; a first resist disposed on the insulating layer and including a first opening vertically overlapping the first outer circuit pattern; a seed metal layer disposed on the first outer circuit pattern in a region vertically overlapping the first opening, and disposed between the first outer circuit pattern and the first resist in a region not vertically overlapping the first opening; a first coupling portion disposed on the seed metal layer in the first opening; a first connection portion disposed on the first coupling portion; a first element disposed on the first connection portion; the first connecting portion is disposed in the first opening and does not contact the first resist; an upper surface of the first connecting portion is located higher than an upper surface of the first resist; the first outer circuit pattern includes a 1-1 circuit pattern that vertically overlaps the first opening and a 1-2 circuit pattern that does not vertically overlap the first opening; the seed metal layer includes a first portion disposed between the first-1 circuit pattern and the first connecting portion, and a second portion disposed between the first-2 circuit pattern and the first resist; A package substrate, wherein the width of the second portion of the seed metal layer is greater than the width of the first-second circuit pattern.

2. the first-1 circuit pattern is provided in plurality and vertically overlaps the single first opening of the first resist; 2. The package substrate of claim 1, wherein each of the plurality of first-1 circuit patterns vertically overlaps the single first opening in common.

3. a second outer circuit pattern including a second-1 circuit pattern and a second-2 circuit pattern disposed under the insulating layer; a second connection portion disposed below the second-1 circuit pattern; a second connection portion disposed below the second-2 circuit pattern; The package substrate according to claim 1 , further comprising: a second element disposed below the second connection portion.

4. a plurality of the first connecting portions and a plurality of the second connecting portions are provided; a width of each of the plurality of first connecting portions is smaller than a width of each of the plurality of second connecting portions; The package substrate according to claim 3 , wherein the spacing between the first connecting portions is smaller than the spacing between the second connecting portions.

5. The package substrate according to claim 4 , further comprising a second resist disposed under the insulating layer and including a second opening that vertically overlaps the second connecting portion.

6. The seed metal layer comprises:

6. The package substrate according to claim 1, wherein the first-1 circuit pattern, the first-2 circuit pattern, and the first connecting portion are seed layers.

7. 7. The package substrate of claim 1, wherein the width of the first portion of the seed metal layer is the same as the width of at least one of the first-1 circuit pattern and the first connecting portion.

8. the second portion of the seed metal layer; 8. The package substrate of claim 7, comprising: a 2-1 portion disposed between the 1-2 circuit pattern and the first resist; and a 2-2 portion extending from the 2-1 portion and disposed between the insulating layer and the first resist.

9. a first molding layer disposed on the insulating layer and molding the first element; a second molding layer disposed under the insulating layer and molding the second element; The package substrate of claim 3 , wherein the second molding layer includes a third opening that vertically overlaps the second connecting portion.

10. an embedded element embedded within the insulating layer; The 2-1 circuit pattern is a first pattern portion vertically overlapping the embedded element; a second pattern portion that does not vertically overlap the embedded element; The second connecting portion is a first post bump disposed under the first pattern portion; 10. The package substrate according to claim 3, further comprising: a second post bump disposed under the second pattern portion and having a width greater than a width of the first post bump.

11. The package substrate of claim 9 , wherein the first molding layer includes an open area vertically overlapping the first element.

12. an upper surface of the first outer circuit pattern is located higher than an upper surface of the insulating layer; The package substrate of claim 11 , wherein an upper surface of the first molding layer in the open area is positioned higher than a lower surface of the first outer circuit pattern and lower than an upper surface of the first outer circuit pattern.

13. The top surface of the first molding layer in the open area includes: The package substrate of claim 12 , wherein a height varies from a side surface of the first outer circuit pattern to a side wall of the open area.

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