Method and apparatus for a phase locked loop circuit

Abstract

The phase-locked loop (PLL) circuit (200) includes a voltage-controlled oscillator (VCO) (208), a first loop circuit (220), and a second loop circuit (222). The first loop circuit includes a first loop filter (206) configured to receive a first signal (224) based on a feedback signal (218) from the VCO and provide a first VCO frequency control signal (226) to the VCO. The second loop circuit includes a compensation circuit (210) configured to receive the reference signal (218) and the first signal and provide a second VCO frequency control signal (228) to the VCO.

Description

[Technical Field]

[0001] Examples of the present disclosure relate generally to integrated circuits ("ICs"), and more particularly to embodiments relating to temperature variation compensation for phase-locked loop (PLL) circuits. [Background technology]

[0002] Temperature changes typically have a significant impact on the locking process of a PLL circuit. During operation of a PLL circuit, temperature changes (e.g., from -40°C to 125°C, or vice versa) can cause frequency drift in the voltage-controlled oscillator (VCO) of the PLL circuit. Typically, to compensate for these frequency drifts, the PLL circuit can shift the VCO frequency control signal to bring the VCO output frequency Fout to a required frequency (e.g., reference frequency Fref × N). However, such a VCO frequency control signal may be outside the operating range of the PLL circuit's charge pump, which can lead to PLL lock failure.

[0003] Therefore, it would be desirable and useful to provide an improved method and system for temperature variation compensation in a PLL. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a phase-locked loop (PLL) circuit may include a voltage-controlled oscillator (VCO), a first loop circuit including a first loop filter, and a second loop circuit including a compensation circuit. The first loop filter may be configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The compensation circuit may be configured to receive a reference signal and the first signal and provide a second VCO frequency control signal to the VCO.

[0005] In some embodiments, the first bandwidth of the first loop circuit may be greater than the second bandwidth of the second loop circuit, and in some embodiments, the first bandwidth may be at least 10 times greater than the second bandwidth.

[0006] In one embodiment, the compensation circuit may include an operational amplifier configured to generate a second signal based on the first signal and the reference signal, and a second loop filter configured to generate a second VCO frequency control signal based on the second signal.

[0007] In one embodiment, the second loop filter may be a low pass filter configured such that the first bandwidth of the first loop circuit is greater than the second bandwidth of the second loop circuit.

[0008] In one embodiment, the second VCO frequency control signal may have a minimum voltage equal to ground voltage.

[0009] In some embodiments, the VCO may include a ring oscillator. In an embodiment, the second VCO frequency control signal may be configured to control at least one of a varactor of the VCO and a current source of the VCO to control the output frequency of the VCO.

[0010] In an embodiment, the VCO may be configured to receive a third VCO frequency control signal from an open loop temperature dependent voltage circuit.

[0011] In some embodiments, the PLL circuit may further include a compensation mode selection circuit configured to select a compensation mode for controlling the output frequency of the VCO. The compensation mode may be selected from a first compensation mode, a second compensation mode, a third compensation mode, and a fourth compensation mode. In the first compensation mode, the second VCO frequency control signal may be configured to control one of the VCO varactor and the VCO current source. In the second compensation mode, the second VCO frequency control signal may be configured to control the other of the VCO varactor and the VCO current source. In the third compensation mode, the second VCO frequency control signal may be configured to control both the VCO varactor and the VCO current source. In the fourth compensation mode, the third VCO frequency control signal may be configured to control both the VCO varactor and the VCO current source.

[0012] In one embodiment, the method includes receiving, by a first loop filter in a first loop circuit, a first signal based on a feedback signal from a voltage-controlled oscillator (VCO), and providing, by the first loop filter, a first VCO frequency control signal to the VCO. The method may also include receiving, by a compensation circuit in a second loop circuit, a reference signal and the first signal, and providing, by the compensation circuit, a second VCO frequency control signal to the VCO based on a difference between the reference signal and the first signal.

[0013] In an embodiment, the first bandwidth of the first loop circuit may be greater than the second bandwidth of the second loop circuit.

[0014] In an embodiment, the first bandwidth may be at least 10 times greater than the second bandwidth.

[0015] In an embodiment, the method may include generating, by a compensation circuit, a second signal based on a difference between the first signal and a reference signal, and generating, using a second loop filter of the compensation circuit, a second VCO frequency control signal based on the second signal.

[0016] In one embodiment, the second loop filter may be a low pass filter configured such that the first bandwidth of the first loop circuit is greater than the second bandwidth of the second loop circuit.

[0017] In one embodiment, the second VCO frequency control signal may have a minimum voltage equal to ground voltage.

[0018] In some embodiments, the VCO may include a ring oscillator. In an embodiment, the method may include controlling at least one of a varactor of the VCO and a current source of the VCO with a second VCO frequency control signal to control an output frequency of the VCO.

[0019] In an embodiment, the method may include receiving, by the VCO, a third VCO frequency control signal from an open-loop temperature dependent voltage circuit.

[0020] In one embodiment, the method may include selecting a compensation mode for controlling the output frequency of the VCO from a first compensation mode, a second compensation mode, a third compensation mode, and a fourth compensation mode. In the first compensation mode, the second VCO frequency control signal may be configured to control one of the VCO varactor and the VCO current source. In the second compensation mode, the second VCO frequency control signal may be configured to control the other of the VCO varactor and the VCO current source. In the third compensation mode, the second VCO frequency control signal may be configured to control both the VCO varactor and the VCO current source. In the fourth compensation mode, the third VCO frequency control signal is configured to control both the VCO varactor and the VCO current source.

[0021] Other aspects and features will become apparent from the following detailed description and accompanying drawings. [Brief explanation of the drawings]

[0022] [Figure 1]FIG. 1 is a block diagram illustrating an example architecture of an IC according to an embodiment of the present disclosure. [Figure 2] 1 is a block diagram illustrating an exemplary phase-locked loop (PLL) circuit including a primary loop circuit and a secondary loop circuit, in accordance with an embodiment of the present disclosure. [Figure 3] FIG. 2 is a block diagram illustrating an example compensation circuit for a secondary loop circuit of a PLL circuit according to an embodiment of the present disclosure. [Figure 4A] FIG. 2 illustrates a gain curve of a PLL circuit according to an embodiment of the present disclosure. [Figure 4B] FIG. 2 illustrates a phase curve of a PLL circuit according to an embodiment of the present disclosure. [Figure 5A] 2A and 2B illustrate a comparison of the voltage of signal 224 when the PLL is operating under different modes, according to an embodiment of the present disclosure. [Figure 5B] 5B shows temperature change over time corresponding to FIG. 5A, according to an embodiment of the present disclosure. [Figure 5C] FIG. 2 illustrates a frequency of an output signal of a VCO according to an embodiment of the present disclosure. [Figure 6A] FIG. 1 illustrates an exemplary ring-type voltage-controlled oscillator (VCO) circuit in accordance with an embodiment of the present disclosure. [Figure 6B] FIG. 2 illustrates a supply control circuit for a VCO according to an embodiment of the present disclosure. [Figure 6C] FIG. 2 illustrates a ground control circuit for a VCO according to an embodiment of the present disclosure. [Figure 6D] FIG. 2 illustrates a current source control circuit for a VCO according to an embodiment of the present disclosure. [Figure 7] FIG. 2 illustrates a compensation mode selection circuit according to an embodiment of the present disclosure. [Figure 8] 1 is a table illustrating various correction modes according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a block diagram illustrating an example PLL circuit including a primary loop circuit, a secondary loop circuit, and an open loop circuit for temperature compensation, in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0023] Detailed Description Various embodiments will be described below with reference to the drawings, in which exemplary embodiments are shown. However, the claimed invention may be embodied in different forms and should not be construed as limited to the embodiments described herein. Like reference numerals refer to like elements throughout. Accordingly, like elements will not be described in detail with respect to the description of each figure. It should also be noted that the drawings are intended only to facilitate the description of the embodiments. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, the illustrated embodiments need not have all aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in any other embodiment even if not so illustrated or explicitly described. Features, functions, and advantages may be achieved independently in various embodiments or may be combined in yet other embodiments.

[0024] Before describing exemplary embodiments exemplarily shown in several figures, a general introduction is provided for further understanding. As described above, in a typical PLL circuit, to compensate for frequency drift caused by temperature changes, the PLL circuit can shift the VCO's output frequency Fout back to a required frequency (e.g., a reference frequency Fref × N) by shifting the VCO frequency control signal. However, such a VCO frequency control signal may fall outside the operating range of the PLL circuit's charge pump, leading to PLL lock failure. An open-loop temperature-dependent voltage circuit may be used to generate a temperature-dependent voltage for controlling Fout and reducing temperature sensitivity. However, such open-loop compensation techniques rely on models and simulations that predict that the VCO's temperature change and the temperature-dependent voltage circuit are synchronized. Furthermore, such open-loop compensation techniques do not maximize the potential of temperature compensation calibration because the temperature-dependent voltage may fall outside the VCO's ground supply range, which may not be sufficient to compensate highly temperature-dependent oscillators such as ring oscillators in 7 nm processes.

[0025] For an integrated circuit (IC) solution, it has been discovered that by using a closed-loop second-order compensation loop in a PLL circuit, a closed-loop temperature tracking loop is provided to continuously monitor temperature-induced changes in the VCO control signal and provide an appropriate control signal to compensate for such changes.

[0026] Various advantages may exist in various applications of the present disclosure. A particular advantage is not required for all embodiments, and different embodiments may provide different advantages. One advantage of certain embodiments is that by using a closed secondary loop having a bandwidth smaller than the bandwidth of the PLL circuit's primary loop, temperature compensation is improved while maintaining PLL circuit stability without requiring knowledge of the VCO's exact temperature behavior. Another advantage of certain embodiments is that the secondary loop can provide a VCO control signal that rails from the VCO's ground voltage to its supply voltage, thereby improving the PLL circuit's temperature compensation capabilities. Yet another advantage of certain embodiments is that greater flexibility is achieved in providing temperature compensation to the VCO by providing a compensation mode selection circuit for selecting from various programmable compensation modes using the primary loop control signal, the secondary loop control signal, and / or an open-loop temperature-dependent voltage control signal.

[0027] Because at least one of the above embodiments is illustrated using a particular type of IC, a detailed description of such an IC is provided below. However, it should be understood that other types of ICs may benefit from at least one of the embodiments described herein.

[0028] Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specific logic functions. One type of PLD, a field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles may include, for example, input / output blocks (“IOBs”), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), etc. As used herein, the terms “include” and “including” mean including without limitation.

[0029] Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes multiple interconnect lines of various lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, etc.

[0030] Programmable interconnects and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., an external PROM) and written to the FPGA by an external device. The collective state of the individual memory cells determines the FPGA's function. Another type of PLD is the Complex Programmable Logic Device (CPLD). CPLDs contain two or more "functional blocks" connected together and connected to input / output ("I / O") resources by an interconnect switch matrix. Each functional block in a CPLD contains a two-level AND / OR structure similar to those used in programmable logic arrays (PLAs) and programmable array logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

[0031] Generally, in each of these programmable logic devices, the functionality of the device is controlled by configuration data provided for the purpose of that device. The configuration data can be stored in volatile memory (e.g., static memory cells common in FPGAs and some CPLDs), non-volatile memory (e.g., flash memory in some CPLDs), or any other type of memory cell.

[0032] Other PLDs are programmed by applying processing layers, such as metal layers, that programmably interconnect various elements on the device. These PLDs are known as mask-programmable devices. PLDs may also be implemented in other ways, for example, using fuse or anti-fuse technology. The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, as well as only partially programmable devices. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.

[0033] As mentioned above, advanced FPGAs may include several different types of programmable logic blocks within an array. For example, FIG. 1 shows an exemplary FPGA architecture 100. FPGA architecture 100 includes a number of different programmable tiles, including multi-gigabit transceivers (MGTs) 101, configurable logic blocks (CLBs) 102, random access memory blocks (BRAMs) 103, input / output blocks (IOBs) 104, configuration and clock logic (CONFIG / CLOCKS) 105, digital signal processing blocks (DSPs) 106, dedicated input / output blocks (“I / O”) 107 (e.g., configuration and clock ports), and other programmable logic 108, such as digital clock managers, analog-to-digital converters, system monitoring logic, etc. Some FPGAs also include a dedicated processor block (“PROC”) 110.

[0034] In some FPGAs, each programmable tile may include at least one programmable interconnect element (INT) 111 with connections to input / output terminals 120 of programmable logic elements within the same tile, as shown by the example included at the top of FIG. 1 . Each programmable interconnect element 111 may also include connections to interconnect segments 122 of adjacent programmable interconnect elements within the same tile or other tiles. Each programmable interconnect element 111 may also include connections to interconnect segments 124 of general routing resources between logic blocks (not shown). The general routing resources may include routing channels between logic blocks (not shown) that configure the tracks of the interconnect segments (e.g., interconnect segments 124) and switch blocks (not shown) for connecting the interconnect segments. An interconnect segment (e.g., interconnect segment 124) of the general routing resources may span at least one logic block. Programmable interconnect elements 111 taken together with general routing resources implement the programmable interconnect structure (programmable interconnect) for the illustrated FPGA.

[0035] In an exemplary implementation, the CLB 102 may include a configurable logic element (CLE) 112 that can be programmed to implement user logic and a single programmable interconnect element (INT) 111. The BRAM 103 may include a BRAM logic element ("BRL") 113 in addition to at least one programmable interconnect element. Typically, the number of interconnect elements included in a tile depends on the tile's height. In the illustrated example, the BRAM tile has the same height as five CLBs, although other numbers (e.g., four) may also be used. The DSP tile 106 may include a DSP logic element (DSPL) 114 in addition to an appropriate number of programmable interconnect elements. The IOB 104 may include, for example, one instance of the programmable interconnect element 111 in addition to two instances of the input / output logic element (IOL) 115. Those skilled in the art will appreciate that, for example, the actual I / O pads connected to input / output logic element 115 are typically not limited to the area of ​​input / output logic element 115. In the example of Figure 1, an area (drawn horizontally) near the center of the die (e.g., the area formed by areas 105, 107, and 108 shown in Figure 1) can be used for configuration, clocks, and other control logic. Column 109 or other columns (drawn vertically) extending from this horizontal area can be used to distribute clock and configuration signals across the width of the FPGA.

[0036] Some FPGAs utilizing the architecture shown in FIG. 1 include additional logic blocks that disrupt the regular column structure that makes up the majority of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic. For example, PROC 110 spans an array of CLBs and BRAMs. PROC 110 can include a variety of components ranging from a single microprocessor to a fully programmable processing system, including microprocessors, memory controllers, peripherals, etc.

[0037] In one aspect, PROC 110 is implemented as a dedicated circuit, e.g., a hardwired processor, fabricated as part of a die that implements the programmable circuitry of an IC. PROC 110 can represent any of a variety of different processor types and / or systems ranging in complexity from an individual processor, e.g., a single core capable of executing program code, to an entire processor system having at least one core, module, coprocessor, interface, etc.

[0038] In another aspect, PROC 110 may be omitted from architecture 100 and replaced with at least one other type of programmable block as described. Furthermore, such blocks may be utilized to form a "soft processor" in that various blocks of programmable circuitry may be used to form a processor capable of executing program code, as in the case of PROC 110.

[0039] The phrase "programmable circuitry" can refer to programmable circuit elements within an IC, e.g., the various programmable or configurable circuit blocks or tiles described herein, as well as interconnect circuitry that selectively couples the various circuit blocks, tiles, and / or elements according to configuration data loaded into the IC. For example, portions shown in FIG. 1 that are external to PROC 110, such as CLB 102 and BRAM 103, can be considered programmable circuitry of the IC.

[0040] In one embodiment, the functionality and connectivity of a programmable circuit is not established until configuration data is loaded into the IC. A set of configuration data can be used to program the programmable circuit of an IC, such as an FPGA. The configuration data is sometimes referred to as a "configuration bitstream." Generally, a programmable circuit is not operational or functional without first loading a configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a particular circuit design within the programmable circuit. The circuit design specifies, for example, the functional aspects of the programmable circuit blocks and the physical connectivity between the various programmable circuit blocks.

[0041] In one embodiment, "hardwired" or "hardened" i.e., non-programmable circuitry is fabricated as part of an IC. Unlike programmable circuitry, hardwired circuits or circuit blocks are not implemented after the IC is fabricated by loading a configuration bitstream.

[0042] In general, a hardwired circuit is considered to have dedicated circuit blocks and interconnects that function without first loading a configuration bitstream into an IC such as, for example, PROC 110.

[0043] In some examples, a hardwired circuit may have at least one operating mode that is configurable or selectable according to register settings or values ​​stored in at least one memory element within the IC. The operating mode may be set, for example, through the loading of a configuration bitstream into the IC. Despite this capability, a hardwired circuit is not considered a programmable circuit because, when fabricated as part of an IC, the hardwired circuit is operable and has a specific function.

[0044] FIG. 1 is intended to illustrate an exemplary architecture that can be used to implement an IC including programmable circuitry such as a programmable fabric. For example, the number of logic blocks within a row, the relative width of the row, the number and order of rows, the types of logic blocks included within a row, the relative sizes of the logic blocks, and the interconnect / logic implementation included at the top of FIG. 1 are merely exemplary. For example, in an actual IC, two or more adjacent rows of CLBs are typically included wherever CLBs appear to facilitate efficient implementation of user logic, although the number of adjacent rows of CLBs will vary depending on the overall size of the IC. Furthermore, the FPGA of FIG. 1 illustrates an example of a programmable IC that can follow the example interconnect circuitry described herein. The interconnect circuitry described herein may be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements.

[0045] It should be noted that ICs that may implement at least one embodiment described herein are not limited to the exemplary IC shown in FIG. 1; ICs having other configurations or other types of ICs may also implement those embodiments.

[0046] 2, a temperature-compensated PLL circuit 200, also referred to as PLL circuit 200, is shown. PLL circuit 200 receives a reference signal 214 (also referred to as reference clock signal 214) that provides a reference frequency Fref and generates an output signal 216 (also referred to as output clock signal 216). When PLL circuit 200 operates in a locked mode, output signal 216 has a phase and frequency relationship with reference signal 214. In one example, in the locked mode, output signal 216 has a frequency Fout that is N times the reference frequency Fref, where N is a programmable positive integer.

[0047] The PLL circuit 200 includes a primary loop 220 (also referred to as a PLL loop 220) and a secondary loop 222 (also referred to as an auxiliary loop 222 or a temperature compensation loop 222). The primary loop 220 includes a phase frequency detector (PFD) circuit 202, a charge pump circuit 204, a filter circuit 206 (also referred to as a loop filter circuit 206), a voltage controlled oscillator (VCO) 208, and a frequency divider circuit 212 (also referred to as a feedback divider circuit 212). The secondary loop 222 includes the PFD circuit 202, the charge pump circuit 204, the compensation circuit 210, the VCO 208, and the frequency divider circuit 212.

[0048] 2, reference signal 214 is coupled to PFD circuit 202. PFD circuit 202 also receives feedback signal 217 having a frequency that is 1 / N of the frequency Fout of output signal 216, where N is a programmable positive integer. PFD circuit 202 generates output signal 219 that indicates the frequency and / or phase difference between reference signal 214 and feedback signal 217. Feedback signal 217 is generated by divider circuit 212 based on output signal 216. Feedback signal 217 may have the same frequency and / or phase as the frequency and / or phase of reference signal 214 when PLL circuit 200 is operating in locked mode.

[0049] The PFD circuit 202 is coupled to a charge pump circuit 204. The charge pump circuit 204 receives a signal 219 from the PFD circuit 202 and generates an output signal 224. The output signal 224 may include a bias voltage responsive to the signal 219 from the PFD circuit 202. The output signal 224 of the charge pump 204 may be coupled to the loop filter circuit 206.

[0050] The loop filter circuit 206 may include any suitable filter circuit, including, for example, a low-pass filter. Examples of low-pass filters include a resistor-capacitor (RC) filter, a resistor-inductor (RL) filter, a resistor-inductor-capacitor (RLC) filter, etc. The loop filter circuit 206 generates a VCO control signal 226 (also referred to as Vctrl1) and provides the VCO control signal 226 to the voltage-controlled oscillator (VCO) 208. In various embodiments, the loop filter circuit 206 determines the loop dynamics of the primary loop 220, also referred to as the stability of the primary loop, and may indicate how the primary loop responds to disturbances (e.g., changes in the reference frequency Fref, changes in the divider circuit 212, etc.). The loop filter circuit 206 may be used to suppress voltage ripple or noise in the signal 224. Some design trade-offs for the loop filter circuit 206 in the PLL circuit 200 include, for example, that a high loop bandwidth can degrade stability, and that excessive damping for better stability can reduce speed and increase settling time. In some examples, the loop filter circuit 206 is programmable and includes a programmable resistor and / or a programmable capacitor.

[0051] The VCO circuit 208 may generate an oscillating output signal 216, which has a higher or lower frequency in response to a VCO control signal 226 (e.g., its bias voltage). The output signal 216 may be provided to a circuit requiring a clock signal having a frequency having a relationship (e.g., N*Fref) to the Fret of the reference signal 214.

[0052] 2, the secondary loop 222 includes a compensation circuit 210. The compensation circuit receives an output signal 224 from the charge pump 204, receives a reference voltage signal 218 having a reference voltage Vref, generates a VCO control signal 228 (also referred to as Vctrl2), and provides the VCO control signal 228 to the VCO circuit 208 to control the frequency Fout of the output signal 216. In one embodiment, the reference voltage Vref is determined based on the operating range of the charge pump 204. In one example, the reference voltage Vref is determined to ensure that the signal 224 is within the operating range of the charge pump 204.

[0053] Referring to FIG. 3, an example of a compensation circuit 300 (e.g., the compensation circuit 210 of FIG. 2) in the secondary loop 222 is shown. The compensation circuit 300 includes an operational amplifier 304 and a filter circuit 306 (also referred to as a loop filter circuit 306). A signal 224 from the charge pump 204 having a voltage V1 is provided to the operational amplifier 304 (e.g., to the non-inverting input of the operational amplifier 304). The operational amplifier 304 also receives a reference voltage Vref 218 (e.g., at the inverting input of the operational amplifier 304). As an example, Vref 218 may be provided based on a predetermined reference voltage value or may be externally set by an operator. Vref 218 may be determined based on the phase noise performance of the VCO circuit. The gain A of the operational amplifier 304 may be determined based on the performance requirements of the PLL circuit 200. For example, a higher gain A may be selected so that the operational amplifier 304 forces the voltage V1 of the signal 224 to approach the reference voltage Vref 218 over a range of voltage changes of the voltage V1.

[0054] In various embodiments, a voltage divider may be used to scale the signal 224 to the input voltage at the non-inverting input of the op-amp 304 based on the parameters of the op-amp 304. In these embodiments, the reference voltage Vref 218 may be scaled appropriately.

[0055] Opamp 304 amplifies the differential input voltage, which is the difference in voltage between V1 of signal 224 and Vref 218, to generate output signal 310. The output voltage of signal 310 may be provided as A*(V1-Vref).

[0056] The loop filter 306 receives the signal 310 from the operational amplifier 304 and generates the output signal 228. In one embodiment, the loop filter 306 is a low-pass filter and is designed so that the loop response of the secondary loop 222 is slower than the loop response of the primary loop 220, which improves the stability of the PLL circuit 200.

[0057] 4A and 4B, open-loop Bode plots (gain and phase curves) are shown for the PLL circuit 200 without the secondary loop 222 (curves 402 and 452 in FIG. 4A) and the PLL circuit 200 with the secondary loop 222 temperature compensation loop (curves 404 and 454 in FIG. 4B). As described in more detail below, in various embodiments, the secondary loop 222 is designed so as not to affect the stability of the PLL circuit 200. Specifically, the secondary loop 222 may be designed (e.g., using design parameters of Vref 218, op amp 304, and / or loop filter 306) such that the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 activated can meet various design requirements, including, for example, phase margin requirements to ensure the stability of the PLL circuit 200.

[0058] 4A shows gain curves 402 and 404 for PLL circuit 200. Specifically, gain curve 402 corresponds to PLL circuit 200 operating with secondary loop 222 disabled. In other words, gain curve 402 corresponds to PLL circuit 200 operating with only primary loop 220 activated. Gain curve 404 corresponds to PLL circuit 200 operating with secondary loop 222 activated. In other words, gain curve 404 corresponds to PLL circuit 200 operating with both primary loop 220 and secondary loop 222 activated.

[0059] 4B shows phase curves 452 and 454 for PLL circuit 200. Specifically, phase curve 452 corresponds to PLL circuit 200 operating with primary loop 220 active and secondary loop 222 disabled. As shown in gain curve 402 and phase curve 452, the phase margin Pm1 456 (e.g., approximately 60°) of primary loop 220 is the difference between the phase of response 452 at frequency 406 and −180° when the loop gain of primary loop 220 is 1.0 (e.g., the gain of the response is 0 dB). Phase curve 454 corresponds to PLL circuit 200 operating with both primary loop 220 and secondary loop 222 active.

[0060] 4A and 4B , the secondary loop 222 is designed so that the phase margin Pm2 of the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 enabled satisfies the phase margin requirement. The phase margin requirement may be based on the phase margin Pm1 456 of the primary loop 220. As one example, the secondary loop 222 is designed so that the difference between the phase margin Pm1 and the phase margin Pm2 is less than 10% of the phase margin Pm1. As another example, the secondary loop 222 is designed so that the difference between the phase margin Pm1 and the phase margin Pm2 is less than 1% of the phase margin Pm1.

[0061] In various embodiments, the design parameters (e.g., cutoff frequency) of the loop filter 306 (e.g., a low-pass filter) may be determined to meet the design requirements of the PLL circuit 200 operating with both the primary loop 220 and the secondary loop 222 activated. In one embodiment, the loop filter 306 is designed so that the loop bandwidth of the secondary loop 222 is less than the loop bandwidth of the primary loop 220. In one example, the loop bandwidth of the primary loop 220 (e.g., approximately 1 MHz) is more than 10 times the loop bandwidth of the secondary loop 222 (e.g., approximately 10 KHz). In this particular example, the difference between the phase margin Pm1 and the phase margin Pm2 is less than 1% of the phase margin Pm1.

[0062] 5A, 5B, and 5C illustrate that the effects of temperature changes on the PLL circuit 200 (e.g., VCO frequency drift) are compensated for by using a secondary loop 222 in conjunction with the primary loop 220 in the PLL circuit 200. Specifically, the secondary loop 222 includes a closed-loop temperature tracking loop that continuously monitors temperature changes and provides an appropriate control signal 228 to the VCO 208 to compensate for the temperature changes. The example in FIG. 5A shows voltage curves 224-1 and 224-2 for the PLL circuit 200. Specifically, the voltage curve 224-1 illustrates the voltage versus time curve of the signal 224 when the PLL circuit 200 is operating with the secondary loop 222 disabled. In other words, the voltage curve 224-1 corresponds to the PLL circuit 200 operating with only the primary loop 220 enabled. Voltage curve 224-2 shows the voltage versus time curve of signal 224 when PLL circuit 200 is operating with secondary loop 222 enabled. In other words, voltage curve 224-2 corresponds to PLL circuit 200 operating with both primary loop 220 and secondary loop 222 enabled.

[0063] The example of Figure 5B shows a temperature difference curve 506 that indicates the temperature difference over a corresponding time. As shown in Figure 5B, between times 502 and 504, the temperature changes from temperature Temp1 to temperature Temp2. ​​In one example, this increase in temperature causes a voltage change in voltage curves 224-1 and / or 224-2.

[0064] Referring again to FIG. 5A, by using the secondary loop 222 in the PLL circuit 200, as shown by voltage curve 224-2, the voltage of signal 224-2 is more stable between times 502 and 504 (e.g., compared to signal 224-1). This is achieved by using the secondary loop 222 to compensate for temperature changes. Referring to the example of FIG. 5C, a frequency curve of the output signal 216 of the VCO 208 is shown. As shown in FIG. 5C, using the secondary loop 222 results in a reduced effect of temperature changes on the frequency of signal 216, thereby providing a more stable frequency for the output signal 216 of the VCO 208.

[0065] Referring to the examples of Figures 6A, 6B, 6C, and 6D, a ring-type VCO 600 (e.g., VCO 208 of Figure 2) is shown. In various embodiments, a PLL circuit using a ring-type VCO has significant area advantages over a PLL circuit using an LC tank-type VCO, but may be more susceptible to temperature variations, especially in highly scaled processes such as 7 nm processes. By using secondary loop 222 as a closed-loop temperature tracking loop that continuously monitors voltage variations with temperature and provides appropriate control signals to counteract the voltage variations, temperature variations in the ring-type VCO-based PLL circuit are compensated for, improving PLL performance by providing a more stable output frequency.

[0066] As shown in FIG. 6A, ring VCO 600 is a pseudo-differential three-stage VCO. As shown in FIGS. 6B and 6C, coarse frequency control in ring VCO 600 can be implemented using pMOS transistors and control signal 622 (e.g., coarse<5:0>) in supply path 620 and nMOS transistors and control signal 642 (e.g., coarse_b<5:0>) in ground path 640. As shown in FIGS. 6A and 6D, fine frequency tuning of ring VCO 600 can be achieved using various control paths. For example, the control paths can include a Kvco1 path using control signal 606 (also referred to as Kvco1 signal 606) that controls varactors 602-1, 602-2, and 602-3 of the three delay cell stages of ring VCO 600, respectively. As a further example, the control path may include a Kvco2 path that uses a control signal 608 (also referred to as Kvco2 signal 608) of closed secondary loop 222 that controls varactors 604-1, 604-2, and 604-3, respectively, of three stages of delay cells of ring-type VCO 600. As shown in FIG. 6D , as a further example, the control path may include a Kvco3 path (e.g., by controlling avss_reg) that uses an nMOS current source control circuit 660 having a control signal 662 (also referred to as Kvco3 signal 662).

[0067] 7 and 8, a PLL circuit including its Kvco1, Kvco2, and Kvco3 paths (e.g., PLL circuit 200 having primary loop 220 and secondary loop 222 of FIG. 2) can be programmed to operate in various compensation modes. FIG. 7 shows a compensation mode control circuit 700 in which compensation mode control signals Ctrl1 702 and Ctrl2 706 can be programmed (e.g., using switches 704 and 708, respectively) to generate Kvco1 signal 606, Kvco2 signal 608, and Kvco3 signal 662 using a temperature-dependent voltage Vte 710 generated by an open loop having Vctrl1 226, Vctrl2 228, and a temperature-dependent voltage circuit 712. For example, the Kvco1 path can be used for primary loop 220 (e.g., signal 226 of primary loop 220 is used as Kvco1 signal 606). As a further example, the Kvco2 path may be programmed to be used for the primary loop 220 (e.g., signal 226 of primary loop 220 is used as Kvco2 signal 608) or the secondary loop 222 (e.g., signal 228 of secondary loop 222 is used as Kvco2 signal 608). In yet another example, the Kvco3 path may be programmed to be used for the secondary loop 222 (e.g., signal 228 of secondary loop 222 is used as Kvco3 signal 662) or an open loop with a temperature dependent voltage circuit 712.

[0068] 8, various compensation modes 802 are shown. For example, in "fully open loop" mode, the signal 226 of the primary loop 220 is provided as both the Kvco1 signal 606 and the Kvco2 signal 608, and the open loop Vte 710 is provided to the Kvco3 signal 662 for temperature compensation. In other words, in "fully open loop" mode, the signal 228 of the secondary loop 222 is not used for temperature compensation.

[0069] As a further example, in the "closed loop through varactors, open loop through current sources" mode, signal 226 of primary loop 220 is provided as Kvco1 signal 606, signal 228 of secondary loop 222 is provided as Kvco2 signal 608 (e.g., providing a closed loop for compensation through varactors 604-1, 604-2, and 604-3), and open loop Vte 710 is provided as Kvco3 signal 662 (e.g., providing an open loop for compensation through current source control circuit 660).

[0070] As a further example, in the "closed loop to current source" mode, the signal 226 of the primary loop 220 is provided as both the Kvco1 signal 606 and the Kvco2 signal 608, and the signal 228 of the secondary loop 222 is provided as the Kvco3 signal 662 for temperature compensation (e.g., providing a closed loop for compensation through the current source control circuit 660).

[0071] As a further example, in the "closed loop through varactors and current sources" mode, signal 226 of primary loop 220 is provided as Kvco1 signal 606, and signal 228 of secondary loop 222 is provided as both Kvco2 signal 608 (e.g., providing a closed loop for compensation through varactors 604-1, 604-2, and 604-3) and Kvco3 signal 662 (e.g., providing a closed loop for compensation through current source control circuit 660).

[0072] Referring to the example of Figure 9, a PLL circuit 900 is shown that is substantially similar to the PLL circuit 200 of Figure 2, except for the following differences. The PLL circuit 900 includes a primary loop 220, a secondary loop 222, and an open loop that uses a temperature-dependent voltage Vte 710 generated by a temperature-dependent voltage circuit 712. The temperature-dependent voltage Vte 710 is provided to the VCO 208 for frequency tuning of the frequency of the output signal 216 (e.g., in a "fully open mode" or a "closed loop via varactor, open loop via current source" mode, discussed above with reference to Figures 7 and 8).

[0073] It should be noted that the various configurations shown in FIGS. 1-9 are illustrative only and are not intended to be limiting beyond what is specifically set forth in the following claims. Those skilled in the art will understand that other configurations may be used. At least one element of various embodiments may be implemented by software, hardware (e.g., application-specific integrated circuits (ASICs), application-specific standard components (ASSPs), logic on a programmable logic IC (e.g., FPGA)), firmware, and / or a combination thereof. Embodiments may be implemented using various hardware resources, such as DSP slices, BRAM, and programmable resources of an FPGA. However, in other embodiments, digital signal processors, microprocessors, multi-core processors, memory, and / or other hardware may be used. When implemented in software, the elements of embodiments of the present disclosure are essentially the code segments that perform the necessary tasks. Programs or code segments may be stored in a processor-readable storage medium or device downloaded by a computer data signal embodied in a transmission wave over a transmission medium or a communications link. The processor-readable storage device may include any medium capable of storing information, including optical, semiconductor, and magnetic media. Examples of processor-readable storage devices include semiconductor devices, semiconductor storage devices, electronic circuits that are read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), floppy disks, CD-ROMs, optical media, hard disks, or other storage devices. Code segments may be downloaded over a computer network such as the Internet, an intranet, or the like.

[0074] While particular embodiments have been shown and described, it is not intended to limit the claimed invention to the preferred embodiments, and it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the claimed invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The claimed invention is intended to cover alternatives, modifications, and equivalents.

Claims

1. A phase locked loop (PLL) circuit, a voltage controlled oscillator (VCO); a first loop circuit including a first loop filter and a charge pump; The first loop filter is receiving a first signal from the charge pump based on a feedback signal from the VCO; and configured to provide a first VCO frequency control signal to the VCO; The phase locked loop (PLL) circuit a second loop circuit including a compensation circuit; The compensation circuit receiving a reference signal determined based on an operating range of the charge pump and the first signal identical to the first signal received by the first loop filter; and providing a second VCO frequency control signal to the VCO; The phase locked loop (PLL) circuit The PLL circuit further comprises a compensation mode selection circuit configured to selectively provide the second VCO frequency control signal to an input of the VCO.

2. 2. The PLL circuit of claim 1, wherein a first bandwidth of the first loop circuit is greater than a second bandwidth of the second loop circuit.

3. 3. The PLL circuit of claim 2, wherein the first bandwidth is at least 10 times greater than the second bandwidth.

4. The compensation circuit an operational amplifier configured to generate a second signal based on the first signal and the reference signal; a second loop filter configured to generate the second VCO frequency control signal based on the second signal;

5. 5. The PLL circuit according to claim 4, wherein the second loop filter is a low-pass filter configured such that a first bandwidth of the first loop circuit is greater than a second bandwidth of the second loop circuit.

6. 6. The PLL circuit according to claim 1, wherein the second VCO frequency control signal has a minimum voltage equal to a ground voltage.

7. 6. The PLL circuit according to claim 1, wherein the VCO includes a ring oscillator.

8. 6. The PLL circuit of claim 1, wherein the second VCO frequency control signal is configured to control at least one of a varactor of the VCO and a current source of the VCO to control the output frequency of the VCO.

9. 6. The PLL circuit of claim 1, wherein the VCO is configured to receive a third VCO frequency control signal from an open-loop temperature dependent voltage circuit.

10. The compensation mode selection circuit a first compensation mode in which the second VCO frequency control signal is configured to control one of a varactor of the VCO and a current source of the VCO; a second compensation mode in which the second VCO frequency control signal is configured to control the other of the varactor of the VCO and the current source of the VCO; a third compensation mode in which the second VCO frequency control signal is configured to control both the varactor of the VCO and the current source of the VCO; 10. The PLL circuit of claim 9, wherein the third VCO frequency control signal is configured to select a compensation mode for controlling the output frequency of the VCO from a fourth compensation mode configured to control both the varactors of the VCO and the current sources of the VCO.

11. receiving a first signal from the charge pump based on a feedback signal from a voltage controlled oscillator (VCO) by a first loop filter in a first loop circuit; providing a first VCO frequency control signal to the VCO via the first loop filter; a compensation circuit of a second loop circuit receives a reference signal determined based on an operating range of the charge pump and the first signal that is identical to the first signal received by the first loop filter; providing, by the compensation circuit, a second VCO frequency control signal to the VCO based on a difference between the reference signal and the first signal; and selectively providing the second VCO frequency control signal to an input of the VCO by a compensation mode selection circuit.

12. generating, by the compensation circuit, a second signal based on the difference between the first signal and the reference signal; 12. The method of claim 11, further comprising using a second loop filter of the compensation circuit to generate the second VCO frequency control signal based on the second signal.

13. 13. The method of claim 11 or 12, wherein the second VCO frequency control signal controls at least one of a varactor of the VCO and a current source of the VCO to control the output frequency of the VCO.

14. 13. The method of claim 11 or 12, further comprising receiving, by the VCO, a third VCO frequency control signal from an open-loop temperature dependent voltage circuit.

15. a first compensation mode in which the second VCO frequency control signal is configured to control one of a varactor of the VCO and a current source of the VCO; a second compensation mode in which the second VCO frequency control signal is configured to control the other of the varactor of the VCO and the current source of the VCO; a third compensation mode in which the second VCO frequency control signal is configured to control both the varactor of the VCO and the current source of the VCO; and a fourth compensation mode configured to control both the varactors of the VCO and the current sources of the VCO, wherein the third VCO frequency control signal selects a compensation mode for controlling the output frequency of the VCO.

Images