Frame Data Processing Circuit

Abstract

To provide a frame data processing circuit configured to classify frames with greater flexibility for filter processing, and to make better use of resources, and which is easier to adapt to different applications.SOLUTION: A frame data processing circuit for use in frame filtering includes a plurality of comparator units. Each comparator unit is configured, in response to receiving at least a part of a frame data, to perform a determination whether at least partial data of the frame data matches respective reference value and to provide a result of the comparator unit based on the determination. The circuit includes: a crossbar unit coupled to outputs of the comparator units and configured to provide at least one set of crossbar switch outputs via configurable interconnects; and a cascade unit coupled to the crossbar switch outputs and configured to provide a logic output by a result-combining logic unit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to frame data processing, and in particular to classifying frame data received from one or more communication networks for use in frame filtering, and to frame filtering. [Background technology]

[0002] Increasingly in automotive and industrial applications, software running on a System on Chip (SoC) or Microcontroller (MCU) uses different dedicated processing paths to exchange data over communication networks such as Ethernet and Control Area Network (CAN) networks.

[0003] Hardware-implemented filters can be used to check parameters of received data received from a communication network interface so that the target SoC or MCU (e.g., CPU) knows how to process the received data. For example, in Ethernet and CAN frames, such parameters include identifiers (e.g., stream ID or CAN ID, among others), addresses (e.g., destination address), message type, and upper layer protocol fields (such as IPv4).

[0004] A hardware implemented filter can be implemented in several different ways.

[0005] Memory-based or register-based filters can be used to determine whether incoming data matches filter criteria. The filter criteria can be a pattern (such as a field in a header), a masked pattern, a range, or a combination thereof. The filter criteria can take the form of values ​​stored in programmable memory or registers.

[0006] A series of filters can be used to process the incoming data. Thus, a first filter can be used to filter based on a first criterion, then a second filter can be used to filter based on a second criterion, and so on. This approach is suitable for protocols with relatively low event rates, such as CAN, where the interval between events is greater than 100 microseconds.

[0007] However, filters can be arranged in parallel using (hardware) registers, Ternary Content Address Memory (TCAM), or hash tables. A parallel approach usually provides much faster results than a serial approach and is therefore suitable for protocols with higher event rates, where the interval between events is less than 1 microsecond, and / or for implementations where several data interfaces use the same pool of filters.

[0008] Filtering is typically customized to a particular protocol and use case.

[0009] For example, in CAN, filtering is primarily done using only Media Access Control (MAC) layer fields, while in Ethernet applications filtering can also use only MAC layer fields, but more sophisticated applications can use higher level protocols such as the IP protocol.

[0010] The use of parallel filters and deeper forms of filtering comes at a cost. For example, deeper forms of filtering increase the complexity of the filter in terms of the number of fields used, their variation, and their depth. Furthermore, complex filters tend to have a large silicon footprint and consume large amounts of power.

[0011] Patent Document 1 discloses a communication network controller module for storing media data in memory. This module is composed of a media access controller and a message handler. When the message handler receives a frame containing frame data from the media access controller, it identifies the frame type of the frame and stores the frame in a receive buffer depending on the frame type. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] U.S. Patent Publication No. 2019 / 0288961 Summary of the Invention [Problem to be solved by the invention]

[0013] It is therefore an object of the present invention to provide filtering by classifying frames with greater flexibility. [Means for solving the problem]

[0014] According to a first embodiment of the present invention, a circuit for use in frame filtering is provided. The circuit includes a plurality of comparators. Each comparator is configured to, in response to receiving at least a portion of frame data, perform a determination as to whether data in the portion of the frame data matches respective reference data and provide a result to a comparator output based on the determination. The circuit includes a crossbar switch having crossbar inputs coupled to respective comparator outputs and configured to provide a set of crossbar switch outputs via configurable interconnections. The circuit includes a set of result-combining logic units, each result-combining logic unit coupled to a respective set of crossbar switch outputs and providing a logic unit output (or "matching output").

[0015] This circuit can be used to classify frames with greater flexibility and thus aid in filtering, which allows for better use of resources and makes it easier to adapt to different applications.

[0016] The configurable interconnection may be provided by a multiplexer. At least one crossbar input may be configurably (or, for example, "reconfigurably," "selectably," or "programmably") provided to at least two of the result combining logic units. Thus, the result of the comparison may be used multiple times. At least one result combining logic output may be configurably provided as a crossbar input. Thus, the result may be reused. The plurality of comparators may include a plurality of configurable comparators operable in at least first and second selectable modes, where in the first mode, the data portion is maskable with a mask. The plurality of configurable comparators may be operable to receive two sets of reference data and perform a decision using both sets of reference data. The two sets of data may be concatenated. At least some of the plurality of comparators may be configured to apply an offset to select the portion of the frame data used in the decision. At least some of the plurality of comparators may comprise one or more finite state machines (FSMs) for processing the comparison of the portion of the data with the reference data. The comparator may include at least one block comparator configured to compare portions of the frame data to B sets of reference data, where B is a positive, non-zero integer greater than or equal to 4, e.g., between 4 and 32. The value of B may take on a value of 2n (where n is a positive, non-zero integer (e.g., B may be 4, 8, 16, and 32)) to identify matches up to B and / or a value of 2n-1 (e.g., B may be 3, 7, 15, or 31) to identify matches up to B-1 or no matches. The result combining logic may be or include an AND gate. The result combining logic may be or include an OR gate, for example, to identify the presence of one of several matches (such as one of several IP addresses).

[0017] The multiple comparators may include configurable (reconfigurable) comparators, preconfigured comparators, and / or block comparators. For example, the multiple comparators may include only configurable comparators. The comparators may be configured to process blocks of data of different sizes, such as 2 bytes, 3 bytes, or 4 bytes. For each type of comparator (e.g., configurable comparator), there may be a first set of comparators configured to process data of a first block size, such as 2 bytes, a second set of comparators configured to process data of a second different block size, such as 3 bytes, and, optionally, a third set of comparators configured to process data of a third different block size, such as 4 bytes. There may be more configurable comparators than preconfigured comparators and / or block comparators.

[0018] According to a second embodiment of the present invention, there is provided a classifier comprising the circuit of the first embodiment and a priority select arranged to receive a logic portion output from the circuit and to generate a classification number in dependence on the logic portion output.

[0019] According to a third embodiment of the present invention, there is provided a filter comprising the circuit of the first embodiment or the classifier of the second embodiment and an operational unit configured to process the frame depending on the logic unit output and / or the classification number.

[0020] According to a fourth embodiment of the present invention, there is provided a semiconductor device including the classifier according to the second embodiment or the filter according to the third embodiment. The semiconductor device is an MCU, an SoC, or an application-specific semiconductor device.

[0021] According to a fifth embodiment of the present invention, there is provided a switch or end station comprising the classifier of the second embodiment or the filter of the third embodiment.

[0022] According to a sixth embodiment of the present invention, there is provided a system including a communication gateway including the semiconductor device of the fifth embodiment, and at least one node (such as a module, electronic control unit, or other computing node) communicating with the semiconductor device, and a filter configured to receive frames from the at least one node and process the frames according to the classification number. The node may be a powertrain module (such as an engine electronic control unit), a chassis module (such as a brake wiring electronic control unit), a body / comfort module (such as an air conditioning electronic control unit), a driver assistance module (such as a lane departure control unit), an infotainment module, etc. The semiconductor device may provide a switch or an end station in the communication system.

[0023] According to a seventh embodiment of the present invention, there is provided a vehicle including the system of the sixth embodiment functionally integrated into the vehicle. The system may be used to provide communication between computing nodes within the vehicle and / or between nodes within the vehicle and nodes outside the vehicle (e.g., via another vehicle or an external communications network), and the vehicle may be an automobile. The automobile may be a motorcycle, a car (sometimes referred to as a "car"), a minibus, a bus, a truck, or a lorry (large truck). The automobile may be powered by an internal combustion engine, one or more electric motors, or both (i.e., a "hybrid"). The vehicle may be an aircraft (or other airborne vehicle), a train, a ship (or other watercraft), or a spacecraft.

[0024] According to an eighth embodiment of the present invention, there is provided a method comprising the steps of receiving at least a portion of frame data for a plurality of reference data sets, performing a determination whether data in at least a portion of the frame data matches the reference data, providing a result based on the determination, selecting a group of the results, and processing the group results using result combination logic to obtain a logic output.

[0025] The method may further include generating a classification number in response to the logic unit output. The method may further include processing the frame in response to the logic unit output and / or the classification number.

[0026] In the following, the invention will be further explained with reference to embodiments shown in the accompanying drawings. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a diagram illustrating the configuration of an IEEE1722 frame. [Figure 2] FIG. 1 is a data flow diagram for AVB filtering. [Figure 3] FIG. 10 is a diagram showing the relationship between the number of filters and the constituent flops in the first filtering process and the second filtering process. [Figure 4] FIG. 2 is a data flow diagram for a frame filter according to the present invention. [Figure 5] FIG. 1 is a schematic block diagram of a configurable comparator including a value comparator and at least one FSM. [Figure 6] FIG. 10 is a circuit schematic diagram of a configurable comparator. [Figure 7A] FIG. 10 illustrates a mask mode of operation for the configurable comparator. [Figure 7B] FIG. 10 illustrates an extended mode and a precise mode of operation for a configurable comparator. [Figure 8] FIG. 2 illustrates a block comparator. [Figure 9] FIG. 1 illustrates three modes in which the filter may operate. [Figure 10] 1A and 1B are diagrams showing an untagged Ethernet frame, single-tagged Ethernet frame data, and double-tagged Ethernet frame data. [Figure 11] FIG. 1 is a diagram illustrating an IPv4 header. [Figure 12] FIG. 1 is a diagram illustrating an IPv6 header. [Figure 13]1 is a table illustrating different modes of filtering based on Ethernet type. [Figure 14] 1 is a table showing different filter regions. [Figure 14A] 1 is a table showing different filter regions. [Figure 14B] 1 is a table showing different filter regions. [Figure 14C] 1 is a table showing different filter regions. [Figure 15] FIG. 1 is a block diagram of an identification stage including a crossbar section and a cascade section. [Figure 16] FIG. 2 is a schematic block diagram of a classification unit. [Figure 17] FIG. 2 is a block diagram showing an example of a crossbar unit and a cascade unit. [Figure 18] FIG. 1 illustrates a dedicated filter for a TCP session request. [Figure 19] FIG. 10 illustrates filter offsets for three different types of frames. [Figure 20] FIG. 10 illustrates different offsets for selecting or hiding Layer 2 and / or Layer 3 headers. [Figure 21] FIG. 1 is a schematic block diagram of a configurable comparator including a value comparator and first and second FSMs. [Figure 22] FIG. 22 illustrates the use of a storage device in the configurable comparator shown in FIG. 21. [Figure 23] FIG. 22 is a state diagram of the first FSM shown in FIG. 21. [Figure 24] FIG. 22 is a state diagram of the second FSM shown in FIG. 21. [Figure 25] FIG. 1 is a block diagram of an MCU. [Figure 26] FIG. 10 is a process flow diagram for frame filtering. [Figure 27] 1 is a schematic diagram of an automobile including a semiconductor device including a frame filter. DETAILED DESCRIPTION OF THE INVENTION

[0028] (AVB reception classification) 1 and 2 show an IEEE 1722 frame 1 and an AVB filter 11 for filtering frames received by a message handler in an AVB (Audio Video Bridging) end station. The IEEE1722 frame 1 includes a preamble 2, a Start Frame Delimiter (SFD) 3, an Ethernet header 4, a payload 5, and a Frame Check Sequence (FCS) 6. The IEEE1722 frame header 4 is composed of a destination address 7, a source address 8, a VLAN tag 9, and an Ethernet type (EthType) 10.

[0029] The filter 12 includes a frame type identification block 13 that can examine the destination address 7, VLAN tag 9, and Ethernet type (EthType) 10 to determine whether a frame 14 (not shown) received from a media access controller (MAC) is an IEEE 1722 frame 1 and whether it complies with IEEE 802.1AS. The filter 12 can include up to 16 other filters 15, for example, to identify frames with a given MAC address. Once a frame is identified, a chain selector 16 selects the corresponding chain. The chain identifier 17 and frame 1 are passed to a direct memory access controller (DMAC) 18 for storage in the appropriate queue in system memory (not shown).

[0030] Different applications (i.e., different use cases) may require different filters and follow different approaches for classification. For example, in one application, a user may want to filter frames based on MAC address, VLAN, and some OSI (Open System Interconnection) Level 4 data, while in another different application, a user may want to filter frames based on IP address and port number.

[0031] The AVB filter 11 mentioned above can only be used to filter 1722 AVB frames and is based on the stream ID. If different filtering is required based on IPv4 or IPv6 addresses, DPI (Deep Package Inspection), etc., different filters are required.

[0032] One way this can be achieved is to provide a full set of filters covering the entire range of applications from which the user can select the filter they are interested in. However, this increases the size of the silicon footprint required for the filter as well as the number of bits used to configure the filter.

[0033] 3, for relatively simple AVB filters 11, the number of configuration flops increases as the number of filters increases. For more complex filters, the number of configuration flops increases significantly with the number of filters.

[0034] (Flexible and configurable frame filtering) FIG. 4 shows a filter 21 that is flexible and configurable depending on the application.

[0035] The filter 21 may provide and / or allow flexible frame identification, flexible filter offsets, multiple filter positions, flexible Direct Memory Access (DMA) chain mapping, and / or filter results to be reused.

[0036] Instead of using hard-coded identification, the filter 21 is configurable. The filter 21 can check one or more selectable parts of the received frame 22. The filter 21 can perform distributed identification across OSI layer headers (e.g., User Datagram Protocol (UDP), Ethernet type, IPv4 address, UDP protocol type, UDP port, and application-specific ID in the UDP payload) and multiple locations within the frame. If frame identification is based only on, for example, the UDP port number, filter results can be reused, thereby requiring fewer hardware resources.

[0037] 4, the filter 21 comprises a classifier 23 for identifying whether a part (or parts) of the frame 22 matches a predetermined criterion (or a number of corresponding criteria) and outputting the result in the form of a classification number 24. The classification number 24 is passed to an operator 25 which decides based on the classification number 24 how the frame 22 should be processed.

[0038] While classification is being performed, the frames 22 may be stored in a memory 26, such as a first in first out (FIFO) buffer.

[0039] The sorter 23 includes a comparator pool 31 (or "set" or "bank") that may include a set of configurable comparators 32, a set of preconfigured comparators 33, and / or a set of block comparators 34.

[0040] The comparator pool 31 may contain only one type of comparator, such as the configurable comparator 32 .

[0041] The comparator pool 31 may include comparators 32, 33, 34 used to process data of different sizes, such as 2 bytes (2-byte filter), 3 bytes (3-byte filter), and / or 4 bytes (4-byte filter). For example, the comparator pool 31 may include 64 2-byte configurable comparators 32, 64 3-byte configurable comparators 32, and 64 4-byte configurable comparators 32. However, there may be fewer or more comparators 32 of each size.

[0042] The comparator pool 31 may include configurable comparators 32, preconfigured comparators 33, and a set of block comparators 34. For example, there may be 64 configurable comparators 32 for each filter size, two preconfigured comparators 33 (optionally, two for each filter size), and one or two block comparators 34 (optionally, one or two for each filter size).

[0043] As will be explained in more detail below, the preconfigured comparator 33 and the block comparator 34 are generally simpler versions of the configurable comparator 32, i.e., they generally include less hardware logic, but the hardware logic is optimized for a particular situation. For example, the preconfigured comparator 33 is intended to be used to filter commonly used fields such as Ethernet type. The block comparator 34 is intended to filter a limited number of fields (e.g., only one field) that can have many values ​​(e.g., up to 16 values), for use with AVB, for example.

[0044] 4, the classification unit 23 includes a matching unit 36 ​​for processing outputs 35 of the comparison units 32, 33, and 34. The matching unit 36 ​​includes a crossbar unit 37 (also referred to herein as a "crossbar block," "crossbar switch," or simply a "crossbar") and a cascade unit 38 (also referred to herein as a "cascade block" or simply a "cascade"). As will be explained in more detail below, the crossbar unit 37 and the cascade unit 38 are programmable and can be used to identify specific combinations of data. Furthermore, at least some of the results 40 from the cascade unit 38 can be reused by the crossbar unit 37.

[0045] The classification unit 23 includes a priority selection unit 41 which processes the results 39 from the matching unit 36 ​​and outputs a classification number 24 .

[0046] Classification unit 23 includes an interface 42 to a host 43. Host 43 can program registers 62 (FIG. 5) used to configure comparators 32, 33, 34, register 125 (FIG. 16) used to configure crossbar unit 37 and cascade unit 38, and register 132 (FIG. 16) used to configure priority selector 41.

[0047] (Comparison section - introduction) 5, the comparison units 32, 33, 34 are built around a value comparator 44. A frame 22 is received from a data bus 45 via a store 46 and a byte selector 47, which selects data 49 for comparison based on an offset 48 using first and second values ​​50, 51 according to a mode 52, and provides first and second outputs 53, 54 indicating a match ("Match 1" and "Match 2").

[0048] The comparators 32, 33, 34 may include an offset / position control 57 that includes an offset counter 58, a mode control 59, and a position control 60. Offsets are described in more detail below.

[0049] The comparison section 32 , 33 , 35 includes a configuration section 61 which includes a set of registers 62 and logic 63 for configuring the value comparator 44 , the byte selector 54 and the offset and position control section 57 .

[0050] The comparison units 32 , 33 , 35 may include one or more FSMs 64 , 65 that can process the outputs 53 , 54 of the value comparators 44 .

[0051] The outputs 66, 67 of the FSMs 64, 65 or the outputs 53, 54 of the value comparator 44 are output to a circuit 70 for further processing. The circuit 70 includes a matching section 36 and a priority selection section 41.

[0052] Referring to FIG. 6, value comparator 44 receives n-bit data 49 from frame 22 (FIG. 5) on a first line 71 (the "data line"), a mode 52 on a second line 72 (the "mode line"), a first n-bit value 50 on a first line 73 (the "first value line"), and a second n-bit value 51 on a second line 71 (the "second value line").

[0053] As described in more detail below, the first value 50 is provided as a mask or filter value ("first filter value" or "first reference value"), and the second value 51 is provided as a filter value ("second filter value" or "second reference value").

[0054] Mode 52 and first value 50 are provided as inputs to bitwise OR gate 75 (in the form of n two-input OR gates) via mode line 72 and first value line 73. The n-bit wide output of bitwise OR gate 75 is passed via line 76 to bitwise AND gate 77 (in the form of n two-input AND gates), which also receives data 49 via data line 71.

[0055] The output of bitwise AND gate 77 is passed via line 78 as one of the inputs to a first bitwise XOR gate 79 (forming n two-input XOR gates), which also receives as its other input the second value 51 via second value line 74. The n-bit wide output of first bitwise XOR gate 79 is output via line 80 to a first n-input AND gate 81. The single-bit output of first n-input AND gate 81 is output via line 82 as the first value comparator output 53.

[0056] The data 49 and the first value 50 are provided as inputs to a second bitwise XOR gate 83 (again forming n two-input XOR gates). The n-bit wide output of the second bitwise XOR gate 83 is output via line 84 to a second n-input AND gate 85. The single-bit output of the second n-input AND gate 85 is output via line 86 as the second value comparator output 54. The bitwise XOR gates 79, 83 are also referred to herein as "comparators."

[0057] As previously mentioned, the comparators 32, 33, 34 may be configured to receive and process 2-byte (16-bit) blocks, 3-byte (24-bit) blocks, or 4-byte (32-bit) blocks of data.

[0058] 7, in the so-called "mask mode," a first value 50 is used as a mask and a second value 51 is provided as a value to match (the "reference value"). The mask 50 is used to mask individual bits so that the comparator 79 only compares the unmasked bits of the data 49 with the reference 51.

[0059] In a so-called "extended mode," the first and second filter values ​​50, 51 can be concatenated to create a double-wide filter that is 2n bits wide. Alternatively, in a so-called "precise mode," each of the first and second filter values ​​50, 51 is used as an n-bit reference, where the mode is handled partly by the value comparator 44 and partly by the FSMs 64, 65. However, in some embodiments, different modes can be implemented within the value comparator 44 using a multiplexer (not shown).

[0060] The preconfigured comparator section 33 is similar to the configurable compare section 32. However, it may differ in that some of the values ​​50, 51 are fixed. The values ​​50, 51 may be hardwired at the time of manufacture or may be one-time programmable. Thus, the preconfigured compare section 33 may be identical to the configurable compare section 32, except that the values ​​cannot be reprogrammed.

[0061] Referring to FIG. 8, the block comparator 34 may include a set of B simplified value comparators 44′, where B is a positive, non-zero integer between 8 and 16, for example. Each simplified value comparator 44′ includes a bitwise XOR gate 79 and an AND gate 81. The same n-bit data is provided to each of the B simplified value comparators 44′, and each simplified value comparator 44′ compares the data with a respective n-bit value, i.e., value[0], value[1], ..., value[B-1]. In some cases, one or more of the values ​​may be fixed and not configurable. This arrangement is useful for routing applications.

[0062] Block comparators 34 are less flexible but simpler and therefore cheaper to implement. Using filter modes (e.g., mask, fine, and extended modes) can help reduce the amount of processing power (flops) required to fully configure classifier 23 (FIG. 4). Using block comparators 34 (e.g., 1 offset / 16 values ​​on the mask) helps reduce the area of ​​classifier 23. Using comparators 34 that share the same offset (e.g., a group of four filters) also helps reduce the area consumed by the offset selector.

[0063] FIG. 9 shows the processing of a stream of data 87 in a frame 22 (FIG. 5) starting from byte 0 and including bytes n, n+1, . . . , n+5 through a configurable comparator 32 having a width of 3 bytes.

[0064] 7 and 9, the offset 88 is used to select the start 89 of the data 87 to be processed, in this case byte n.

[0065] In mask mode, three bytes of data N, N+1 and N+2 are masked using a stored mask provided by a first value 50 and compared by a first comparator 79 with reference data provided by a second value 51.

[0066] In the extended mode, six bytes of data N, N+1, N+2, N+3, N+4, N+5 are left unmasked and are compared by the first and second comparators 79, 83 with the concatenated data provided by the first and second values ​​50, 51.

[0067] In precise mode, the first three bytes of data N, N+1, N+2 are left unmasked and are compared by a first comparator 79 with data provided by a first value 50. The second three bytes of data N+3, N+4, N+5 are also left unmasked and are compared by a second comparator 83 with a second value 51.

[0068] How the value comparator 44 and modes are set is explained in more detail below.

[0069] (Offset (General)) The classifier 23 can examine individual portions or parts of the frame by using one or more offsets. The relevant parts of the frame differ between protocols, and it may be desirable to use different protocols in parallel and check different parts of the frame in parallel.

[0070] Before describing how the offset is used, some examples of different communication protocols and what parts of the frame they may be of interest will be given.

[0071] Referring to FIG. 10, first, second and third Ethernet frames 1-1, 1-2 and 1-3 are shown.

[0072] The first Ethernet frame 1-1 is an untagged Ethernet frame with the IEEE 802.3 frame structure, where the 16-bit Ethernet type (EthType) 10 immediately follows the source MAC address 8. The Ethernet type (EthType) 10 is used to indicate which protocol is encapsulated in the payload of the frame. For IPv4, the Ethernet type (EthType) is "0X800", and for IPv6, the Ethernet type (EthType) is "0X86DD".

[0073] The second and third Ethernet frames 1-2 and 1-3 support VLAN (Virtual LAN) and are IEEE802.1Q compliant. In the second Ethernet frame 1-2, a 32-bit VLAN header is added immediately after the source MAC address 8, so the Ethernet type (EthType) 10 is shifted by four bytes. In the third Ethernet frame 13, two VLAN headers are added (this is called "double tagging"). A 32-bit service tag (S-VLAN tag) is added immediately after the source MAC address 8, followed by a 32-bit customer tag (C-VLAN tag), so the Ethernet type (EthType) 10 is shifted by eight bytes.

[0074] Ethernet frames can be used to send data as UDP datagrams or in Transmission Control Protocol (TCP) segments transported over Internet Protocol version 4 (IPv4) or Internet Protocol version 6 (IPv6).

[0075] Referring to Figures 11 and 12, an IPv4 header 90 and an IPv6 header 91 are shown.

[0076] Referring specifically to Figure 11, the IPv4 header consists of 20 bytes and has 12 fields including: Version (i.e., b100), IP Header Length (IHL), Type of Service, Total Length (i.e., size of the datagram including header and payload), Identification, Flags, Fragment Offset, Time To Live (TTL), Protocol (e.g., 6 indicates TCP, 17 indicates UDP), Header Checksum, Source Address (i.e., IP address of the sending node), and Destination Address (i.e., IP address of the intended receiving node).

[0077] Referring specifically to Figure 12, the IPv6 header consists of 40 bytes and has eight fields including the version (i.e., b110), traffic class, flow label, payload length, next header type (and uses the same scheme as used in the protocol field in IPv4), hop limit (which replaces the TTL field in IPv4), source address (i.e., the IP address of the sending node), and destination address (i.e., the IP address of the intended receiving node).

[0078] The classifier 23 can be tunably configured to check multiple fields to identify the Ethernet type (EthType) (ie, IPv4 or IPv6) and the protocol or next header (ie, UDP or TCP).

[0079] Variations in the location of the Ethernet Type (EthType) field are accommodated by using a dynamic offset that can be set depending on whether the IEEE 802.1Q header is used or not.

[0080] (Ethernet type) The Ethernet type can be analyzed by a two-byte configurable comparator 32. This can be achieved, for example, by using two comparators 32 operating in precise mode. However, this can be considered unnecessary overhead because no offset is needed, offset multiplexing is computationally expensive, and logic for different modes is not required. Therefore, a block comparator 34 can be used to examine the Ethernet type field and, optionally, the protocol / next header field. Such a block comparator 34 is referred to herein as an "Ethernet block comparator 34." In addition to checking the Ethernet type, the Ethernet block comparator 34 can also check the protocol field and / or the next header field.

[0081] As explained above, the reference values ​​in the comparators may be configurable, i.e., the values ​​stored in registers may be configurable or may be fixed. Given that the pool of potential values ​​for the Ethernet Type and Protocol field and / or Next Header field is small, at least some of the values ​​in the Ethernet block comparators 34 may be fixed.

[0082] 13, the Ethernet block comparator 34 includes a register 62 (FIG. 5) that stores the protocol and next header values, such as "0X806" for Address Resolution Protocol (ARP), "0X800" for IPv4, "0X08DD" for IPv6, "0X06" for TCP, and "0X11" for UDP. FIG. 13 shows a table 92 for describing the header types, EtherType values, and corresponding protocols.

[0083] For Ethernet protocols, the number of fields (and therefore offset values) is limited, so classification keys tend to be limited, focusing primarily on the 1722 stream ID, IPv4 address, and MAC address. Therefore, the Ethernet type is particularly useful for frame type identification, and it is useful to use dedicated logic, for example in the form of an Ethernet block comparator 34, which consumes less area.

[0084] (Example of a filter area) FIG. 14 shows a table 97 listing different types of frames and five different types of filters, ie, five different configurations of comparators 32, 33, 34.

[0085] Frame types include IEEE802.1AS network control traffic such as gPTP (generic Precision Time Protocol) or SPR, ARP (Address Resolution Protocol), LLDP (Link Layer Discovery Protocol), IEEE1722, IPv4, TCP / IPv4, UDP / IPv4, SOME / IPv4, ICMP / IPv4, IPv6, TCP / IPv6, UDP / IPv6, SOME / IPv6, ICMP / IPv6, double tagged, and Null Stream Identification for FREER (IEEE802.1CB).

[0086] A first filter (eg, first configurable comparator 32), input 0, may examine the protocol (PROT) and Ethernet type (TYPE) fields, as well as specific frame type filter bits.

[0087] A second filter (eg, second configurable comparator 32), input 1, can examine four bytes using a reference value and an optional mask in either precise or extended mode.

[0088] A third filter (e.g., third configurable comparator 32), input 2, can examine four bytes using a reference value and an optional mask in either mask mode, precise mode, or extended mode.

[0089] A fourth filter (eg, fourth configurable comparator 32), input 3, can examine four bytes using a reference value and an optional mask in either precise or extended mode.

[0090] A fifth filter (eg, fifth configurable comparator 32), input 4, can examine two bytes using a VLAN C tag, a fixed mask of X000F, and a mask in mask mode.

[0091] In Figure 14, i is the index of the matching filter. The index number varies depending on the software setting of the filter type.

[0092] For example, for TCP / IPv4: Input 0 has a protocol (PROT) of 1, an Ethernet type (TYPE) of "0XXX06", and a specific frame type filter bit of "i". Input 1 has a reference value of IPv4 address, a mask of "NO", and a mode of "PRECISE". Input 2 has a reference value of "PORT", a mask of "NO", and a mode of "PRECISE". Input 3 is unused. Input 4 has a reference value of "VLAN C-tag", a mask of "0X000F", and a mode of "MASK".

[0093] For example, in the case of TCP / IPv6, input 0 has protocol (PROT) of "2", ether type (TYPE) of "0XXX06", and specific frame type filter bit of "i".

[0094] Input 1 has a lookup value of "IPv6 Address", a mask of "IPv6 Address", and a mode of "EXPAND". Input 2 has a lookup value of "PORT", a mask of "NO", and a mode of "PRECISE". Input 3 has a lookup value of "IPv6 Address", a mask of "IPv6 Address", and a mode of "EXPAND". Input 4 has a lookup value of "VLAN C Tag", a mask of "X000F", and a mode of "MASK".

[0095] Therefore, for TCP / IPv4 and TCP / IPv6, either the destination IP address, source IP address, and port value are used, depending on whether the node is a server or a client.

[0096] (Matching section) Referring again to FIG. 4, the matching section 36 includes a crossbar section 37 and a cascade section 38 .

[0097] 15 , the crossbar unit 37 includes M multiplexers 111 (where M is a positive, non-zero integer), each of which can select one of the n matches (where n is a positive, non-zero integer), i.e., one of the n outputs 35 from the comparison units 32, 33, and 34, and provide it as input 0, input 1, ..., input M to an AND gate 123, an example of a result combining logic unit. This arrangement is repeated U times (where U is a positive, non-zero integer). One of the inputs to the multiplexer 111 can include one or more outputs 39 from one or more AND gates 123 as a reusable result 40. Additionally or alternatively, an OR gate (not shown) can be used to receive, for example, the outputs 35 of the comparison units 32, 33, and 34 and / or one or more results 40 from the cascade unit 38.

[0098] Referring also to FIG. 16, the comparator pool 31, the matching unit 36 ​​and the priority selection unit 37 are shown in a different way.

[0099] 16, crossbar section 37 (or "crossbar switch") provides junctions 124 (or "cross junctions") between comparison sections 32, 33, 34 and AND gates 123. Junctions 124 are configurable via registers 125.

[0100] Each AND gate 123-1, 123-2, ..., 123-M is provided as a set of crossbar outputs 126-1, 123-2, ..., 126-M. Each set of crossbar outputs 126-1, 123-2, ..., 126-M may have zero, one, two, three or more crossbar outputs coupled to comparator outputs 35.

[0101] Although not shown in FIG. 16 for clarity, outputs 39-1, 39-2, 39-M from one or more AND gates 123-1, 123-2, ..., 123-M can be returned as inputs to crossbar section 37. This can reduce the number of crossbar inputs. For example, all traffic for a particular UDP destination port can be pre-qualified and a second round of the crossbar can be used to distinguish between possible sources, such as source IP and source port.

[0102] For a 1Gbps link, the minimum event rate is 700ns. If filter 21 (Figure 3) runs at 100MHz, there are approximately 70 clock cycles that can be used to pipeline the complete filtering.

[0103] Continuing with reference to FIG. 16, the priority selection unit 41 includes logic 131 and a register 132.

[0104] The priority selector 41 can implement a strict priority scheme. For example, a simple embodiment can be used that prioritizes the outputs according to the output of the cascade unit 38. Thus, the first output (identification number 0) has the highest priority and the last output (identification number U) has the lowest priority.

[0105] For example, three comparison units 32, 33, 34 can be used to identify (a) IPv4 destination address, (b) IP protocol as TCP, and (c) TCP destination port as 80. Only three AND gates 123 (cascade) can be used: (I) a+b+c, (II) a+b, and (III) a.

[0106] In the priority selection unit 41, the cascades 123 can be ordered so that cascade I has the highest priority (#0) and cascade III has the lowest priority (e.g., #2). Thus, according to the hierarchical sorting, the three types of frames are sorted in the following order: (1) A frame of TCP port 80 (priority #0) using classification number I. For example, it may be transferred to a DMA channel (not shown) of a web server (not shown). (2) Remaining TCP frames using classification number II (priority #1), which may be forwarded, for example, to a DMA channel (not shown) in a TCP stack (not shown). (3) All other IPv4 frames using classification number III (priority #2), which may be forwarded, for example, to a DMA channel (not shown) in a standard IP stack (not shown).

[0107] We can use a chain transform that converts between U and the output priority V using a table of numeric values.

[0108] Priority selection allows for simple coding of hierarchy criteria, as mentioned above. For IPv6 traffic, based on the classification number, the frame can be directed to its own DMA channel, or, depending on the chain selection setting, to the web server's DMA channel (same target as for IPv4).

[0109] FIG. 17 shows the configuration of crossbar section 37 for some of the frame types listed in Table 97 (FIG. 14).

[0110] Referring to Figures 14 and 17, the same output 35 can be used to distinguish between different frames.

[0111] 18, there is shown an example of a dedicated filter 21 (i.e., a configured filter 21) for TCP session requests. In this example, the filter 21 is configured to catch synchronization requests (or "SYN requests") sent by a client (not shown).

[0112] The filter 21 can be configured as follows: (1) An Ethernet type field with a 2-byte filter that uses "0X08DD" as a reference value. (2) Next header and hop limit fields with a 2-byte filter using "0X1100" as a lookup value and "0XFF00" as a mask. (3) Destination address with two 4-byte filters in extended mode (4) A destination port with a two-byte filter using 0X8080 as a reference value. A destination port with a two-byte filter using 0X200 as a reference and 0X200 as a mask. (5) Offset and Control Field

[0113] The destination address and destination port are unique for flow control in the VM (Virtual Machine) (not shown). If a match is found, the VM sets up filtering for the connection.

[0114] In this example, the "always present" entry for "TCP SYN" triggers the management software (not shown). The management software (not shown) checks whether there is a problem with the TCP connection. If yes, the management software (not shown) sets a lower pre-filter for this TCP connection. When the "TCP FIN" frame is seen, it goes back to the management software (not shown). This removes the TCP connection from the filter.

[0115] (Offset (more detailed explanation)) 19, various offset counters 141-0, 141-1, 141-2 can be used to simplify filter programming for a use case. For example, the first offset counter 141-1 can hide optional 802.1Q headers, and the second offset counter 141-2 can start with the IPv4 / IPv6 payload and hide optional IP headers.

[0116] Referring to FIG. 20, untagged, single tagged and double tagged Ethernet frames 11, 12, 13 are again shown.

[0117] The distinction between regions before and after the Ethernet Type (EthType) 10 is useful because it can compensate for the presence of a VLAN tag 9 during offset calculations. The distinction between Layer 2 and Layer 3 offsets can be made by dedicated configuration or by using a programmed offset value.

[0118] Referring to Figure 21, the Ethernet MAC 151 typically provides received data in serial format, for example in blocks of 32-bit data words (with size information if the frame size is not a multiple of 4 bytes).

[0119] The comparator can take two approaches to filtering such data.

[0120] In the parallel approach, all data potentially needed by the comparator is provided in parallel. This approach requires a sufficiently large storage device, such as 1024 flops for a 128-byte offset range. This approach uses byte offset selector logic that uses an n x 128-to-1 multiplexer for the n-bit comparator, since each byte offset is valid.

[0121] In the sequential approach, data is compared on the serial received data stream, for example on chunks of data (data words) provided by the MAC 151. The FSM is used to identify the relevant portion within the frame. In this approach, the byte offset selector is restricted to a position within the data word. This can be achieved by shifting / splitting the value to fit the byte position within the frame (filter check sequential), or by expanding the received data to the width of the comparator.

[0122] Referring also to Figure 22, byte extraction is used using a mix of the two approaches: the comparator is extended by B - 1 bytes (where B is 4 for a 32-bit MAC data bus) and simply byte offset processing is performed; comparators larger than B are processed consecutively (e.g., a 64-bit comparator on a 32-bit MAC data bus).

[0123] (configurable comparison section) FIG. 21 shows the 32-bit configurable comparator 32 in more detail.

[0124] When frame data arrives at the receive buffer 26 via the data bus 45, it is forwarded by the MAC 151.

[0125] 22, data bus 45 is 32 bits wide, so 8-bit data 160, 161, ..., 167 are grouped into 32-bit blocks 168, 169. For example, to allow for the processing of two bytes of data bridging adjacent blocks 168, 169, storage unit 46 can store the last three bytes from the previous block 168, thereby expanding the data to 48 bits.

[0126] 21, byte selector 47 selects which bytes of the extended data to pass to value comparator 44 based on an offset defined by configuration unit 61. Configuration unit 61 passes a reference value and an optional mask to value comparator 44. Configuration unit 61 also sets the mode (e.g., masked, extended, precise) that is passed to value comparator 44 and FSMs 64, 65. The offset is processed by offset counter 58, mode control unit 59, and position control unit 60 according to configuration unit 61.

[0127] In the extended mode, the position control unit 60 checks byte position P and byte position P+1. In the other two modes, the position control unit 60 checks only byte position P.

[0128] As previously explained, value comparator 44 receives n bytes of data 49 and performs a comparison using two n-byte values ​​(eg, N=2).

[0129] A first output 53 of the value comparator 44 is provided to a first, three-state FSM 64 and a second output 54 of the value comparator 44 is provided to a first, three-state FSM 64 and a second, two-state FSM 65, respectively.

[0130] Referring to FIG. 23, the three-state FSM 64 includes first, second, and third states 171, 172, 173, and a checkpoint 174.

[0131] Following a "reset," FSM 64 enters a first state 171 (or "wait" state). In response to detecting the beginning of a frame ("start"), FSM 64 changes to a second state 172 ("check 1"). Match 1 is used to determine how to proceed after checkpoint 174.

[0132] At the checkpoint, if the output 53 of the first value comparator is set to "1" (i.e., matches) and the mode is "no extension", the first FSM output 66 is set to "1", otherwise it is kept at "0".

[0133] At the checkpoint, if the first output 53 is set to "1" (i.e., there is a match) and the mode is "extend," the FSM 64 changes to the third state 173 ("check 2"). When the next n bytes are received, another check is performed for match 2, and the first FSM output 66 returns to the first state 171 (i.e., the "wait" state), depending on whether the second value comparator output 54 is set to "1" or "0."

[0134] Referring to FIG. 24, the two-state FSM 65 includes first and second states 181, 182 and a checkpoint 183.

[0135] Following reset, FSM 65 enters a first state 181 (or "wait state") In response to detecting the beginning of a frame ("start"), FSM 65 changes to a second state 182 ("check 1").

[0136] At the checkpoint, if the second value comparator output 54 is set to "1" (i.e., matches), the second FSM output 67 is set to "1", otherwise it is kept at "0".

[0137] The implementation of block comparator 34 (FIG. 4) is similar to that of configurable comparator 32, except for B reference values ​​and therefore B value comparators 44' (FIG. 8) and B outputs, but with B two-state FSMs 65 and B matching outputs 71 to further circuitry 70. Because block comparator 34 does not have an extended mode, only a simple two-state FSM 65 is required.

[0138] (electronic circuit) Referring to FIG. 25, a semiconductor device 200 in the form of an MCU is shown.

[0139] MCU 200 includes a CPU subsystem 211, an integrated level 2 and level 3 switch 212 interconnected by a system bus 215, and a system memory 213. CPU subsystem 211 includes one or more CPUs 216 (referred to herein as CPU 216 for clarity) and memory 217 that stores application software 218. CPU 216 loads and executes application software 218. System memory 213 is used to store data in a transmit queue 219 and a receive queue 220.

[0140] 25, the switch 212 includes a layer 2 control unit 231 (e.g., a media access controller) and a corresponding temporary storage unit 232. In some cases (e.g., if the integrated layer 2 and layer 3 device is not a switch but instead an end station), there may be only one layer 2 control unit and one temporary storage unit 232. If there are multiple layer 2 control units 231, the switch 212 may include an arbitration unit 233 that provides frames to the classifier 23. The classifier 23 is coupled to a transfer control unit 243 that can pass received data to an appropriate transmit message handler 244 for forwarding or to a bus master interface 255 for passing the received data to the system memory 213. The transfer control unit 243 and the bus master interface 255 function as the operation unit 25.

[0141] The layer 2 controller is connected to an external physical layer transceiver (PHY) (not shown) or an internal (i.e., on-chip) PHY module (not shown). The switch 212 has direct memory access capability and can transfer data between the layer 2 controller 231 and the system memory 213 without CPU intervention.

[0142] The switch 212 includes a special function register (SFR) 246. The switch 212 is controlled by the CPU 216 via the SFR 246 and a peripheral bus interface 247.

[0143] (operation) The operation of the filter 21 will be described with reference to FIGS.

[0144] A frame 22 is received by the filter 21 (step S1). The frame 22 is stored in the receive buffer 26 (step S2) and classified by the classification unit 23 (step S3). The classification unit 23 outputs a classification number 24. The operation unit 25 processes the frame 22 according to the classification number 24 (step S4). The operation unit 25 can, for example, drop the frame, manipulate the frame, forward it to a port, or forward the frame to an on-chip subsystem or a peripheral module.

[0145] (application) FIG. 27 shows a communication system 1000 installed in a vehicle 1001 such as an automobile.

[0146] Network traffic typically increases with the addition of ADAS Electronic Control Units (ECUs) 1010 and new cloud services 1011. Therefore, to help prevent unauthorized access, the communication module 1021 and cockpit module 1022 on which third-party applications (not shown) run must be isolated from the in-vehicle network modules, such as the sensing module 1023 and perception module 1024, and data must be appropriately filtered.

[0147] The communication system 1000 includes a communication gateway 1031 including an MCU 200 having an integrated L2 / L3 Ethernet switch 212 that provides Layer 2 ("L2") switching and Layer 3 ("L3") routing, and L2 Ethernet switches 1032, 1033.

[0148] The integrated L2 / L3 switch 212 can have multiple Gigabit Ethernet ports 1041, 1042, 1043 and provides VLAN tagging / untagging, MAC / IP address filtering and TCP / UDP port filtering.

[0149] FIG. 27 shows a configuration in which the integrated L2 / L3 switch 212 is a separate in-vehicle network using VLANs 1051, 1052, and 1053.

[0150] The integrated L2 / L3 switch 212 is connected to the communication module 1021, which forms a first VLAN 1051. The integrated L2 / L3 switch 212 can be connected to the cockpit module 1022 via a first L2 Ethernet switch 1032 and a second VLAN 1052. The integrated L2 / L3 switch 212 can be connected to the sensing module 1023 and the perception module 1024 via a third L2 Ethernet switch 1033 and a third VLAN 1052. Meanwhile, the integrated L2 / L3 switch 212 can be connected to the ADAS electronic control unit (ECU) 1010 via a CAN-FD network 1060.

[0151] (change) It will be understood that various modifications can be made to the above-described embodiments. Such modifications may involve equivalent and other features which are already known in the design, manufacture, and use of communication network controller modules and components thereof and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0152] The filters described herein can be included in semiconductor devices other than MCUs and SoCs, for example, they can be used in application specific integrated circuits (ASICs).

[0153] The filters can be used in communication peripherals and can be used in automotive, industrial and data center applications. Communication protocols are not limited to Ethernet and CAN (FD, XL).

[0154] Although claims have been formulated in this application to particular combinations of features, it is to be understood that the scope of the present disclosure also includes any novel feature or any novel combination of features disclosed herein, either explicitly or implicitly, or by generalization thereof, regardless of whether it pertains to the same invention as presently claimed in any claim and whether it alleviates any or all of the same technical problems as the present invention. Applicant hereby notifies that new claims may be formulated to such features and / or combinations of such features during the prosecution of this application or any further application derived therefrom. [Explanation of symbols]

[0155] 1 IEEE1722 frame 2 Preamble 3 SFD 4 Ethernet headers 5 Payload 6 FCS 7 Destination (MAC) Address 8 Source (MAC) address 9. VLAN Tags 10 Ethernet Type 11 AVB Filters 12 Filters 13 Frame type identification block 14 Received Frames 15 filters 16 Chain selection section 17 Chain Identifier 18 DMAC 21 Filters 22 frames 23 Classification Department 24 Classification number 25 Operating unit 26 memory 31 Comparator Pool 32, 33, 34 Comparison section 35, 39, 40, 53, 54, 66, 67 (Result) Output 36 Matching Section 37 Crossbar section 38 Cascade section 41 Priority selection section 42 Interface 43 Host 44 Value Comparator 45 Data Bus 46 Storage area 47 Byte Selector 48, 88 offset 49, 87 data 50, 51 values 52 Mode 57 Offset / position control section 58, 141 Offset counter 59 Mode control section 60 Position control section 61 Components 62, 125, 132 registers 63, 131 Logic 64, 65 FSM 70 circuits 71~74, 76, 78, 80, 82, 84, 86 line 75 OR gate 77 AND Gate 81, 85 n-input AND gate 79, 83 XOR gate 89 Start 90 IPv4 Header 91 IPv6 Header 111 Multiplexer 123 Result combination logic part, AND gate 124 Junction 126 Crossbar Output 160~167 8-bit data 168, 169 32-bit blocks 171~173, 181, 182 Status Checkpoints 174 and 183 200 MCU 211 CPU Subsystem 212 Switch 213 System Memory 215 System Bus 216 CPU 217 memory 218 Application Software 219 Send Queue 220 receive queue 231 Layer Control Unit 232 Temporary storage 243 Transfer control section 244 Message Handler 246 SFR 247 Peripheral Bus Interface 255 Bus Master Interface 92, 97 table 1000 Communication Systems 1001 vehicles 1010 ECU 1011 Cloud Services 1021~1024 Various modules (nodes) 1031 Communication Gateway 1032, 1033 Ethernet Switch 1041~1043 Ethernet ports 1051~1053 VLAN 1060 CAN-FD Network

Claims

1. It has a plurality of comparison units and matching units, each of the plurality of comparators, in response to receiving at least a portion of the frame data, determines whether the portion of the frame data matches a reference value, and outputs a result based on the determination; the matching unit includes a crossbar unit configured to receive the results output from the plurality of comparison units as input and provide a plurality of first output sets via a configurable interconnection; and a cascade unit configured to connect to each of the plurality of first output sets and provide a plurality of second output sets; A frame data processing circuit, wherein the plurality of comparators comprises a plurality of configurable comparators operable in at least a first mode and a second mode that are selectable, and in the first mode, a portion of the frame data can be masked.

2. 2. The frame data processing circuit of claim 1, wherein at least one of said plurality of first sets of outputs is configurably provided to at least two of said plurality of second sets of outputs.

3. 2. The frame data processing circuit of claim 1, wherein at least one of said second set of outputs is configurably provided as an input to said crossbar section.

4. 2. The frame data processing circuit of claim 1, wherein the plurality of configurable comparators are operable to receive two sets of reference values ​​and to perform the determination using the two sets of reference values.

5. 5. The frame data processing circuit according to claim 4, wherein the two sets of reference values ​​are used in conjunction with each other.

6. 2. The frame data processing circuit according to claim 1, wherein at least some of said plurality of comparison sections are arranged with an offset applied thereto so as to select a portion of said frame data to be used in said determination.

7. 2. The frame data processing circuit according to claim 1, wherein at least some of the plurality of comparison sections have one or more FSMs for comparing a portion of the frame data with the reference value and outputting the result.

8. 2. The frame data processing circuit of claim 1, wherein the plurality of comparators comprises at least one block comparator configured to compare a portion of the frame data with a predetermined number of sets of the reference values, the predetermined number being a positive non-zero integer.

9. A device having a plurality of comparison units and matching units, each of the plurality of comparators, in response to receiving at least a portion of the frame data, determines whether the portion of the frame data matches a reference value, and outputs a result based on the determination; the matching unit includes a crossbar unit configured to receive the results output from the plurality of comparison units as input and provide a plurality of first output sets via a configurable interconnection; and a cascade unit configured to connect to each of the plurality of first output sets and provide a plurality of second output sets; A frame data processing circuit, wherein the cascade unit has a plurality of result combination logic units, each of which is an AND gate, an OR gate, or a combination of an AND gate and an OR gate.

10. A device having a plurality of comparison units and matching units, each of the plurality of comparators, in response to receiving at least a portion of the frame data, determines whether the portion of the frame data matches a reference value, and outputs a result based on the determination; The matching unit includes a crossbar unit configured to receive the results output from the plurality of comparison units and provide a plurality of first output sets via configurable interconnections; and a cascade unit configured to connect to each of the plurality of first output sets and provide a plurality of second output sets. a priority selection unit that receives the plurality of second output sets and generates a classification number based on the plurality of second output sets.

11. a frame data processing circuit according to claim 10; an operating unit configured to process the frame data based on the classification number output from the frame data processing circuit.

12. A semiconductor device comprising the filter according to claim 11.

13. a communication gateway including the semiconductor device according to claim 12; at least one module in communication with the semiconductor device, The system wherein the filter is configured to receive the frame data from the at least one module and process the frame data according to the classification number.

14. A vehicle including the system of claim 13.

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