Processing device and electronic system including same

Abstract

To provide a processing apparatus and an electronic system including it.SOLUTION: There is provided an in-memory processing device with improved calculation reliability. The processing device has a bit cell line including a plurality of bit cells serially connected, a mirror circuit unit for duplicating a current flowing to the bit cell line at a predetermined ratio, a charging unit for charging electric charge by using a mirror current duplicated by the mirror circuit unit, and a voltage measuring unit for outputting a value corresponding to a MAC (multiply accumulate) calculation result of an input applied to the bit cell line and a weight based on the electric charge charged by the charging unit.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an apparatus for performing processing and an electronic system including the same. [Background technology]

[0002] A neural network device can perform a multiply-accumulate (MAC) operation, which involves repeated multiplication and addition. A neural network repeatedly performs a MAC operation at a specific node, which involves multiplying the output of a node in a previous layer by the weight mapped to that node, and adding the resulting value. The neural network then applies an activation function to the resulting value of the MAC operation. To achieve this, a memory access operation may be performed to load appropriate inputs and weights at a desired time. Instead of using a commonly known digital computer to process a neural network, various approaches have been attempted to perform neural network operations, such as a MAC operation, using other hardware architectures. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,243,574 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a processing device and an electronic system including the same that improve the reliability and power efficiency of analog operations, and other technical problems can be inferred from the embodiments described below. [Means for solving the problem]

[0005] In one embodiment, the processing device may include a bit cell line including a plurality of bit cells connected in series, a mirror circuit unit capable of replicating the current flowing through the bit cell line at a predetermined ratio, a charge charging unit that charges with the mirror current replicated by the mirror circuit unit, and a voltage measuring unit that outputs a result corresponding to a MAC (multiply accumulate) operation value of the input and weight applied to the bit cell line from the charge stored in the charge charging unit.

[0006] In one embodiment, a processing method may include applying a first input and a first weight to a bit cell line including a plurality of bit cells connected in series; applying a voltage to the bit cell line and transmitting a first mirror current, which is a copy of a current flowing through the bit cell line due to the voltage, to a charge charging unit; charging a capacitor with the first mirror current for a predetermined time; applying a second input and a second weight to the bit cell line; applying a voltage to the bit cell line and transmitting a second mirror current, which is a copy of a current flowing through the bit cell line due to the voltage, to a charge charging unit; charging the capacitor with the second mirror current for a predetermined time; and outputting a result corresponding to a MAC operation value of the input and weight applied to the bit cell line using the charge stored in the capacitor.

[0007] An electronic system according to one embodiment includes a neural network device and a processing unit that controls the functions of the neural network device. The neural network device may include a bit cell line including a plurality of bit cells connected in series, a mirror circuit that can replicate the current flowing through the bit cell line at a predetermined ratio, a charge charging unit that charges the bit cell line with the mirror current replicated by the mirror circuit, and a voltage measuring unit that outputs a result corresponding to a MAC operation value of the input and weight applied to the bit cell line from the charge stored in the charge charging unit. [Brief explanation of the drawings]

[0008] [Figure 1]1 is a diagram for explaining a biological neuron and its operation. [Figure 2] 1 is a diagram for explaining an example of a neural network. [Figure 3] 1 is a diagram illustrating a circuit diagram of a bit cell used in a processing device. [Figure 4A] 4 is a diagram illustrating the structure and operation of a variable resistor applied to the bit cell of FIG. 3; [Figure 4B] 4 is a diagram illustrating the structure and operation of a variable resistor applied to the bit cell of FIG. 3; [Figure 5] 1 is a diagram illustrating an embodiment of a processing device. [Figure 6] FIG. 6 is a perspective view of a transistor in the mirror circuit section of FIG. 5. [Figure 7] 1 is a diagram showing an example of a neural network. [Figure 8] 1 is a flowchart illustrating an embodiment of a processing method. [Figure 9] 9 is a diagram for explaining outputting partial sums by the processing method of FIG. 8. [Figure 10] 10 is a flowchart illustrating another embodiment of a processing method. [Figure 11] 11 is a diagram for explaining a voltage change of the capacitor in FIG. 10. [Figure 12] 11 is a diagram for explaining a step of outputting the total sum according to the processing method of FIG. 10; [Figure 13] 10 is a flowchart illustrating yet another embodiment of a processing method. [Figure 14] 14 is a diagram for explaining a step of outputting an activation function value according to the processing method of FIG. 13; [Figure 15] FIG. 2 is a chip block diagram of a processing device according to an embodiment. [Figure 16]FIG. 1 is a block diagram illustrating an electronic system according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Various embodiments will now be described with reference to the accompanying drawings. The terms used to describe the present embodiments are not intended to limit the scope of the present invention to a particular embodiment, and various modifications, equivalents, and / or alternatives to the particular embodiment are also encompassed within the scope of the present invention. In describing the drawings, like reference numerals may be used for like elements. A singular expression may include a plural expression unless the context clearly dictates otherwise. Expressions such as "A or B" or "A and / or B" may include all possible combinations of the listed items. Terms such as "first" and "second" may modify the elements, regardless of order or importance, and are used only to distinguish one element from other elements, not to limit the elements.

[0010] In the description of the present embodiment, when a part is said to be connected to another part, this does not only mean that they are directly connected to each other, but also that they are connected via other components in between. Furthermore, when a part is said to "comprise" a component, this does not mean that it excludes other components, but that it may further include other components, unless otherwise specified. However, the term "comprise" should not be interpreted as necessarily including all of the components or various steps described in the specification.

[0011] The embodiments described below relate to the technical field of processing devices (e.g., neuromorphic processors, neural processors, etc.), and detailed descriptions of matters that are well known to those skilled in the art will be omitted.

[0012] Unlike typical digital computers, which communicate using a common data bus, a processing device may include analog circuits for performing multiplication and addition operations. In other words, the processing device may perform in-memory processing or internal processing. Therefore, the processing device may be referred to by various terms, such as an in-memory processing device, PIM (processor in memory), or FIM (function in memory).

[0013] FIG. 1 is a diagram for explaining a biological neuron and its operation.

[0014] Referring to Figure 1, a biological neuron 10 represents a cell present in the human nervous system and is one of the fundamental biological computational entities. The human brain contains approximately 100 billion biological neurons and approximately 100 trillion interconnections between them.

[0015] A biological neuron 10 is a single cell that includes a nucleus and a neuron cell body that contains various organelles, including mitochondria, numerous dendrites that emanate from the cell body, and an axon that terminates in many branching extensions.

[0016] Generally, the axon functions to transmit signals from one neuron to another, and the dendrites function to receive signals from other neurons. For example, when different neurons are connected to each other, signals transmitted through the axon of one neuron are also received by the dendrites of the other neurons. Signals between neurons are transmitted through specialized connections called synapses, and various neurons are connected to each other to form a neural network. Based on the synapse, the neuron that secretes neurotransmitters is called a presynaptic neuron, and the neuron that receives information transmitted through neurotransmitters is also called a post-synaptic neuron.

[0017] The human brain can learn and memorize vast amounts of information by transmitting and processing various signals through a neural network formed by interconnecting such a large number of neurons. Various attempts have been made to develop processing or computer devices that can efficiently process vast amounts of information by replicating such biological neural networks.

[0018] FIG. 2 is a diagram for explaining an example of a neural network.

[0019] Referring to Figure 2, neural network 20 is an example of an artificial neural network that replicates the aforementioned biological neural network and also corresponds to a deep neural network (DNN). For ease of explanation, neural network 20 is illustrated as including two hidden layers, but may include any number of hidden layers. Also, in Figure 2, neural network 20 is illustrated as including a separate input layer 21 for receiving input data, but input data may also be input directly to the hidden layer.

[0020] In the neural network 20, artificial nodes in layers other than the output layer are connected to artificial nodes in the next layer via links for transmitting output signals. A value obtained by multiplying the node value of an artificial node included in a previous layer by a weight assigned to each link can be input to one artificial node via these links. The node values ​​of the previous layer correspond to axon values, and the weights correspond to synaptic weights. The weights are also referred to as parameters of the neural network 20. Activation functions may include sigmoid, hyperbolic tangent (Tanh), and ramp functions (ReLU: rectified linear unit), and nonlinearity can be formed in the neural network 20 by the activation functions.

[0021] The output of any one node 22 included in such a neural network 20 can be expressed as in Equation 1 below.

[0022]

number

[0023] FIG. 3 is a circuit diagram illustrating one embodiment of a bit cell for use in a processing device, with reference to which the structure and operation of the bit cell will be described.

[0024] The bit cell BC in Figure 3 may also be a circuit configuration included in a processing device for realizing a neuromorphic processor, a neural processor, etc. The processing device may also be, for example, an in-memory processing unit that stores data in a memory (such as a resistive memory element) and uses the stored data when an operation is required.

[0025] The bit cell BC consists of a pair of variable resistors R a ,R b , variable resistor R a ,R b A pair of switches S connected in series to a ,S b , and the first bit data line BLD a and the second bit data line BLD b The switches SBDL are connected to a ,SBDL b However, the circuit configuration of the bit cell BC shown in FIG. 3 is merely exemplary, and the bit cell BC may also be embodied as an equivalent circuit using other circuit elements.

[0026] A pair of variable resistors R a ,R b is a resistance element that can be set to different resistance values, and the variable resistor R a ,R bThe resistance value of each variable resistor R is also determined by the weight applied to the bit cell BC. a ,R b can have one of two resistance values, for example, 15 MΩ or 10 MΩ. Assuming that the weight that can be applied to the bit cell BC is −1 or 1, when a weight of 1 is applied, the first variable resistor R a becomes 15MΩ, and the second variable resistor R b can be as much as 10 MΩ, and when a weight of -1 is applied, the first variable resistor R a becomes 10MΩ, and the second variable resistor R b As shown in the example, a pair of variable resistors R a ,R b are also set to be complementary to each other so as to have different resistance values.

[0027] Specifically, the variable resistor R a ,R b The resistive memory element is also a resistive memory element. The resistive memory element can have multiple resistance states and can be switched between different resistance states depending on a voltage or current applied across the resistive memory element. The resistive memory element can have a single-layer structure or a multi-layer structure including, for example, a transition metal oxide, a metal oxide such as a perovskite-based material, a phase-change material such as a chalcogenide-based material, a ferroelectric material, or a ferromagnetic material. Meanwhile, the operation of the resistive memory element to change from a high resistance state to a low resistance state can be referred to as a set operation, and the operation of changing from a low resistance state to a high resistance state can be referred to as a reset operation.

[0028] Variable resistor R a ,R b First, connect both ends of the variable resistor to be changed to the first bit data line BDL a and the second bit data line BDL b Connect to the first variable resistor R a For example, the first variable resistor Ra One end of the variable resistor R a The upper end of the upper bit data line switch S BDLb via the second bit data line BDL b is also connected to the first variable resistor R a The other end (the lower end of the variable resistor Ra in FIG. 3) is connected to the first switch S a and the lower bit data line switch SBDLa, and the first bit data line BDL a It is also connected to

[0029] Upper bit data line switch S BDLb is also a switch that is not included in the bit cell BC in FIG. 3. For example, the upper bit data line switch S BDLb is a switch included in a bit cell (not shown) adjacent to bit cell BC in FIG. 3, or is an independent switch not included in any other bit cell.

[0030] First variable resistor R a Gabeat Data Line BDL a ,BDL b , the first variable resistor R a The voltage across the first variable resistor R a By controlling the current flowing through the first variable resistor R a In contrast, a set or reset operation can be performed on the second switch S b and the bit data line switches SBDL at both ends of the bit cell BC. a ,SBDL b When this is closed, the second variable resistor R b Gabeat Data Line BDL a ,BDL b and the second variable resistor R b A set or reset operation can be performed on the .

[0031] Variable resistor R a ,R bThe voltage and / or current applied to change the resistance of the variable resistor R a ,R b It is also a value that is relatively much larger than the voltage and / or current that is applied to read the resistance value of the variable resistor R. a ,R b Depending on the voltage and / or current applied to read the resistance of the variable resistor R a ,R b The resistance value of does not change.

[0032] Variable resistor R a ,R b An example of this being implemented by a magnetic tunnel junction (MTJ) element will be described below with reference to FIGS. 4A and 4B.

[0033] Variable resistor R a ,R b A pair of switches S connected in series with a ,S b The switch S can perform an ON / OFF operation depending on the input applied to the bit cell BC. a ,S b can operate in a complementary manner so that when one is closed, the other is opened. For example, assuming that the inputs that can be applied to the bit cell BC are "-1 or 1", when an input "1" is applied, the first switch S a is closed, and the second switch S b is open, and when input "-1" is applied, the first switch S a is opened, and the second switch S b is also designed to be closed.

[0034] According to the operation method of the variable resistor and the switch described above, the resistance measured across the bit cell BC may vary depending on the weight and input applied to the bit cell BC in Figure 3. The relationship between the weight, the input, and the resistance across the bit cell BC is summarized in Table 1 below.

[0035] [Table 1] Referring to Table 1, when the product of the input and the weight is 1, the resistance of the bit cell BC is 15 MΩ, and when the product of the input and the weight is -1, the resistance of the bit cell BC is 10 MΩ. In other words, the product of the input and the weight applied to the bit cell BC can be determined by measuring the resistance of the bit cell BC or by measuring the voltage drop of the bit cell BC due to a constant current. By utilizing such characteristics of the bit cell BC, a processing device (e.g., a neuromorphic processor) that calculates the sum of the products of the input and the weight can be realized.

[0036] 4A and 4B are diagrams illustrating the structure and operation of a variable resistor applicable to the bit cell BC of FIG. a ,R b This can also be realized by a magnetic tunnel junction (MTJ) element, and the resistance value changes depending on the magnitude and direction of the current (or voltage), and even if the input current (or voltage) is cut off, the resistance value can be maintained as it is, which is a non-volatile characteristic.

[0037] 4A and 4B, a magnetic tunnel junction (MTJ) element may include a pinned layer L3, a free layer L1, and a tunnel layer L2 therebetween. The magnetization direction of the pinned layer L3 is fixed, and the magnetization direction of the free layer L1 may be the same as or different from the magnetization direction of the pinned layer L3, depending on the conditions.

[0038] FIG. 4A shows a state in which the magnetization directions of the free layer L1 and the pinned layer L3 of a magnetic tunnel junction (MTJ) element are parallel. When the magnetization directions are parallel, the magnetic tunnel junction (MTJ) element can have a low resistance value, for example, 10 MΩ. FIG. 4B shows a state in which the magnetization directions of the free layer L1 and the pinned layer L3 of the magnetic tunnel junction (MTJ) element are anti-parallel. When the magnetization directions are opposite, the magnetic tunnel junction (MTJ) element can have a high resistance value, for example, 15 MΩ. Therefore, the resistance value of the variable resistor can be changed by changing the magnetization direction of the free layer L1.

[0039] The magnetization direction of the free layer L1 can also be changed by electrical / magnetic factors provided externally and / or internally to the resistive memory cell. The free layer L1 may include a material having a changeable magnetization direction, such as a ferromagnetic material. Examples of the free layer L1 include CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O. 12 , and / or combinations thereof.

[0040] The tunnel layer L2 may have a thickness less than the spin diffusion distance and may include a non-magnetic material, such as oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn), and magnesium boron (MgB), titanium (Ti), vanadium (V), and / or combinations thereof.

[0041] The pinned layer L3 can have its magnetization direction fixed by an antiferromagnetic layer. The pinned layer L3 can be made of a ferromagnetic material, such as CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, or Y3Fe5O 12 , and / or combinations thereof, and may further include an antiferromagnetic layer and / or a synthetic antiferromagnetic layer to fix the magnetization direction. The antiferromagnetic layer may include an anti-ferromagnetic material such as PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, Cr, and / or combinations thereof. The synthetic antiferromagnetic layer may include Cu, Ru, Ir, and / or combinations thereof.

[0042] FIG. 5 is a diagram illustrating one embodiment of a processing device.

[0043] Referring to FIG. 5, the processing device 100 includes three serially connected bit cells BC 11 ,BC 12 ,BC 13 5, the bit cell line 110 may include a mirror circuit 130 that replicates the current flowing through the bit cell line 110, a charge charging unit 150 that includes a capacitor C1 that charges with the mirror current to be transmitted to the mirror circuit 130, and a voltage measuring unit 170 that can measure the potential difference across the capacitor C1. In FIG. 5, x and w may represent an input and a weight, respectively.

[0044] The bit cell line 110 includes a plurality of serially connected bit cells BC 11 ,BC 12 ,BC 13 , each bit cell also having a structure similar to bit cell BC in FIG. 3. Bit cell line 110 in FIG. 5 may include bit cell BC 11 ,BC 12 ,BC13 Although an example including three bit cells is shown, the number of bit cells included in one column of the bit cell line 110 may be three or more, for example, 64 to 256. 11 ,BC 12 ,BC 13 Since the bit cells are connected in series, the amount of current flowing through each bit cell is the same. For example, the first bit cell BC 11 When a current of 1 A flows through the second bit cell BC 12 and the third bit cell BC 13 The magnitude of the current flowing through the bit cell line 110 is determined by the bit cell line voltage V applied to the upper end of the bit cell line 110. BC and Bitcell BC 11 ,BC 12 ,BC 13 The combined resistance of the bit cell line 110 can also be determined by Ohm's law from the combined resistance of the first bit cell BC and the weights applied to the bit cells, as previously described for the bit cell BC in FIG. 3, and the combined resistance of the first bit cell BC and the weights applied to the bit cells. 11 and the second bit cell BC 12 is 15MΩ, and the third bit cell BC 13 For example, if the bit cell line voltage V is 10 MΩ, the combined resistance of the bit cell line 110 is 40(15+15+10) MΩ. BC is 80V, a current of 2 μA can flow through the bit cell line 110.

[0045] The mirror circuit section 130 includes a first transistor TR M1 and the second transistor TR M2 and an amplifier 131, which can replicate the current flowing through the bit cell line 110 and transfer it to the charge storage unit 150. The current replicated by the mirror circuit unit 130 is transferred to the first transistor TR M1 The bit cell line current I flows through the bit cell line 110 via the second transistor TR M2It is also a mirror current I' that flows to the charge storage unit 150 via

[0046] That is, the mirror circuit unit 130 generates a mirror current by duplicating the current flowing through the bit cell line at a constant ratio (predetermined ratio). The operation of the mirror circuit unit 130 for duplicating the current will be described below.

[0047] The first transistor TR of the mirror circuit unit 130 M1 is also a p-type MOSFET (metal oxide semiconductor field effect transistor), and the first transistor TR M1 The bit cell line current I flowing through the bit cell line 1 can satisfy the following equation 2:

[0048]

number

[0049] Second transistor TR M2The second transistor TR is also a p-type MOSFET. M2 The mirror current I' flowing through the inverter 1 can satisfy the following equation 3:

[0050]

number

[0051] Referring to Equation 2 and Equation 3, the first transistor TR M1 and the second transistor TR M2 If we compare the magnitudes of the currents I and I' flowing through the first transistor TR M1 and the second transistor TR M2 are generally manufactured using the same materials and processes, so k p1 and V th1 is k p2 and V th2 Also, referring to FIG. 5, the first transistor TR M1 and the second transistor TR M2 The source voltage V S and gate voltage V G Therefore, the factor that determines the magnitude of the bit cell line current I and the mirror current I′ is also the channel aspect ratio (W / L) of each transistor. For example, the first transistor TR M1 The channel aspect ratio W1 / L1 of the second transistor TR M2 If the channel aspect ratio W2 / L2 is larger than the bit cell line current I', the first transistor TR M1 The channel aspect ratio W1 / L1 of the second transistor TR M2If the channel aspect ratios W2 / L2 of the second transistor and W1 / L1 of the first transistor are the same, the bit cell line current I will also be the same as the mirror current I'. In other words, by adjusting the ratio between the channel aspect ratio W2 / L2 of the second transistor and the channel aspect ratio W1 / L1 of the first transistor, a desired ratio of the mirror current I' can be obtained. For example, by setting the channel aspect ratio W2 / L2 of the second transistor to 1 / 2 of the channel aspect ratio W1 / L1 of the first transistor, the magnitude of the mirror current I' can be reduced to 1 / 2 of the bit cell line current I. In other words, the channel aspect ratios W1 / L1 of the first transistor and W2 / L2 of the second transistor can be 1 or less, or 1 / 2 or less. In the following, unless otherwise specified, the first transistor TR M1 and the second transistor TR M2 The following description will be given on the assumption that the channel aspect ratios W1 / L1 and W2 / L2 are the same.

[0052] The amplifier 131 has two input terminals 131 i+ ,131 i- and one output terminal 131 o and a bit cell line voltage V BC The amplifier 131 can maintain a constant value at the positive (+) input terminal 131. i+ Voltage V in+ and negative (-) input terminal 131 i- Voltage V in- The difference between these is amplified by the gain G and output terminal 131 o Voltage V out The amplifier 131 is also an operational amplifier that outputs a i+ ,131 i- Voltage V in+ ,V in- and output terminal 131 o Voltage V out can satisfy the following equation 4.

[0053]

number

[0054] On the other hand, since the operational amplifier has a characteristic that there is no current outlet to the input terminal, the first transistor TR M1 The current flowing through the negative (-) input terminal 131 of the amplifier 131 i- Instead, the current flows through the bit cell line 110. Therefore, the first transistor TR M1 The current flowing through the bit cell line I is maintained the same as the bit cell line current I.

[0055] To explain the operation of the bit cell line 110 and the mirror circuit unit 130, the current flowing through the bit cell line 110 is calculated by the combined resistance of the bit cell line 110 and the bit cell line voltage V BCand the first transistor TR M1 The current flowing through the first transistor TR M1 and the second transistor TR M2 Since the channel aspect ratio (W / L) of the first transistor TR M1 The current flowing through the second transistor TR M2 Therefore, a mirror current I′ having the same magnitude as the current I flowing through the bit cell line 110 is also transferred to the charge storage unit 150.

[0056] The charge charging unit 150 includes a capacitor C1 and a charging transistor TR C and reset transistor TR R The charge unit 150 may include a transistor TR , which can charge the mirror current I' transferred from the mirror circuit unit 130 for a desired time. That is, the charge unit 150 can charge a voltage corresponding to the mirror current I' by applying the mirror current I' replicated by the mirror circuit unit 130. C ,TR R can be turned on / off by a control signal from a controller (not shown).

[0057] Charge transistor TR C The time for the mirror current I' to charge the capacitor C1 can be controlled by the on / off operation of the charging transistor TR. For example, when the mirror current I' is 5 μA, the charging transistor TR C If the charge transistor TR is kept on for 2 ns, a charge of 10 fC can be charged to the capacitor C1. C When the switch is turned off, the charge stored in the capacitor C1 does not flow out, so the potential difference across the capacitor C1, that is, the capacitor voltage, is maintained constant.

[0058] Reset transistor TR R The charge stored in the capacitor C1 can be removed by the on / off operation of the reset transistor TR. RWhen turned on, the voltage across the capacitor C1 becomes the ground voltage (0V), and the charge stored in the capacitor C1 can be removed.

[0059] The voltage measuring unit 170 outputs a value corresponding to the MAC operation result of the input applied to the bit cell line 110 and the weight based on the voltage charged in the charge charging unit 150 (ie, the capacitor voltage of the capacitor C1).

[0060] Specifically, the voltage measurement unit 170 measures the voltage of the capacitor C1 of the charge charging unit 150 and the reference voltage V Ref The reference voltage V Ref is a predetermined voltage provided to relatively measure the voltage magnitude of the capacitor C1, and one or more voltages may be provided. The voltage measuring unit 170 has a reference voltage V Ref Alternatively, a reference voltage V Ref The voltage measuring unit 170 may include a receiving unit (not shown) for receiving and using the voltage of the capacitor C1 and the reference voltage V Ref The voltage measuring unit 170 may include an ADC (analog-to-digital converter) 171 that outputs the comparison result as a digital value. The output of the voltage measuring unit 170 is also a value that indicates the sum of the products of the inputs and weights applied to the bit cell lines 110, and the specific operation of the voltage measuring unit 170 will be described below with reference to FIG. 8.

[0061] FIG. 7 is a diagram showing an example of a neural network.

[0062] FIG. 7 exemplarily illustrates a neural network having six nodes in a first layer 701 and two nodes in a second layer 702.

[0063] Referring to FIG. 7, in the first node a1 of the second layer 702, as shown in the following Equation 5, inputs x1, x2, x3, x4, x5, and x6 coming from the nodes of the first layer 701 and their respective weights w 11 ,w21 ,w 31 ,w 41 ,w 51 ,w 61 and a MAC operation to add up the multiplication results, and in the second node a2, as shown in the following Equation 6, the inputs x1, x2, x3, x4, x5, x6 coming in from the nodes in the first layer 701 and their respective weights w 12 ,w 22 ,w 32 ,w 42 ,w 52 ,w 62 Six multiplication operations are performed to multiply the arithmetic unit 1 by 1 and a MAC operation is performed to add up the multiplication results.

[0064]

number

[0065]

number

[0066] FIG. 8 is a flowchart illustrating one embodiment of a method for operating the processing device of FIG. 5. Hereinafter, a method for performing a MAC operation as shown in Equation 5 using the processing device 100 of FIG. 5 will be described with reference to FIG. 8. Note that the operations described in FIG. 8 may be performed in the order shown, but the order of some operations may be changed or some operations may be omitted without departing from the scope of the embodiment described in FIG. 8. Furthermore, the operations described in FIG. 8 may be performed in parallel or simultaneously. Furthermore, the descriptions regarding FIGS. 1 to 6 may also be applied to FIG. 7.

[0067] The inputs and weights of Equation 5 will be explained using the case shown in Table 2 below as an example.

[0068] [Table 2] Referring to Table 2, the number of inputs and weights is six, so the bit cell BC 11 ,BC 12 ,BC 13 The processing device 100 of FIG. 5, which has only three inputs x1, x2, x3 and a weight w, cannot complete the calculation of Equation 5 in one go. In other words, the number of multiplications that can be performed in one go using the processing device 100 of FIG. 5 is three, but Equation 5 includes six multiplications, so it cannot be completed in one go. Therefore, the calculation of Equation 5 is divided into two parts, and three inputs x1, x2, x3 and a weight w are used. 11 ,w 21 ,w 31 First, calculate the first partial sum for the remaining three inputs x4, x5, x6 and the weight w 41 ,w 51 ,w 61 After calculating the second partial sum for , the first partial sum and the second partial sum are finally added together to derive the total sum.

[0069] Referring to FIG. 8, the processing method may include a step of applying weights and inputs to a bit cell (S801), a step of applying a voltage to a bit cell line and charging a capacitor with a current replicated by a mirror circuit (S802), a step of comparing the capacitor voltage with a reference voltage, outputting a partial sum, and storing it in memory (S803), a step of resetting the capacitor (S804), a step of determining whether operations for all inputs and weights have been completed (S805), and, if operations for all partial sums have been completed, a step of adding up the partial sums and outputting a total sum (S806).

[0070] First, in the S801 stage, each bit cell BC 11 ,BC 12 ,BC 13 The inputs x1, x2, x3 and weights w required for the first partial sum calculation are 11 ,w 21 ,w 31The method of applying the weights and inputs for each bit cell is the same as that described for bit cell BC in Figure 3. The inputs x1, x2, x3 and the weights w 11 ,w 21 ,w 31 and the bit cell BC 11 ,BC 12 ,BC 13 The situation is summarized in Table 3 below.

[0071] [Table 3] Bitcell BC 11 ,BC 12 ,BC 13 When the input and weight are applied, in step S802, the positive (+) input terminal 131 of the amplifier 131 is connected to the positive (+) input terminal 131 of the amplifier 131. i+ A voltage of 1.008 V is applied to the first transistor TR M1 and the second transistor TR M2 At the source terminal of S The voltage application is also performed by a controller (not shown). As mentioned above, the bit cell line voltage V BC is the positive (+) input terminal 131 of the amplifier 131 i+ Since this is the same as 1.008V applied to the bit cell line 110, according to Ohm's law, a current flows through the bit cell line 110. Referring to Table 3, the combined resistance of the bit cell line 110 is 40MΩ, so a bit cell line current I of 25.2nA flows.

[0072] The bit cell line current I is replicated by the mirror circuit unit 130, and a mirror current I' of the same size is transmitted to the charge charging unit 150. A controller (not shown) controls the charge switch TR of the charge charging unit 150. CBy turning on the mirror current I', the mirror current I' can charge the capacitor C1 for a certain period of time (predetermined time). In the embodiment of FIG. 8, the capacitor C1 is charged for 1 ns as an example. Since Q=I*t, the charge is 25.2 aC. If the capacitance of the capacitor C1 is 20 fF, for example, the capacitor C1 can be charged to a voltage of 1.26 mV. The charge state of the capacitor C1 for calculating the first partial sum can be summarized as shown in Table 4 below. In the embodiment of FIG. 8, the capacitance is 20 fF, but the capacitance of the capacitor C1 can also be 10 to 100 fF or 20 to 80 fF.

[0073] [Table 4] In step S803, the capacitor voltage is compared with a reference voltage to output a partial sum, which may be stored in memory. The voltage charged to capacitor C1 corresponds to the combined resistance of the bit cell lines 110, and the combined resistance of the bit cell lines 110 corresponds to the first partial sum, so the partial sum can be determined from the voltage charged to capacitor C1. The relationship between the voltage of capacitor C1, the combined resistance of the bit cell lines 110, and the partial sum is summarized in Table 5 below.

[0074] [Table 5] FIG. 9 is a diagram for explaining output of partial sums by the processing method of FIG.

[0075] Referring to FIG. 9, the process in which the voltage measurement unit 170 outputs the partial sum from the voltage of the capacitor C1 is illustrated.

[0076] To determine the voltage of capacitor C1, the voltage measurement unit 170 may compare the voltage of capacitor C1 with a reference voltage using an internal comparator. The reference voltage may be a value that can distinguish between voltages that can be measured by capacitor C1 and may be an intermediate value between the voltages that capacitor C1 can exhibit. Referring to Table 5 above, for example, the reference voltage for determining whether the voltage that capacitor C1 can exhibit is 1.12 mV may be 1.19 mV, which is the intermediate value between 1.12 mV and the adjacent value 1.26 mV. If the voltage of capacitor C1 is less than the reference voltage of 1.19 mV, the voltage measurement unit 170 may determine that the voltage of capacitor C1 is 1.12 mV and output the corresponding partial sum 3. The reference voltages, intervals between the reference voltages, and partial sums corresponding to each interval in the embodiment of FIG. 8 are summarized in Table 6 below.

[0077] [Table 6] Referring to Table 4, the voltage of capacitor C1 for the first partial sum in the embodiment of FIG. 8 is 1.26 mV. Referring to FIG. 9 and Table 6, this voltage value is greater than the reference voltage of 1.19 mV and less than 1.35 mV. Therefore, the voltage measurement unit 170 outputs a first partial sum of "1" as a result, which may be stored in a storage device such as a memory. While the embodiment of FIG. 8 illustrates an example in which the voltage measurement unit 170 outputs the first partial sum, the voltage measurement unit 170 may output a result in other forms corresponding to the first partial sum. For example, the voltage measurement unit 170 may output a digital value corresponding to the first partial sum, e.g., a 2-bit number such as 00, 01, 10, or 11, which may also be derived from Table 7 below.

[0078] [Table 7] When the calculation of the first partial sum is completed, the capacitor C1 is reset in step S804. At this time, a controller (not shown) resets the reset transistor TR R can be turned on to make the potential difference across the capacitor C1 the same and reset the capacitor C1.

[0079] In step S805, it is determined whether the calculation is complete for all inputs and weights. Since the calculation of the second partial sum is not yet complete, steps S801 through S804 are repeated to calculate the second partial sum.

[0080] First, each bit cell BC 11 ,BC 12 ,BC 13 Then, inputs x4, x5, x6 and weights w 41 ,w 51 ,w 61 Inputs x4, x5, x6 and weights w 41 ,w 51 ,w 61 Bit cell BC with 11 ,BC 12 ,BC 13 The situation is summarized in Table 8 below.

[0081] [Table 8] Bitcell BC 11 ,BC 12 ,BC 13 Then, when the input and weight are applied, the positive (+) input terminal 131 of the amplifier 131 i+ A voltage of 1.008 V is applied to the first transistor TR M1 and the second transistor TR M2 If the source of the S Referring to Table 8, the combined resistance of the bit cell line 110 is 35 MΩ, so that according to Ohm's law, a bit cell line current I of 28.8 nA can flow.

[0082] The bit cell line current I is replicated by the mirror circuit unit 130, and a mirror current I' of the same magnitude is transmitted to the charge storage unit 150. The charge state of the capacitor C1 for calculating the second partial sum can be summarized as shown in Table 9 below.

[0083] [Table 9] Referring to Table 9, the voltage of capacitor C1 is 1.44 mV. Referring again to FIG. 9 and Table 6, 1.44 mV corresponds to the interval between the reference voltage of 1.35 mV and the reference voltage of 1.56 mV, so voltage measurement unit 170 outputs a result value of "-1," which is also stored in a storage device such as a memory as the second partial sum.

[0084] If it is determined that the calculation of the first and second partial sums is complete (S805), a processing unit (not shown) may output a total sum, which is the sum of all the partial sums (first and second partial sums). The total sum is also the result of the calculation of Equation 5, and the summing of the partial sums and the output of the total sum may be performed by a processing unit (not shown), such as a central processing unit (CPU) of an electronic system including the processing device 100. Since the first partial sum is "1" and the second partial sum is "-1," the total sum "0" is output and stored in a storage device, such as a memory.

[0085] An activation function value obtained by applying an activation function such as a sigmoid to the total sum, as shown in the above formula 1, is also provided as an input (activation) of the next node. For example, the activation function value of the above formula 5 is also provided as one input to node b1 included in the third layer 703. The calculation of the activation function may also be performed by a processor such as a CPU.

[0086] While the embodiment of Figure 8 has been described using an example of an operating method of processing device 100 including only one bit cell line 110, processing device 100 may include multiple bit cell lines and may process operations required for multiple nodes in parallel. Taking a processing device including two bit cell lines as an example, the first bit cell line may perform the operation of Equation 5 required for first node a1 of second layer 702 of Figure 7, while the second bit cell line may perform the operation of Equation 6 required for second node a2 of second layer 702 of Figure 7. The number of bit cell lines included in processing device 100 may be, for example, 40 to 100, but is not limited thereto.

[0087] FIG. 10 is a flowchart illustrating another embodiment of a method for operating the processing device of FIG. 5. Hereinafter, a method for performing the calculation of Equation 5 using the processing device 100 of FIG. 5 will be described with reference to FIG. 10. The operations illustrated in FIG. 10 may be performed in the order shown, but the order of some operations may be changed or some operations may be omitted without departing from the scope of the embodiment illustrated in FIG. 10. Furthermore, the operations illustrated in FIG. 10 may be performed in parallel or simultaneously. Furthermore, the descriptions regarding FIGS. 1 through 8 also apply to FIG. 10.

[0088] The embodiment of FIG. 10 will also be described by taking as an example the case where the inputs and weights of Equation 5 are as shown in Table 2 above. The embodiment of FIG. 10 differs from the embodiment of FIG. 8 in that the capacitor C1 reset step is not performed between the first and second partial sum operations of Equation 5. In the embodiment of FIG. 10, three inputs x1, x2, x3 and a weight w 11 ,w 21 ,w 31 The voltage related to the remaining three inputs x4, x5, x6 and the weight w 41 ,w 51 ,w 618 in that the voltages related to the voltages are accumulated and charged into the capacitor C1.

[0089] Referring to FIG. 10, the processing method may include a step of applying weights and inputs to a bit cell (S1001), a step of applying a voltage to a bit cell line and charging a capacitor with a current replicated by a mirror circuit (S1002), a step of determining whether operations for all inputs and weights have been completed (S1003), and a step of repeatedly performing steps S1001 and S1002 until operations for all inputs and weights have been completed, and then a step of comparing the capacitor voltage with a reference voltage and outputting a total sum (S1004).

[0090] First, in the S1001 stage, each bit cell BC 11 ,BC 12 ,BC 13 In the first interval t1, the inputs x1, x2, x3 and the weights w 11 ,w 21 ,w 31 The inputs x1, x2, x3 and weights w are calculated in the first interval t1. 11 ,w 21 ,w 31 and the bit cell BC 11 ,BC 12 ,BC 13 The status is as shown in Table 3 above.

[0091] Bitcell BC 11 ,BC 12 ,BC 13 After applying the input and weight to the bit cell line voltage V of 1.008V, the amplifier 131 is used in step S1002. BC Since the combined resistance of the bit cell line 110 is 40 MΩ, the applied voltage allows a bit cell line current I of 25.2 nA to flow.

[0092] The bit cell line current I is mirrored by the mirror circuit unit 130, and the mirror current I' is transferred to the charge charging unit 150, where it is transferred to the charging transistor TR C This operation charges capacitor C1 for 1 ns. In the embodiment of Figure 10, a current of 25.2 nA charges capacitor C1, which is 20 fF, to a voltage of 1.26 mV. The charge state of capacitor C1 during the first section t1 is as shown in Table 4 above.

[0093] Thereafter, steps S1001 and S1002 are repeatedly performed until it is determined that the calculations for all inputs and weights are completed (S1003). 11 ,BC 12 ,BC 13 In the second interval t2, the inputs x4, x5, x6 and the weights w 41 ,w 51 ,w 61 and are applied to the bit cell BC 11 ,BC 12 ,BC 13 Between the application of the input and the weight, the charging transistor TR C Therefore, the charge stored in the capacitor C1 is conserved, and the voltage of the capacitor C1 is maintained at the voltage to which it was charged in the first interval t1. 11 ,BC 12 ,BC 13 When the variable resistor included in is a magnetic tunnel junction (MTJ), the time required to apply the input and weight to one variable resistor is generally about 20 ns to 40 ns, and the amount of charge discharged from the capacitor C1 while applying the input and weight calculated in the second section t2 can be ignored. 41 ,w 51 ,w 61 and the bit cell BC 11 ,BC 12 ,BC 13 The status is as shown in Table 8 above.

[0094] Bitcell BC 11 ,BC 12 ,BC 13 After applying the input and weight to the bit cell line voltage VB of 1.008V, C In the second section t2, the combined resistance of the bit cell line 110 is 35 MΩ, allowing a bit cell line current I of 28.8 nA to flow.

[0095] The bit cell line current I is mirrored by the mirror circuit unit 130, and the mirror current I' is transferred to the charge charging unit 150, where it is transferred to the charging transistor TR C is turned on, and capacitor C1 charges for 1 ns. The charge charged to capacitor C1 by a 28.8 nA current for 1 ns is 28.8 aC. Since capacitor C1 stores 25.2 aC of charge during the first interval t1, the accumulated charge during the second interval t2 can reach 54 aC. Since Q = CV, the voltage of capacitor C1 after the second interval t2 is 2.7 mV. Figure 11 shows the change in voltage of capacitor C1 during the first interval t1 and the second interval t2. The charge and voltage during the first interval t1 and the second interval t2 are summarized in Table 10 below.

[0096] [Table 10] If it is determined that the calculations for all inputs and weights are complete (S1003), the voltage of capacitor C1 is compared with a reference voltage and the total sum is output in step S1004. Since the voltage charged to capacitor C1 corresponds to the sum of the combined resistance of the bit cell lines in the first interval t1 and the combined resistance of the bit cell lines in the second interval t2, the total sum can be determined from the voltage charged to capacitor C1.

[0097] The embodiment of Fig. 10 differs from the embodiment of Fig. 8 in that it does not output a partial sum, which is the sum of the products of the inputs and weights applied in the first interval t1 and the second interval t2, but outputs a total sum from the final voltage of capacitor C1. The relationship between the voltage of capacitor C1, the sum of the combined resistance of the first interval t1 and the combined resistance of the second interval t2, and the total sum is as shown in Table 11 below.

[0098] [Table 11] FIG. 12 is a diagram for explaining a process of outputting the total sum from the capacitor C1 voltage in the voltage measurement unit 170 in the processing method of FIG.

[0099] The voltage measuring unit 170 can compare the voltage of the capacitor C1 with a reference voltage using an internal comparator (not shown) to determine the voltage of the capacitor C1. The ranges that can be divided according to the reference voltage and the total sums corresponding to each range are shown in Table 12 below.

[0100] [Table 12] In the embodiment of Figure 10, the voltage 2.7mV of capacitor C1, which has been charged to the second section t2, belongs to a section greater than the reference voltage 2.61mV and less than the reference voltage 2.79mV. Therefore, referring to Figure 12 and Table 12, the voltage measurement unit 170 can output a result value of "0." The result value "0" derived by the voltage measurement unit 170 is also the calculation result of Equation 5, to which an activation function is applied and provided as an input to node b1 of the third layer 703 of Figure 7. The activation function value is also a binary value of -1 or 1, as provided from the first layer 701 to the second layer 702 of Figure 7.

[0101] In the embodiment of FIG. 10, the capacitor C1 is charged by accumulating charge twice, during the first interval t1 and the second interval t2. However, the capacitor C1 can be charged by accumulating charge three or more times. For example, to calculate an equation including 12 multiplications using the processing device 100 of FIG. 5, which has three bit cells, a value accumulated four times can be used. If the capacitance of the capacitor C1 is not sufficient to accumulate the charge required for the operation, the mirror circuit unit 130 can be designed so that the mirror current I' is smaller than the bit cell current I. For example, if the amount of charge that can be accumulated in the operation is 20 μC but the maximum storage capacity of the capacitor C1 is 10 μC, the mirror circuit unit 130 can be designed so that the mirror current I' is smaller than half the bit cell current I. As described above with reference to FIG. 6, the mirror current I' can be reduced by adjusting the channel aspect ratio (W / L) of the transistor included in the mirror circuit unit 130, and if the mirror current I' is reduced to 1 / 2, the required storage capacity of the capacitor C1 can be doubled.

[0102] 13 and 14 are diagrams for explaining the operation of a processing method in which the voltage measurement unit of FIG. 5 outputs an activation function value.

[0103] As previously described with respect to Equation 1, since a value obtained by applying an activation function such as a sigmoid to the MAC calculation result such as Equation 5 is used in the next node, if the voltage measurement unit 170 of FIG. 5 outputs an activation function value other than the overall sum, calculation efficiency may be improved. In other words, if the voltage measurement unit 170 outputs an activation function value of the overall sum other than the overall sum, the process of outputting the overall sum and storing it in memory and calculating the activation function of the overall sum using a processor such as a CPU may be skipped. In the processing method of FIG. 13, steps S1301 through S1303 may be performed similarly to steps S1001 through S1003 in the processing method of FIG. 10. However, in the processing method of FIG. 10, step S1004 of outputting the overall sum may be changed (or replaced) to a step of outputting an activation function value, as in step S1304 of FIG. 13.

[0104] 10, for example, if the voltage measurement unit 170 does not output the total sum but outputs an activation function value of 1 or -1, when the total sum is 2 or more, an activation function value of "1" is output, and when the total sum is 0 or less, an activation function value of "-1" is output. In this regard, referring to Table 11, the capacitor C1 voltage, total sum, and activation function value are organized as shown in Table 13 below.

[0105] [Table 13] Referring to Table 13, when the total sum is 2 or more, it corresponds to the voltage of capacitor C1 being less than 2.52 mV, and when the total sum is 0 or less, it corresponds to the voltage of capacitor C1 being greater than 2.70 mV. Therefore, by setting 2.61 mV, which is the intermediate value between 2.52 mV and 2.70 mV, as the reference voltage, and outputting -1 when the voltage of capacitor C1 exceeds the reference voltage and 1 when it is less than the reference voltage, the voltage measurement unit 170 can output the activity function value of Table 13. The reference voltages and the outputs of the voltage measurement unit 170 can be summarized as shown in Table 14 below.

[0106] [Table 14] 14 and Table 14, since the capacitor C1, which has been fully charged up to the second section t2 in the embodiment of FIG. 10, is charged with a voltage of 2.70 mV, the voltage measurement unit 170 can output an activation function value of "-1." This activation function value can be stored in memory and then used, or can be immediately provided as an input to the node b1 of the third layer 703 in FIG. 7.

[0107] FIG. 15 is a chip block diagram of a processing device according to an embodiment.

[0108] Referring to FIG. 15, the processing device 700 includes a bit cell array 710, a controller 720, a row decoder 730, a column decoder 740, a weight driver 750, a power supply controller 760, a data buffer 770, and a data output unit 780.

[0109] The controller 720 can decode instructions necessary to drive and operate the processing device 700. For example, the controller 720 decodes instructions such as setting weights, checking weight settings, applying inputs, measuring voltages, outputting partial sums / total sums, and outputting activation function values, and transmits signals to components necessary to execute those instructions.

[0110] The bit cell array 710 is also an array of bit cells configured by the aforementioned variable resistors and switches, where the variable resistors are also magnetic tunnel junction (MTJ) elements having magnetic materials.

[0111] The row decoder 730 receives a row address and an input signal and applies an input value to the bit cell array 710. The row decoder 730 may include a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC), and can apply a driving voltage to a switch connected in series with a variable resistor based on the input value. The row decoder 730 can also change the resistance value of a variable resistor included in a bit cell in the bit cell array 710, and at this time, can apply a driving voltage to an associated switch so that a target variable resistor can be selected.

[0112] The column decoder 740 receives a column address and a weight setting signal and applies a voltage / current to a variable resistor. The column decoder 740 selects a bit cell line for which voltage measurement is required and a weight line connected to a bit cell for which weight setting is required.

[0113] The weight driver 750 can transmit weight data to bit cells selected by the row decoder 730 and the column decoder 740. The weight driver 750 can set weights and check the set weights by driving weight lines connected to the column decoder 740 based on data received from the data buffer 770. The weight driver 750 can include a current source that applies a check current to the weight lines to check whether a desired resistance value is set in the variable resistor.

[0114] The power supply controller 760 receives a signal from the controller 720 to drive the power supply, and can apply a voltage to the positive (+) input terminal of the amplifier and a source voltage to the transistor of the mirror circuit section.

[0115] 5, measures the voltage of the bit cell line or a capacitor connected to one end of the bit cell line, and stores the measured value in an external memory (not shown). The data output unit 780 may include an ADC that outputs the measured value as a digital value.

[0116] FIG. 16 is a block diagram illustrating an electronic system according to an example.

[0117] 16, electronic system 800 can analyze input data and extract useful information based on a neural network device 830 including a processing device, and can make a situational decision based on the extracted information or control the configuration of an electronic device in which electronic system 800 is installed. For example, electronic system 800 can be applied to robotic devices such as drones and advanced driver assistance systems (ADAS), smart televisions, smartphones, medical devices, mobile devices, video display devices, measurement devices, and Internet of Things (IoT) devices, and can also be installed in various other types of electronic devices.

[0118] The electronic system 800 may include a processing unit 810, a RAM (random access memory) 820, a memory 840, a sensor module 850, and a communication module (Tx / Rx module) 860 in addition to the neural network device 830. The electronic system 800 may further include an input / output module, a security module, a power control device, etc. Part of the hardware configuration of the electronic system 800 may also be mounted on a semiconductor chip. The neural network device 830 may be an on-chip implementation of the processing device of the above-described embodiment, or may be a device that includes the processing device of the above-described embodiment as a part thereof.

[0119] The processing unit 810 can control the overall operation of the electronic system 800. The processing unit 810 can also be a CPU and can include one processor core (single core) or multiple processor cores (multi-core). The processing unit 810 can process or execute programs and / or data stored in the memory 840, and can control the functions of the neural network device 830 by executing the programs stored in the memory 840. The processing unit 810 can be embodied as a GPU (graphics processing unit), an AP (application processor), etc., in addition to a CPU.

[0120] The RAM 820 can temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 840 may also be temporarily stored in the RAM 820 by control or boot code of the processing unit 810. The RAM 820 may also be embodied by a memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0121] The neural network device 830 performs neural network operations based on received input data and generates an information signal based on the results of the operations. The neural network device 830 may include the processing device described in the above-described embodiments. The neural network may include, but is not limited to, a convolutional neural network (CNN), a recurrent neural network (RNN), deep belief networks, restricted Boltzmann machines, etc. The neural network device 830 may also be a dedicated hardware accelerator for neural networks.

[0122] The information signal may include various types of recognition signals, such as a voice recognition signal, an object recognition signal, a video recognition signal, and a biometric recognition signal. For example, the neural network device 830 may receive frame data included in a video stream as input data and generate a recognition signal related to an object included in an image represented by the frame data. Depending on the type or function of the electronic device installed in the electronic system 800, the neural network device 830 may receive various types of input data and generate a recognition signal based on the input data.

[0123] The memory 840 is a storage location for storing data and can store an operating system (OS), various programs, and various data. The memory 840 may include volatile memory or nonvolatile memory. The nonvolatile memory includes read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM). The volatile memory includes dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Memory 840 may include, for example, a hard disk drive (HDD), a solid static drive (SSD), a compact flash (CF), a secure digital (SD), a micro-SD (micro secure digital), a mini-SD (mini secure digital), an extreme digital (xD), or a memory stick.

[0124] The sensor module 850 can collect information about the surroundings of an electronic device in which the electronic system 800 is installed. The sensor module 850 can sense or receive signals (e.g., video signals, audio signals, magnetic signals, biosignals, touch signals, etc.) from outside the electronic device and convert the sensed or received signals into data. To this end, the sensor module 850 can be any of various types of sensing devices, such as a microphone, an imaging device, an image sensor, a LIDAR (light detection and ranging) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, or a touch sensor.

[0125] The sensor module 850 can provide the converted data as input data to the neural network device 830. For example, the sensor module 850 can include an image sensor that captures an external environment of the electronic device, generates a video stream, and sequentially provides successive data frames of the video stream as input data to the neural network device 830. However, without being limited thereto, the sensor module 850 can provide various types of data to the neural network device 830.

[0126] The communication module 860 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module 860 may include a communication interface connectable to a wired local area network (LAN), a wireless local area network (WLAN) such as wireless fidelity (Wi-Fi), a wireless personal area network (WPAN) such as Bluetooth, a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), or a mobile cellular network such as 3G (3rd generation), 4G (4th generation), LTE (long term evolution), or 5G (5th generation).

[0127] The electronic system 800 may further include a processor, a memory device for storing and executing program data, permanent storage such as a disk drive, a communication port for communicating with external devices, and user interface devices such as a touch panel, keys, and buttons. Methods embodied by software modules or algorithms may also be stored on a computer-readable recording medium as computer-readable code or program instructions executable on a processor.

[0128] The above-described embodiments are merely examples and are not intended to limit the technical scope in any way. For the sake of brevity, descriptions of well-known electronic configurations, control systems, software, and other functional aspects have been omitted. Furthermore, wire connections or the absence of connections between components shown in the drawings are merely illustrative of functional connections and / or physical or circuit connections, and may be embodied in an actual device as various alternative or additional functional connections, physical connections, or circuit connections.

[0129] Those skilled in the art in the art of the above embodiments will understand that the embodiments may be embodied in modified forms without departing from the essential characteristics of the above description. The description of the present embodiment should be considered from an explanatory perspective, not a limiting perspective. The scope of the claims is defined in the appended claims, not the above description, and all differences within the scope of the claims are to be construed as being within the scope of the claims. [Explanation of symbols]

[0130] 10 Biological Neurons 20 Neural Networks 100,700 processing units 110 bit cell device 130 Mirror circuit section 150 Charge charging section 170 Voltage measurement section 710-bit cell array 720 Controller 730 Row Decoder 740 column decoder 750 weight driver 760 Power Supply Controller 770 Data Buffer 780 Data Output Unit 800 Electronic Systems 810 Processing System 820 RAM 830 Neural Network Device 840 memory 850 Sensor Module 860 Communication Module

Claims

1. a bit cell line including a plurality of bit cells connected in series; a mirror circuit section for generating a mirror current by replicating the current flowing through the bit cell line at a predetermined ratio; a charge charging unit configured to charge a voltage corresponding to the mirror current by applying the mirror current replicated by the mirror circuit unit; a voltage measuring unit that outputs a value corresponding to a result of a multiply accumulate (MAC) operation between an input and a weight applied to the bit cell line based on the voltage charged in the charge charging unit; the mirror circuit unit includes an amplifier connected to the bit cell line to maintain a voltage at one end of the bit cell line constant; an output terminal of the amplifier is connected to a gate of a first transistor of the mirror circuit unit and a gate of a second transistor of the mirror circuit unit; One input terminal of the amplifier is coupled to the bit cell line.

2. the mirror circuit unit includes the first transistor connected to the bit cell line and the second transistor connected to the charge charging unit and providing the mirror current to the charge charging unit; 2. The processing device of claim 1, wherein a gate of the first transistor and a gate of the second transistor are coupled to each other.

3. 3. The processing device of claim 2, wherein a channel aspect ratio of said second transistor is less than or equal to a channel aspect ratio of said first transistor.

4. 2. The processing device of claim 1, wherein the negative (-) input terminal of the amplifier is coupled to the bit cell line.

5. The processing device according to claim 1 , wherein the predetermined ratio is 1 or less.

6. 5. The processing device according to claim 1, wherein the predetermined ratio is 1 / 2 or less.

7. The charge charging unit is a capacitor that charges based on the time the mirror current is applied; 7. The processing device of claim 1, further comprising: a charging transistor that controls the time during which the capacitor is charged by the mirror current.

8. 8. The processing device according to claim 7, wherein the voltage measurement unit includes a comparator that compares the voltage across the capacitor with a reference voltage.

9. 9. The processing apparatus of claim 1, wherein the value corresponding to the MAC operation result comprises an activation function value relating to the MAC operation result of the input and the weight applied to the bit cell line.

10. 10. The processing device of claim 1, wherein each of the bit cells includes two variable resistors connected in parallel and a switch connected in series with each of the variable resistors.

11. The bit cell line a bit data line transmitting a signal for changing the resistance value of each of the variable resistors; 11. The processing device of claim 10, further comprising: a bit data line switch for connecting each of the variable resistors to the bit data line.

12. A method of generating a plurality of bit cells, the method comprising: applying a first input and a first weight to a bit cell line including a plurality of bit cells connected in series by a controller provided in a processing device; a mirror circuit unit provided in the processing device transmitting a first mirror current, which is a copy of a current flowing through the bit cell line at a predetermined ratio according to a voltage applied to the bit cell line, to a charge charging unit; charging a capacitor with the first mirror current for a predetermined time in a charge charging unit provided in the processing device; applying, by the controller, a second input and a second weight to the bit cell line; transmitting a second mirror current, which is a copy of a current flowing through the bit cell line at a predetermined ratio in the mirror circuit unit according to the voltage applied to the bit cell line, to a charge charging unit; charging the capacitor with the second mirror current for a predetermined time in the charge charging unit; a voltage measuring unit provided in the processing device, using a capacitor voltage charged in the capacitor, outputting a value corresponding to a result of a MAC (multiply accumulate) operation between an input applied to the bit cell line and a weight; The mirror circuit unit includes an amplifier connected to the bit cell line to maintain a voltage at one end of the bit cell line constant, an output terminal of the amplifier connected to a gate of a first transistor of the mirror circuit unit and a gate of a second transistor of the mirror circuit unit, and one input terminal of the amplifier connected to the bit cell line.

13. 13. The processing method of claim 12, wherein the predetermined ratio is 1 or less.

14. 13. The processing method according to claim 12, wherein the predetermined ratio is 1 / 2 or less.

15. Charging a capacitor with the second mirror current for a predetermined time includes:

15. The processing method according to claim 12, further comprising accumulating charges on the capacitor charged by the first mirror current.

16. The outputting step includes:

16. A processing method according to any one of claims 12 to 15, wherein the value is output by comparing the charged capacitor voltage with a reference voltage.

17. 17. The method of claim 12, wherein the value corresponding to the MAC operation result comprises an activation function value relating the MAC operation result of the input and the weight applied to the bit cell line.

18. a neural network device; a processing unit that controls the function of the neural network device; The neural network device comprises: a bit cell line including a plurality of bit cells connected in series; a mirror circuit section that generates a mirror current by replicating the current flowing through the bit cell line at a predetermined ratio; a charge charging unit configured to charge a voltage corresponding to the mirror current by applying the mirror current replicated by the mirror circuit unit; a voltage measuring unit configured to output a value corresponding to a result of a multiply-accumulate (MAC) operation of an input applied to the bit cell line and a weight based on the voltage charged in the charge charging unit; the mirror circuit unit includes an amplifier connected to the bit cell line to maintain a voltage at one end of the bit cell line constant; an output terminal of the amplifier is connected to a gate of a first transistor of the mirror circuit unit and a gate of a second transistor of the mirror circuit unit; An input terminal of the amplifier is coupled to the bit cell line.

19. The mirror circuit unit the first transistor connected to the bit cell line, and the second transistor connected to the charge storage unit and providing the mirror current to the charge storage unit; 20. The electronic system of claim 18, wherein a gate of the first transistor and a gate of the second transistor are coupled to each other.

20. 20. The electronic system of claim 19, wherein a channel aspect ratio of the second transistor is less than or equal to a channel aspect ratio of the first transistor.

21. 20. The electronic system of claim 18, wherein the negative (-) input terminal of the amplifier is coupled to the bit cell line.

22. 22. The electronic system of claim 18, wherein the predetermined ratio is less than or equal to 1.

23. The charge charging unit is a capacitor that charges based on the time the mirror current is applied; 20. The electronic system of claim 18, further comprising: a charging transistor that controls the time that the capacitor is charged by the mirror current.

24. 24. The electronic system of claim 23, wherein the voltage measurement unit includes a comparator that compares the voltage across the capacitor with a reference voltage.

25. 25. The electronic system of claim 18, wherein the value corresponding to the MAC operation result comprises an activation function value for the MAC operation result of the input and the weight applied to the bit cell line.

26. 26. The electronic system of claim 18, wherein each of the bit cells includes two variable resistors coupled in parallel and a switch coupled in series with each of the variable resistors.

27. The bit cell lines are: a bit data line for transmitting a signal for changing the resistance value of each of the variable resistors; 27. The electronic system of claim 26, further comprising: a bit data line switch for coupling each of the variable resistors to the bit data line.

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