Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device improved in reliability.SOLUTION: A semiconductor device of an embodiment includes: a silicon carbide layer including a first face parallel to a first direction and a second direction perpendicular to the first direction; a trench extending in the first direction and repeatedly provided in the second direction; a gate electrode; an n-type first silicon carbide region; a p-type second silicon carbide region provided between the first silicon carbide region and the trench, extending in the second direction, and repeatedly provided in the first direction; an n-type third silicon carbide region extending in the second direction, and alternately and repeatedly provided with the second silicon carbide region in the first direction; a p-type fourth silicon carbide region between the third silicon carbide region and the first face; and an n-type fifth silicon carbide region between the fourth silicon carbide region and the first face. The first face is inclined with respect to a (0001) face by 0.1 degrees or more and 8 degrees or less in a <11-20> direction. The first direction is along the <11-20> direction, and the second direction is along a <1-100> direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these physical properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) using silicon carbide are required to have low on-resistance. To reduce the on-resistance of MOSFETs, vertical MOSFETs with a trench gate structure, in which the gate electrode is provided inside a trench, are used.

[0004] In vertical MOSFETs, a superjunction structure (hereinafter also referred to as "SJ structure") in which p-type and n-type regions are arranged alternately in the horizontal direction is one structure that achieves both high breakdown voltage and low on-resistance. The SJ structure achieves high breakdown voltage in MOSFETs by alleviating the electric field strength in the semiconductor through depletion layers that extend horizontally in the p-type and n-type regions. At the same time, low on-resistance in MOSFETs can be achieved by increasing the concentration of n-type impurities in the region.

[0005] By combining a vertical MOSFET with a trench gate structure and an SJ structure and further miniaturizing it, it is possible to further reduce the on-resistance.

[0006] Vertical MOSFETs using silicon carbide have a built-in pn junction diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the built-in diode allows a freewheeling current to flow even when the MOSFET is off.

[0007] However, when a return current is passed through the built-in diode, stacking faults grow in the silicon carbide layer due to carrier recombination energy, which increases the on-resistance of the MOSFET, reducing its reliability. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent Publication No. 2021-64723 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of the present invention is to provide a semiconductor device with improved reliability. [Means for solving the problem]

[0010] The semiconductor device of the embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a gate insulating layer provided between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer; a p-type second silicon carbide region provided in the silicon carbide layer between the first silicon carbide region and the trench, extending in the second direction in a plane parallel to the first surface, and repeatedly provided with a second period in the first direction; an n-type third silicon carbide region provided between the first silicon carbide region and the trench, extending in the second direction in a plane parallel to the first surface, and repeatedly alternately with the second silicon carbide regions at the second period in the first direction; a p-type fourth silicon carbide region provided in the silicon carbide layer, between the second silicon carbide region and the first surface and between the third silicon carbide region and the first surface, and between the trenches; and an n-type fifth silicon carbide region provided in the silicon carbide layer, between the fourth silicon carbide region and the first surface. p-type seventh silicon carbide regions provided in the silicon carbide layer, located between the fourth silicon carbide region and the trench and between the fifth silicon carbide region and the trench, and repeatedly arranged with a third period in the first direction; a first electrode provided on the first surface side of the silicon carbide layer and electrically connected to the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode provided on the second surface side of the silicon carbide layer, wherein the first surface is inclined at an angle of 0.1 to 8 degrees in a <11-20> direction with respect to a (0001) plane, the first direction being along the <11-20> direction and the second direction being along the <1-100> direction. The seventh silicon carbide region is in contact with the second silicon carbide region. . [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 5] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 6] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 7] FIG. 1 is a diagram showing the crystal structure of a silicon carbide semiconductor. [Figure 8] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 9] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 10] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 11] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 12] FIG. 10 is a schematic plan view of a semiconductor device of a comparative example. [Figure 13] FIG. 10 is a schematic cross-sectional view of a semiconductor device of a comparative example. [Figure 14] 4A and 4B are equivalent circuit diagrams of the semiconductor devices of the comparative example and the first embodiment. [Figure 15] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 16] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 17] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 18] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 19] FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a first modified example of the first embodiment. [Figure 20] FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a first modified example of the first embodiment. [Figure 21] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second modified example of the first embodiment. [Figure 22] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second modified example of the first embodiment. [Figure 23] FIG. 5 is a schematic diagram of a drive device according to a second embodiment. [Figure 24] FIG. 10 is a schematic diagram of a vehicle according to a third embodiment. [Figure 25] FIG. 10 is a schematic diagram of a vehicle according to a fourth embodiment. [Figure 26]FIG. 10 is a schematic diagram of an elevator according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0013] In the following description, n ++ , n + , n, n - and p ++ , p, p - When the notation is used, these notations represent the relative level of impurity concentration in each conductivity type. ++ is n + The n-type impurity concentration is relatively higher than that of + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. ++ HAp + The p-type impurity concentration is relatively higher than that of p + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. ++ type, n + type, n - The type is simply n-type, p ++ type, p + type, p - The type is sometimes simply referred to as p-type.

[0014] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0015] The trench width, trench spacing, trench depth, insulating layer thickness, etc. can be measured on an image obtained by, for example, SIMS or a Transmission Electron Microscope (TEM).

[0016] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; trenches provided in the silicon carbide layer, extending in the first direction in the first surface, and repeatedly provided with a first period in the second direction; a gate electrode provided in the trench; a gate insulating layer provided between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer; and n-type third silicon carbide regions alternately arranged with the second silicon carbide regions at a second period in the first direction; p-type fourth silicon carbide regions provided in the silicon carbide layer between the second silicon carbide regions and the first surface and between the third silicon carbide regions and the first surface and between the trenches; and n-type fourth silicon carbide regions provided in the silicon carbide layer between the fourth silicon carbide region and the first surface. a first electrode provided on the first surface side of the silicon carbide layer and electrically connected to the fourth silicon carbide region and the fifth silicon carbide region; and a second electrode provided on the second surface side of the silicon carbide layer, wherein the first surface is inclined at an angle of 0.1 to 8 degrees in the <11-20> direction with respect to the (0001) plane, the first direction being along the <11-20> direction, and the second direction being along the <1-100> direction.

[0017] 1, 2, 3, and 4 are schematic cross-sectional views of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a vertical MOSFET 100 having a trench gate structure and using silicon carbide. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers. The MOSFET 100 has an SJ structure.

[0018] Fig. 5 is a schematic plan view of the semiconductor device of the first embodiment. Fig. 5 is a plan view of the first plane (F1 in Figs. 1, 2, 3, and 4). The first direction and the second direction are parallel to the first plane F1. The second direction is perpendicular to the first direction.

[0019] 1 is a cross section taken along line AA' in FIG. 5. FIG. 2 is a cross section taken along line BB' in FIG. 5. FIG. 3 is a cross section taken along line CC' in FIG. 5. FIG. 4 is a cross section taken along line DD' in FIG. 5.

[0020] Fig. 6 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along a plane (Fx in Figs. 1, 2, 3, and 4) parallel to the first face F1 of the silicon carbide layer.

[0021] In the MOSFET 100, the direction in which the trench gate structure extends and the direction in which the SJ structure extends intersect.

[0022] The MOSFET 100 includes a silicon carbide layer 10, a trench 11, a gate electrode 12, a gate insulating layer 14, a source electrode 16 (first electrode), a drain electrode 18 (second electrode), and an interlayer insulating layer 20.

[0023] In the silicon carbide layer 10, n + a drain region 22 (first silicon carbide region), an n-type buffer region 24 (ninth silicon carbide region), a p-pillar region 26 (second silicon carbide region), an n-type n-pillar region 28 (third silicon carbide region), a p-type body region 30 (fourth silicon carbide region), an n-type + a source region 32 (fifth silicon carbide region), p + The electric field relaxation region 34 (sixth silicon carbide region), p + An n-type connection region 36 (seventh silicon carbide region), and an n-type charge diffusion region 38 (eighth silicon carbide region) are provided.

[0024] The silicon carbide layer 10 is made of single crystal SiC. The silicon carbide layer 10 is made of 4H—SiC.

[0025] Silicon carbide layer 10 has a first surface (F1 in FIG. 1) and a second surface (F2 in FIG. 1). First surface F1 and second surface F2 face each other. Hereinafter, first surface F1 will also be referred to as the front surface, and second surface F2 will also be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth in the direction toward second surface F2, with first surface F1 as the reference.

[0026] 1 to 6, the first direction and the second direction are parallel to the first plane F1 and the second plane F2, and the third direction is perpendicular to the first plane F1 and the second plane F2.

[0027] Figure 7 shows the crystal structure of a silicon carbide semiconductor. A typical crystal structure of a silicon carbide semiconductor is a hexagonal system such as 4H-SiC. One of the faces (top faces of the hexagonal prism) normalized to the c-axis along the axial direction of the hexagonal prism is the (0001) face. A face equivalent to the (0001) face is called the silicon face and is expressed as the {0001} face. Silicon (Si) is arranged on the silicon face.

[0028] The other surface (top surface of the hexagonal prism) normal to the c-axis along the axial direction of the hexagonal prism is the (000-1) surface. The surface equivalent to the (000-1) surface is called the carbon surface and is written as the {000-1} surface. Carbon (C) is arranged on the carbon surface.

[0029] On the other hand, the side surfaces of the hexagonal prism (cylindrical surfaces) are m-planes, i.e., {1-100} planes, which are equivalent to the (1-100) plane. Furthermore, the planes passing through pairs of non-adjacent ridges are a-planes, i.e., {11-20} planes, which are equivalent to the (11-20) plane. Both silicon (Si) and carbon (C) are arranged on the m-plane and a-plane.

[0030] The first plane F1 is a plane inclined at an angle of 0.1 to 8 degrees with respect to the (0001) plane. That is, the normal to the plane is inclined at an angle of 0.1 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off angle with respect to the (0001) plane is 0 to 8 degrees. The second plane F2 is, for example, a plane inclined at an angle of 0.1 to 8 degrees with respect to the (000-1) plane.

[0031] The (0001) plane is called the silicon plane, and the (000-1) plane is called the carbon plane.

[0032] The tilt direction of the first plane F1 is the <11-20> direction, which is perpendicular to the a-plane.

[0033] 1 to 6, the first direction parallel to the first plane F1 is the direction along the <11-20> direction, and the second direction parallel to the first plane F1 is the direction along the <1-100> direction.

[0034] The first direction being along the <11-20> direction means that the first direction is along a plane including the <0001> direction and the <11-20> direction, i.e., an m-plane. The first direction has an inclination angle of 1 degree or less with respect to the m-plane, for example.

[0035] The second direction being along the <1-100> direction means that the second direction is along a plane including the <0001> direction and the <1-100> direction, i.e., the a-plane. The first direction has an inclination angle of 1 degree or less with respect to the a-plane, for example.

[0036] The thickness of the silicon carbide layer 10 in the third direction is, for example, not less than 5 μm and not more than 150 μm.

[0037] The trench 11 exists in the silicon carbide layer 10. The trench 11 is a recess provided in the silicon carbide layer 10. The trench 11 extends in a first direction as shown in FIG.

[0038] The width of trench 11 in the second direction (Wt in FIGS. 1 and 5) is, for example, equal to or less than the distance between two adjacent trenches 11 (St in FIGS. 1 and 5).

[0039] The width Wt of the trench 11 in the second direction is, for example, not less than 0.2 μm and not more than 1.0 μm.

[0040] The distance St between two adjacent trenches 11 is, for example, 1.0 μm or less. The distance St between two adjacent trenches 11 is, for example, 0.2 μm or more and 1.0 μm or less.

[0041] The trenches 11 are repeatedly provided in the second direction at a first period (C1 in FIGS. 1 and 5). The trenches 11 are repeatedly arranged in the second direction.

[0042] The first period (C1 in FIGS. 1 and 5) of the repetition of trenches 11 in the second direction is, for example, 0.4 μm or more and 2.0 μm or less. The repetition pitch of trenches 11 in the second direction is, for example, 0.4 μm or more and 2.0 μm or less.

[0043] The first period C1 of repetition of trenches 11 in the second direction is the sum of width Wt of trenches 11 in the second direction and spacing St of trenches 11 in the second direction.

[0044] The length of trench 11 in the third direction (d1 in FIG. 1) is, for example, 0.5 μm or more and 2.0 μm or less. In other words, the depth of trench 11 is, for example, 0.5 μm or more and 2.0 μm or less.

[0045] The inclination angle of the side surface of trench 11 with respect to the m-plane is, for example, not less than 0 degrees and not more than 5 degrees. The m-plane is a plane perpendicular to the <1-100> direction.

[0046] The gate electrode 12 is provided in the trench 11. The gate electrode 12 is provided between the source electrode 16 and the drain electrode 18. The gate electrode 12 extends in a first direction.

[0047] The gate electrode 12 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0048] The gate insulating layer 14 is provided between the gate electrode 12 and the silicon carbide layer 10. The gate insulating layer 14 is provided between the gate electrode 12 and each of the source region 32, the body region 30, the p-pillar region 26, and the n-pillar region 28. The gate insulating layer 14 contacts the gate electrode 12 and each of the source region 32, the body region 30, the p-pillar region 26, and the n-pillar region 28.

[0049] The gate insulating layer 14 is, for example, a silicon oxide film. For example, a high-k insulating film (a high-dielectric-constant insulating film such as HfSiON, ZrSiON, or AlON) can be used as the gate insulating layer 14. Alternatively, for example, a stacked film of a silicon oxide film (SiO2) and a high-k insulating film can also be used as the gate insulating layer 14.

[0050] The interlayer insulating layer 20 is provided on the gate electrode 12. The interlayer insulating layer 20 is, for example, a silicon oxide film.

[0051] The source electrode 16 is provided on the front surface side of the silicon carbide layer 10. The source electrode 16 is provided on the front surface of the silicon carbide layer 10.

[0052] The source electrode 16 is electrically connected to the source region 32. The source electrode 16 contacts the source region 32.

[0053] The source electrode 16 is electrically connected to the connection region 36. The source electrode 16 contacts the connection region 36.

[0054] The source electrode 16 includes a metal. The metal forming the source electrode 16 has a laminated structure of titanium (Ti) and aluminum (Al), for example.

[0055] The drain electrode 18 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 18 is provided on the back surface of the silicon carbide layer 10. The drain electrode 18 is in contact with the drain region 22.

[0056] The drain electrode 18 is, for example, a metal or a metal-semiconductor compound, and includes a material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0057] n + The drain region 22 is provided on the back surface side of the silicon carbide layer 10. The drain region 22 is an example of a first silicon carbide region.

[0058] The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0059] The n-type buffer region 24 is provided on the drain region 22. The buffer region 24 is an example of a ninth silicon carbide region.

[0060] The buffer region 24 is provided between the drain region 22 and the surface of the silicon carbide layer 10. The buffer region 24 is provided between the drain region 22 and the p-pillar region 26. The buffer region 24 is provided between the drain region 22 and the n-pillar region 28.

[0061] The buffer region 24 is in contact with, for example, the p-pillar region 26. The buffer region 24 is also in contact with, for example, the n-pillar region 28.

[0062] The buffer region 24 functions as a current path when the MOSFET 100 is in an on-state. In addition, the buffer region 24 has a function of suppressing the extension of the depletion layer toward the drain region 22 when the MOSFET 100 is in an off-state, thereby maintaining the breakdown voltage of the MOSFET 100.

[0063] The buffer region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the buffer region 24 is lower than the n-type impurity concentration of the drain region 22. The n-type impurity concentration of the buffer region 24 is equal to or higher than the n-type impurity concentration of the n-pillar region 28. The n-type impurity concentration of the buffer region 24 is, for example, 1×10 16 cm -3 5x10 or more 19 cm -3 The following is the result.

[0064] The p-type p-pillar region 26 is provided between the drain region 22 and the trench 11. The p-pillar region 26 is an example of a second silicon carbide region.

[0065] The p-pillar region 26 is in contact with, for example, the trench 11. The p-pillar region 26 is provided between the buffer region 24 and the trench 11.

[0066] 6, the p-pillar regions 26 extend in a second direction on a plane Fx parallel to the first plane F1. The p-pillar regions 26 are repeatedly provided in the first direction at a second period (C2 in FIGS. 3 and 6). The p-pillar regions 26 are repeatedly arranged in the first direction.

[0067] The second period (C2 in FIGS. 3 and 6) of the repetition of the p-pillar regions 26 in the first direction is, for example, 0.4 μm or more and 10 μm or less, more preferably 0.6 μm or more and 10 μm or less. The repetition pitch of the p-pillar regions 26 in the first direction is, for example, 0.4 μm or more and 10 μm or less, more preferably 0.6 μm or more and 10 μm or less.

[0068] The n-type n-pillar region 28 is provided between the drain region 22 and the trench 11. The n-pillar region 28 is an example of a third silicon carbide region.

[0069] The n-pillar region 28 is in contact with, for example, the trench 11. The n-pillar region 28 is provided between the buffer region 24 and the trench 11.

[0070] As shown in Figure 6, the n-pillar regions 28 extend in the second direction in a plane Fx parallel to the first plane F1. The n-pillar regions 28 are repeatedly provided in the first direction at a second period (C2 in Figures 3 and 6). The n-pillar regions 28 are repeatedly provided alternating with the p-pillar regions 26 in the first direction. The n-pillar regions 28 are repeatedly arranged in the first direction.

[0071] The second period (C2 in FIGS. 3 and 6) of the repetition of the n-pillar regions 28 in the first direction is, for example, 0.4 μm or more and 10 μm or less, more preferably 0.6 μm or more and 10 μm or less. The repetition pitch of the n-pillar regions 28 in the first direction is, for example, 0.4 μm or more and 10 μm or less, more preferably 0.6 μm or more and 10 μm or less.

[0072] The second period C2 of the repetition in the first direction of the p-pillar regions 26 and the n-pillar regions 28 is the sum of the width in the first direction of the p-pillar regions 26 (Wp in Figures 3 and 6) and the width in the first direction of the n-pillar regions 28 (Wn in Figures 3 and 6).

[0073] The second period C2 of the repetition in the first direction of the p-pillar regions 26 and the n-pillar regions 28 is, for example, longer than the first period C1 of the repetition in the second direction of the trenches 11. The second period C2 is, for example, 1.5 to 5 times the first period C1.

[0074] The p-pillar regions 26 and the n-type n-pillar regions 28 are alternately arranged in a first direction. The alternating p-pillar regions 26 and n-pillar regions 28 form an SJ structure.

[0075] The p-pillar region 26 is p + The p-pillar region 26 is connected to the source electrode 16 through a connecting region 36. The potential of the p-pillar region 26 is fixed to the source potential.

[0076] The length (d2 in FIGS. 1 and 3) of the p-pillar region 26 in the third direction from the first face F1 toward the second face F2 is longer than the width (Wp in FIG. 3) of the p-pillar region 26 in the first direction. The length d2 of the p-pillar region 26 in the third direction from the first face F1 toward the second face F2 is, for example, not less than two times and not more than 20 times the width Wp of the p-pillar region 26 in the first direction.

[0077] The length d2 of the p-pillar region 26 in the third direction is, for example, longer than the length (d1 in FIG. 1) of the trench 11 in the third direction. The length d2 of the p-pillar region 26 in the third direction is, for example, at least twice the length d1 of the trench 11 in the third direction. Preferably, it is at least three times as long, and more preferably at least four times as long.

[0078] The p-pillar region 26 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-pillar region 26 is, for example, 1×10 17 cm -3 The p-type impurity concentration of the p-pillar region 26 is, for example, 1×10 18 cm -3 5x10 or more 19 cm -3 The following is the result.

[0079] The width in the first direction of the n-pillar region 28 (Wn in FIG. 3) is, for example, larger than the width in the first direction (Wp in FIG. 3) of the p-pillar region 26. The width in the first direction Wn of the n-pillar region 28 is, for example, 1.2 to 3 times the width in the first direction Wp of the p-pillar region 26.

[0080] The length (d3 in FIGS. 2 and 3) of the n-pillar region 28 in the third direction from the first face F1 toward the second face F2 is longer than the width (Wn in FIG. 3) of the n-pillar region 28 in the first direction. The length d3 of the n-pillar region 28 in the third direction from the first face F1 toward the second face F2 is, for example, not less than 2 times and not more than 20 times the width Wn of the n-pillar region 28 in the first direction.

[0081] The length d3 in the third direction of the n-pillar region 28 is, for example, longer than the length in the third direction of the trench 11 (d1 in FIG. 1). The length d3 in the third direction of the n-pillar region 28 is, for example, at least twice the length d1 in the third direction of the trench 11. Preferably, it is at least three times as long, and more preferably at least four times as long.

[0082] The n-pillar region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-pillar region 28 is lower than the n-type impurity concentration of the drain region 22. The n-type impurity concentration of the n-pillar region 28 is equal to or lower than the n-type impurity concentration of the buffer region 24. The n-type impurity concentration of the n-pillar region 28 is, for example, 1×10 16 cm -3 More than 1×10 19 cm -3 The following is the result.

[0083] For example, when the width of the p-pillar region 26 in the first direction is Wp, the p-type impurity concentration of the p-pillar region 26 is N1, the width of the n-pillar region 28 in the first direction is Wn, and the n-type impurity concentration of the n-pillar region 28 is N2, the relationship of the following equation is satisfied. 0.8≦(Wp×N1) / (Wn×N2)≦1.2

[0084] The p-type body region 30 is provided between the p-pillar region 26 and the first face F1. The body region 30 is also provided between the n-pillar region 28 and the first face F1. The body region 30 is also provided between the trenches 11. The body region 30 is an example of a fourth silicon carbide region.

[0085] The body region 30 is in contact with the gate insulating layer 14. The body region 30 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-state, a channel through which electrons flow is formed in the region of the body region 30 in contact with the gate insulating layer 14.

[0086] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 30 is, for example, 5×10 16 cm-3 5x10 or more 17 cm -3 The depth of the body region 30 is, for example, not less than 0.5 μm and not more than 1.0 μm.

[0087] n + The source region 32 is provided between the body region 30 and the first face F1. The source region 32 is an example of a fifth silicon carbide region.

[0088] The source region 32 is in contact with the source electrode 16. The source region 32 is in contact with the trench 11. The source region 32 is the gate insulating layer 14.

[0089] The n-type impurity concentration of the source region 32 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The depth of the source region 32 is shallower than the depth of the body region 30. The depth of the source region 32 is, for example, not less than 0.1 μm and not more than 0.6 μm.

[0090] p + The electric field relaxation region 34 is provided between the n-pillar region 28 and the trench 11. The electric field relaxation region 34 is an example of a sixth silicon carbide region.

[0091] The n-pillar region 28 contacts the bottom surface of the trench 11. The n-pillar region 28 extends in a first direction. The n-pillar region 28 is provided between the p-pillar region 26 and the trench 11.

[0092] The electric field buffer region 34 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field buffer region 34 is higher than the p-type impurity concentration of the body region 30. The p-type impurity concentration of the electric field buffer region 34 is, for example, 1×10 20 cm -3 The p-type impurity concentration of the electric field relaxation region 34 is, for example, 5×10 20 cm -3 5x10 or more 22 cm -3 The following is the result.

[0093] The electric field relaxation region 34 is p + The electric field relaxation region 34 is connected to the source electrode 16 through a connecting region 36. The potential of the electric field relaxation region 34 is fixed to the source potential. The electric field relaxation region 34 has the function of relaxing the electric field applied to the gate insulating layer 14 at the bottom of the trench 11.

[0094] The width in the second direction of the electric field relaxation region 34 (We in FIG. 2) is, for example, smaller than the width in the second direction (Wt in FIG. 2) of the trench 11. The width in the second direction We of the electric field relaxation region 34 is, for example, 50% or more and 90% or less of the width in the second direction Wt of the trench 11.

[0095] p + The connecting region 36 is in contact with, for example, the p-pillar region 26. The connecting region 36 is in contact with, for example, the electric field relaxation region 34. The connecting region 36 is an example of a seventh silicon carbide region.

[0096] The connection region 36 is provided between the body region 30 and the trench 11. The connection region 36 is provided between the source region 32 and the trench 11.

[0097] The connection region 36 contacts the side surface of the trench 11. The connection region 36 contacts, for example, the bottom surface of the trench 11. The connection region 36 contacts, for example, the first face F1.

[0098] The connection region 36 contacts the gate insulating layer 14. The connection region 36 contacts the source electrode 16 on the first face F1, for example.

[0099] 5, the connection regions 36 are repeatedly provided in the first direction at a third period (C3 in FIG. 5). The connection regions 36 are repeatedly arranged in the first direction. The third period C3 of the repetition of the connection regions 36 in the first direction is, for example, not less than 10 μm and not more than 2000 μm.

[0100] The third period C3 of the repetition of the connection regions 36 in the first direction is the sum of the width (Wc in FIG. 5) of the connection regions 36 in the first direction and the spacing (SC in FIG. 5) of the connection regions 36 in the first direction. The width Wc of the connection regions 36 in the first direction is, for example, not less than 2 μm and not more than 5 μm.

[0101] The third period C3 of the repetition in the first direction of the connection region 36 is, for example, longer than the second period C2 of the repetition in the first direction of the p-pillar regions 26 and the n-pillar regions 28. The third period C3 is, for example, not less than two times and not more than 1000 times the second period C2.

[0102] The connection region 36 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the connection region 36 is, for example, higher than the p-type impurity concentration of the body region 30. The p-type impurity concentration of the connection region 36 is, for example, 1×10 20 cm -3 The p-type impurity concentration of the connection region 36 is, for example, 5×10 20 cm -3 5x10 or more 22 cm -3 The following is the result.

[0103] The connection region 36 serves to electrically connect the p-pillar region 26 and the source electrode 16. The connection region 36 is a connecting portion that connects the p-pillar region 26 and the source electrode 16. The connection region 36 fixes the p-pillar region 26 to the potential of the source electrode 16.

[0104] The connection region 36 also functions to electrically connect the electric field reduction region 34 and the source electrode 16. The connection region 36 also functions to reduce the electrical resistance between the source electrode 16 and the body region 30.

[0105] The n-type charge diffusion region 38 is provided between the p-pillar region 26 and the body region 30. The charge diffusion region 38 is an example of an eighth silicon carbide region.

[0106] When the MOSFET 100 is turned on, the charge diffusion region 38 has the function of diffusing carriers flowing in the body region 30 immediately above the p-pillar region 26 laterally and causing them to flow to the n-pillar region 28. By providing the charge diffusion region 38, the body region 30 immediately above the p-pillar region 26 can be effectively used as a channel, thereby reducing the on-resistance of the MOSFET 100.

[0107] The charge diffusion region 38 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the charge diffusion region 38 is higher than the n-type impurity concentration of the n-pillar region 28. The n-type impurity concentration of the charge diffusion region 38 is, for example, 5×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0108] The MOSFET 100 can be manufactured using a known manufacturing method.

[0109] For example, n + A first n-type layer is formed by epitaxial growth on a silicon carbide substrate having a surface of a drain region 22. P-type impurities are implanted into the first n-type layer by ion implantation to form p-pillar regions 26 and n-pillar regions 28 that extend in a second direction and are alternately formed in the first direction. The p-pillar regions 26 and n-pillar regions 28 form an SJ structure.

[0110] Thereafter, a second n-type layer is formed on the p-pillar region 26 and the n-pillar region 28 by epitaxial growth. A transistor with a trench gate structure having a trench 11 extending in the first direction is formed on the second n-type layer. For example, a p-type body region 30, an n-pillar region 28, and a p-type body region 30 are formed on the second n-type layer. + A source region 32 of a type is formed by ion implantation, a trench 11 extending in a first direction is excavated, a mask is formed on the side surface of the trench, and p + The mask is removed and p is implanted into the bottom of the trench. + A molded electric field relaxation region 34 is formed, and activation annealing is performed at high temperature.

[0111] By the above manufacturing method, the MOSFET 100 is formed in which the extending direction of the SJ structure and the extending direction of the trench gate structure intersect.

[0112] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0113] The MOSFET 100 of the first embodiment can achieve a reduced on-resistance and improved reliability, as will be described in detail below.

[0114] A trench gate structure in which a gate electrode is provided in a trench is applied to the MOSFET 100. By applying the trench gate structure, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is reduced.

[0115] Furthermore, the MOSFET 100 has p-type p-pillar regions 26 and n-type n-pillar regions 28 arranged alternately in a first direction. The alternating arrangement of the p-pillar regions 26 and the n-type n-pillar regions 28 forms an SJ structure. Depletion layers extending laterally in the p-pillar regions 26 and the n-type n-pillar regions 28 mitigate the electric field strength in the silicon carbide layer 10, thereby achieving a high breakdown voltage for the MOSFET 100. At the same time, increasing the n-type impurity concentration in the n-pillar regions 28 reduces the on-resistance of the MOSFET 100.

[0116] Vertical MOSFETs using silicon carbide have a built-in pn junction diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the built-in diode allows a freewheeling current to flow even when the MOSFET is off.

[0117] However, when a return current is passed through the built-in diode, stacking faults grow in the silicon carbide layer due to carrier recombination energy, which increases the on-resistance of the MOSFET, reducing its reliability.

[0118] 8, 9, 10, and 11 are schematic cross-sectional views of a semiconductor device of a comparative example. The semiconductor device of the comparative example is a vertical MOSFET 901 with a trench gate structure using silicon carbide. The MOSFET 901 is an n-channel MOSFET that uses electrons as carriers. The MOSFET 901 has an SJ structure.

[0119] Fig. 12 is a schematic plan view of a semiconductor device of a comparative example. Fig. 12 is a plan view of a first plane (F1 in Figs. 8, 9, 10, and 11). The first direction and the second direction are parallel to the first plane F1. The second direction is perpendicular to the first direction.

[0120] Fig. 8 is a cross section taken along line AA' in Fig. 12. Fig. 9 is a cross section taken along line BB' in Fig. 12. Fig. 10 is a cross section taken along line CC' in Fig. 12. Fig. 11 is a cross section taken along line DD' in Fig. 12.

[0121] Fig. 13 is a schematic cross-sectional view of a semiconductor device of a comparative example, taken along a plane (Fx in Figs. 8, 9, 10, and 11) parallel to the first face F1 of the silicon carbide layer.

[0122] The MOSFET 901 differs from the MOSFET 100 of the first embodiment in that the extension direction of the trench gate structure and the extension direction of the SJ structure coincide with each other. In the MOSFET 901, the trench gate structure and the SJ structure extend in a first direction.

[0123] The MOSFET 901 includes a silicon carbide layer 10 , a trench 11 , a gate electrode 12 , a gate insulating layer 14 , a source electrode 16 , a drain electrode 18 , and an interlayer insulating layer 20 .

[0124] In the silicon carbide layer 10, n + A drain region 22, an n-type buffer region 24, a p-pillar region 26, an n-pillar region 28, a p-type body region 30, and an n + Type source region 32, p + Type electric field relaxation region 34, p +In this case, a p-type connection region 36 and an n-type charge diffusion region 38 are provided. Since the MOSFET 901 has a structure without a p-pillar under the channel, it is not necessary to introduce the charge diffusion region 38. In this case, the trench can be made shallower.

[0125] The trench 11 exists in the silicon carbide layer 10. The trench 11 is a recess provided in the silicon carbide layer 10. The trench 11 extends in a first direction as shown in FIG.

[0126] The trenches 11 are repeatedly provided in the second direction at a first period (C1 in FIG. 12). The trenches 11 are repeatedly arranged in the second direction.

[0127] 13, the p-pillar regions 26 extend in a first direction on a plane Fx parallel to the first plane F1. The p-pillar regions 26 are repeatedly provided in a second direction with a second period (C2 in FIG. 13). The p-pillar regions 26 are repeatedly arranged in the second direction.

[0128] As shown in Fig. 13, the n-pillar regions 28 extend in a first direction on a plane Fx parallel to the first plane F1. The n-pillar regions 28 are repeatedly provided in a second direction with a second period (C2 in Fig. 13). The n-pillar regions 28 are repeatedly provided alternating with the p-pillar regions 26 in the second direction. The n-pillar regions 28 are repeatedly arranged in the second direction.

[0129] The second period C2 of the repetition of the p-pillar regions 26 and the n-pillar regions 28 in the second direction is equal to the first period C1 of the repetition of the trenches 11 in the second direction.

[0130] As shown in Fig. 12, the connection regions 36 are repeatedly provided in the first direction at a third period (C3 in Fig. 12). The connection regions 36 are repeatedly arranged in the first direction.

[0131] 14 is an equivalent circuit diagram of the semiconductor devices of the comparative example and the first embodiment. In the MOSFET 901 of the comparative example and the MOSFET 100 of the first embodiment, a pn junction diode is connected in parallel to the transistor between the source electrode 16 and the drain electrode 18 as a built-in diode.

[0132] For example, consider a case where a MOSFET is used as a switching element connected to an inductive load. When the MOSFET is off, a load current caused by the inductive load may apply a voltage to the source electrode 16 that is positive with respect to the drain electrode 18. In this case, a forward current flows through the pn junction diode. This state is also called a reverse conduction state.

[0133] The pn junction diode performs bipolar operation, and as a result of this bipolar operation, stacking faults grow in the silicon carbide layer 10 due to carrier recombination energy.

[0134] 15 and 16 are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment.

[0135] 15 is a cross section taken along line CC' of a comparative example MOSFET 901. FIG. 15 is a view corresponding to FIG.

[0136] In MOSFET 901 of the comparative example, when the pn junction diode, which is the built-in diode, operates, stacking faults STF grow in silicon carbide layer 10 due to the recombination energy of carriers, as shown in FIG.

[0137] The stacking faults STF grow, for example, from the interface between the drain region 22 and the buffer region 24 along a plane parallel to the C-plane. The stacking faults STF grow in the <11-20> direction. Therefore, in the MOSFET 901, the stacking faults STF grow upward along the first direction, as shown in FIG. 15 .

[0138] 16 is a cross-sectional view of a plane Fx parallel to the first plane F1 of the silicon carbide layer of a MOSFET 901 of the comparative example. FIG. 16 is a view corresponding to FIG.

[0139] 16 shows the pattern of stacking faults STF grown in silicon carbide layer 10. The pattern of stacking faults STF is shown not only on plane Fx but also including patterns present above and below plane Fx.

[0140] As described above, the stacking faults STF grow in the <11-20> direction. Therefore, in the MOSFET 901, the stacking faults STF grow upward while spreading along the first direction, as shown in FIG.

[0141] However, it is known that the growth of stacking faults STFs stops at the pn junction. Therefore, as shown in Figure 16, the growth of stacking faults STFs stops at the pn junction between the p-pillar region 26 and the n-pillar region 28. Therefore, stacking faults STFs grow upward in the n-pillar region 28 sandwiched between the p-pillar regions 26.

[0142] The p-pillar regions 26 and n-pillar regions 28 of the MOSFET 901 extend along the <11-20> direction. The p-n junction plane between the p-pillar regions 26 and n-pillar regions 28 of the MOSFET 901 is a plane parallel to the <11-20> direction. In other words, the p-n junction plane between the p-pillar regions 26 and n-pillar regions 28 is an m-plane perpendicular to the <1-100> direction.

[0143] The presence of stacking faults STF in the n-pillar region 28 increases the electrical resistance of the n-pillar region 28. Therefore, the on-resistance of the MOSFET 901 increases.

[0144] 17 and 18 are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment.

[0145] 17 is a cross section taken along line CC' of the MOSFET 100 according to the first embodiment. FIG. 17 corresponds to FIG.

[0146] In the MOSFET 100 of the first embodiment, when the pn junction diode, which is the built-in diode, operates, stacking faults STF grow in the silicon carbide layer 10 due to the recombination energy of carriers, as shown in FIG.

[0147] The stacking faults STF grow, for example, from the interface between the drain region 22 and the buffer region 24 along a plane parallel to the C-plane. As described above, the stacking faults STF grow in the <11-20> direction. Therefore, in the MOSFET 100, similar to the MOSFET 901, the stacking faults STF grow along the first direction as shown in FIG. 17 .

[0148] The MOSFET 100 of the first embodiment differs from the MOSFET 901 of the comparative example in that the p-pillar regions 26 and the n-pillar regions 28 extend in the <1-100> direction. Therefore, the p-n junction plane between the p-pillar regions 26 and the n-pillar regions 28 of the MOSFET 100 is a plane parallel to the <1-100> direction. In other words, the p-n junction plane between the p-pillar regions 26 and the n-pillar regions 28 is an a-plane that intersects with the <11-20> direction.

[0149] 17, in the MOSFET 100 of the first embodiment, a pn junction plane exists in a direction intersecting the <11-20> direction in which the stacking faults STF extend. The stacking faults STF extending in the <11-20> direction stop growing at the pn junction plane perpendicular to the first direction. The stacking faults STF stop growing at the pn junction plane at the bottom of the p-pillar region 26.

[0150] 18 is a cross-sectional view of a plane Fx parallel to the first plane F1 of the silicon carbide layer of the MOSFET 100 according to the first embodiment. FIG. 18 is a view corresponding to FIG.

[0151] 18 shows the pattern of stacking faults STF grown in silicon carbide layer 10. The pattern of stacking faults STF is shown not only on plane Fx but also including patterns present above and below plane Fx.

[0152] As described above, stacking faults STF grow in the direction along the <11-20> direction. In the MOSFET 100, stacking faults STF grow upward while spreading along the first direction, as shown in FIG. 18 , but the growth stops at the pn junction plane that exists in a direction perpendicular to the first direction. The growth of stacking faults STF stops at the pn junction plane at the bottom of the p-pillar region 26.

[0153] 17 and 18 , in the MOSFET 100, the growth of stacking faults STF stops at the pn junction surface that exists in a direction perpendicular to the first direction or at the pn junction surface at the bottom surface of the p-pillar region 26. Therefore, in the MOSFET 100 of the first embodiment, the growth of stacking faults is suppressed compared to the MOSFET 901 of the comparative example. Therefore, an increase in the on-resistance of the MOSFET 100 is suppressed, and the reliability of the MOSFET 100 is improved.

[0154] In the MOSFET 100 of the first embodiment, the trench 11 extends in a first direction along the <11-20> direction. Therefore, the plane orientations of both side surfaces of the trench 11, in which the channel of the MOSFET 100 is formed, are equivalent to plane orientations along the m-plane.

[0155] Consider a case where the trench 11 is formed to extend in a second direction along the <1-100> direction in the MOSFET 100. In this case, the extension direction of the trench gate structure and the extension direction of the SJ structure coincide with each other.

[0156] However, in this case, since the first face F1 of the MOSFET 100 is inclined in the <11-20> direction, the plane orientations of both side faces of the trench 11 in which the channel of the MOSFET 100 is formed are different from the a-plane in that the inclination angle is different.

[0157] If the plane orientation of the plane where the channel is formed differs, for example, the mobility of carriers will differ on both sides of the trench 11. This will undesirably result in a MOSFET with unbalanced and unstable characteristics.

[0158] In the first embodiment, the extension direction of the trench gate structure and the extension direction of the SJ structure are made to intersect, thereby achieving both stable transistor characteristics and suppression of stacking faults, thereby realizing a MOSFET 100 with excellent characteristics.

[0159] In the MOSFET 901 of the comparative example, the extension direction of the trench gate structure and the extension direction of the SJ structure coincide with each other, and therefore the second period C2 of the repetition of the p-pillar regions 26 and the n-pillar regions 28 in the second direction is equal to the first period C1 of the repetition of the trenches 11 in the second direction.

[0160] On the other hand, in the MOSFET 100 of the first embodiment, by intersecting the extension direction of the trench gate structure and the extension direction of the SJ structure, it is possible to set the second period C2 of the repetition of the p-pillar regions 26 and the n-pillar regions 28 in the first direction and the first period C1 of the repetition of the trenches 11 in the second direction independently. This increases the degree of freedom in designing the trench gate structure and the SJ structure, thereby realizing a MOSFET 100 with excellent characteristics.

[0161] From the viewpoint of achieving both a reduction in on-resistance through miniaturization of the transistor structure and an improvement in breakdown voltage through the SJ structure, it is preferable that the second period C2 of repetition in the first direction of the p-pillar regions 26 and the n-pillar regions 28 is greater than the first period C1 of repetition in the second direction of the trenches 11.

[0162] The width in the first direction of the n-pillar region 28 (Wn in FIG. 3) is preferably larger than the width in the first direction (Wp in FIG. 3) of the p-pillar region 26. Reducing the proportion of the p-pillar region 26 that intersects with the trench 11 increases the proportion of the effectively usable channel area, thereby reducing the on-resistance of the MOSFET 100.

[0163] It is preferable that the n-type impurity concentration of the buffer region 24 is higher than the n-type impurity concentration of the n-pillar region 28, and that the p-pillar region 26 be in contact with the buffer region 24. By limiting most of the region where stacking faults are formed to the buffer region 24, which has low electrical resistance, an increase in the on-resistance of the MOSFET 100 is suppressed, and the reliability of the MOSFET 100 is improved.

[0164] The MOSFET 100 has a p + The trench 11 has a field relaxation region 34 of a type. By having the field relaxation region 34, the electric field applied to the gate insulating layer 14 at the bottom of the trench 11 is relaxed when the MOSFET 100 is in an off state. This improves the reliability of the gate insulating layer 14. This improves the reliability of the MOSFET 100.

[0165] The width in the second direction of the electric field relaxation region 34 (We in FIG. 2) is preferably smaller than the width in the second direction (Wt in FIG. 2) of the trench 11. This prevents the electric field relaxation region 34 from narrowing the current path of carriers when the MOSFET 100 is in an on-state, thereby reducing the on-resistance.

[0166] (First Modification) The semiconductor device of the first modified example of the first embodiment differs from the semiconductor device of the first embodiment in that the second silicon carbide region includes a first region and a second region that is provided between the first region and the fourth silicon carbide region and has a p-type impurity concentration higher than the p-type impurity concentration of the first region.

[0167] 19 and 20 are schematic cross-sectional views of a semiconductor device according to a first modification of the first embodiment. Figures 19 and 20 correspond to Figures 1 and 3 of the first embodiment, respectively. The semiconductor device according to the first modification of the first embodiment is a vertical MOSFET 101 with a trench gate structure using silicon carbide.

[0168] The p-type p-pillar region 26 has a first region 26x and a second region 26y. The second region 26y is provided between the first region 26x and the body region 30. The second region 26y is provided between the first region 26x and the charge diffusion region 38.

[0169] The p-type impurity concentration of the second region 26y is higher than the p-type impurity concentration of the first region 26x, and is, for example, at least twice the p-type impurity concentration of the first region 26x.

[0170] In the MOSFET 101, the p-pillar region 26 includes the second region 26y having a high p-type impurity concentration, thereby reducing the electrical resistance between the p-pillar region 26 and the source electrode 16. Therefore, for example, the discharge of carriers from the p-pillar region 26 is promoted, and the switching loss of the MOSFET 100 is reduced.

[0171] Furthermore, the n-pillar region 28 is sandwiched between the second regions 26y in the MOSFET 101. Therefore, for example, when the load of the MOSFET 101 is short-circuited, the current path of the n-pillar region 28 is narrowed by the second regions 26y, improving the short-circuit resistance of the MOSFET 101.

[0172] (Second Modification) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that it does not include the eighth silicon carbide region.

[0173] 21 and 22 are schematic cross-sectional views of a semiconductor device according to a second modification of the first embodiment. Figures 21 and 22 correspond to Figures 1 and 3 of the first embodiment, respectively. The semiconductor device according to the second modification of the first embodiment is a vertical MOSFET 102 with a trench gate structure using silicon carbide.

[0174] The MOSFET 102 does not include an n-type charge diffusion region 38. By not including the charge diffusion region 38, for example, the depth of the trench 11 can be made shallower in the MOSFET 102. On the other hand, the charge diffusion region 38 has the function of diffusing carriers flowing in the body region 30 immediately above the p-pillar region 26 laterally and causing them to flow to the n-pillar region 28 when the MOSFET 100 is turned on. In the MOSFET 102, the removal of the charge diffusion region 38 makes it more difficult for some carriers to flow.

[0175] As described above, according to the first embodiment and the modifications, a semiconductor device with improved reliability can be realized.

[0176] (Second embodiment) The inverter circuit and the drive device of the second embodiment are an inverter circuit and a drive device that include the semiconductor device of the first embodiment.

[0177] 23 is a schematic diagram of a driving device according to the second embodiment. The driving device 700 includes a motor 140 and an inverter circuit 150.

[0178] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140.

[0179] According to the second embodiment, the inverter circuit 150 and the driving device 700 are provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the inverter circuit 150 and the driving device 700.

[0180] (Third embodiment) The vehicle of the third embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0181] 24 is a schematic diagram of a vehicle according to the third embodiment. The vehicle 800 according to the third embodiment is a railway vehicle. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0182] The inverter circuit 150 is composed of three semiconductor modules that use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 800 are rotated by the motor 140.

[0183] According to the third embodiment, the vehicle 800 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 800.

[0184] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0185] 25 is a schematic diagram of a vehicle according to the fourth embodiment. The vehicle 900 according to the fourth embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0186] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0187] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 900.

[0188] According to the fourth embodiment, the vehicle 900 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 900.

[0189] (Fifth embodiment) The elevator of the fifth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0190] 26 is a schematic diagram of an elevator according to the fifth embodiment. The elevator 1000 according to the fifth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0191] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0192] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoisting machine 616, causing the car 610 to rise and fall.

[0193] According to the fifth embodiment, the elevator 1000 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the elevator 1000.

[0194] In the first embodiment, aluminum (Al) has been used as an example of a p-type impurity, but boron (B) can also be used as a p-type impurity.

[0195] In the first embodiment, a MOSFET is used as an example of a semiconductor device, but the present invention can also be applied to an Insulated Gate Bipolar Transistor (IGBT). For example, an IGBT can be realized by replacing the region corresponding to the drain region 22 of the MOSFET 100 from n-type to p-type.

[0196] Furthermore, in the second to fifth embodiments, the semiconductor device of the present invention has been described as being applied to vehicles and elevators, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0197] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0198] 10 Silicon carbide layer 11 Trench 12 gate electrode 14 Gate insulating layer 16 Source electrode (first electrode) 18 Drain electrode (second electrode) 22 drain region (first silicon carbide region) 24 buffer region (9th silicon carbide region) 26 p-pillar region (second silicon carbide region) 26x First Region 26y Second Area 28 n-pillar region (third silicon carbide region) 30 Body region (fourth silicon carbide region) 32 source region (fifth silicon carbide region) 34 Electric field relaxation region (sixth silicon carbide region) 36 Connection region (7th silicon carbide region) 38 Charge diffusion region (8th silicon carbide region) 100 MOSFET (semiconductor device) 150 Inverter circuit 700 Drive Unit 800 vehicles 900 vehicles 1000 elevators F1 First Side F2 Second side C1 1st period C2 Second Period C3 Third Cycle

Claims

1. a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; trenches provided in the silicon carbide layer, extending in the first direction in the first surface and repeatedly provided with a first period in the second direction; a gate electrode disposed in the trench; a gate insulating layer provided between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer; p-type second silicon carbide regions provided in the silicon carbide layer, between the first silicon carbide region and the trench, extending in the second direction in a plane parallel to the first surface, and repeatedly provided with a second period in the first direction; n-type third silicon carbide regions provided in the silicon carbide layer, between the first silicon carbide regions and the trench, extending in the second direction in a plane parallel to the first surface, and repeatedly provided alternately with the second silicon carbide regions at the second period in the first direction; a p-type fourth silicon carbide region provided in the silicon carbide layer, between the second silicon carbide region and the first surface and between the third silicon carbide region and the first surface, and between the trenches; and an n-type fifth silicon carbide region provided in the silicon carbide layer and between the fourth silicon carbide region and the first surface; p-type seventh silicon carbide regions provided in the silicon carbide layer, located between the fourth silicon carbide region and the trench and between the fifth silicon carbide region and the trench, and repeatedly arranged with a third period in the first direction; a first electrode provided on the first surface side of the silicon carbide layer and electrically connected to the fourth silicon carbide region and the fifth silicon carbide region; a second electrode provided on the second surface side of the silicon carbide layer; Equipped with the first surface is inclined at an angle of 0.1 to 8 degrees in the <11-20> direction with respect to the (0001) plane; the first direction is along the <11-20> direction and the second direction is along the <1-100> direction; the seventh silicon carbide region is in contact with the second silicon carbide region.

2. 2. The semiconductor device according to claim 1, wherein said second period is longer than said first period.

3. 2. The semiconductor device according to claim 1, further comprising: a p-type sixth silicon carbide region provided in said silicon carbide layer, between said third silicon carbide region and said trench, in contact with a bottom surface of said trench, and extending in said first direction.

4. 2. The semiconductor device according to claim 1, wherein said second period is longer than said first period, and said third period is longer than said second period.

5. The semiconductor device according to claim 1 , further comprising: an n-type eighth silicon carbide region provided in said silicon carbide layer and between said second silicon carbide region and said fourth silicon carbide region.

6. 2. The semiconductor device according to claim 1, further comprising: an n-type ninth silicon carbide region provided in said silicon carbide layer, between said first silicon carbide region and said second silicon carbide region, in contact with said second silicon carbide region, and having an n-type impurity concentration higher than an n-type impurity concentration of said third silicon carbide region and lower than an n-type impurity concentration of said first silicon carbide region.

7. 2 . The semiconductor device according to claim 1 , wherein a length of said second silicon carbide region in a third direction from said first surface toward said second surface is longer than a width of said second silicon carbide region in said first direction.

8. A silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; trenches provided in the silicon carbide layer, extending in the first direction in the first surface and repeatedly provided with a first period in the second direction; a gate electrode disposed in the trench; a gate insulating layer provided between the gate electrode and the silicon carbide layer; an n-type first silicon carbide region provided in the silicon carbide layer; p-type second silicon carbide regions provided in the silicon carbide layer, between the first silicon carbide region and the trench, extending in the second direction in a plane parallel to the first surface, and repeatedly provided with a second period in the first direction; n-type third silicon carbide regions provided in the silicon carbide layer, between the first silicon carbide regions and the trench, extending in the second direction in a plane parallel to the first surface, and repeatedly provided alternately with the second silicon carbide regions at the second period in the first direction; a p-type fourth silicon carbide region provided in the silicon carbide layer, between the second silicon carbide region and the first surface and between the third silicon carbide region and the first surface, and between the trenches; and an n-type fifth silicon carbide region provided in the silicon carbide layer and between the fourth silicon carbide region and the first surface; a first electrode provided on the first surface side of the silicon carbide layer and electrically connected to the fourth silicon carbide region and the fifth silicon carbide region; a second electrode provided on the second surface side of the silicon carbide layer; Equipped with the first surface is inclined at an angle of 0.1 to 8 degrees in the <11-20> direction with respect to the (0001) plane; the first direction is along the <11-20> direction and the second direction is along the <1-100> direction; the second silicon carbide region includes a first region and a second region provided between the first region and the fourth silicon carbide region, the second region having a p-type impurity concentration higher than a p-type impurity concentration of the first region.

9. The semiconductor device according to claim 1 , wherein a width of said third silicon carbide region in said first direction is larger than a width of said second silicon carbide region in said first direction.

10. 10. An inverter circuit comprising the semiconductor device according to claim 1.

11. A driving device comprising the semiconductor device according to any one of claims 1 to 9.

12. A vehicle comprising the semiconductor device according to any one of claims 1 to 9.

13. An elevator comprising the semiconductor device according to any one of claims 1 to 9.

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