Information processing device and control method for information processing device

Abstract

The present invention provides an information processing device and a method for controlling an information processing device that can increase the number of devices that can be recognized without special software. The information processing device includes a central processing unit and a host bus adapter in which input / output (I / O) devices conforming to the PCI Express standard are connected to a fabric, wherein the host bus adapter is an input / output interface of the PCI Express standard and uses a fabric communication function to communicate with an input / output unit (IOU) including at least one of the I / O devices, and the host bus adapter includes a functional part including a plurality of functions conforming to the PCI Express standard, and a mapping table in which the functions of the functional part and external I / O devices connected to the fabric are mapped in association with each other.

Description

[Technical Field]

[0001] The present invention relates to an information processing apparatus and a control method for the information processing apparatus, and more particularly to an information processing apparatus to which external devices such as network devices and storage devices are connected, and a control method for the information processing apparatus. [Background technology]

[0002] An information processing device is provided with, for example, an HBA (Host Bus Adapter) as an I / O (Input / Output) interface to which external devices such as network devices and storage devices are connected. One example of such an I / O interface is PCI Express (Peripheral Component Interconnect Express) (registered trademark). In this specification, PCI Express may be abbreviated as PCIe. PCIe is a type of expansion bus established by PCI-SIG (PCI Special Interest Group) and is used in computers. PCIe employs a serial transfer interface and a full-duplex communication method.

[0003] In PCIe, connected external devices are identified by three numbers called BDF (Bus, Device, Function). In PCIe, the bus number is defined as 8 bits.

[0004] Patent Document 1 relates to extending a PCIe fabric. Patent Document 1 proposes that a PCIe device has a host PCIe fabric including a host root complex, and that the host PCIe fabric has a first set of bus numbers and a first memory-mapped input / output (MMIO) space on a host CPU. Patent Document 1 also proposes that the PCIe fabric includes a root complex endpoint (RCEP) as part of the endpoints of the host PCIe fabric. Patent Document 1 also proposes that the PCIe fabric has a second set of bus numbers and a second MMIO space that are separate from the first set of bus numbers and the first MMIO space, respectively.

[0005] Patent Document 2 relates to a computer system in which multiple computers and multiple I / O devices are connected via PCIe switches. Patent Document 2 proposes changing the association of PCI-PCI bridge connections in a configuration in which PCIe switches are connected to an I / O controller in multiple stages and I / O devices are connected to the PCIe switches at the ends. Patent Document 2 proposes changing the association of PCI-PCI bridge connections to flexibly assign bus numbers to I / O devices and prevent a decrease in the number of connectable I / O devices.

[0006] Patent Document 3 relates to a communication system that controls an Express Ether network. Patent Document 3 describes that Express Ether is a technology that realizes "PCI Express over Ether." Note that "PCI Express over Ether" is a technology that extends the PCI Express bus onto Ethernet (registered trademark). Patent Document 3 also describes that in Express Ether, TLP (Transaction Layer Packet) defined in the PCI Express specifications is encapsulated and transmitted and received via a network. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2018-125028 [Patent Document 2] International Publication No. 2012 / 073304 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-144142 Summary of the Invention [Problem to be solved by the invention]

[0008] However, in information processing devices that use PCIe as an I / O interface, the PCIe specification defines bus numbers as 8 bits, which poses a problem that only up to 256 devices can be recognized and implemented in one information processing device.

[0009] PCIe defines a technology called SR-IOV (Single Root-I / O Virtualization), which virtually implements multiple functions within a single device. This technology allows a system to recognize a single bus number as if it were multiple devices. However, devices that do not support SR-IOV cannot be made to appear as multiple devices. For this reason, there is a demand for technology that allows a single information processing device to recognize more than 257 devices, even if the devices do not support SR-IOV.

[0010] Patent Documents 2 and 3 do not propose a means for enabling the recognition of a number of devices exceeding the PCIe specifications. Patent Document 2 only proposes preventing bus numbers from being consumed within a PCIe switch, and does not propose a means for enabling a single information processing device to recognize 257 or more devices.

[0011] In Patent Document 1, the PCIe configuration space of the first level PCIe fabric can only be used up to 256 MB. Therefore, special software is required to assign and access the extended PCIe fabric to a space separate from the first level PCIe fabric.

[0012] In view of the above-mentioned problems, an object of the present invention is to provide an information processing device and a control method for an information processing device that can increase the number of recognizable devices without preparing special software. [Means for solving the problem]

[0013] In order to achieve the above object, an information processing apparatus according to the present invention is an information processing apparatus having a central processing unit and a host bus adapter to which an I / O (Input / Output) device conforming to the PCI Express standard is connected to a fabric, The host bus adapter is an input / output interface conforming to the PCI Express standard, and communicates with an IOU (Input / Output Unit) including at least one of the I / O devices via a fabric communication function; The host bus adapter includes a functional unit that includes multiple functions conforming to the PCI Express standard, and a mapping table that associates and maps the functions of the functional unit with external I / O devices connected to the fabric.

[0014] A method for controlling an information processing device according to the present invention includes a central processing unit and a host bus adapter to which an I / O (Input / Output) device conforming to the PCI Express standard is connected via a fabric, the method comprising: The host bus adapter is a PCI Express standard input / output interface. The host bus adapter communicates with an IOU (Input / Output Unit) containing at least one of the I / O devices using the fabric communication function by referring to a mapping table that associates multiple functions conforming to the PCI Express standard with external I / O devices connected to the fabric. [Effects of the Invention]

[0015] According to the present invention, it is possible to provide an information processing apparatus and a method for controlling an information processing apparatus that can increase the number of recognizable devices without preparing special software. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a block diagram illustrating an example of an information processing device according to a higher-level embodiment of the present invention; [Figure 2] 1 is a block diagram illustrating an information processing apparatus according to an embodiment of the present invention; [Figure 3] FIG. 3 is a block diagram for explaining the detailed configuration of the main part of FIG. 2. [Figure 4] FIG. 4 is a conceptual diagram showing an example of a mapping table 22 in FIG. 3. [Figure 5] FIG. 10 is a conceptual diagram illustrating an example of a routing table. [Figure 6A] 1 is a sequence chart illustrating an operation of an information processing device according to an embodiment. [Figure 6B] 1 is a sequence chart illustrating an operation of an information processing device according to an embodiment. [Figure 6C] 1 is a sequence chart illustrating an operation of an information processing device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] (Outline of the embodiment) An information processing device according to an embodiment of the present invention is an information processing system based on technology that enables PCI Express (PCIe), such as Express Ether, to be extended to a fabric. An HBA (Host Bus Adapter) installed in the information processing device terminates PCIe as a multi-function compatible endpoint. An I / O device connected to the end of the fabric is mapped to the multi-function in the HBA. This allows the information processing system to recognize more than 257 I / O devices (PCIe standard).

[0018] [Embodiments of a general concept] Before describing specific embodiments of the present invention, an information processing device and a control method for an information processing device according to a generic embodiment of the present invention will be described. Fig. 1 is a block diagram illustrating an example of an information processing device according to a generic embodiment of the present invention.

[0019] The information processing apparatus in Fig. 1 includes a central processing unit (not shown) and a host bus adapter 100 to which an I / O (Input / Output) device 111 conforming to the PCI Express standard is connected via a fabric. The host bus adapter 100 in the information processing apparatus in Fig. 1 is an input / output interface conforming to the PCI Express standard, and communicates with an IOU (Input / Output Unit) 110 including at least one of the I / O devices 111 via a fabric communication function.

[0020] The host bus adapter 100 includes a functional unit 101 and a mapping table 102 that associates and maps an external I / O device 111. Here, the functional unit 101 includes multiple functions that comply with the PCI Express standard. The external I / O device 111 is connected to the functions of the functional unit 101 and the fabric. The mapping table 102 of the host bus adapter 100 manages the mapping between the functions of the functional unit 101 and the I / O device 111 connected via the fabric communication function.

[0021] In the information processing apparatus of FIG. 1, a mapping table 102 is referred to which associates and maps the function of the functional unit 101 with an external I / O device 111 connected to the fabric. An I / O device connected to the fabric is mapped to a multi-function in the HBA. As a result, the number of recognizable devices can be increased without preparing special software. This enables recognition of 257 or more I / O devices (PCIe standard). Hereinafter, more specific embodiments will be described in detail with reference to the drawings.

[0022] 〔One Embodiment〕 Next, an information processing apparatus and a control method of the information processing apparatus according to an embodiment of the present invention will be described. FIG. 2 is a block diagram for explaining an information processing apparatus according to an embodiment of the present invention. FIG. 3 is a block diagram for explaining a detailed configuration of a main part of FIG. 2. FIG. 4 is a conceptual diagram showing an example of the mapping table 22 of FIG. 3. FIG. 5 is a conceptual diagram showing an example of a routing table.

[0023] (Configuration of the Embodiment) The information processing apparatus of FIG. 2 includes a CPU (Central Processing Unit) 10 and an HBA (Host Bus Adapter) 20. An IOU (Input / Output Unit) 30 is connected to the information processing apparatus of FIG. 2 via a fabric 25. FIG. 2 shows a case where a plurality of IOU are connected, and an example is shown where IOU301, IOU30 k and IOU30 n are connected. Here, as an example, k and n are integers satisfying 1 < k < n. FIG. 2 further shows a case where a plurality of I / O devices are connected, where an I / O device 401 is connected to IOU301, and an I / O device 40 k is connected to IOU30 k , and an I / O device 40 m is connected to IOU30 nThis shows an example of the case when it is connected. Here, as an example, k and m are integers that satisfy 1 < k < 256 < m.

[0024] FIG. 3 shows, as a detailed configuration of the information processing apparatus in FIG. 2, a case including the HBA20 in FIG. 2 and IOU301 and IOU302 as examples of a plurality of IOU30s. The HBA20 in FIG. 3 includes a plurality of function units (Func#0 to Func#255) as an example of a plurality of function units, a mapping table 22, and a fabric communication function unit 23. Regarding the plurality of function units (Func#0 to Func#255), hereinafter, they may be referred to as a plurality of function units 21, or function units 210 to 21 255 or the like. Here, in FIG. 3, a case where the number of function units 21 is a total of 256 from 0 to 255 is shown, but in the embodiment of the present invention, the number of a plurality of function units is not limited to this, and may be more than this.

[0025] The IOU30 connected to the HBA20 in FIG. 3 includes a fabric communication function unit 31, a virtual Root Port 32, and one or more I / O devices 40. In FIG. 3, IOU301 includes a fabric communication function unit 31, a virtual Root Port 32, and an I / O device 40. Also in FIG. 3, IOU302 includes a fabric communication function unit 31, a virtual Root Port 32, and a plurality of I / O devices (I / O device 400 and I / O device 401).

[0026] The plurality of function units 21 of the HBA20 are functions conforming to the PCIe standard and are defined as a multi-function device. For configuration registers and the like other than the part indicating multi-function, those of the I / O device 40 to be mapped are used as they are. Therefore, for configuration registers and the like other than the part indicating multi-function, they are not implemented in the function unit 21. In FIG. 3, the number of function units 21 is set to a total of 256 from 0 to 255, but the number to be implemented is arbitrary.

[0027] The mapping table 22 manages the mapping between the function unit 21 and the I / O device 40. Information managed by the mapping table 22 is shown in FIG. 4. The "Func number" in FIG. 4 represents the number of the function unit 21. The "IOU number" in FIG. 4 represents the number of the IOU 30, which is the number of the IOU 30 on which the I / O device 40 mapped to the function unit 21 is mounted. As shown by IOU 302 in FIG. 3, multiple I / O devices (e.g., I / O device 400 and I / O device 401) may be mounted in one IOU. The "IOU MAC" in FIG. 4 represents the MAC (Media Access Control) address used by the corresponding IOU 30 when communicating via the fabric. This makes it possible to determine to which IOU a packet should be sent via the fabric communication function when the function unit 21 is accessed.

[0028] The fabric communication function units 23, 31 have the function of managing the connection between the HBA 20 and the IOU 30. The fabric communication function of the fabric communication function units 23, 31 includes the function of sharing information between connected devices. This shared information includes which HBA and which IOU are logically connected, and / or the MAC address of the connection destination. Information sharing is performed by periodic packet transmission or a group management function, as with Express Ether. The MAC addresses obtained here are used in the mapping table 22. The information in the mapping table 22 is shared between the HBA 20 and the IOU 30 through the fabric communication function.

[0029] The virtual RootPort 32 of each IOU 30 includes a routing table and has the function of setting virtual bus numbers for the I / O devices 40 under its control as a RootPort. The set bus numbers are managed by the routing table. An example of the routing table is shown in FIG. 5.

[0030] The I / O device 40 (40, 400, or 401) in FIG. 3 is a general I / O device that conforms to the PCIe standard.

[0031] Next, the operation of the information processing system 50 including the information processing device and the IOU will be described. When the information processing system 50 starts up, PCI bus numbers and BAR spaces are generally assigned to the devices that make up the information processing system 50 by PCI enumeration software.

[0032] In the information processing system 50 according to this embodiment, it is assumed that the HBA 20 and the IOU 30 are connected by the fabric communication function before the PCI enumeration software runs. Furthermore, it is assumed that the Func number, IOU number, and IOU MAC have already been registered in the mapping table 22, and the "I / O device number," "virtual bus number," and "assigned Func number" have already been registered in the routing table before the PCI enumeration software runs.

[0033] Next, the PCI enumeration software runs, and a PCI bus number and BAR space are assigned to the device. In the information processing system 50 according to this embodiment, only one PCI bus number is assigned by the system: HBA 20. BAR space is allocated to each function as required by the function. At this time, the PCI enumeration software obtains the BAR size required by the function from the configuration register of the function.

[0034] In the information processing system 50 according to this embodiment, access to the configuration register from the PCI enumeration software is routed to the I / O device using information in the mapping table 22. The BAR size requested by the I / O device is obtained by routing using the information in the mapping table 22. This allows the I / O device 40 to be recognized as a function in the information processing system 50. The obtained BAR space is registered in the mapping table and routing table as a "Mem range" and an "IO range" as shown in FIGS. 4 and 5. Next, the actual access procedure will be explained in order.

[0035] (Access from the CPU to I / O devices) 6A, access from the CPU 10 to the I / O device 40 will be described. For a packet received from the CPU 10 at the HBA 20, the HBA 20 determines the IOU to which it is connected by referencing the mapping table 22 (S11). Furthermore, the HBA 20 transmits this packet to the IOU determined in S11 using the fabric communication function.

[0036] The IOU 30 that receives the packet references the routing table of the virtual root port 32 (S12). The IOU 30 then forwards the received packet to the I / O device 40 based on the results of the reference to the routing table. At this time, if the packet uses ID routing using a bus number, the IOU 30 converts the bus number to a virtual bus number in the routing table and forwards the converted bus number (virtual bus number) to the I / O device. Through these procedures, the CPU 10 can access the I / O device 40.

[0037] (Access from I / O devices to the CPU) 6B, an access from the I / O device 40 to the CPU 10 will be described. The IOU 30 refers to the routing table of the virtual root port 32 for a packet received from the I / O device 40 (S21). If, as a result of referring to the routing table, it is determined that the received packet is destined for the CPU 10, the IOU 30 transmits the packet to the HBA 20 using the fabric communication function.

[0038] The HBA 20 receives a packet via the fabric communication function and transfers the packet to the function unit 21 based on the mapping table 22 .

[0039] The function unit 21 replaces the packet with its own bus number (BDF [Bus, Device, Function] number) and transmits it to the CPU 10. Through these procedures, the I / O device 40 can access the CPU 10.

[0040] (Access from an I / O device to an I / O device) 6C, an explanation will be given of access from an I / O device 401 to another I / O device 402. When a packet arrives from the I / O device 401, the IOU 30 including this I / O device 401 refers to the routing table of the virtual root port 32 (S31).

[0041] If, as a result of referring to the routing table, it is determined that the received packet is destined for the I / O device 402, the IOU 30 determines the IOU 30 to which the target I / O device 402 is connected from the mapping table shared by the HBA 20 (S32). Furthermore, the IOU 30 directly transmits the packet between the IOUs 30 via the fabric communication function.

[0042] An IOU 30 that receives a packet via the fabric communication function references the routing table of its virtual root port 32 and, based on the reference result of the routing table, forwards the received packet to an I / O device 402. At this time, if the packet uses ID routing using a bus number, it is converted to a virtual bus number in the routing table and forwarded to the I / O device. Through these procedures, an I / O device 401 can access another I / O device (I / O device 402).

[0043] (Effects of the embodiment) According to the information processing device of this embodiment, it is possible to connect I / O devices conforming to the PCI Express standard to one information processing system, exceeding the number defined by the PCI Express standard's bus numbers. Specifically, it is possible to connect 257 or more I / O devices conforming to the PCI Express standard to one information processing system. In addition, it is possible to connect 257 or more devices to one information processing system, exceeding the upper limit (256 devices) defined by the PCI Express standard, which defines bus numbers as 8 bits. This makes it possible to build a variety of systems.

[0044] In the information processing system 50 shown in FIGS. 2 and 3, the HBA 20 has a mapping table 22, which is referenced when accessing. The mapping table 22 associates and maps the functions (Func#0 to Func#255) of the multiple function units 21 with the I / O devices 40 connected to the fabric. In other words, the mapping table 22 maps the I / O devices 40 connected to the other end of the fabric to multifunctions within the HBA 20. This makes it possible to increase the number of recognizable devices without providing special software. As a result, the information processing system 50 shown in FIGS. 2 and 3 can recognize 257 or more I / O devices (PCIe standard).

[0045] Other Embodiments Although the preferred embodiment of the present invention has been described above, the present invention is not limited to this. In the detailed configuration of the information processing device of FIG. 3, the function units 21 (210 to 211) of 0 to 255 are 255 2, the number of the function units 21 is not limited to this, and any number of the function units 21 may be implemented. k , …, 30 n ) and the number of I / O devices 40 (401, ..., 40 k , …, 40 m The number of ) is also arbitrary.

[0046] Using the above-described embodiment of the present invention, a maximum of 256 devices can be connected to one bus number. Therefore, more than 60,000 devices can be connected to the system, but the system software may not be able to support such a configuration. In such cases, it may be possible to estimate the upper limit that the system software can support and limit the number of functions to that estimated upper limit. Various modifications are possible within the scope of the invention as defined in the claims, and needless to say, these are also included in the scope of the present invention.

[0047] A part or all of the above-described embodiments can be described as, but not limited to, the following supplementary notes. (Supplementary Note 1) An information processing device having a central processing unit and a host bus adapter to which an I / O (Input / Output) device conforming to the PCI Express standard is connected to a fabric, the host bus adapter is an input / output interface conforming to the PCI Express standard, and communicates with an IOU (Input / Output Unit) including at least one of the I / O devices via a fabric communication function; The host bus adapter includes a functional unit including a plurality of functions conforming to the PCI Express standard, and a mapping table that associates and maps the functions of the functional unit with external I / O devices connected to the fabric. Information processing device. (Supplementary Note 2) An IOU including at least one of the I / O devices includes a virtual root port. 10. The information processing device according to claim 1. (Supplementary Note 3) The virtual root port includes a routing table; The virtual root port forwards the packet received via the fabric communication function to the corresponding I / O device based on the routing table. 3. The information processing device according to claim 2. (Supplementary Note 4) A method for controlling an information processing device having a central processing unit and a host bus adapter to which an I / O (Input / Output) device conforming to the PCI Express standard is connected to a fabric, comprising: the host bus adapter is a PCI Express standard input / output interface, The host bus adapter refers to a mapping table that associates a plurality of functions conforming to the PCI Express standard with external I / O devices connected to the fabric, and communicates with an IOU (Input / Output Unit) including at least one of the I / O devices using a fabric communication function. A method for controlling an information processing device.

[0048] This application claims priority based on Japanese Patent Application No. 2021-204359, filed on December 16, 2021, the disclosure of which is incorporated herein in its entirety. [Explanation of symbols]

[0049] 10 CPU 20 HBA 21, 210~21 255 Function section 22 Mapping Tables 23 Fabric Communication Function Unit 25 Fabric 30, 301~30 k , 30 n IOU 31 Fabric Communication Function Unit 32 Virtual Root Port 40, 401-40 k , 40 n I / O devices 50 Information Processing Systems 100 Host Bus Adapter 101 Functional section 102 Mapping Table 110 IOU 111 I / O Devices

Claims

1. a central processing unit; The PCI Express standard input / output interface has an IOU (Input / Output Unit) including an I / O (Input / Output) device conforming to the PCI Express standard, and a host bus adapter that communicates with the IOU via a fabric communication function; The host bus adapter a functional unit including a plurality of functions conforming to the PCI Express standard; a mapping table that associates and maps the functions of the functional units with external I / O devices connected to the fabric. Information processing device.

2. an IOU including at least one I / O device includes a virtual root port; The information processing device according to claim 1 .

3. The virtual root port includes a routing table; The virtual root port transfers the packet received via the fabric communication function to the corresponding I / O device based on the routing table. The information processing device according to claim 2 .

4. A method for controlling an information processing device having a central processing unit and a host bus adapter, comprising: The host bus adapter It is an input / output interface of PCI Express standard, Refer to a mapping table that associates a plurality of functions conforming to the PCI Express standard with external I / O devices connected to the fabric, It communicates with IOUs (Input / Output Units) including I / O (Input / Output) devices conforming to the PCI Express standard using fabric communication functions. A method for controlling an information processing device.

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