Semiconductor Module

Abstract

To provide a semiconductor device in which a semiconductor element formed of a compound semiconductor and a temperature sensor formed on a silicon (Si) substrate are mounted.SOLUTION: A semiconductor device includes: an insulating circuit board 1; a semiconductor element including a first main electrode bonded to an upper surface of a first conductive layer of the insulating circuit board 1 through a first bonding material, a semiconductor substrate provided on an upper surface of a first main electrode, and a second main electrode provided on an upper surface of the semiconductor substrate; and a resistor element 4 provided on an upper surface of the insulating circuit board 1.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a power semiconductor device (semiconductor module) used as an electrical equipment module, an industrial module, or the like. [Background technology]

[0002] In power semiconductor devices such as inverters that convert DC power to AC power, power semiconductor elements (hereinafter simply referred to as "semiconductor elements"), which are switching elements, are mounted on an insulated circuit board. When the semiconductor elements are made of silicon (Si), an on-chip sensor or a negative temperature coefficient (NTC) thermistor is generally used as a temperature sensor to detect the temperature around the semiconductor element.

[0003] On-chip sensors consist of pn junction diodes formed on semiconductor elements. On-chip sensors detect temperature using the temperature characteristics of the pn junction diodes. NTC thermistors are mounted on an insulated circuit board. NTC thermistors also detect temperature using the temperature characteristics of the materials that make up the NTC thermistor.

[0004] Patent Document 1 discloses that a temperature detector for a switch circuit is formed using a temperature-sensitive resistor element. Patent Document 2 discloses a vertical resistor element having a resistive layer provided on a semiconductor substrate. Patent Document 3 discloses that a common auxiliary source terminal is connected to multiple transistor chips connected in parallel that form a switching element. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-315383 [Patent Document 2] Japanese Patent Application Publication No. 2019-106485 [Patent Document 3] Patent No. 6562173 Summary of the Invention [Problem to be solved by the invention]

[0006] When mounting a semiconductor element made of silicon carbide (SiC) in a power semiconductor device, the application of an on-chip sensor is currently difficult due to cost considerations. Also, when an NTC thermistor is used, there is a problem that the back electrode of the NTC thermistor, which is made of nickel (Ni) and tin (Sn) plating, deteriorates during the process of soldering the semiconductor element to an insulated circuit board by heat treatment in a hydrogen atmosphere.

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor device in which a temperature sensor formed on a silicon (Si) substrate is mounted on an insulating circuit board together with a semiconductor element made of a compound semiconductor. [Means for solving the problem]

[0008] One aspect of the present invention is A semiconductor module comprising: a plurality of terminals each having a temperature detection terminal; a first chip whose semiconductor substrate is formed of a compound semiconductor substrate; and a second chip whose semiconductor substrate is formed of a silicon substrate, wherein the first chip has a transistor and the second chip has a diode, the diode being electrically connected to the temperature detection terminal. The gist of the present invention is as follows. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device in which a temperature sensor formed on a silicon (Si) substrate is mounted on an insulating circuit board together with a semiconductor element made of a compound semiconductor. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the AA direction in FIG. [Figure 3] FIG. 2 is a cross-sectional view seen from the direction BB in FIG. [Figure 4] FIG. 2 is a cross-sectional view seen from the CC direction in FIG. [Figure 5] FIG. 2 is a circuit diagram of a resistance element according to the first embodiment. [Figure 6]1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 7] 3 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] FIG. 4 is a cross-sectional view of a resistance element according to a first modified example of the first embodiment. [Figure 9] FIG. 10 is a cross-sectional view of a resistance element according to a second modified example of the first embodiment. [Figure 10] FIG. 10 is a circuit diagram of a resistance element according to a second modified example of the first embodiment. [Figure 11] FIG. 10 is a cross-sectional view of a resistance element according to a third modified example of the first embodiment. [Figure 12A] FIG. 10 is a circuit diagram of a resistance element according to a third modified example of the first embodiment. [Figure 12B] FIG. 10 is another circuit diagram of the resistance element according to the third modified example of the first embodiment. [Figure 13] FIG. 10 is a plan view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a circuit diagram of a semiconductor device according to a first comparative example of the second embodiment. [Figure 17] FIG. 10 is a circuit diagram of a semiconductor device according to a second comparative example of the second embodiment. [Figure 18] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 19] FIG. 10 is a plan view of a semiconductor device according to a first modified example of the second embodiment. [Figure 20] FIG. 10 is a circuit diagram of a semiconductor device according to a first modified example of the second embodiment. [Figure 21] FIG. 10 is a plan view of a semiconductor device according to a second modification of the second embodiment. [Figure 22] FIG. 10 is a plan view of a semiconductor device according to a third modified example of the second embodiment. [Figure 23] FIG. 10 is a circuit diagram of a semiconductor device according to a third modification of the second embodiment. [Figure 24]FIG. 10 is a circuit diagram of a semiconductor device according to a fourth modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, first and second embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0012] In the following description, the term "first main electrode" refers to either the source electrode or the drain electrode in a field-effect transistor (FET) or a static induction transistor (SIT). It refers to either the emitter electrode or the collector electrode in an insulated gate bipolar transistor (IGBT). It refers to either the anode electrode or the cathode electrode in a static induction thyristor (SI thyristor), a gate turn-off thyristor (GTO), or a diode. Furthermore, the term "second main electrode" refers to either the source electrode or the drain electrode that is not the first main electrode in a FET or SIT. It refers to either the emitter electrode or the collector electrode that is not the first main electrode in an IGBT. It refers to either the anode electrode or the cathode electrode that is not the first main electrode in a SI thyristor, a GTO, or a diode. That is, if the "first main electrode" is the source electrode, the "second main electrode" refers to the drain electrode. If the "first main electrode" is the emitter electrode, the "second main electrode" refers to the collector electrode. If the "first main electrode" is an anode electrode, the "second main electrode" means a cathode electrode.

[0013] In addition, the definitions of directions such as "up," "down," "up and down," "left," "right," and "left and right" in the following description are merely definitions for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right," and of course, if it is rotated 180 degrees and observed, "up and down" is read inverted. Furthermore, "top surface" and "bottom surface" may be read as "front surface" and "back surface," respectively.

[0014] (First embodiment) 1, the semiconductor device according to the first embodiment includes a case member 8, an insulating circuit board 1 arranged inside the case member 8, semiconductor elements (semiconductor chips) 3a to 3h that are switching elements mounted on the insulating circuit board 1, and a resistive element (resistor chip) 4 mounted on the insulating circuit board 1. In FIG. 1, the bonding points of bonding wires 5a to 5v are schematically indicated by black circles.

[0015] In the semiconductor device according to the first embodiment, semiconductor elements 3a to 3d constitute an upper arm for one phase of a three-phase inverter circuit, and semiconductor elements 3e to 3 h The semiconductor device according to the first embodiment is not limited to a 2-in-1 type semiconductor module, and may be, for example, a 1-in-1 type semiconductor module.

[0016] 2 shows a cross-sectional view taken along the line AA passing through the semiconductor elements 3a and 3c in FIG. 1. As shown in FIGS. 1 and 2, the insulating circuit board 1 is made of, for example, a direct copper bonded (DCB) board or an active soldered (AM) board. B The insulating circuit board 1 includes an insulating substrate 10, upper conductor layers (circuit layers) 11a to 11i arranged on the upper surface of the insulating substrate 10, and a lower conductor layer (heat dissipation layer) 12 arranged on the lower surface of the insulating substrate 10.

[0017] The insulating substrate 10 is made of a ceramic substrate made of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), boron nitride (BN), or the like, or a resin insulating substrate made of a polymer material, etc. The upper conductor layers 11a to 11i and the lower conductor layer 12 are made of conductor foil made of, for example, copper (Cu), aluminum (Al), or the like. The planar pattern, arrangement position and number of the upper conductor layers 11a to 11i are not particularly limited.

[0018] A base plate (heat sink) 2 made of metal or the like is disposed on the lower surface of the lower conductor layer 12. A case member 8 made of resin or the like is disposed on the upper surface of the base plate 2 so as to surround the periphery of the insulating circuit board 1. The case member 8 has a stepped portion 81 and a stepped portion 8 1 The side wall portion 8 is disposed outside the 2 Equipped with.

[0019] As shown in FIG. 2, the semiconductor elements 3a to 3h are sealed with a sealing member 9 made of resin or the like. The sealing member 9 is not shown in FIG. 1. As shown in FIG. 1, the semiconductor elements 3a and 3b are mounted on the upper conductor layer 11a of the insulating circuit board 1. The semiconductor elements 3c and 3d are mounted on the upper conductor layer 11e of the insulating circuit board 1. The semiconductor elements 3e and 3f are mounted on the upper conductor layer 11a of the insulating circuit board 1. b The semiconductor elements 3g and 3h are mounted on the upper conductor layer 11b of the insulating circuit board 1.

[0020] The semiconductor elements 3a to 3h may be, for example, field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), static induction (SI) thyristors, or gate turn-off (GTO) thyristors. In the following, a case where the semiconductor elements 3a to 3h are MOSFETs will be described. The arrangement positions and number of the semiconductor elements 3a to 3h are not particularly limited.

[0021] FIG. 3 shows a cross-sectional view taken along the line BB passing through the semiconductor element 3a in FIG. 1. The base plate 2 and the sealing member 9 are not shown in FIG. 3. As shown in FIG. 3, the semiconductor element 3a is bonded to the upper conductor layer 11a of the insulating circuit board 1 via a bonding material 2a. The bonding material 2a is made of, for example, solder or a sintered material. Examples of solder that can be used include tin-antimony (SnSb)-based and tin-silver (SnAg)-based solders. Examples of sintered materials that can be used include silver (Ag)-based and copper (Cu)-based metal particle pastes (conductive pastes).

[0022] The semiconductor element 3a has a semiconductor substrate 30, a first main electrode (drain electrode) 31 provided on the lower surface of the semiconductor substrate 30, and a second main electrode (source electrode) 32 and a control electrode (gate electrode) 33 provided on the upper surface of the semiconductor substrate 30. The semiconductor substrate 30 is made of a compound semiconductor substrate made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). The semiconductor substrate 30 may also be made of a silicon (Si) substrate.

[0023] The drain electrode 31 has a three-layer structure including a first electrode layer 31a bonded to the upper surface of the bonding material 2a, a second electrode layer 31b provided in contact with the upper surface of the first electrode layer 31a, and a third electrode layer 31c provided in contact with the upper surface of the second electrode layer 31b and in contact with the lower surface of the semiconductor substrate 30.

[0024] The first electrode layer 31a and the second electrode layer 31b constitute a bonding layer. The first electrode layer 31a is made of, for example, gold (Au). The second electrode layer 31b is made of, for example, nickel (Ni). The second electrode layer 31b may be an alloy (Ni-p) layer mainly composed of Ni. The third electrode layer 31c constitutes a barrier layer. The third electrode layer 31c is made of, for example, titanium (Ti). The third electrode layer 31c may have a laminated structure of Ti and titanium nitride (TiN).

[0025] Like the semiconductor element 3a shown in FIG. 3, the semiconductor elements 3b to 3h shown in FIG. 1 are joined to the insulating circuit board 1 by a joining material such as solder, and have the same configuration as the semiconductor element 3a shown in FIG.

[0026] The resistive element 4 shown in FIG. 1 is used as a temperature sensor that detects the temperature around the semiconductor elements 3a to 3h. The resistive element 4 has, for example, a rectangular planar pattern. FIG. 4 shows a cross-sectional view taken along the CC direction, which is a line segment passing through the resistive element 4 in FIG. 1. In FIG. 4, the base plate 2 and the sealing member 9 are not shown. As shown in FIG. 4, the resistive element 4 includes a low-resistivity semiconductor substrate 41, a first insulating film 42 disposed on the semiconductor substrate 41, and thin-film resistive layers 43a and 43b disposed on the first insulating film 42.

[0027] A low resistivity substrate such as a silicon substrate doped with a high concentration of n-type or p-type impurities can be used as the semiconductor substrate 41. The resistance component of the semiconductor substrate 41 is preferably small enough to be negligible compared to the resistance components of the resistive layers 43a and 43b. In other words, the resistance component of the semiconductor substrate 41 is preferably about 1 / 100 or less of the resistance components of the resistive layers 43a and 43b. The resistivity of the semiconductor substrate 41 may be, for example, about 2 mΩ·cm to 60 mΩ·cm.

[0028] A silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film of these can be used as the first insulating film 42. The first insulating film 42 may also be an insulating film (TEOS film) formed by a chemical vapor deposition (CVD) method or the like using tetraethoxysilane (TEOS) gas, an organosilicon compound.

[0029] The sheet resistance of the resistive layers 43a and 43b is, for example, about 150 Ω / □. The resistance values ​​of the resistive layers 43a and 43b can be controlled by adjusting the width (depth direction in FIG. 4) and length (left and right direction in FIG. 4) of the resistive layers 43a and 43b.

[0030] For example, n-type or p-type doped polysilicon can be used as the resistance layers 43a and 43b. N-type doped polysilicon can be formed by ion implanting n-type impurities such as phosphorus (P) into polycrystalline silicon (polysilicon) or by adding polycrystalline silicon during deposition using a CVD apparatus. P-type doped polysilicon can also be formed by ion implanting p-type impurities such as boron (B) into polysilicon.

[0031] The resistive layers 43a and 43b are not limited to doped polysilicon, but may be made of tantalum nitride (TaN x ) and chromium (Cr)-nickel (Ni)-manganese (Mn The resistive layers 43a and 43b may be a laminated film of high melting point metal films laminated in this order. The resistive layers 43a and 43b may be made of thin films of silver palladium (AgPd), ruthenium oxide (RuO2), or the like.

[0032] The resistive layers 43a and 43b have a positive or negative temperature coefficient. The temperature coefficient of the doped polysilicon constituting the resistive layers 43a and 43b can be controlled by adjusting the dose when impurities are ion-implanted into the polysilicon. The resistive element 4 may have only one of the resistive layers 43a and 43b, or may have three or more resistive layers.

[0033] A second insulating film (interlayer insulating film) 44 is disposed to cover the first insulating film 42 and the resistive layers 43a and 43b. The second insulating film 44 may be a single layer of a silicon oxide film (SiO2 film) that does not contain phosphorus (P) or boron (B), commonly referred to as an "NSG film," a silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), a silicon oxide film doped with phosphorus and boron (BPSG film), or a silicon nitride film (Si3N4 film), or a composite film made by selecting and combining two or more of these. For example, the second insulating film 44 may be a composite film made by stacking an NSG film and a PSG film.

[0034] An upper surface electrode 45a, relay wirings 45b and 45c, and a guard ring layer 45d are disposed on the second insulating film 44. The upper surface electrode 45a, relay wirings 45b and 45c, and guard ring layer 45d are made of, for example, titanium (Ti) / titanium nitride (TiN) as a barrier metal, aluminum The substrate can be made of a laminated film of aluminum (Al)-silicon (Si), and a TiN / Ti anti-reflection film. Instead of Al-Si, Al or an Al alloy such as Al-Cu-Si or Al-Cu may be used.

[0035] One end of the upper electrode 45a is connected to one end of the resistive layer 43a via a contact region 46a. One end of the relay wiring 45b is connected to the other end of the resistive layer 43a via a contact region 46c. The other end of the relay wiring 45b is ohmically connected to the semiconductor substrate 41 with low contact resistance via a contact region 46e.

[0036] The other end of the upper electrode 45a is connected to one end of the resistive layer 43b via a contact region 46b. One end of the relay wiring 45c is connected to the other end of the resistive layer 43b via a contact region 46d. The other end of the relay wiring 45c is ohmically connected to the semiconductor substrate 41 with low contact resistance via a contact region 46f.

[0037] The guard ring layer 45d is connected to the semiconductor substrate 41 via contact regions 46g and 46h. The guard ring layer 45d has the function of preventing moisture from entering from the side surface of the chip.

[0038] A protective film (passivation film) 47 is disposed on the upper electrode 45a, the relay wirings 45b and 45c, and the guard ring layer 45d. The protective film 47 may be formed of a composite film in which, for example, a TEOS film, a Si3N4 film, and a polyimide film are laminated in this order. An opening 47a is provided in the protective film 47. The portion of the upper electrode 45a exposed through the opening 47a serves as an electrode pad.

[0039] A lower electrode 49 is disposed on the lower surface of the semiconductor substrate 41. The lower electrode 49 has a four-layer structure including a first electrode layer 49a bonded to the upper surface of a bonding material 2b such as solder, a second electrode layer 49b provided in contact with the upper surface of the first electrode layer 49a, a third electrode layer 49c provided in contact with the upper surface of the second electrode layer 49b, and a fourth electrode layer 49d provided in contact with the upper surface of the third electrode layer 49c and in contact with the lower surface of the semiconductor substrate 41.

[0040] The first electrode layer 49a and the second electrode layer 49b constitute a bonding layer. The first electrode layer 49a is made of, for example, gold (Au). The second electrode layer 49b is made of, for example, nickel (Ni) or an alloy (Ni-p) mainly composed of Ni. The third electrode layer 49c constitutes a barrier layer. The third electrode layer 49c is made of, for example, titanium (Ti). The third electrode layer 49c may have a layered structure of Ti and titanium nitride (TiN). The fourth electrode layer 49d is made of aluminum (Al)-silicon (Si).

[0041] The junction layer (49a, 49b) consisting of the first electrode layer 49a and the second electrode layer 49b of the lower electrode 49 of the resistor element 4 shown in Fig. 4 has the same structure and is made of the same material as the junction layer (31a, 31b) consisting of the first electrode layer 31a and the second electrode layer 31b of the drain electrode 31 of the semiconductor element 3a shown in Fig. 3. In addition, the barrier layer consisting of the third electrode layer 49c of the lower electrode 49 of the resistor element 4 shown in Fig. 4 may have the same structure and be made of the same material as the barrier layer consisting of the third electrode layer 31c of the drain electrode 31 of the semiconductor element 3a shown in Fig. 3.

[0042] The first electrode layer 49a, the second electrode layer 49b, and the third electrode layer 49c of the lower electrode 49 of the resistor element 4 shown in FIG. 4 may have the same thickness as or different thickness from the first electrode layer 31a, the second electrode layer 31b, and the third electrode layer 31c of the drain electrode 31 of the semiconductor element 3a shown in FIG. 3, respectively.

[0043] An equivalent circuit of the resistive element 4 shown in FIG. 4 is shown in FIG. 5. As shown in FIG. 5, one end of each of resistors R11 and R12 is connected in parallel to terminal T11. One end of resistor R13 is connected to the other end of each of resistors R11 and R12. Terminal T12 is connected to the other end of resistor R13. Resistors R11, R12, and R13 in FIG. 5 correspond to resistive layer 43a, resistive layer 43b, and semiconductor substrate 41 in FIG. 4, respectively. Terminals T11 and T12 in FIG. 5 correspond to upper surface electrode 45a and lower surface electrode 49 in FIG. 4, respectively.

[0044] 1, one ends of the auxiliary positive terminal (voltage detection terminal) 7a, the temperature detection terminals 7b and 7c, the control terminals 7d and 7f, and the auxiliary source terminals (voltage detection terminals) 7e and 7g are provided on a stepped portion 81 of the case member 8. The auxiliary positive terminal 7a, the temperature detection terminals 7b and 7c, the control terminals 7d and 7f, and the auxiliary source terminals 7e and 7g extend into a side wall portion 82 of the case member 8. The other ends of the auxiliary positive terminal 7a, the temperature detection terminals 7b and 7c, the control terminals 7d and 7f, and the auxiliary source terminals 7e and 7g protrude from the upper surface of the side wall portion 82.

[0045] The auxiliary positive terminal 7a is connected to the upper conductor layer 11e via a bonding wire 5t. The auxiliary positive terminal 7a detects the voltage of the drain electrodes of the semiconductor elements 3c and 3d.

[0046] The temperature detection terminal 7b is connected via a bonding wire 5u to an electrode pad formed by the upper electrode 45a of the resistive element 4. The temperature detection terminal 7c is connected via a bonding wire 5v to the upper conductor layer 11d on which the resistive element 4 is mounted. A current application circuit (not shown) that applies a constant DC current to both ends of the resistive element 4 is connected to the temperature detection terminals 7b and 7c. The ambient temperatures of the semiconductor elements 3a to 3h are detected based on the temperature detection signals obtained via the temperature detection terminals 7b and 7c.

[0047] The control terminal 7d is connected to the upper conductor layer 11f via a bonding wire 5f. The upper conductor layer 11f is electrically connected to the gate electrodes of the semiconductor elements 3a to 3d via bonding wires 5g to 5j. A control signal is applied to the gate electrodes of the semiconductor elements 3a to 3d via the control terminal 7d.

[0048] The auxiliary source terminal 7e is connected to the upper conductor layer 11g via a bonding wire 5a. The upper conductor layer 11g is connected to the source electrodes of the semiconductor elements 3a to 3d via bonding wires 5b to 5e. The auxiliary source terminal 7e detects the current flowing through the source electrodes of the semiconductor elements 3a to 3d.

[0049] The control terminal 7f is electrically connected to the gate electrodes of the semiconductor elements 3e to 3h via bonding wires 5p to 5s. The auxiliary source terminal 7g is connected to the upper conductor layer 11i via a bonding wire 5k. The upper conductor layer 11i is connected to the source electrodes of the semiconductor elements 3e to 3h via bonding wires 5l to 5o.

[0050] Furthermore, the case member 8 is provided with a positive terminal 8a, a negative terminal 8b, and an output terminal 8c. The positive terminal 8a is connected to upper conductor layers 11a and 11e. The negative terminal 8b is connected to upper conductor layer 11h. The upper conductor layer 11h is electrically connected to the source electrodes of the semiconductor elements 3e to 3h via wirings 6e to 6h. The output terminal 8c is connected to upper conductor layer 11b. The upper conductor layer 11b is electrically connected to the source electrodes of the semiconductor elements 3a to 3d via wirings 6a to 6d.

[0051] Fig. 6 shows an equivalent circuit of the upper arm side formed by the semiconductor elements 3a to 3d shown in Fig. 1. Transistors T1 to T4 in Fig. 6 correspond to the semiconductor elements 3a to 3d, respectively, in Fig. 1. Freewheeling diodes (FWD) D1 to D4 are connected in anti-parallel to the transistors T1 to T4. The freewheeling diodes D1 to D4 may be built into the semiconductor elements 3a to 3d of FIG.

[0052] The drain electrodes of the transistors T1 to T4 are connected to the positive terminal P. The source electrodes of the transistors T1 to T4 are connected to the output terminal OUT via parasitic inductances L1 to L4. The source electrodes of the transistors T1 to T4 are connected to the auxiliary source terminal S. The gate electrodes of the transistors T1 to T4 are connected to the control terminal G. The positive terminal P, output terminal OUT, control terminal G, and auxiliary source terminal S in FIG. 6 correspond to the positive terminal 8a, output terminal 8c, control terminal 7d, and auxiliary source terminal 7e shown in FIG. 1, respectively.

[0053] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the flowchart in Fig. 7. In step S1, an insulating circuit board 1 made of a DCB substrate or the like is prepared. In step S2, a bonding material such as solder is mounted on the insulating circuit board 1. Furthermore, semiconductor elements 3a-3h and resistor element 4 are mounted on the insulating circuit board 1 via the bonding material. In step S3, the insulating circuit board 1 is bonded to the semiconductor elements 3a-3h and resistor element 4 with the bonding material by heat treatment in a hydrogen atmosphere. In step S4, an X-ray inspection is performed to determine whether the insulating circuit board 1 on which the semiconductor elements 3a-3h and resistor element 4 are mounted is pass or fail. Thereafter, the semiconductor elements 3a-3h and resistor element 4 are mounted in a case member 8, and the semiconductor elements 3a-3h and resistor element 4 are sealed with a sealing member 9.

[0054] According to the semiconductor device of the first embodiment, the resistive element 4 is mounted on the insulating circuit board 1 and used as a temperature sensor, thereby making it possible to detect the temperature around the semiconductor elements 3a to 3h.

[0055] Furthermore, when an NTC thermistor is used as a temperature sensor in a conventional semiconductor device, there is a problem in that the Ni plating or Sn plating of the lower electrode of the NTC thermistor deteriorates during the soldering process in a hydrogen atmosphere in step S3 of Fig. 7. In contrast, in the semiconductor device according to the first embodiment, at least the bonding layers (49a, 49b) of the lower electrode 49 of the resistor element 4 have the same structure as the bonding layers (31a, 31b) of the drain electrode 31 of the semiconductor element 3a, and no Ni plating or Sn plating is used. This makes it possible to prevent deterioration of the lower electrode 49 of the resistor element 4 even during the soldering process in a hydrogen atmosphere in step S3 of Fig. 7.

[0056] (First Modification of the First Embodiment) As shown in FIG. 8, the resistance element 4 according to the first modification of the first embodiment differs from the resistance element 4 according to the first embodiment shown in FIG. 4 in that the semiconductor substrate 41 is not a silicon (Si) substrate but a compound semiconductor substrate such as silicon carbide (SiC), and the lower electrode 49 has a three-layer structure.

[0057] The lower electrode 49 of the resistor element 4 shown in Figure 8 includes a first electrode layer 49a bonded to the upper surface of the bonding material 2b, a second electrode layer 49b provided in contact with the upper surface of the first electrode layer 49a, and a third electrode layer 49c provided in contact with the upper surface of the second electrode layer 49b and in contact with the lower surface of the semiconductor substrate 41.

[0058] The first electrode layer 49a and the second electrode layer 49b constitute a bonding layer. The first electrode layer 49a is made of, for example, gold (Au). The second electrode layer 49b is made of, for example, nickel (Ni) or an alloy (Ni-p) mainly composed of Ni. The third electrode layer 49c constitutes a barrier layer. The third electrode layer 49c is made of, for example, titanium (Ti). The third electrode layer 49c may have a laminated structure of Ti and titanium nitride (TiN).

[0059] The lower electrode 49 of the resistor element 4 shown in Fig. 8 has the same structure as the drain electrode 31 of the semiconductor element 3a shown in Fig. 4. That is, the junction layer (49a, 49b) formed by the first electrode layer 49a and the second electrode layer 49b of the lower electrode 49 of the resistor element 4 shown in Fig. 8 has the same structure as the junction layer (31a, 31b) formed by the first electrode layer 31a and the second electrode layer 31b of the drain electrode 31 of the semiconductor element 3a shown in Fig. 4. Furthermore, the barrier layer formed by the third electrode layer 49c of the lower electrode 49 of the resistor element 4 shown in Fig. 8 has the same structure as the barrier layer formed by the third electrode layer 31c of the drain electrode 31 of the semiconductor element 3a shown in Fig. 4.

[0060] According to the first variant of the first embodiment, even when the resistive element 4 shown in FIG. 8 is used, deterioration of the lower electrode 49 of the resistive element 4 can be prevented in the soldering process in a hydrogen atmosphere in step S3 of FIG. 7.

[0061] (Second Modification of the First Embodiment) 9, the resistance element 4 according to the second modification of the first embodiment differs from the resistance element 4 according to the first embodiment shown in Fig. 4 in that it has two upper surface electrodes 45e and 45f. The exposed portions of the upper surface electrodes 45e and 45f from the openings 47a and 47b of the protective film 47 serve as electrode pads, respectively.

[0062] The upper surface electrodes 45e and 45f are provided to sandwich the relay wiring 45g. One end of the upper surface electrode 45e is connected to one end of the resistive layer 43a via a contact region 46a. One end of the relay wiring 45g is connected to the other end of the resistive layer 43a via a contact region 46b. One end of the upper surface electrode 45f is connected to one end of the resistive layer 43b via a contact region 46c. The other end of the resistive layer 43b is connected to the other end of the relay wiring 45g via a contact region 46d. A central portion of the relay wiring 45g is ohmically connected to the semiconductor substrate 41 with low contact resistance via the contact region 46e.

[0063] FIG. 10 shows an equivalent circuit of the resistive element 4 shown in FIG. 9. As shown in FIG. 10, the resistive element 4 has three terminals T11, T12, and T13. One end of a resistor R11 is connected to the terminal T11. One end of a resistor R12 is connected to the terminal T13. One end of a resistor R13 is connected to the other end of each of the resistors R11 and R12. The other end of the resistor R13 is connected to the terminal T12. The resistors R11, R12, and R13 in FIG. 10 correspond to the resistive layer 43a, the resistive layer 43b, and the semiconductor substrate 41 in FIG. 9, respectively. The terminals T11, T13, and T12 in FIG. 10 correspond to the upper surface electrodes 45e, 45f, and the lower surface electrode 49 in FIG. 9, respectively.

[0064] When the resistive layer 43a of the resistive element 4 shown in Fig. 9 is used as a temperature sensor, the electrode pad formed by the upper surface electrode 45e may be connected by a bonding wire to the temperature detection terminal 7b shown in Fig. 1. Alternatively, when the resistive layer 43b of the resistive element 4 shown in Fig. 9 is used as a temperature sensor, the electrode pad formed by the upper surface electrode 45f may be connected by a bonding wire to the temperature detection terminal 7b shown in Fig. 1.

[0065] 9 are used as temperature sensors, two electrode pads formed by the upper surface electrodes 45e and 45f may be connected to a common temperature detection terminal 7b by bonding wires. Alternatively, when the resistive layers 43a and 43b of the resistive element 4 shown in Fig. 9 are used individually as temperature sensors, another temperature detection terminal similar to the temperature detection terminal 7b shown in Fig. 1 may be provided, and one of the two electrode pads formed by the upper surface electrodes 45e and 45f may be connected to the temperature detection terminal 7b, and the other electrode pad may be connected to the other temperature detection terminal.

[0066] According to the second modification of the first embodiment, even when the resistance element 4 shown in FIG. In the soldering process in a hydrogen atmosphere in step S3 of 7, deterioration of the lower electrode 49 of the resistor element 4 can be prevented.

[0067] (Third Modification of the First Embodiment) As shown in FIG. 11, the resistance element 4 according to the third modification of the first embodiment differs from the resistance element 4 according to the second modification of the first embodiment shown in FIG. 9 in that it has pn junction diodes (43c, 43d) instead of the resistance layer 43b. The pn junction diodes (43c, 43d) are composed of an n-type semiconductor layer 43c disposed on the first insulating film 42 and a p-type semiconductor layer 43d disposed on the first insulating film 42 and in contact with the n-type semiconductor layer 43c. The n-type semiconductor layer 43c is connected to a relay wiring 45g via a contact region 46d. The p-type semiconductor layer 43d is connected to an upper surface electrode 45f via a contact region 46c.

[0068] 12A shows an equivalent circuit of the resistance element 4 shown in FIG. 11. As shown in FIG. 12A, one end of a resistor R11 is connected to a terminal T11. An anode of a diode D11 is connected to a terminal T13. One end of a resistor R13 is connected to the other end of the resistor R11 and the cathode of the diode D11. The other end of the resistor R13 is connected to a terminal T12. The resistor R11, diode D11, and resistor R13 in FIG. 12A correspond to the resistance layer 43a, pn junction diodes (43c, 43d), and semiconductor substrate 41 in FIG. 11, respectively. The terminals T11, T13, and terminal T12 in FIG. 12A correspond to the upper surface electrodes 45e, 45f and the lower surface electrode 49 in FIG. 11, respectively.

[0069] When the resistive layer 43a of the resistive element 4 shown in Fig. 11 is used as a temperature sensor, the electrode pad formed by the upper surface electrode 45e may be connected to the temperature detection terminal 7b shown in Fig. 1. Alternatively, when the pn junction diode (43c, 43d) of the resistive element 4 shown in Fig. 11 is used as a temperature sensor, the electrode pad formed by the upper surface electrode 45f may be connected to the temperature detection terminal 7b shown in Fig. 1.

[0070] Alternatively, when both the resistive layer 43a and the pn junction diodes (43c, 43d) of the resistive element 4 shown in Fig. 11 are used as temperature sensors, two electrode pads formed by the upper surface electrodes 45e, 45f may be connected to a common temperature detection terminal 7b. Alternatively, when the resistive layer 43a and the pn junction diodes (43c, 43d) of the resistive element 4 shown in Fig. 11 are used individually as temperature sensors, another temperature detection terminal similar to the temperature detection terminal 7b shown in Fig. 1 may be provided, and one of the two electrode pads formed by the upper surface electrodes 45e, 45f may be connected to the temperature detection terminal 7b, and the other electrode pad may be connected to the other temperature detection terminal.

[0071] According to the third variant of the first embodiment, even when the resistive element 4 shown in FIG. 11 is used, deterioration of the upper electrodes 45e, 45f and the lower electrode 49 of the resistive element 4 can be prevented in the soldering process in a hydrogen atmosphere in step S3 of FIG. 7.

[0072] 11 and 12A, the anode and cathode of the pn junction diode may be interchanged. That is, the n-type semiconductor layer 43c constituting the pn junction diode (43c, 43d) shown in FIG. 11 may be p-type, and the p-type semiconductor layer 43d may be n-type. An equivalent circuit of the resistance element 4 in this case is shown in FIG. 12B. As shown in FIG. 12B, the cathode of the diode D11 is connected to the terminal T13, and the anode of the diode D11 is connected to one end of the resistors R11 and R13.

[0073] (Fourth Modification of the First Embodiment) As shown in FIG. 13, the semiconductor device according to the fourth modification of the first embodiment has a temperature sensor. 1 in that the resistor element 4 used in the semiconductor device is mounted on the upper surface of the upper conductor layer 11g, which is a relay point that electrically connects the auxiliary source terminal 7e to the source electrodes of the semiconductor elements 3a to 3d.

[0074] The resistor element 4 has a structure similar to that of the resistor element 4 shown in FIG. 4. As shown in FIG. 13, an electrode pad formed by an upper electrode of the resistor element 4 is connected to the temperature detection terminal 7b via a bonding wire 5u. The lower electrode of the resistor element 4 is bonded to the upper surface of the upper conductor layer 11g via a bonding material such as solder. The lower electrode of the resistor element 4 is electrically connected to the auxiliary source terminal 7e via the upper conductor layer 11g and the bonding wire 5a.

[0075] According to the semiconductor device of the fourth modification of the first embodiment, by mounting the resistor element 4 on the upper conductor layer 11g to which the source electrodes of the semiconductor elements 3a to 3d are joined, the terminal to which the lower electrode of the resistor element 4 is connected can be made common to the auxiliary source terminal 7e. Therefore, compared to the semiconductor device of the first embodiment shown in FIG. 1, the temperature detection terminal 7c electrically connected to the lower electrode of the resistor element 4 is not necessary, and the number of terminals can be reduced by one.

[0076] (Second embodiment) As shown in FIG. 14, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 1 in that multiple (eight) resistive elements 4a to 4h are mounted on an insulating circuit board 1, and each of the multiple resistive elements 4a to 4h is used as a resistor (source resistor) connected to the source electrode of each of the semiconductor elements 3a to 3h.

[0077] Each of the resistance elements 4a to 4h has the same structure as the resistance element 4 shown in Fig. 4. In the semiconductor device according to the second embodiment, the resistance elements 4a to 4h function as source resistors, and therefore preferably have no temperature characteristics and maintain a substantially constant resistance value regardless of temperature changes.

[0078] 14, the resistor elements 4a to 4d are mounted on an upper conductor layer 11g. The lower electrodes of the resistor elements 4a to 4d are bonded to the upper surface of the upper conductor layer 11g via a bonding material such as solder. The upper electrodes of the resistor elements 4a to 4d are connected to the source electrodes on the upper surfaces of the semiconductor elements 3a to 3d via bonding wires 5b to 5e.

[0079] Resistor element 4e~4 h are mounted on the upper conductor layer 11i. The lower electrodes of the resistor elements 4e to 4f are bonded to the upper surface of the upper conductor layer 11i via a bonding material such as solder. The upper electrodes of the resistor elements 4e to 4f are connected to the source electrodes on the upper surfaces of the semiconductor elements 3e to 3h via bonding wires 5l to 5o. The other configuration of the semiconductor device according to the second embodiment is the same as that of the semiconductor device according to the first embodiment shown in FIG. 1, so a duplicated description will be omitted.

[0080] FIG. 15 shows an equivalent circuit of the upper arm side formed by the semiconductor elements 3a to 3d shown in FIG. 14. As shown in FIG. 15, this is different from the equivalent circuit of the semiconductor device according to the first embodiment shown in FIG. 6 in that resistors (source resistors) R1 to R4 are connected between the source electrodes of the transistors T1 to T4 and the auxiliary source terminal S. The resistance values ​​of the source resistors R1 to R4 are, for example, about 1 Ω, but are not limited to this. The resistors R1 to R4 shown in FIG. 15 correspond to the resistive elements 4a to 4d shown in FIG. 14.

[0081] Here, as shown in FIG. 16, we will focus on the semiconductor elements 3a and 3b, and consider a case where there are no resistors R1 and R2 between the source electrodes of the semiconductor elements 3a and 3b and the auxiliary source terminal S. As the semiconductor elements 3a and 3b switch, the di / dt of the main circuit increases. The difference in gate threshold voltage between the semiconductor elements 3a and 3b, etc. b If turns on first, a back electromotive force is generated in the parasitic inductance L2 of the main circuit due to the di / dt of the main circuit. In this case, an excessive loop current I1 (schematically shown by the arrow) flows between the auxiliary sources of the semiconductor elements 3a and 3b, which may cause the bonding wire to break.

[0082] Next, as shown in Figure 17, similar to Figure 16, there are no resistors R1 and R2 between the source electrodes of semiconductor elements 3a and 3b and auxiliary source terminal S, but consider the case where gate resistors R5 and R6 are connected to the gate electrodes of semiconductor elements 3a and 3b. If semiconductor element 3a turns on first, gate resistor R6 suppresses the di / dt of the main circuit, making it possible to suppress the back electromotive force of parasitic inductance L2. However, because there is no resistance between the auxiliary sources of semiconductor elements 3a and 3b, a loop current I1 is generated between the auxiliary sources of semiconductor elements 3a and 3b.

[0083] In contrast, in the semiconductor device according to the second embodiment, as shown in FIG. 18, source resistors R1 and R2 are connected between the source electrodes of semiconductor elements 3a and 3b and auxiliary source terminal S. When semiconductor element 3a is turned on first, the source resistors R1 and R2 suppress the di / dt of the main circuit, thereby suppressing the back electromotive force of parasitic inductance L2. Furthermore, the loop current I1 between the auxiliary sources of semiconductor elements 3a and 3b can be suppressed, thereby preventing disconnection of bonding wires.

[0084] (First modified example of the second embodiment) 19, the semiconductor device according to the first modification of the second embodiment differs from the semiconductor device according to the second embodiment shown in Fig. 14 in that it does not have two resistance elements 4a and 4e, but has six resistance elements 4b to 4d and 4f to 4g. The configurations and positions of the resistance elements 4b to 4d and 4f to 4g are the same as those of the semiconductor device according to the second embodiment shown in Fig. 14.

[0085] Fig. 20 shows an equivalent circuit of the upper arm side formed by the semiconductor elements 3a to 3d shown in Fig. 19. As shown in Fig. 20, the equivalent circuit differs from the equivalent circuit of the semiconductor device according to the second embodiment shown in Fig. 15 in that a resistor (source resistor) R1 is not connected between the source electrode of the transistor T1 and the auxiliary source terminal S.

[0086] According to the semiconductor device of the first modification of the second embodiment, the source resistance R2 ~R 4 This suppresses the di / dt of the main circuit, thereby suppressing the back electromotive force of the parasitic inductances L2 to L4, and also suppresses the loop current between the auxiliary sources of the semiconductor elements 3a to 3d and semiconductor elements 3e to 3h, thereby preventing the bonding wires from breaking.

[0087] (Second Modification of the Second Embodiment) As shown in FIG. 21, the semiconductor device according to the second modification of the second embodiment includes two resistor elements 4a and 4b corresponding to the semiconductor elements 3a to 3d, and semiconductor elements 3e to 3f. h 14 in that it includes two resistance elements 4e and 4f corresponding to the first and second resistance elements 4a and 4b.

[0088] Each of the resistance elements 4a, 4b, 4e, and 4f has the same structure as the resistance element 4 having two electrode pads formed by two upper surface electrodes 45e and 45f shown in FIG.

[0089] 21, the resistor elements 4a and 4b are mounted on an upper conductor layer 11g. The lower electrodes of the resistor elements 4a and 4b are bonded to the upper surface of the upper conductor layer 11g via a bonding material such as solder. One electrode pad composed of the two upper electrodes of the resistor element 4a is connected to the source electrode on the upper surface of the semiconductor element 3a via a bonding wire 5b. The other electrode pad of resistor element 4a is connected to the source electrode on the upper surface of semiconductor element 3c via bonding wire 5i. One electrode pad consisting of two upper surface electrodes of resistor element 4b is connected to the source electrode on the upper surface of semiconductor element 3b via bonding wire 5c. The other electrode pad of resistor element 4b is connected to the source electrode on the upper surface of semiconductor element 3d via bonding wire 5e.

[0090] The resistor elements 4e and 4f are mounted on the upper conductor layer 11i. The lower electrodes of the resistor elements 4e and 4f are bonded to the upper surface of the upper conductor layer 11i via a bonding material such as solder. One electrode pad consisting of the two upper electrodes of the resistor element 4e is connected to the source electrode on the upper surface of the semiconductor element 3e via a bonding wire 5l. The other electrode pad of the resistor element 4e is connected to the source electrode on the upper surface of the semiconductor element 3g via a bonding wire 5n. One electrode pad consisting of the two upper electrodes of the resistor element 4f is connected to the source electrode on the upper surface of the semiconductor element 3f via a bonding wire 5m. The other electrode pad of the resistor element 4f is connected to the source electrode on the upper surface of the semiconductor element 3h via a bonding wire 5o.

[0091] According to the semiconductor device of the second variant of the second embodiment, each of the resistive elements 4a, 4b, 4e, and 4f has two electrode pads each consisting of two upper surface electrodes, and therefore the number of resistive elements 4a, 4b, 4e, and 4f can be reduced compared to the semiconductor device of the second embodiment.

[0092] (Third modified example of the second embodiment) As shown in Fig. 22, the semiconductor device according to the third modification of the second embodiment is similar to the semiconductor device according to the second embodiment shown in Fig. 14 in that it includes eight resistance elements 4a to 4h. However, it differs from the semiconductor device according to the second embodiment shown in Fig. 14 in that the resistance element 4a functions as a temperature sensor in addition to functioning as a source resistor for the semiconductor element 3a. On the other hand, the resistance elements 4b to 4d function only as source resistors for the semiconductor elements 3b to 3d.

[0093] Each of the resistive elements 4a to 4h has a structure similar to that of the resistive element 4 shown in Fig. 4. An electrode pad formed by the upper surface electrode of the resistive element 4a is connected to the source electrode on the upper surface of the semiconductor element 3a via a bonding wire 5b, and is also connected to the temperature detection terminal 7b via a bonding wire 5u. The other configurations of the semiconductor device according to the third modification of the second embodiment are the same as those of the semiconductor device according to the second embodiment, so redundant explanations will be omitted.

[0094] Fig. 23 shows an equivalent circuit of the upper arm side formed by the semiconductor elements 3a to 3d shown in Fig. 22. As shown in Fig. 23, resistors (source resistors) R1 to R4 are connected between the source electrodes of the transistors T1 to T4, respectively, and the auxiliary source terminal S. A temperature detection terminal A is connected between the source electrode of the transistor T1 and the auxiliary source terminal S. The temperature detection terminal A corresponds to the temperature detection terminal 7b in Fig. 22.

[0095] In the semiconductor device according to the third modification of the second embodiment, the resistor elements 4a to 4h function as source resistors of the semiconductor elements 3a to 3h, thereby suppressing loop currents between the auxiliary sources of the semiconductor elements 3a to 3h and preventing disconnection of bonding wires. Furthermore, the resistor element 4a also functions as a temperature sensor, thereby detecting the temperature around the semiconductor elements 3a to 3h.

[0096] (Fourth Modification of the Second Embodiment) The semiconductor device according to the fourth modification of the second embodiment has a common planar layout with the semiconductor device according to the third modification of the second embodiment shown in FIG. 22, and the resistor element 4a is disposed in the semiconductor element 3a. The semiconductor device according to the third modification of the second embodiment also has a function as a temperature sensor in addition to a function as a source resistor. However, the semiconductor device according to the fourth modification of the second embodiment differs from the semiconductor device according to the third modification of the second embodiment in that the type of resistor element 4a is different from the other resistor elements 4b to 4h.

[0097] The resistor element 4a has two electrode pads formed by two upper electrodes 45e, 45f shown in FIG. 11, and has a structure similar to that of the resistor element 4 having a resistive layer 43a and pn junction diodes (43c, 43d) on a single chip. As shown in FIG. 22, the lower electrode of the resistor element 4a is bonded to the upper surface of the upper conductor layer 11g via a bonding material such as solder. One electrode pad of the resistor element 4a is connected to the source electrode on the upper surface of the semiconductor element 3a via a bonding wire 5b. The other electrode pad of the resistor element 4a is connected to the temperature detection terminal 7b via a bonding wire 5u.

[0098] The resistor elements 4b to 4h function only as source resistors for the semiconductor elements 3b to 3h. Each of the resistor elements 4b to 4d has a structure similar to that of the resistor element 4 having one electrode pad formed by one upper surface electrode 45a shown in FIG.

[0099] FIG. 24 shows an equivalent circuit of the upper arm side formed by semiconductor elements 3a to 3d of a semiconductor device according to a fourth modification of the second embodiment. As shown in FIG. 24, resistors (source resistors) R1 to R4 are connected between the source electrodes of transistors T1 to T4 and auxiliary source terminal S, respectively. Resistance element 4a has source resistor R1 and diode D11. The cathode of diode D11 is connected to the source electrode of transistor T1. The anode of diode D11 is connected to temperature detection terminal A. Temperature detection terminal A corresponds to temperature detection terminal 7b in FIG. 22.

[0100] In the semiconductor device according to the fourth modification of the second embodiment, the resistor elements 4a to 4h function as source resistors of the semiconductor elements 3a to 3h, thereby suppressing loop currents between the auxiliary sources of the semiconductor elements 3a to 3h and preventing disconnection of bonding wires. Furthermore, the resistor element 4a also functions as a temperature sensor, thereby detecting the temperature around the semiconductor elements 3a to 3h.

[0101] The resistor element 4a may have two electrode pads formed by two upper surface electrodes 45e and 45f shown in FIG. 9, and may have the same structure as the resistor element 4 having the resistor layers 43a and 43b. In this case, for example, one resistor layer 43a functions as a temperature sensor, and the other resistor layer 43b functions as a source resistor. The resistor layer 43a as the temperature sensor and the resistor layer 43b as the source resistor may be formed in the same process or in separate processes.

[0102] (Other embodiments) As described above, the present invention has been described by the first and second embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0103] For example, the configurations disclosed in the first and second embodiments can be appropriately combined within a range that does not cause a contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0104] 1...Insulated circuit board 2a,2b…Joining material 3a to 3h: Semiconductor elements (semiconductor chips) 4, 4a to 4h...Resistor element (resistor chip) 5a~5v...bonding wire 6a~6h...Wiring 7a…Auxiliary positive electrode terminal 7b,7c…Temperature detection terminal 7d,7 f …Control terminal 7 e ,7g...Auxiliary source terminal 8...Case material 8a...Positive terminal 8b…Negative terminal 8c...Output terminal 9...Sealing member 10...Insulating substrate 11a to 11i: Upper conductor layers (circuit layers) 12...Lower conductor layer (heat dissipation layer) 30...Semiconductor substrate 31...First main electrode (drain electrode) 31a...first electrode layer 31b...Second electrode layer 31c...Third electrode layer 32...Second main electrode (source electrode) 33...gate electrode (gate electrode) 41...Semiconductor substrate 43a, 43b...resistance layer 43c, 43d...Semiconductor layer 45a, 45e, 45f…Top electrode 45b, 45c, 45g...Relay wiring 45d... Guard ring layer 46a~46h...Contact area 47...Protective film (passivation film) 47a,47b...opening 49…Bottom electrode 49a...first electrode layer 49b…Second electrode layer 49c...Third electrode layer 49d...4th electrode layer 81...Step 82...Side wall D1 to D4: Freewheeling diodes D11...Diode L1 to L4: Parasitic inductance R1~R6,R11~R13...Resistance T1 to T4: Transistors T11~T 1 3...Terminal

Claims

1. a plurality of terminals each having a temperature detection terminal; a first chip whose semiconductor substrate is a compound semiconductor substrate; a second chip whose semiconductor substrate is made of a silicon substrate; Equipped with the first chip has a transistor; the second chip has a diode and a resistor electrically connected to the transistor; The diode is electrically connected to the temperature detection terminal. Semiconductor module.

2. The second chip has a first electrode pad connected to the resistor and a second electrode pad separate from the first electrode pad connected to the diode. The semiconductor module according to claim 1 .

3. A bonding wire and a wiring are provided, a main electrode provided on the same surface as the gate electrode of the first chip is connected to both the bonding wire and the wiring; The first electrode pad or the second electrode pad of the second chip is connected to the bonding wire. The semiconductor module according to claim 2 .

4. the temperature detection terminal is electrically connected to the anode of the diode; The cathode of the diode is electrically connected to the main electrode. The semiconductor module according to claim 3 .

5. The resistor has polysilicon disposed on the silicon substrate via an insulating film. The semiconductor module according to claim 2 .

6. The resistor has a resistance component of the silicon substrate to which n-type impurities or p-type impurities are added. The semiconductor module according to claim 2 .

7. The diode is a pn junction diode disposed on the silicon substrate via an insulating film. The semiconductor module according to claim 1 .

8. a plurality of the first chips are arranged in a first direction, The second chip is provided in a second direction perpendicular to the first direction with respect to at least one of the first chips. The semiconductor module according to claim 1 .

9. The semiconductor module is a 2-in-1 type or a 1-in-1 type, an output terminal protruding from the resin member in the first direction; The semiconductor module according to claim 8 .

10. a plurality of the first chips are arranged in a first direction, the second chip is provided in a second direction perpendicular to the first direction with respect to at least one of the first chips, the first chip has a gate electrode and a main electrode formed on the same plane as the gate electrode; At least two of the first chips arranged side by side are arranged so that the gate electrodes of the first chips face each other. The semiconductor module according to claim 1 .

11. the temperature detection terminal is electrically connected to the anode of the diode via a bonding wire; The cathode of the diode is electrically connected via a bonding wire to a main electrode provided on the same surface as the gate electrode of the transistor of the first chip.

3. The semiconductor module according to claim 1.

12. The first chip is a SiC MOSFET. The semiconductor module according to claim 1 .

13. A main electrode provided on the same surface as the gate electrode of the first chip is connected to one end of a bonding wire; The first electrode pad or the second electrode pad of the second chip is directly connected to the other end of the bonding wire. The semiconductor module according to claim 2 .

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