Information processing device, method, and program

Abstract

This information processing device comprises: a generator that generates a plurality of quantum bits and a plurality of signals; a converter that converts the plurality of signals to a plurality of analog signals of which the signal levels are equalized; a multiplexer that outputs a multiplexed signal obtained by multiplexing the plurality of analog signals; a divider that divides the multiplexed signal into a plurality of divided signals; a plurality of attenuators that attenuate the plurality of divided signals and apply the attenuated signals to the plurality of quantum bits; and a setter that transmits, to the plurality of attenuators, a shared setting signal that indicates the respective attenuation amounts of the plurality of attenuators, wherein the attenuation amounts of the plurality of attenuators is set on the basis of the setting signal.

Description

[Technical Field]

[0001] The present disclosure relates to an information processing device, a method, and a program. [Background technology]

[0002] Conventionally, a quantum computer system has been known in which multiplexed analog control signals are supplied to a quantum processor in a cryostat via a demultiplexer in the cryostat. The quantum processor includes a plurality of quantum bits (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0350270 Summary of the Invention [Problem to be solved by the invention]

[0004] In some cases, an attenuator is provided to attenuate a signal supplied to a quantum bit. However, as the number of quantum bits increases, the number of attenuators also increases, resulting in an increase in the number of setting signals transmitted to set the attenuation amounts of the attenuators. If the number of setting signals increases, for example, the number of lines transmitting the setting signals increases, which may make it difficult to secure space for arranging the lines transmitting the setting signals.

[0005] The present disclosure provides an information processing device, method, and program that can reduce the number of setting signals for an attenuator. [Means for solving the problem]

[0006] In one aspect of the present disclosure, Multiple qubits, a generator for generating a plurality of signals; a converter that converts the plurality of signals into a plurality of analog signals with uniform signal levels; a multiplexer that multiplexes the plurality of analog signals and outputs a multiplexed signal; a divider for dividing the multiplexed signal into a plurality of divided signals; a plurality of attenuators attenuating the plurality of split signals and providing the attenuated signals to the plurality of quantum bits, respectively; a setter that transmits a common setting signal indicating the attenuation amount of each of the plurality of attenuators to the plurality of attenuators, An information processing device is provided in which the attenuation amounts of the plurality of attenuators are set based on the setting signal. [Effects of the Invention]

[0007] According to the present disclosure, the number of setting signals for the attenuator can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 illustrates an example of the configuration of an information processing apparatus according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of the internal configuration of a cooling machine. [Figure 3] FIG. 10 is a diagram illustrating an example of the configuration of an information processing apparatus according to a second embodiment. [Figure 4] 1 is a diagram for explaining multiplexing of a plurality of types of signals and attenuation of each type of signal. [Figure 5] 10A and 10B are diagrams for explaining fine adjustment of the signal levels of some analog signals among a plurality of analog signals of the same type whose signal levels are made uniform. [Figure 6] 4 is a flowchart showing a first example of a signal attenuation method executed by the information processing device of the present embodiment. [Figure 7] FIG. 7 is an explanatory diagram corresponding to the signal attenuation method of FIG. 6. [Figure 8] 10 is a flowchart illustrating a second example of a signal attenuation method executed by the information processing device of the present embodiment. [Figure 9] FIG. 9 is an explanatory diagram corresponding to the signal attenuation method of FIG. 8. [Figure 10] 10 is a flowchart illustrating a third example of a signal attenuation method executed by the information processing device of the present embodiment. [Figure 11] 11 is an explanatory diagram corresponding to the signal attenuation method of FIG. 10. [Figure 12] 1 is a flowchart illustrating the overall flow of a signal attenuation method executed by the information processing device of the present embodiment. [Figure 13] FIG. 2 is a hardware configuration diagram of a computer. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described below.

[0010] Fig. 1 is a diagram showing an example of the configuration of an information processing device according to the first embodiment. The information processing device 101 shown in Fig. 1 processes information using multiple quantum bits (Qubits) and outputs the processing result to the outside. The information processing device 101 is used as a quantum computer or a quantum computing system.

[0011] FIG. 1 illustrates a plurality of quantum bits q (n quantum bits q1, q2, ..., qn), where n is an integer equal to or greater than 2. Each of the quantum bits q carries information in a quantum mechanical two-state system. The quantum bit q is, for example, a superconducting quantum bit formed by a superconducting circuit including a superconducting Josephson junction. The type of quantum bit is not limited to this.

[0012] The information processing device 101 includes a cooling device 200 and a control device 300 .

[0013] The refrigerator 200 cools a plurality of quantum bits q. The refrigerator 200 is, for example, a dilution refrigerator that uses the heat of dilution generated when liquid helium 3 is diluted with liquid helium 4. The refrigerator 200 may also be a device that cools quantum bits using another cooling method. The refrigerator 200 includes a plurality of quantum bits q (n quantum bits q1, q2, ..., qn), a plurality of amplifiers p (n amplifiers p1, p2, ..., pn), a divider 70, a plurality of attenuators ATT (n ATTs 11, 12, ..., 1n), and a multiplexer 80.

[0014] The control device 300 controls the multiple quantum bits q in the refrigerator 200, processes information based on data read from the quantum bits q, and outputs the processing results to the outside. The control device 300 includes a computer 500, a controller 50, a multiplexer 60, and a programmable power supply 55.

[0015] The computer 500 is a host computer for controlling the multiple quantum bits q. The computer 500 generates commands cmd for controlling the multiple quantum bits q and transmits them to the controller 50, and receives data d representing the readout results of the multiple quantum bits q from the controller 50. The computer 500 processes the data d and outputs the processing results to an external device such as a display. The computer 500 is connected to the controller 50 by wire or wirelessly.

[0016] The controller 50 generates a plurality of signals for the plurality of quantum bits q in accordance with a command cmd input from the computer 500, outputs the signals to the line 81, and acquires the readout results of the plurality of quantum bits q via the line 82. The controller 50 outputs data d representing the readout results of the plurality of quantum bits q acquired via the line 82 to the computer 500.

[0017] The controller 50 includes a generator 51, a converter 52, a read processing unit 53, and a power supply control unit 54. Some or all of the generator 51, the converter 52, the read processing unit 53, the power supply control unit 54, the multiplexer 60, and the programmable power supply 55 are formed by, for example, an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), a microcomputer, or the like.

[0018] The generator 51 is a circuit that generates multiple control signals a1 (n control signals a11, a12, ..., a1n) for multiple quantum bits q. The control signal a11 is a signal for quantum bit q1. The control signal a12 is a signal for quantum bit q2. The control signal a1n is a signal for quantum bit qn. The generator 51 generates multiple control signals a1 corresponding to the contents of a command cmd, for example, in accordance with a command cmd supplied from the computer 500. The multiple control signals a1 are digital signals used to control the states of the multiple quantum bits q. The n control signals a11, a12, ..., a1n are each signals for controlling the state of a corresponding quantum bit among the multiple quantum bits q.

[0019] Converter 52 is a circuit that converts the multiple control signals a1 generated by generator 51 into multiple analog signals b1 (n analog signals b11, b12, ..., b1n) with uniform signal levels. Analog signal b11 is a signal for quantum bit q1. Analog signal b12 is a signal for quantum bit q2. Analog signal b1n is a signal for quantum bit qn. The multiple analog signals b1 are, for example, electromagnetic wave signals (microwave signals as a specific example) transmitted to the multiple quantum bits q.

[0020] The converter 52 adjusts the signal level of at least one of the plurality of analog signals b1 using a DAC (digital-analog converter), for example, to make the signal levels of the plurality of analog signals b1 approximately the same level value.

[0021] Converter 52 converts the multiple control signals a1 into multiple analog signals b1 having a frequency higher than the frequency (usage frequency f0) used by generator 51. Converter 52, for example, adjusts the frequency of the multiple analog signals b1 to a predetermined frequency F1 (for example, the resonant frequency of the multiple quantum bits q).

[0022] The frequencies of the analog signals b1 may be the same or different from one another. For example, if the resonant frequencies of the quantum bits q are the same, the frequencies of the analog signals b1 may be the same from one another. However, if the resonant frequencies of the quantum bits q are different from one another, the frequencies of the analog signals b1 may be different from one another. For example, the converter 52 adjusts the frequency of each of the analog signals b1 to the resonant frequency of a corresponding quantum bit among the quantum bits q.

[0023] Converter 52 may have a function of adjusting the frequency f0 so that an integer multiple (harmonic frequency) of operating frequency f0 differs from predetermined frequency F. This prevents harmonics having a frequency that is a multiple of operating frequency f0 from appearing in the frequency of analog signal b1 (predetermined frequency F), thereby reducing malfunction of refrigerator 200 (particularly quantum bit p) due to noise from the harmonics.

[0024] The multiplexer 60 is a circuit that multiplexes multiple analog signals b1 and outputs a multiplexed signal M obtained by multiplexing the multiple analog signals b1. A multiplexer is also called a combiner. The multiplexed signal M is transmitted from the multiplexer 60 of the control device 300 to the divider 70 of the cooling device 200 via a line 81 (e.g., a transmission line such as a coaxial cable). By multiplexing the multiple analog signals b1 and transmitting them as the multiplexed signal M, the number of lines 81 and their arrangement space can be reduced compared to a configuration in which the multiple analog signals b1 are transmitted individually without being multiplexed. This type of multiplexing is particularly advantageous when there are a huge number of quantum bits q or analog signals b1, such as hundreds or thousands. The number of lines 81 may be one, or multiple lines 81 may be used by dividing the multiplexed signals into multiple groups.

[0025] The multiplexing method used in the multiplexer 60 includes frequency division multiplexing, time division multiplexing, and the like.

[0026] The divider 70 divides the multiplexed signal M into a plurality of divided signals c1 (n divided signals c11, c12, ..., c1n) corresponding to a plurality of control signals a1. The divider is also called a demultiplexer or a demultiplexer. FIG. 1 illustrates divided signal c11 corresponding to control signal a11, divided signal c12 corresponding to control signal a12, and divided signal c1n corresponding to control signal a1n. The divider 70 divides the multiplexed signal M into a plurality of divided signals c1 using, for example, a BPF (band pass filter).

[0027] The multiple attenuators ATT attenuate the multiple split signals c1 for the multiple quantum bits q and provide them to the multiple quantum bits q, respectively. ATT11 attenuates the signal level of a corresponding split signal c11 among the multiple split signals c1 to a level value used to control the state of quantum bit q1. The attenuated split signal c11 is supplied from ATT11 to quantum bit q1, thereby enabling control of the resonant state of quantum bit q1. ATT12 attenuates the signal level of a corresponding split signal c12 among the multiple split signals c1 to a level value used to control the state of quantum bit q2. The attenuated split signal c12 is supplied from ATT12 to quantum bit q2, thereby enabling control of the resonant state of quantum bit q2. ATT1n attenuates the signal level of a corresponding split signal c1n among the multiple split signals c1 to a level value used to control the state of quantum bit qn. The attenuated split signal c1n is supplied from ATT1n to quantum bit qn, thereby enabling control of the resonant state of quantum bit qn.

[0028] Quantum computers may be controlled by supplying a weak power of -100 dBm or less to the quantum bit q. However, digital circuits such as the generator 51 that generates the digital signal can produce large noise such as digital noise. Therefore, the signal to noise ratio (SNR) can be ensured by amplifying the signal component of the analog signal b1 and then attenuating the entire signal using the attenuator ATT.

[0029] The amplifiers p amplify the readout signals representing the readout results of the states of the quantum bits q and output the amplified readout signals c4 (n readout signals c41, c42, ..., c4n). Figure 1 illustrates readout signal c41 representing the readout result of the state of quantum bit q1, readout signal c42 representing the readout result of the state of quantum bit q2, and readout signal c4n representing the readout result of the state of quantum bit qn.

[0030] The multiplexer 80 is a circuit that multiplexes multiple analog readout signals c4 and outputs a multiplexed signal D obtained by multiplexing the multiple readout signals c4. The multiplexed signal D is transmitted from the multiplexer 80 of the cooling device 200 to the readout processing unit 53 of the control device 300 via a line 82 (e.g., a transmission line such as a coaxial cable). By multiplexing the multiple readout signals c4 and transmitting them as the multiplexed signal D, the number of lines 82 and the space required for their placement can be reduced compared to a configuration in which the multiple readout signals c4 are transmitted individually without being multiplexed. This type of multiplexing is particularly advantageous when there are a huge number of quantum bits q or readout signals c4, such as hundreds or thousands. The number of lines 82 may be one, or multiple lines 82 may be used by dividing the multiplexed signals into multiple groups.

[0031] The multiplexing method used in the multiplexer 80 may be frequency division multiplexing, time division multiplexing, or the like.

[0032] The read processing unit 53 extracts a plurality of read signals c4 from the multiplexed signal D and converts the plurality of read signals c4 into data d. The read processing unit 53 outputs the data d representing the read results of the plurality of quantum bits q to the computer 500.

[0033] The control device 300 includes a setter 56 that transmits a common setting signal s1 to the plurality of attenuators ATT for setting the attenuation of each of the plurality of attenuators ATT. In this example, the setter 56 has a power supply control unit 54 and a programmable power supply 55. The power supply control unit 54 controls the programmable power supply 55 so that the common setting signal s1 is transmitted to the plurality of attenuators ATT. The common setting signal s1 indicates the attenuation of each of the plurality of attenuators ATT. The attenuation of the plurality of attenuators ATT is set based on the setting signal s1.

[0034] The setting signal s1 is transmitted in common from the setting device 56 to the plurality of attenuators ATT via a line 83. If the setting signal s1 is a variable DC voltage value, the line 83 may be a DC cable. The plurality of attenuators ATT attenuate the plurality of divided signals c1 by an attenuation amount according to the setting value set by the setting signal s1. In other words, the n ATTs 11, 12, ..., 1n each attenuate a corresponding divided signal among the plurality of divided signals c1 by the same attenuation amount according to the setting value set by the setting signal s1.

[0035] In the first embodiment, the signal levels of the multiple analog signals b1 (n analog signals b11, b12, ..., b1n) are adjusted to approximately the same level value by the converter 52. As a result, the signal levels of the multiple divided signals c1 (n divided signals c11, c12, ..., c1n) before being input to the multiple attenuators ATT are also adjusted to approximately the same level value. Therefore, by using a common setting signal s1 to set the attenuation amount of each of the multiple attenuators ATT (n ATTs 11, 12, ..., 1n), the signal levels of the multiple divided signals c1 are attenuated to the same level value used to control the states of the multiple quantum bits q.

[0036] In this way, when attenuating the signal levels of the multiple divided signals c1 to levels used to control the states of the multiple quantum bits q, the signal levels of the multiple analog signals b1 are aligned, making it possible to use a common setting signal s1. Therefore, the number of setting signals for setting the attenuation amounts of the multiple attenuators ATT can be reduced to at least one, and ultimately the number and arrangement space of the lines 83 that transmit the setting signal s1 can be reduced.

[0037] 2 is a diagram showing an example of the internal configuration of a chiller. The chiller 200 includes a chamber 221 separated from the surrounding environment by a boundary surface 201 and an outer wall 220. The chamber 221 includes a plurality of plates 202-206 arranged at predetermined intervals from the boundary surface 201 and a plurality of support posts 222 that support the plurality of plates 202-206 at predetermined intervals from the boundary surface 201. The plurality of plates 202-206 divide the chamber 221 into a plurality of chambers 211-216 so that the internal temperature of the chamber 221 at each position of the plurality of plates 202-206 gradually decreases with increasing distance from the boundary surface 201. In other words, the chiller 200 has a plurality of chambers 211-216 that are arranged so that the temperature gradually decreases with increasing distance from the boundary surface 201.

[0038] Among the multiple rooms 211 to 216, room 216, which has the lowest temperature, houses multiple quantum bits q, multiple ATTs, and divider 70. Lines 81, 82, and 83 are connected to and pass through boundary surface 201. Lines 81, 82, and 83 may each be a combination of multiple lines connected via connectors between adjacent rooms.

[0039] The line 81 extends from the room 211 with the highest temperature to the room 216 with the lowest temperature among the multiple rooms 211 to 216 in order, and transmits the multiplexed signal M to the splitter 70. The line 83 extends from the room 211 with the highest temperature to the room 216 with the lowest temperature among the multiple rooms 211 to 216 in order, and transmits the setting signal s1 to the multiple ATTs.

[0040] If the divider 70 were located in one of the rooms 211 to 215, the signal lines connecting the divider 70 and the quantum bits q would be relatively long, making it difficult to secure the space for arranging these signal lines and to miniaturize the refrigerator 200. On the other hand, in the embodiment shown in FIG. 2, the line 81 extends to the divider 70 located in the same room 216 as the quantum bits q, thereby reducing the length of the signal lines connecting the divider 70 and the quantum bits q. This makes it easier to secure the space for arranging these signal lines and to miniaturize the refrigerator 200. This effect also applies to the second embodiment described below.

[0041] 3 is a diagram showing an example of the configuration of an information processing device according to the second embodiment. In the second embodiment, the description of the configuration, actions, and effects similar to those of the first embodiment will be omitted or simplified by invoking the above description. The information processing device 102 according to the second embodiment differs from the information processing device 101 according to the first embodiment in that the generator 51 multiplexes multiple types of signals, the converter 52 converts the multiple types of signals into multiple analog signals with uniform signal levels, and the setter 56 transmits a common setting signal to multiple ATTs for each signal type.

[0042] The generator 51 generates multiple types of signals for multiple quantum bits q. In this example, the generator 51 generates n control signals a11, a12, ..., a1n, n readout signals a21, a22, ..., a2n, and n pump signals a31, a32, ..., a3n. The control signals a11, a12, ..., a1n may be the same as those in the first embodiment.

[0043] Read signal a21 is a signal for quantum bit q1. Read signal a22 is a signal for quantum bit q2. Read signal a2n is a signal for quantum bit qn. For example, in accordance with a command cmd supplied from computer 500, generator 51 generates multiple read signals a2 (n read signals a21, a22, ..., a2n) corresponding to the contents of the command cmd. The multiple read signals a2 are digital signals used to read out the states of the multiple quantum bits q. Each of the n read signals a21, a22, ..., a2n is a signal for reading out the state of a corresponding quantum bit among the multiple quantum bits q.

[0044] Pump signal a31 is a signal for quantum bit q1. Pump signal a32 is a signal for quantum bit q2. Pump signal a3n is a signal for quantum bit qn. For example, generator 51 generates multiple pump signals a3 (n pump signals a31, a32, ..., a3n) corresponding to the contents of command cmd in accordance with command cmd supplied from computer 500. The multiple pump signals a3 are digital signals used for multiple amplifiers p that parametrically amplify multiple readout signals c4 representing readout results of the states of multiple quantum bits q. Each of the n pump signals a31, a32, ..., a3n is a signal for controlling the parametric amplification of a corresponding amplifier among the multiple amplifiers p.

[0045] As in the first embodiment, the converter 52 converts the plurality of control signals a1 into a plurality of analog signals b1 (n analog signals b11, b12, . . . , b1n) with uniform signal levels.

[0046] Converter 52 converts the multiple read signals a2 into multiple analog signals b2 (n analog signals b21, b22, ..., b2n) with uniform signal levels. Analog signal b21 is a signal for quantum bit q1. Analog signal b22 is a signal for quantum bit q2. Analog signal b2n is a signal for quantum bit qn. The multiple analog signals b2 are, for example, electromagnetic wave signals (microwave signals as a specific example) transmitted to the multiple quantum bits q.

[0047] Converter 52 converts the multiple pump signals a3 into multiple analog signals b3 (n analog signals b31, b32, ..., b3n) with uniform signal levels. Analog signal b31 is a signal for quantum bit q1. Analog signal b32 is a signal for quantum bit q2. Analog signal b3n is a signal for quantum bit qn. The multiple analog signals b3 are, for example, electromagnetic wave signals (microwave signals as a specific example) transmitted to the multiple quantum bits q.

[0048] The converter 52 adjusts the signal level of at least one of the multiple analog signals b1, b2, and b3 using a DAC (digital-to-analog converter) to align the signal levels of the multiple analog signals b1, b2, and b3 to approximately the same level value L0 (see FIG. 4).

[0049] 4 is a diagram illustrating the multiplexing of multiple types of signals and the attenuation of each signal type. If multiple types of analog signals with different signal levels are multiplexed as is, signals with low signal levels may be affected by noise, which may reduce the signal-to-noise ratio of the signals divided by the divider. By adjusting the signal levels of multiple analog signals b1, b2, and b3 to approximately the same level value L0, such a reduction in the signal-to-noise ratio is suppressed.

[0050] 3, converter 52 converts a plurality of control signals a1 into a plurality of analog signals b1 having a frequency higher than the frequency (used frequency f0) used by generator 51. Similarly, converter 52 converts a plurality of read signals a2 into a plurality of analog signals b2 having a frequency higher than the used frequency f0, and converts a plurality of pump signals a3 into a plurality of analog signals b3 having a frequency higher than the used frequency f0.

[0051] Converter 52 adjusts the frequencies of the multiple analog signals b1 to a predetermined frequency F1 used to control the states of the multiple quantum bits q. Converter 52 adjusts the frequencies of the multiple analog signals b2 to a predetermined frequency F2 used to read out the states of the multiple quantum bits q. Converter 52 adjusts the frequencies of the multiple analog signals b3 to a predetermined frequency F3 used to control the amplification of the multiple amplifiers p.

[0052] The frequencies F1, F2, and F3 are different from one another. For example, the frequency F1 is in a frequency band of 5 GHz or more and 7 GHz or less, the frequency F2 is in a frequency band of 8 GHz or more and 10 GHz or less, and the frequency F3 is in a frequency band of 16 GHz or more and 20 GHz or less.

[0053] The multiplexer 60 is a circuit that multiplexes a plurality of analog signals b1, b2, b3 regardless of the signal type, and outputs a multiplexed signal M obtained by multiplexing the plurality of analog signals b1, b2, b3 by frequency division multiplexing or the like.

[0054] The cooling device 200 includes a plurality of quantum bits q (n quantum bits q1, q2, ..., qn), a plurality of amplifiers p (n amplifiers p1, p2, ..., pn), a divider 70, a plurality of attenuators ATT (3 x n ATTs 11, 12, ..., 1n, 21, 22, ..., 2n, 31, 32, ..., 3n), and a multiplexer 80.

[0055] The divider 70 uses a BPF to divide the multiplexed signal M into a plurality of divided signals c1 (n divided signals c11, c12, ..., c1n) corresponding to a plurality of control signals a1. The divider 70 uses a BPF to divide the multiplexed signal M into a plurality of divided signals c2 (n divided signals c21, c22, ..., c2n) corresponding to a plurality of read signals a2. The divider 70 uses a BPF to divide the multiplexed signal M into a plurality of divided signals c3 (n divided signals c31, c32, ..., c3n) corresponding to a plurality of pump signals a3. In this way, the divider 70 divides the multiplexed signal M into a plurality of divided signals c1, c2, c3 corresponding to the plurality of signals generated by the generator 51.

[0056] The multiple attenuators ATT attenuate multiple types of split signals c1, c2, c3 for the multiple quantum bits q. As in the first embodiment, the n ATTs 11, 12, ..., 1n attenuate the signal levels of corresponding split signals c11, c12, ..., c1n among the multiple split signals c1 to level values ​​used to control the state of quantum bit q1.

[0057] The n ATTs 21, 22, ..., 2n attenuate the signal levels of corresponding split signals c21, c22, ..., c2n among the multiple split signals c2 to level values ​​used to read out the state of the corresponding quantum bit among the multiple quantum bits q. The attenuated split signal c21 is supplied from the ATT 21 to quantum bit q1, making it possible to read out the state of quantum bit q1. The same applies to split signals c22, ..., c2n.

[0058] The n ATTs 31, 32, ..., 3n attenuate the signal levels of corresponding split signals c31, c32, ..., c3n among the multiple split signals c3 to levels used for amplification control of corresponding amplifiers p. The attenuated split signal c31 is supplied from the ATT 31 to amplifier p1, thereby enabling appropriate amplification of readout signal c41, which represents the readout result of the state of quantum bit q1. The same applies to split signals c32, ..., c3n.

[0059] The control device 300 includes a setter 56 that transmits common setting signals s1, s2, and s3 set for each signal type to the plurality of attenuators ATT to set the attenuation amounts of the plurality of attenuators ATT. The power supply control unit 54 controls the programmable power supply 55 so that the common setting signals s1, s2, and s3 for each signal type are transmitted to the plurality of attenuators ATT.

[0060] A setting signal s1 is transmitted in common from the setter 56 to n ATTs 11, 12, ..., 1n via a line 83. Each of the n ATTs 11, 12, ..., 1n attenuates a corresponding divided signal among the multiple divided signals c1 by the same attenuation amount ΔL1 according to a setting value set by the setting signal s1. A setting signal s2 is transmitted in common from the setter 56 to n ATTs 21, 22, ..., 2n via a line 83. Each of the n ATTs 21, 22, ..., 2n attenuates a corresponding divided signal among the multiple divided signals c2 by the same attenuation amount ΔL2 according to a setting value set by the setting signal s2. Each of the n ATTs 31, 32, ..., 3n attenuates a corresponding divided signal among the multiple divided signals c3 by the same attenuation amount ΔL3 according to a setting value set by the setting signal s3. In this way, the setting device 56 transmits common setting signals s1, s2, and s3 set for each signal type to the multiple attenuators ATT so that split signals of the same type among the multiple types of split signals are attenuated by the same amount of attenuation.

[0061] As shown in FIG. 4 , in the second embodiment, the signal levels of the multiple types of analog signals b1, b2, and b3 are adjusted to approximately the same level value L0 by the converter 52. A common setting signal s1 that sets the value of the attenuation amount ΔL1 attenuates the signal levels of the multiple split signals c1 to the same level value used to control the states of the multiple quantum bits q. A common setting signal s2 that sets the value of the attenuation amount ΔL2 attenuates the signal levels of the multiple split signals c2 to the same level value used to read out the states of the multiple quantum bits q. A common setting signal s3 that sets the value of the attenuation amount ΔL3 attenuates the signal levels of the multiple split signals c3 to the same level value used to control the amplification of the multiple amplifiers p. In this way, the attenuation amount can be set individually for each signal type.

[0062] Therefore, in the second embodiment, similarly to the first embodiment, it is possible to use common setting signals s1, s2, and s3. Therefore, it is possible to reduce the number of setting signals for setting the attenuation amounts of the plurality of attenuators ATT, and further to reduce the number and arrangement space of the lines 83 for transmitting the setting signals s1, s2, and s3.

[0063] 3, the setter 56 sets common setting signals s1, s2, and s3 to setting signals whose expected values ​​are returned from some or all of the multiple quantum bits q via a line 82. This allows the setter 56 to set common setting signals s1, s2, and s3 that are appropriate for attenuation of the multiple divided signals c1, c2, and c3.

[0064] The setter 56 sets a common setting signal s1 used to attenuate the multiple divided signals c1 corresponding to the multiple control signals a1, for example, to setting signals that return expected control results from some or all of the multiple quantum bits q via line 82. This allows the setter 56 to set a common setting signal s1 appropriate for attenuating the multiple divided signals c1.

[0065] The setter 56 sets a common setting signal s2 used to attenuate the multiple divided signals c2 corresponding to the multiple readout signals a2, for example, to a setting signal that returns an expected response from some or all of the multiple quantum bits q via the line 82. This allows the setter 56 to set a common setting signal s2 appropriate for attenuating the multiple divided signals c2.

[0066] The setter 56 sets the common setting signal s3 used to attenuate the multiple divided signals c3 corresponding to the multiple pump signals a3 to, for example, a setting signal that returns an expected output level from the amplifiers p of some or all of the multiple quantum bits q via the line 82. This allows the setter 56 to set the common setting signal s3 appropriate for attenuating the multiple divided signals c3.

[0067] 3, converter 52 may use a DAC to fine-tune the signal levels of some of the multiple analog signals of the same type, whose signal levels have been aligned. Due to variations in the characteristics of the multiple quantum bits q or the multiple amplifiers p, it is conceivable that when a common setting signal s1 is used, the expected values ​​are not returned from some or all of the multiple quantum bits q via line 82. Similarly, when setting signal s2 or setting signal s3 is used, it is conceivable that the expected values ​​are not returned from some or all of the multiple quantum bits q via line 82. In such cases, converter 52 may use a DAC to fine-tune the signal levels of some of the multiple analog signals of the same type, whose signal levels have been aligned, so that the expected values ​​are returned from all of the multiple quantum bits q.

[0068] 5 is a diagram for explaining fine adjustment of the signal levels of some analog signals among a plurality of analog signals of the same type whose signal levels are made uniform. While FIG. 5 illustrates the case of a control signal, the converter 52 may also perform fine adjustment of the signal levels of a readout signal or a pump signal.

[0069] When the expected value is not returned from quantum bit q2, converter 52 fine-tunes the signal level of analog signal b12 corresponding to control signal a12 for quantum bit q2 from L0 to L0'. L0' is the signal level at which the expected value is returned from quantum bit q2. By fine-tuning the signal level of analog signal b12 from L0 to L0', the signal level of divided signal c12 output from ATT12 for quantum bit q2 becomes lower by the amount of fine-tuning than the signal level of divided signal c11 output from ATT11 for quantum bit q1. This causes the expected value to be returned from quantum bit q2.

[0070] Next, a control method executed by the information processing device of each embodiment according to the present disclosure will be described.

[0071] Fig. 6 is a flowchart showing a first example of a signal attenuation method executed by the information processing device of this embodiment. The signal attenuation method of Fig. 6 is realized by the operation of the control device 300 in accordance with a command cmd from the computer 500. Fig. 7 is an explanatory diagram corresponding to the signal attenuation method of Fig. 6. The signal attenuation method of Fig. 6 will be described with reference to Fig. 7.

[0072] The signal attenuation method in Figure 6 derives the setting value that returns the expected value from the most number of quantum bits in the calibration using the variable ATT, and minimizes the number of adjustments to the signal level of the analog signal by the DAC, which simplifies the adjustment of the signal level of the analog signal by the DAC.

[0073] In step S10, the computer 500 transmits a command cmd to the converter 52 to set the initial values ​​of the signal levels of the multiple analog signals b1, b2, and b3, and to the setter 56 to transmit common setting signals s1, s2, and s3 that set the initial values ​​of the setting values.

[0074] In step S13, a multiplexed signal M obtained by multiplexing multiple analog signals b1, b2, and b3 is divided into multiple divided signals c1, c2, and c3. Then, with the set value set by a common setting signal, the attenuated divided signals c1 and c2 are supplied to multiple quantum bits p for a fixed time, and the attenuated divided signal c3 is supplied to multiple amplifiers p for a fixed time.

[0075] In step S15, computer 500 records the setting value set by the setting signal and the quantum bit that returns an expected value at that setting value in database (DB 501). Computer 500 may estimate, from the setting value, the level value of the analog signal that returns an expected value from a quantum bit that does not return an expected value at that setting value, and record the estimated value in DB 501.

[0076] In step S17, the computer 500 determines whether expected values ​​have been returned from all of the quantum bits p using the setting values ​​set in the immediately preceding step S13. If the computer 500 determines that expected values ​​have been returned from all of the quantum bits p, it executes the process of step S19, and if it determines that expected values ​​have not been returned from all of the quantum bits p, it executes the process of step S25.

[0077] In step S25, the computer 500 determines whether or not all of the setting values ​​set by the setting signals s1, s2, and s3 have been changed within the predetermined adjustment ranges 1 to i. If the computer 500 determines that all of the setting values ​​set by the setting signals s1, s2, and s3 have been changed within the predetermined adjustment ranges 1 to i, it executes the process of step S29. On the other hand, if the computer 500 determines that all of the setting values ​​set by the setting signals s1, s2, and s3 have not been changed within the predetermined adjustment ranges 1 to i, it executes the process of step S27.

[0078] In step S27, the computer 500 changes the setting values ​​set by the setting signals s1, s2, and s3 to the next values. The computer 500 transmits a command cmd to cause the setter 56 to transmit setting signals s1, s2, and s3 that set the setting values ​​to the next values. The process of step S13 is executed with the next set values.

[0079] By repeating the processing loop of steps S13, S15, S17, S25, and S27, DB501 is created that defines the relationship between the setting value and the quantum bit that returns the expected value at that setting value in the adjustment range 1 to i (see FIG. 7).

[0080] In step S19, the computer 500 reads from the DB 501 setting values ​​that return expected values ​​from all of the quantum bits q. In step S21, the computer 500 transmits a command cmd to the setter 56 to transmit setting signals s1, s2, and s3 that set the setting values ​​read in step S19. This allows the setter 56 to set common setting signals s1, s2, and s3 to setting signals identified using the DB 501 as signals that return expected values ​​from all of the multiple quantum bits. At this time, expected values ​​are returned from all of the quantum bits q, so the processing of step S23 is not executed.

[0081] Meanwhile, in step S29, computer 500 reads from DB 501 the setting value that returns expected values ​​from the largest number of quantum bits. In step S31, computer 500 reads from DB 501 the level value that returns expected values ​​from quantum bits that do not return expected values ​​with the setting value in step S29.

[0082] In step S21 after processing of step S31, the computer 500 transmits a command cmd to the setter 56 to transmit setting signals s1, s2, and s3 that set the setting values ​​read out in step S29. This enables the setter 56 to set common setting signals s1, s2, and s3 to setting signals identified using the DB 501 as signals that return expected values ​​from some of the multiple quantum bits. The setter 56 can then set the common setting signals s1, s2, and s3 to setting signals that return expected values ​​from the largest number of quantum bits.

[0083] In step S23, computer 500 transmits a command cmd to converter 52 to adjust the signal levels of analog signals b1, b2, b3 for quantum bits that do not return expected values ​​to the level values ​​read out in step S31. This enables converter 52 to adjust the signal levels of the analog signals b1, b2, b3 for quantum bits that do not return expected values ​​using a common setting signal to level values ​​that return expected values ​​from quantum bits that do not return expected values ​​using a common setting signal.

[0084] Fig. 8 is a flowchart showing a second example of the signal attenuation method executed by the information processing device of this embodiment. The signal attenuation method of Fig. 8 is realized by the operation of the control device 300 in accordance with a command cmd from the computer 500. Fig. 9 is an explanatory diagram corresponding to the signal attenuation method of Fig. 8. The signal attenuation method of Fig. 8 will be described with reference to Fig. 9.

[0085] The signal attenuation method shown in Figure 8 derives a central setting value from among multiple setting values ​​that return expected values ​​from some or all of the multiple quantum bits q in calibration using a variable ATT, and minimizes the adjustment range of the analog signal level by the DAC, thereby ensuring the signal-to-noise ratio of the attenuated divided signal.

[0086] The processing contents of steps S41 to S57 and S61 shown in Fig. 8 are the same as the processing contents of steps S11 to S27 and S31 shown in Fig. 6. The processing content of step S59 shown in Fig. 8 is different from the processing content of step S29 shown in Fig. 6.

[0087] In step S59, the computer 500 reads from the DB 501 the median setting value among the multiple setting values ​​at which expected values ​​are returned from some or all of the multiple quantum bits q. In step S61, the computer 500 reads from the DB 501 the level values ​​at which expected values ​​are returned from quantum bits that do not return expected values ​​with the setting values ​​in step S59.

[0088] In step S51 after processing of step S61, the computer 500 transmits a command cmd to the setter 56 to transmit setting signals s1, s2, and s3 that set the setting values ​​read out in step S59. This allows the setter 56 to set common setting signals s1, s2, and s3 to setting signals identified using the DB 501 as signals that return expected values ​​from some of the multiple quantum bits. The setter 56 can then set the common setting signals s1, s2, and s3 to setting signals with central setting values ​​among the multiple setting signals that return expected values ​​from some or all of the multiple quantum bits q.

[0089] In step S53, computer 500 transmits a command cmd to converter 52 to adjust the signal levels of analog signals b1, b2, b3 for quantum bits that do not return expected values ​​to the level values ​​read out in step S61. This enables converter 52 to adjust the signal levels of the analog signals b1, b2, b3 for quantum bits that do not return expected values ​​using a common setting signal to level values ​​at which the expected values ​​are returned from quantum bits that do not return expected values ​​using a common setting signal.

[0090] Fig. 10 is a flowchart showing a third example of a signal attenuation method executed by the information processing device of this embodiment. The signal attenuation method of Fig. 10 is realized by the operation of the control device 300 in accordance with a command cmd from the computer 500. Fig. 11 is an explanatory diagram corresponding to the signal attenuation method of Fig. 10. The signal attenuation method of Fig. 10 will be described with reference to Fig. 11.

[0091] The signal attenuation method shown in Figure 10 derives the maximum setting value among multiple setting values ​​that return expected values ​​from some or all of the multiple quantum bits q in calibration using a variable ATT, and uses the full range of the DAC that adjusts the signal level of the analog signal. This allows the dynamic range of the DAC to be used effectively.

[0092] The processing contents of steps S71 to S87 and S91 shown in Fig. 10 are the same as the processing contents of steps S11 to S27 and S31 shown in Fig. 6. The processing contents of step S89 shown in Fig. 10 are different from the processing contents of step S29 shown in Fig. 6.

[0093] In step S89, the computer 500 reads from the DB 501 the maximum setting value among the multiple setting values ​​at which expected values ​​are returned from some or all of the multiple quantum bits q. In step S91, the computer 500 reads from the DB 501 level values ​​at which expected values ​​are returned from quantum bits that do not return expected values ​​with the setting values ​​in step S89.

[0094] In step S81 after processing of step S91, the computer 500 transmits a command cmd to the setter 56 to transmit setting signals s1, s2, and s3 that set the setting values ​​read out in step S89. This allows the setter 56 to set common setting signals s1, s2, and s3 to setting signals identified using the DB 501 as signals that return expected values ​​from some of the multiple quantum bits. The setter 56 can then set the common setting signals s1, s2, and s3 to the setting signal with the largest setting value among the multiple setting signals that return expected values ​​from some or all of the multiple quantum bits q.

[0095] In step S83, computer 500 transmits a command cmd to converter 52 to adjust the signal levels of analog signals b1, b2, b3 for quantum bits that do not return expected values ​​to the level values ​​read out in step S91. This enables converter 52 to adjust the signal levels of the analog signals b1, b2, b3 for quantum bits that do not return expected values ​​using a common setting signal to level values ​​that will return expected values ​​from quantum bits that do not return expected values ​​using a common setting signal.

[0096] Fig. 12 is a flowchart illustrating the overall flow of a signal attenuation method executed by the information processing device of this embodiment. The signal attenuation method of Fig. 12 is realized by the operation of the control device 300 in accordance with commands cmd from the computer 500. By executing the processing of each step in the order shown in Fig. 12, it is possible to efficiently adjust and check each signal.

[0097] In step S100, the computer 500 sends a command cmd to the converter 52 to set initial values ​​of the signal levels of the multiple analog signals b1, b2, and b3, and to the setter 56 to send common setting signals s1, s2, and s3 that set the initial values ​​of the setting values.

[0098] In step S101, the computer 500 transmits a command cmd to adjust and confirm the plurality of readout signals a2 (n readout signals a21, a22, ..., a2n). As a result, the setter 56 adjusts the common setting signal s2 for the readout signals a2 to a setting signal that returns the expected response from some or all of the plurality of quantum bits q. In step S101, the setter 56 executes, for example, the signal attenuation method of FIG. 6, FIG. 8, or FIG. 10 for the readout signal a2.

[0099] In step S102, the computer 500 transmits a command cmd to adjust and confirm the plurality of pump signals a3 (n pump signals a31, a32, ..., a3n). As a result, the setter 56 adjusts the common setting signal s3 for the pump signals a3 to a setting signal that returns the expected output levels from the amplifiers p of some or all of the plurality of quantum bits q. In step S102, the setter 56 executes, for example, the signal attenuation method of FIG. 6, FIG. 8, or FIG. 10 for the pump signal a3.

[0100] In step S103, the computer 500 transmits a command cmd to adjust and confirm the plurality of control signals a1 (n control signals a11, a12, ..., a1n). As a result, the setter 56 adjusts the common setting signal s1 related to the control signals a1 to a setting signal that returns the expected control results from some or all of the plurality of quantum bits q. In step S103, the setter 56 executes, for example, the signal attenuation method of FIG. 6, FIG. 8, or FIG. 10 with respect to the control signal a1.

[0101] 13 is a hardware configuration diagram of a computer. A computer 500 includes a drive device 508, an auxiliary storage device 502, a memory device 503, a CPU (Central Processing Unit) 504, and an interface device 505, all of which are interconnected via a bus 506.

[0102] A program for realizing processing in computer 500 is provided by recording medium 507. When recording medium 507 on which the program is recorded is set in drive device 508, the program is installed from recording medium 507 to auxiliary storage device 502 via drive device 508. However, the program does not necessarily have to be installed from recording medium 507, but may be downloaded from another computer via a network. Auxiliary storage device 502 stores the installed program as well as necessary files, data, etc.

[0103] When an instruction to start a program is received, the memory device 503 reads the program from the auxiliary storage device 502 and stores it. The CPU 504 is a processor that executes functions related to the computer 500 in accordance with the program stored in the memory device 503. The interface device 505 is used as an interface for connecting to the outside.

[0104] Examples of the recording medium 507 include portable recording media such as a CD-ROM, a DVD disk, or a USB memory. Examples of the auxiliary storage device 502 include a hard disk drive (HDD) or a flash memory. Both the recording medium 507 and the auxiliary storage device 502 correspond to computer-readable recording media.

[0105] 6, 8, and 10 may be stored in the auxiliary storage device 502. The DB 501 may be stored in the auxiliary storage device 502 or the memory device 503.

[0106] Although the embodiments have been described above, they are presented as examples and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims. [Explanation of symbols]

[0107] 11,12,1n Attenuator (ATT) 50 Controller 51 Generator 52 Converter 53 Read processing section 54 Power supply control unit 55 Programmable Power Supply 56 Setting device 60 multiplexer 70 divider 80 multiplexer 81,82,83 railroad track 101, 102 Information processing equipment 200 Cooler 300 control device 500 computers 501 Database a11, a12, a1n control signals a21, a22, a2n readout signals a31, a32, a3n pump signal b11, b12, b1n analog signal c11,c12,c1n split signal c41, c42, c4n readout signal cmd command d Data q1,q2,qn qubits p1, p2, pn amplifier s1,s2,s3 setting signal D,M multiplex signal

Claims

1. Multiple qubits, a generator for generating a plurality of signals; a converter that converts the plurality of signals into a plurality of analog signals with uniform signal levels; a multiplexer that multiplexes the plurality of analog signals and outputs a multiplexed signal; a divider for dividing the multiplexed signal into a plurality of divided signals; a plurality of attenuators attenuating the plurality of split signals and providing the attenuated signals to the plurality of quantum bits, respectively; a setter that transmits a common setting signal indicating the attenuation amount of each of the plurality of attenuators to the plurality of attenuators, The information processing device, wherein the attenuation amounts of the plurality of attenuators are set based on the setting signal.

2. The information processing device according to claim 1 , wherein the setter sets the common setting signal to a setting signal that returns an expected value from some or all of the plurality of quantum bits.

3. 3. The information processing device according to claim 2, wherein the setting device changes the common setting signal to be transmitted to the plurality of attenuators and sets the common setting signal to a setting signal that returns expected values ​​from some or all of the plurality of quantum bits.

4. a computer that changes the common setting signal transmitted from the setting device to the plurality of attenuators and records the setting signal and the quantum bit that returns an expected value in response to the setting signal in a database; The information processing device according to claim 3 , wherein the setter sets the common setting signal to a setting signal identified using the database as a signal that returns an expected value from some or all of the plurality of quantum bits.

5. The information processing device according to claim 2 , wherein the setter sets the common setting signal to a setting signal that returns expected values ​​from the largest number of quantum bits.

6. 5. The information processing device according to claim 2, wherein the setter sets the common setting signal to a setting signal with a central setting value among a plurality of setting signals that return expected values ​​from some or all of the plurality of quantum bits.

7. 5. The information processing device according to claim 2, wherein the setter sets the common setting signal to a setting signal having a maximum setting value among a plurality of setting signals that return expected values ​​from some or all of the plurality of quantum bits.

8. 5. The information processing device according to claim 1, wherein, when it is determined that there is a quantum bit for which an expected value is not returned using the common setting signal, the converter adjusts the signal level of an analog signal for the quantum bit for which an expected value is not returned using the common setting signal, among the plurality of analog signals, to a level value at which an expected value is returned from the quantum bit for which an expected value is not returned using the common setting signal.

9. the plurality of signals includes a plurality of types of signals, the converter converts the plurality of types of signals into the plurality of analog signals with uniform signal levels; the plurality of divided signals include a plurality of types of divided signals corresponding to the plurality of types of signals, The information processing apparatus according to claim 1 , wherein the setting device transmits the common setting signal to the plurality of attenuators so that divided signals of the same type among the plurality of types of divided signals are attenuated by the same attenuation amount.

10. The information processing device according to claim 9 , wherein the plurality of types of signals include a control signal for a quantum bit, a read signal for a quantum bit, and a pump signal for a quantum bit amplifier.

11. the plurality of signals includes a plurality of control signals for qubits; 5. The information processing device according to claim 2, wherein the setting device sets the common setting signal used to attenuate the plurality of divided signals corresponding to the plurality of control signals to a setting signal that returns an expected control result from some or all of the plurality of quantum bits.

12. the plurality of signals includes a plurality of readout signals for quantum bits; 5. The information processing device according to claim 2, wherein the setting device sets the common setting signal used to attenuate the plurality of split signals corresponding to the plurality of readout signals to a setting signal that returns an expected response from some or all of the plurality of quantum bits.

13. the plurality of signals includes a plurality of pump signals controlling amplifiers for qubits; 5. The information processing device according to claim 2, wherein the setting device sets the common setting signal used to attenuate the plurality of split signals corresponding to the plurality of pump signals to a setting signal that returns an expected output level from the amplifiers for some or all of the plurality of quantum bits.

14. a refrigerator having a plurality of chambers arranged so that the temperature decreases gradually; a line extending from the room with the highest temperature to the room with the lowest temperature among the plurality of rooms and transmitting the multiplexed signal to the splitter; The information processing device according to claim 1 , wherein the room with the lowest temperature accommodates the plurality of quantum bits, the divider, and the plurality of attenuators.

15. a generator generating a plurality of signals for a plurality of qubits; The converter aligns the levels of the plurality of signals, a multiplexer that multiplexes the plurality of signals whose levels have been made uniform by the converter and outputs a multiplexed signal; a divider that divides the multiplexed signal into a plurality of divided signals corresponding to the plurality of signals; a plurality of attenuators attenuating the plurality of split signals for the plurality of quantum bits; A method according to claim 1, wherein a setting unit transmits a common setting signal to the plurality of attenuators for setting the attenuation of each of the plurality of attenuators.

16. generating a plurality of signals for a plurality of qubits by a generator; a converter for adjusting the levels of the plurality of signals; a multiplexer multiplexing the plurality of signals whose levels have been made uniform by the converters to output a multiplexed signal; a divider for dividing the multiplexed signal into a plurality of divided signals corresponding to the plurality of signals; attenuating the split signals for the quantum bits with a plurality of attenuators; a setting device transmitting a common setting signal to the plurality of attenuators for setting the attenuation of each of the plurality of attenuators; A program that causes a computer to execute a process.

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