IC device with chip for packaging interconnects from copper metal interconnect levels

Abstract

An integrated circuit device (100) and method includes an IC chip (102) having metal interconnect levels (M1-Mn) including a final copper interconnect level (Mn), and a chip-to-package interconnect (110) overlying and connected to the final copper interconnect level (Mn). The chip-to-package interconnect (110) has a via (112) connected to a first element of the final copper interconnect level (Mn) and a copper conductive structure (118) (e.g., bump copper). The via (112) includes a barrier material (112a) and a tungsten fill layer (112b), and the via is coupled between the copper conductive structure (118) and the first element.

Description

[Technical Field]

[0001] The present invention relates generally to the field of integrated circuit devices, and more particularly to integrated circuit devices having copper interconnect levels. [Background technology]

[0002] Integrated circuits are formed on chips or dies on semiconductor wafers, such as silicon. Each integrated circuit chip typically includes multiple aluminum interconnect levels to interconnect the integrated circuit elements with each other and to provide connections external to the chip. The chip is then assembled and packaged using one of several different packaging technologies. Depending on the packaging technology used, different chip-to-package interconnects are formed to package the chip. Chip-to-package interconnects can include wire bonds, solder bumps, copper pillars, etc. Chip-to-package interconnects connect the top or final metal interconnect level of the chip to, for example, another IC chip or device in the same package or to external pins (e.g., via a lead frame). Summary of the Invention

[0003] The integrated circuit device and method includes an IC chip having metal interconnect levels (M1-Mn) including a final copper interconnect level Mn, and a chip-to-package interconnect overlying and connected to the final copper interconnect level Mn. The chip-to-package interconnect has a via connected to a first element of the final copper interconnect level Mn and a copper conductive structure (e.g., bump copper). The via includes a barrier material and a tungsten fill layer, and the via is coupled between the copper conductive structure and the first element. [Brief explanation of the drawings]

[0004] In the drawings: [Figure 1] FIG. 1 is a flow diagram from wafer fab to assembly packaging of an IC device.

[0005] [Figure 2] 1 is a cross-sectional view of an IC chip-to-IC device according to one embodiment.

[0006] [Figure 3A] 1A-1C are cross-sectional views of an IC device at various stages of IC fabrication according to one embodiment. [Figure 3B] 1A-1C are cross-sectional views of an IC device at various stages of IC fabrication according to one embodiment. [Figure 3C] 1A-1C are cross-sectional views of an IC device at various stages of IC fabrication according to one embodiment. [Figure 3D] 1A-1C are cross-sectional views of an IC device at various stages of IC fabrication according to one embodiment. [Figure 3E] 1A-1C are cross-sectional views of an IC device at various stages of IC fabrication according to one embodiment. [Figure 3F] 1A-1C are cross-sectional views of an IC device at various stages of IC fabrication according to one embodiment.

[0007] [Figure 4] 1 is a cross-sectional view of an IC device according to various embodiments. [Figure 5] 1 is a cross-sectional view of an IC device according to various embodiments. [Figure 6] 1 is a cross-sectional view of an IC device according to various embodiments. [Figure 7] 1 is a cross-sectional view of an IC device according to various embodiments. [Figure 8] 1 is a cross-sectional view of an IC device according to various embodiments. [Figure 9] 1 is a cross-sectional view of an IC device according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0008] The embodiments are described in the context of chip-to-package interconnects for integrated circuit devices having a top / final interconnect level formed by a damascene copper process. The embodiments described below are particularly useful for analog power devices with increased current density requirements, but are also suitable for other devices such as low-power digital devices (sometimes referred to as advanced CMOS).

[0009] As used herein, an integrated circuit device (IC device) refers to an assembly-packaged integrated circuit chip. One exemplary process is shown in FIG. 1. When integrated circuit chips are fabricated on semiconductor wafers in a semiconductor manufacturing facility (fab), they may be bumped, and the wafers may then be transported to an assembly test site for assembly packaging. In some cases, a single site may include both bumping and assembly packaging, or both fab and bumping operations. Exemplary assembly packaging steps include backgrinding, singulation (laser or mechanical sawing), attachment to lead frames, molding, trimming / forming the leads from the lead frames, and pre-shipment testing. Other suitable assembly packaging processes, such as wafer-chip scale packaging, are known in the art and may alternatively be used with the chip-to-package interconnect embodiments described herein.

[0010] An overview of an integrated circuit device 100 according to one embodiment will now be described with reference to FIG. 2. Further details will be described below with reference to FIGS. 3A-3F. An integrated circuit chip 102 is fabricated. Transistors and other devices (not shown) are formed in or on a substrate 104. A first metal interconnect level M1 is formed on the substrate. Additional metal interconnect levels M2-Mn are also formed. The metal interconnect level Mn comprises copper and may be formed using a copper damascene process. The metal interconnect levels M1-Mn-1 may comprise copper (predominantly copper) or aluminum (predominantly aluminum). The metal interconnect levels M1-Mn are used to interconnect transistors and other devices with each other. The final metal interconnect level Mn is also used to make connections external to the chip 102. The final metal interconnect level Mn may be thicker than the lower metal interconnect levels M1-Mn-1, particularly for analog devices. For example, Mn may have a thickness in the range of 0.2 μm to 6 μm. A passivation layer / protective overcoat 106 is formed over the final metal interconnect level Mn. By way of example, the protective overcoat 106 may include a layer of silicon nitride 106a and a layer of silicon nitride or silicon oxynitride 106b.

[0011] Next, the chip-to-package interconnect 110 is formed. This is sometimes referred to as bumping and can be done in a bump facility separate from the fab. Vias 112 and probe contact areas 114 are formed through the passivation layer 106 to elements of the final metal interconnect level Mn. The vias 112 include a tungsten fill layer 112b. The vias 112 may also include a barrier layer 112a. The barrier layer 112a can be, for example, TaN or a stack of TiN on Ti on TaN (TaN / Ti / TiN stack). Other examples include Ta / TaN, TaN / TiN, and Ta / TaN / Ti / TiN stacks (stack materials listed from bottom to top). The barrier layer prevents interaction between the tungsten fill 112b and the copper of the metallization level Mn.

[0012] The probe contact area 114 is used for testing and is wide enough to allow contact by a probe from a probe card. Probe pads are typically located in the scribe area of ​​the wafer, but probe contact areas such as 114 can also be included within the IC chip 102. The probe contact area 114 is significantly wider than the via 112 to allow contact by the probe. Therefore, the tungsten fill layer 112b does not fill the probe contact area 114 in the same way that it fills the via 112. The probe contact area 114 also includes a probe metal stack 116 on the tungsten layer 112b. The probe metal stack 116 is not disposed in or on the via 112. The probe metal stack 116 includes a material that provides a structurally suitable surface for the probe. For example, the probe metal stack 116 can include a layer of palladium (Pd) on a layer of nickel (Ni). The probe metal stack 116 can further include a layer of TaN or other barrier layer below the Ni layer.

[0013] Conductive copper structures 118 are formed over the vias 112 but not over the probe contact areas 114. The conductive copper structures 118 are sometimes referred to as bump copper. With bump copper, the thickness of the conductive copper structures 118 is significantly greater than that of fab metals such as Mn, and the conductive copper structures 118 may have thicknesses ranging from 3 μm to 25 μm for copper interconnects or from 25 μm to 100 μm in height for copper pillars. One or more vias 112 connect each conductive copper structure 118 to elements of the final metal interconnect level Mn.

[0014] After forming the copper structure 118, further assembly and packaging operations occur. These operations may be performed in a separate assembly / test (A / T) facility. These may include solder ball placement in a WCSP process, or attachment to a lead frame or other IC device, singulation, molding, backgrinding, testing, tape, and reel. In one example, the IC chip 102 may then be attached to the structure 122. The IC chip 102 may be flipped over with the structure 122 being a lead frame lead. Alternatively or additionally, the structure 122 may be a contact point for one or more other IC chips. Additionally, the means of attachment may vary depending on the packaging technology utilized. FIG. 2 illustrates the solder connection 120 between the conductive copper structure 118 and the structure 122. The integrated circuit chip 102, the chip-to-package interconnect 110, and the structure 122 are then attached to a mold 130.

[0015] A more detailed process for forming the chip-to-package interconnect 110 with a tungsten via will now be described with reference to FIGS. 3A-3F. FIG. 3A shows the integrated circuit chip 102 after a first opening 302 and a second opening 304 have been formed through the passivation layer 106 to the final metallization level Mn. The integrated circuit chip 102 has completed semiconductor fabrication, meaning that the final metallization level Mn has been formed and covered with the passivation layer 106. The final metallization level Mn comprises copper, rather than aluminum as in prior art analog devices. The final metallization level Mn includes a first element 306a for electrical connection to / from the IC chip 102 within the final IC device and a second element 306b for probe access during testing. The passivation layer may include a layer of silicon dioxide 106a and a layer of silicon nitride or silicon oxynitride 106b.

[0016] First opening 302 is a narrower, via-sized opening, and second opening 304 is a wider, probe pad-sized opening. By way of example, first opening 302 may have a width in the range of 0.1 μm to 1.5 μm, and second opening 304 may have a width in the range of 8 μm to 120 μm. First opening 302 overlaps / exposes first element 306 a, and second opening 304 overlaps / exposes second element 306 b.

[0017] FIG. 3B illustrates the IC chip 102 after forming the via 112. The via 112 may be formed by depositing a conductive barrier layer 112a over the passivation layer 106 and within the first and second openings 302, 304, such that the barrier layer 112a lines the sidewalls and bottom of the first and second openings 302, 304. The barrier layer 112a may include, for example, TaN. Alternatively, the barrier layer 112a may include TiN on Ti on Ta. Other examples include Ta / TaN, TaN / TiN, and TaN / Ti / TiN stacks (where the stack materials are listed from bottom to top). The purpose of the barrier layer 112a is to prevent diffusion of the underlying copper and to allow good adhesion to the tungsten deposited thereon. Tungsten 112b is then deposited over the barrier layer 112a, including the first and second openings 302, 304. Tungsten is deposited to a thickness that fills first opening 302, but because second opening 304 is significantly wider than first opening 302, the tungsten does not fill second opening 304. As shown in Figure 3B, tungsten 112b, along with barrier 112a, may line the sidewalls and bottom of second opening 304. Chemical-mechanical polishing (CMP) is then performed to remove barrier layers 112a and 112b from the surface of passivation layer 106, leaving a filled via 112.

[0018] After forming the filled via 112, a probe metal / metal stack 116 is deposited over the passivation layer 106 and the filled via 112, as shown in FIG. 3B. The probe metal stack 116 is also deposited in the second opening 304. Because the via 112 is completely filled, the probe metal stack 116 does not extend into the first opening 302. The probe metal stack 116 includes a metal suitable for probing without causing extensive wear to the probe card used for probing. One suitable example is Pd on Ni. Another suitable example is a stack of Pd on Ni on TaN. Other examples include Pd on Ni on TaN on Ta or aluminum.

[0019] As shown in FIG. 3D, a second CMP is performed on the probe metal stack 116 to remove the probe metal stack from over the passivation layer 106 and via 112 while leaving the probe metal stack 116 on top of the tungsten 112b and the barrier 112a on the sidewalls and bottom of the second opening 304.

[0020] Because the final metallization level Mn contains copper rather than aluminum, it presents several challenges for probing the IC chip 102. Unlike aluminum, copper oxidizes when exposed to environments such as those required for probing. This is particularly problematic during data-retention bakes, in which the IC chip is subsequently baked for a given period of time and then re-probed. Therefore, it is undesirable to expose the copper during probing and / or to probe between forming the opening in the passivation layer and filling the via. Using tungsten plugs for probing would result in extensive probe card wear, making their use undesirable in manufacturing. Filling the openings above the copper Mn with other materials suitable for probing, such as physical vapor deposition (PVD) aluminum or PVD Ni / Pd, leaves voids when filling narrow vias.

[0021] Accordingly, some embodiments herein utilize narrow and wide openings in the passivation layer to balance the competing requirements of the probe and efficient chip-to-package interconnect formation to provide different surfaces for the narrow first opening 302 (tungsten) and the wide second opening 304 (Pd).

[0022] After the second CMP, the IC chip 102 can be probed. FIG. 3E shows a second opening 304 in the scribe area 320. The scribe area is the area where the IC chip 102 is singulated or separated from the other IC chips on the wafer. This is where a saw or laser passes during assembly packaging. Various test structures can be formed in the scribe area, while the IC chip's functional circuit elements and associated interconnects are located in the die area 322. Optionally, a second opening 304 can also be formed in the die area 322, as shown in FIG. 3E, and can remain part of the completed IC device.

[0023] Referring to FIG. 3F, a copper conductive structure 118 is formed over the via 112. Prior to forming the copper conductive structure 118, a barrier layer 115 may be formed over the via. The barrier layer 115 may include, for example, TiW or Ti. The conductive structure 118 may be formed by forming a pattern and electroplating copper into openings in the pattern. The via 112 electrically connects the copper conductive structure 118 to the first element 306a of the final metallization level Mn. The copper conductive structure 118, sometimes referred to as bump copper, may take many forms, as described below with reference to FIGS. 4-9.

[0024] After forming the copper conductive structure 118, the IC device can be completed by performing any desired assembly packaging steps on the IC chip 102. Several different chip-to-package interconnect and assembly packaging options are described below with respect to Figures 4-9.

[0025] 4 shows an IC chip 402 with bumping in the form of copper pillars 418 (as the copper conductive structures 118 in FIG. 2). Similar to the other embodiments, the IC chip 402 includes a first element 306a and a via 112 through a passivation layer 106. A protective dielectric layer 408 is formed over the passivation layer 106 and the via 112. For example, the protective dielectric layer 408 comprises a polyimide. Other polymers, such as polybenzoxazole (PBO) or bisbenzocyclobutene (BCB), may alternatively be used.

[0026] An opening is formed through the protective dielectric layer 408 to expose the top of the via 112. A barrier layer 415 is formed on the protective layer 408, including in the opening, to contact the top of the via 112. The barrier layer 415 may include, for example, TiW or Ti. A bump copper process is formed on the barrier layer 415 to form a thick copper pillar 418. The copper pillar 418 is significantly thicker than the first element 306a (Mn) and may have a thickness in the range of 25 μm to 100 μm, compared to 0.1 μm to 6 μm for the first element 306a. An adhesive 420, such as solder, is formed on the surface of the copper pillar 418. The IC chip 402 is then transferred to assembly packaging, where the adhesive 420 may be used to connect the copper pillar 418 to a lead frame or the leads of another IC chip after singulation (similar to that described above with respect to FIG. 2), completing the formation of the IC device.

[0027] FIG. 5 illustrates an IC chip 502 with a bump process in the form of a copper conductive structure 518 with an overlying metal 520. The metal 520, sometimes referred to as a wirebond metal stack or a probe metal stack, may include a stack of Ni / Pd or alternatives such as Ni / Au or Ni / Pd / Au or aluminum. A barrier layer 515 is formed on top of the protective layer 106 and abuts the top of the via 112. The barrier layer 515 may include, for example, TiW or Ti. A bump copper process is formed on the barrier layer 515 to form a thick copper conductive structure 518. The copper structure 518 is significantly thicker than the first element 306a (Mn) and may have a thickness ranging from 3 μm to 25 μm. The metal 520 (e.g., Ni / Pd) is formed on the copper structure 518. The IC chip 502 may then be transferred to assembly packaging where it may be wire bonded, singulated, and molded with a molding compound to complete the formation of the IC device.

[0028] FIG. 6 shows an IC chip 602 with bumping in the form of a first copper conductive structure 618 and copper posts 622. A barrier layer 615 is formed on the protective layer 106 and abuts the top of the via 112. The barrier layer 615 may comprise, for example, TiW or Ti. A copper conductive structure 618 is formed on the barrier layer 615. The copper structure 618 is thicker than the first element 306a (Mn) and may have a thickness in the range of 3 μm to 25 μm. Next, a protective dielectric layer 608, such as polyimide, is formed on the IC chip 602. Openings are formed in the protective dielectric layer 608, and copper posts 622 are formed in the openings. The IC chip 602 can then be singulated, for example, at an assembly and packaging facility. The copper posts 622 are attached to a lead frame, and the IC chip 602 is molded.

[0029] FIG. 7 illustrates an IC chip 702 with further processing in the form of a copper redistribution layer 718 (as the copper conductive structure 118 in FIG. 2 ) and an underbump metallization (UBM) layer 722 on which solder balls 724 are disposed. The packaging of the IC device 700 is sometimes referred to as WCSP, where the solder balls 724 are exposed for mounting the completed IC device 700, for example, to a printed circuit board as desired by a customer. A first optional protective dielectric layer 708, such as polyimide, is formed over the IC chip 702. Openings, if present, are formed in the protective dielectric layer 708, and a copper redistribution layer (RDL) 718 is formed over the first protective dielectric layer 708, including within the openings. The RDL layer 718 makes electrical contact to the Mn first elements 306a through the vias 112. A second protective dielectric layer 719, such as polyimide, is formed over the copper RDL 718. Openings are formed in the second protective dielectric layer 719, and a UBM layer 722 is formed over the second protective dielectric layer 719, including within the openings. This process may be performed in a bump facility. After placing the solder balls 724 in the openings, the IC chips 702 are singulated.

[0030] 8 illustrates another wafer-chip-scale type IC device 800 in which the copper conductive features 118 take the form of a UBM layer 818. The IC chip 802 is further processed by applying a protective layer 808, such as polyimide, forming openings in the protective layer 808 to expose the tops of the vias 112, forming a copper UBM layer 818 on the protective layer 808, including in the openings to the contact vias 112, and forming solder balls 824 on the copper UBM layer 818. The UBM layer 818 makes electrical contact to the first elements 306a through the vias 112. After the solder balls 824 are placed, the IC chip 802 is singulated.

[0031] 9 illustrates another wafer-chip-scale type IC device 900 in which the copper conductive features 118 take the form of a UBM layer 818. The IC chip 902 is further processed by forming a copper UBM layer 918 on the passivation layer 106 and forming solder balls 924 on the UBM layer 918. The copper UBM layer 918 makes electrical contact to the first element 306a through the vias 112. After the solder balls 924 are placed, the IC chip 902 is singulated.

[0032] While the present invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. Accordingly, the appended claims encompass any such modifications or examples.

Claims

1. 1. An integrated circuit device comprising: a chip having metal interconnect levels including a final copper interconnect level; a chip-to-package interconnect overlying and connected to the final copper interconnect level, a first via connected to a first element of the final copper interconnect level, the first via having a barrier material on the sidewalls and bottom and tungsten filling the first via, the barrier material comprising Ti, TiN, Ta, TaN, or a combination thereof; a copper conductive structure coupled to the first element through the first via; the chip-to-package interconnect comprising:

1. An integrated circuit device comprising:

2. 10. The integrated circuit device of claim 1, the copper conductive structure is an under-bump metallurgy; The integrated circuit device, wherein the chip-to-package interconnect further comprises a solder bump on the underbump metal structure.

3. 10. The integrated circuit device of claim 1, An integrated circuit device wherein the copper conductive structures are copper pillars.

4. 10. The integrated circuit device of claim 1, An integrated circuit device wherein the copper conductive structure is a copper structure with an overlying Ni / Pd layer.

5. 10. The integrated circuit device of claim 1, The copper conductive structure is a copper structure extending over the first element and a portion of the chip adjacent to the first element; a copper post overlying and connected to the copper structure, the copper post being offset from the first element; 1. An integrated circuit device comprising:

6. 10. The integrated circuit device of claim 1, the copper conductive structure includes a copper structure extending over the first element and a portion of the chip adjacent to the first element; the chip-to-package interconnect comprises: an underbump metal structure offset from the first element; a solder bump on the under-bump metal structure; 10. The integrated circuit device according to claim 9, further comprising:

7. 10. The integrated circuit device of claim 1, The integrated circuit device, wherein the first via extends through a passivation layer.

8. 8. The integrated circuit device of claim 7, The integrated circuit device, wherein the passivation layer comprises an oxide layer and a silicon nitride layer over the oxide layer.

9. 8. The integrated circuit device of claim 7, The integrated circuit device, wherein the passivation layer comprises an oxide layer and a silicon oxynitride layer over the oxide layer.

10. 10. The integrated circuit device of claim 1, The integrated circuit device, wherein the chip-to-package interconnect further includes a second via connected between the first element and the copper conductive structure.

11. 10. The integrated circuit device of claim 1, 10. The integrated circuit device of claim 1, wherein the chip-to-package interconnect further comprises a barrier layer disposed between the first via and the copper conductive structure, the barrier layer comprising TiW or Ti.

12. 10. The integrated circuit device of claim 1, 10. The integrated circuit device of claim 9, wherein the chip-to-package interconnect further comprises a protective dielectric layer disposed between the first via and the copper conductive structure, the protective dielectric layer having an opening through which the first via is connected to the copper conductive structure.

13. 13. The integrated circuit device of claim 12, An integrated circuit device, wherein the protective dielectric layer comprises polyimide, polybenzoxazole (PBO), or bisbenzocyclobutene (BCB).

14. 10. The integrated circuit device of claim 1, the copper conductive structure includes a redistribution layer; the integrated circuit device a polyimide layer on the redistribution layer; an underbump metal structure connected to the redistribution layer through the opening in the polyimide layer; a solder bump on the under-bump metal structure; The integrated circuit device further comprises:

15. 10. The integrated circuit device of claim 1, 1. An integrated circuit device, further comprising: a probe contact area where the chip-to-package interconnect is connected to a second element of the final copper interconnect level, the probe contact area including a second barrier material on sidewalls and a bottom and tungsten on the second barrier material.

16. 16. The integrated circuit device of claim 15, The integrated circuit device, wherein the probe contact area further comprises a probe metal stack on the tungsten.

17. 17. The integrated circuit device of claim 16, An integrated circuit device wherein the probe metal stack comprises a layer of Ni and a layer of Pd.

18. 10. The integrated circuit device of claim 1, the first via has a first width at the bottom and a second width at the top of the first via, the first width and the second width being the same.

19. 1. A method of manufacturing an integrated circuit device, comprising: forming a final metal interconnect level of the integrated circuit chip using a damascene copper process; depositing a passivation layer over the final metal interconnect level; forming a chip-to-package interconnect, forming a first opening and a second opening wider than the first opening in the passivation layer; depositing a barrier layer over the passivation layer and into the first and second openings; depositing tungsten over the barrier layer, the tungsten filling the first opening and lining but not filling the second opening; removing the tungsten and the barrier layer from over the passivation layer by chemical mechanical polishing, leaving the tungsten and the barrier layer in the first and second openings; depositing a probe metal stack over the passivation layer and the first opening, the probe metal stack extending into the second opening but not into the first opening; removing the probe metal stack from over the passivation layer and the first opening, leaving the probe metal stack in the second opening; forming copper conductive structures over the first openings, each copper conductive structure being electrically coupled to the final metal interconnect level by the tungsten in the first opening; forming the chip-to-package interconnect by A method comprising:

20. 20. The method of claim 19, The method wherein the probe metal stack comprises a layer of Ni and a layer of Pd.

21. 20. The method of claim 19, The method, wherein the barrier layer comprises Ti, TiN, Ta, TaN, or a combination thereof.

22. 20. The method of claim 19, The method further includes probing the integrated circuit chip by contacting the probe metal stack in at least some of the second openings.

23. 20. The method of claim 19, The method wherein the copper conductive structure is a copper bump.

24. 20. The method of claim 19, The method wherein the copper conductive structure is an under-bump metal structure underlying a solder bump.

25. 20. The method of claim 19, The method wherein the copper conductive structures are copper pillars.

26. 20. The method of claim 19, the copper conductive structure is a redistribution layer; The method comprises: forming a polyimide layer on the redistribution layer; forming an under-bump metal structure through the polyimide layer to the redistribution layer; forming a solder bump on the under-bump metallurgy; The method further comprises:

27. 20. The method of claim 19, singulating the integrated circuit chips from other integrated circuit chips on a wafer; attaching the integrated circuit chip to a leadframe via the chip-to-package interconnect; applying a molding compound to the integrated circuit chip attached to the lead frame; The method further comprises:

Images