Method for manufacturing aluminum nitride substrate, aluminum nitride substrate, and method for suppressing crack generation in aluminum nitride layer

Abstract

The problem to be solved by the present invention is to provide a novel technique with which it is possible to suppress the occurrence of cracks in an AlN layer. The present invention is a method for producing an AlN substrate, the method including an embrittlement step S10 for lowering the strength of an SiC base substrate 10, and a crystal growth step S20 for forming an AlN layer 20 on the SiC base substrate 10. The present invention is also a method for suppressing the occurrence of cracks in an AlN layer 20, the method including an embrittlement step S10 for lowering the strength of an SiC base substrate 10 prior to forming an AlN layer 20 on the SiC base substrate 10.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing an aluminum nitride substrate, an aluminum nitride substrate, and a method for suppressing the occurrence of cracks in an aluminum nitride layer. [Background technology]

[0002] Ultraviolet light-emitting devices are next-generation light sources that are expected to be used in a wide range of applications, such as sterilization light sources, high-brightness white light sources combined with phosphors, light sources for high-density information recording, light sources for resin curing, etc. Aluminum nitride (AlN) is expected to be a promising semiconductor material for these ultraviolet light-emitting devices.

[0003] Conventionally, the method of manufacturing AlN substrates has been to grow AlN crystal on a base substrate with a different chemical composition from that of the AlN crystal.

[0004] Patent Document 1 describes that a silicon carbide (SiC) substrate is preferably used as a base substrate for AlN crystal growth because it is durable in the high-temperature atmosphere used in the sublimation method and has a small lattice constant mismatch with AlN crystals. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-13390 Summary of the Invention [Problem to be solved by the invention]

[0006] However, Patent Document 1 had a problem in that cracks were likely to occur in the AlN crystal grown on the SiC substrate due to the difference in thermal expansion coefficient between the SiC substrate used to grow the AlN crystal and the AlN crystal itself.

[0007] An object of the present invention is to provide a novel technique that can suppress the occurrence of cracks in an AlN layer. [Means for solving the problem]

[0008] The present invention, which solves the above-mentioned problems, provides a method for manufacturing an aluminum nitride substrate, which includes an embrittlement processing step for reducing the strength of a silicon carbide base substrate, and a crystal growth step for forming an aluminum nitride layer on the silicon carbide base substrate.

[0009] In this way, by including a brittle processing step that reduces the strength of the SiC base substrate, stress generated in the AlN layer can be released to the SiC base substrate, preventing cracks from occurring in the AlN layer.

[0010] In a preferred embodiment of the present invention, the embrittlement processing step includes a through-hole forming step of forming through-holes in the silicon carbide base substrate, and a strained layer removing step of removing the strained layer introduced by the through-hole forming step.

[0011] In a preferred embodiment of the present invention, the through-hole forming step is a step of forming the through-hole by irradiating the silicon carbide base substrate with a laser.

[0012] In a preferred embodiment of the present invention, the strained layer removal step is a step of etching the silicon carbide base substrate by heat treatment.

[0013] In a preferred embodiment of the present invention, the strained layer removal step is a step of etching the silicon carbide base substrate in a silicon atmosphere.

[0014] In a preferred embodiment of the present invention, the crystal growth step is a step of growing the crystal by physical vapor transport.

[0015] The present invention also relates to a method for suppressing cracking in an AlN layer. That is, the present invention, which solves the above-mentioned problems, is a method for suppressing cracking in an aluminum nitride layer, which includes an embrittlement process step of reducing the strength of a silicon carbide base substrate before forming an aluminum nitride layer on the silicon carbide base substrate.

[0016] In a preferred embodiment of the present invention, the embrittlement processing step includes a through-hole forming step of forming through-holes in the silicon carbide base substrate, and a strained layer removing step of removing the strained layer introduced by the through-hole forming step.

[0017] In a preferred embodiment of the present invention, the strained layer removal step is a step of removing the strained layer of the silicon carbide base substrate by heat treatment.

[0018] In a preferred embodiment of the present invention, the silicon carbide base substrate is silicon carbide, and the strained layer removal step is a step of etching the silicon carbide base substrate in a silicon atmosphere. [Effects of the Invention]

[0019] The disclosed technology can provide a novel technology that can suppress the occurrence of cracks in the AlN layer.

[0020] Other objects, features and advantages will become apparent from a reading of the following detailed description when taken in conjunction with the drawings and claims. [Brief explanation of the drawings]

[0021] [Figure 1] 2A to 2C are explanatory diagrams illustrating steps of a method for manufacturing an AlN substrate according to an embodiment. [Figure 2] 2A to 2C are explanatory diagrams illustrating steps of a method for manufacturing an AlN substrate according to an embodiment. [Figure 3] 10A to 10C are explanatory views of a through-hole forming step according to the embodiment. [Figure 4]FIG. 2 is an explanatory diagram illustrating a crystal growth process according to an embodiment. [Figure 5] FIG. 3 is an explanatory view of a through-hole forming step according to the first embodiment. [Figure 6] FIG. 4 is an explanatory diagram of a strained layer removing step according to the first embodiment. [Figure 7] FIG. 2 is an explanatory diagram of a crystal growth process according to Example 1. [Figure 8] FIG. 3 is an explanatory diagram of a temperature lowering step according to Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0022] Preferred embodiments of the AlN substrate manufacturing method according to the present invention will be described in detail below with reference to the accompanying drawings. The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and appropriate modifications are possible within the scope of the claims. Furthermore, the accompanying drawings are conceptual diagrams, and the relative dimensions of each component do not limit the present invention. Furthermore, in this specification, for the purpose of explaining the invention, the top and bottom may be referred to based on the top and bottom of the drawings, but this does not limit the top and bottom in relation to the use mode of the AlN substrate of the present invention. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0023] <<Manufacturing method for AlN substrates>> 1 and 2 show steps in a method for manufacturing an AlN substrate according to an embodiment of the present invention. The method for manufacturing an AlN substrate according to the embodiment may include a brittle processing step S10 for reducing the strength of the SiC base substrate 10, a crystal growth step S20 for forming an AlN layer 20 on the SiC base substrate 10, and a temperature reduction step S30 for reducing the temperature of the SiC base substrate 10 and the AlN layer 20 after the crystal growth step S20.

[0024] Furthermore, this embodiment can be understood as a method for suppressing the occurrence of cracks in the AlN layer 20 by including a brittle processing step S10 for reducing the strength of the SiC base substrate 10 before forming the AlN layer 20 on the SiC base substrate 10. Each step of the embodiment will be described in detail below.

[0025] <Brittle processing process> The embrittlement processing step S10 is a step of reducing the strength of the SiC base substrate 10. In other words, the embrittlement processing step S10 is a step of processing the SiC base substrate 10 so that it is easily deformed or broken by an external force. In yet other words, the embrittlement processing step S10 is a step of increasing the brittleness of the SiC base substrate 10. In this specification, "strength" refers to the ability to withstand physical external forces such as compression and tension, and includes the concept of mechanical strength.

[0026] The embrittlement processing step S10 according to the embodiment reduces the strength of SiC base substrate 10 by forming through holes 11 in SiC base substrate 10. In other words, by reducing the volume of SiC base substrate 10, processing is performed so that it can be easily deformed or broken by an external force.

[0027] More specifically, the embrittlement processing step S10 includes a through hole formation step S11 for forming through holes 11 in the SiC base substrate 10, and a strained layer removal step S12 for removing the strained layer 12 introduced by this through hole formation step S11.

[0028] The SiC base substrate 10 may be a wafer or substrate processed from a bulk crystal, or may be a substrate having a buffer layer made of the semiconductor material described above.

[0029] The through hole forming step S11 is a step of reducing the strength of the SiC base substrate 10 by forming through holes 11 in the SiC base substrate 10. Naturally, any method that can form through holes 11 in the SiC base substrate 10 can be used for this through hole forming step S11.

[0030] The through-holes 11 can be formed, for example, by laser processing, focused ion beam (FIB) system, reactive ion etching (RIE) or other plasma etching. Note that Fig. 2 showing this embodiment illustrates a method for forming the through-holes 11 by irradiating the SiC base substrate 10 with a laser L.

[0031] The through-hole 11 may be formed in one or more shapes that reduce the strength of the SiC base substrate 10. Alternatively, a through-hole group (pattern) in which a plurality of through-holes 11 are arranged may be used.

[0032] An example of a pattern for growing a hexagonal semiconductor material will now be described in detail. FIG. 3 is an explanatory diagram illustrating a pattern 100 according to an embodiment. The line segments shown in the pattern 100 represent the SiC substrate 10. The pattern 100 preferably has a regular hexagonal displaced shape with three-fold symmetry. The "regular hexagonal displaced shape" in the description of this specification will be explained in detail below with reference to FIG. 3. The regular hexagonal displaced shape is a dodecagon. The regular hexagonal displaced shape is composed of 12 straight line segments of equal length. The regular hexagonal displaced shape pattern 100 contains a reference figure 101 that is a regular triangle, has an area 101a, and includes three vertices 104. Each of the three vertices 104 is included in the vertices of the pattern 100. It can be understood that the three vertices 104 may be located on the line segments that constitute the pattern 100. Pattern 100 includes line segment 102 (corresponding to a first line segment) that extends from and includes vertex 104, and line segment 103 (corresponding to a second line segment) that does not extend from vertex 104 and is adjacent to line segment 102 without including vertex 104. Here, the angle θ formed by the two adjacent line segments 102 in pattern 100 is constant and equal to the angle θ formed by the two adjacent line segments 103 in pattern 100. Note that the term "regular hexagon-displaced shape" in the description herein can be understood to mean a dodecagon formed by displacing / deforming a regular hexagon while maintaining the area of ​​the regular hexagon based on angle θ, which indicates the degree of irregularity.

[0033] The angle θ is preferably greater than 60°, and is preferably 66° or greater, and is preferably 80° or greater, and is preferably 83° or greater, and is preferably 120° or greater, and is preferably 150° or greater, and is preferably 155° or greater. The angle θ is preferably 180° or less, and is preferably 155° or less, and is preferably 150° or less, and is preferably 120° or less, and is preferably 83° or less, and is preferably 80° or less, and is preferably 66° or less.

[0034] The pattern 100 according to the embodiment may have a configuration of a displaced regular dodecagon with six-fold symmetry, instead of a displaced regular hexagon with three-fold symmetry. The displaced regular dodecagon is a 24-sided polygon. The displaced regular dodecagon is composed of 24 straight line segments of equal length. The pattern 100 having a displaced regular dodecagon contains a reference figure 101 that is a regular hexagon, has an area 101a, and includes six vertices 104. Each of the six vertices 104 is included as a vertex of the pattern 100. As with the displaced regular hexagon, the angle θ between two adjacent line segments 102 in the pattern 100 is constant and equal to the angle θ between two adjacent line segments 103 in the pattern 100. In other words, the "regular dodecagon-displaced shape" in the description herein can be understood as a 24-gon obtained by displacing (deforming) a regular dodecagon while maintaining the area of ​​the regular dodecagon based on the angle θ, which indicates the degree of irregularity. Note that the pattern 100 may be configured to present a 2n-gon-displaced shape, which is a 4n-gon obtained by displacing (deforming) a regular 2n-gon while maintaining the area of ​​the regular 2n-gon based on the angle θ, which indicates the degree of irregularity. In this case, the 2n-gon-displaced shape can be understood to include a regular n-gon (corresponding to the reference figure 101). Here, the reference figure 101 can be understood to include n vertices.

[0035] The pattern 100 according to the embodiment may include a displaced regular 2n-gon shape (including a displaced regular hexagon shape and a displaced regular dodecagon shape). The pattern 100 may further include, in addition to the line segments constituting the displaced regular 2n-gon shape, at least one line segment (corresponding to a third line segment) connecting the intersection of two adjacent line segments 103 in the displaced regular 2n-gon shape to the center of gravity of the reference figure 101. The pattern 100 may further include, in addition to the line segments constituting the displaced regular 2n-gon shape, at least one line segment connecting the intersection of two adjacent line segments 103 in the displaced regular 2n-gon shape to a vertex 104 constituting the reference figure 101. The pattern 100 may further include, in addition to the line segments constituting the displaced regular 2n-gon shape, at least one line segment constituting the reference figure 101 included in the displaced regular 2n-gon shape.

[0036] Furthermore, the through-hole forming step S11 is preferably a step of removing 50% or more of the effective area of ​​the SiC base substrate 10. More preferably, it is a step of removing 60% or more of the effective area, even more preferably, it is a step of removing 70% or more of the effective area, and even more preferably, it is a step of removing 80% or more of the effective area.

[0037] In this specification, the term "effective area" refers to the surface of the SiC base substrate 10 to which the source material adheres in the crystal growth step S20. In other words, it refers to the remaining area on the growth surface of the SiC base substrate 10 other than the area removed by the through holes 11.

[0038] The strained layer removal step S12 is a step of removing the strained layer 12 formed in the SiC base substrate 10 by the through-hole formation step S11. This strained layer removal step S12 can naturally be adopted by any means capable of removing the strained layer 12 introduced into the SiC base substrate 10.

[0039] The strained layer 12 can be removed by, for example, a hydrogen etching method using hydrogen gas as an etching gas, a Si-Vapor Etching (SiVE) method in which heating is performed under a Si atmosphere, or an etching method described in Example 1 below.

[0040] <Crystal growth process> The crystal growth step S20 is a step of forming an AlN layer 20 on the SiC base substrate 10 after the embrittlement processing step S10.

[0041] The crystal growth step S20 can employ known vapor phase growth methods (corresponding to vapor phase epitaxial methods) such as physical vapor transport (PVT), sublimation recrystallization, modified Rayleigh process, chemical vapor transport (CVT), molecular-organic vapor phase epitaxy (MOVPE), and hydride vapor phase epitaxy (HVPE) as a growth method for the AlN layer 20. Note that the crystal growth step S20 can employ physical vapor deposition (PVD) instead of PVT. Note that the crystal growth step S20 can employ chemical vapor deposition (CVD) instead of CVT.

[0042] FIG. 4 is an explanatory diagram illustrating the crystal growth step S20 according to the embodiment. The crystal growth step S20 according to the embodiment is a step of arranging the SiC base substrate 10 and the semiconductor material 40, which will be the raw material for the AlN layer 20, facing each other in a crucible 30 having a semi-closed space, and heating them. Note that the "semi-closed space" in this specification refers to a space in which the inside of the container can be evacuated, but which is also capable of containing at least a portion of the vapor generated within the container.

[0043] Furthermore, the crystal growth step S20 is a step of heating so as to form a temperature gradient along the vertical direction of the SiC base substrate 10. By heating the crucible 30 (SiC base substrate 10 and semiconductor material 40) in this temperature gradient, the raw material is transported from the semiconductor material 40 onto the SiC base substrate 10 via the raw material transport space 31. The above-mentioned temperature gradient can be used as the driving force for transporting the raw material.

[0044] Specifically, within the semi-closed space, vapor consisting of elements sublimated from semiconductor material 40 is transported by diffusion within source transport space 31, and condenses in a supersaturated state onto SiC base substrate 10, which is set at a lower temperature than semiconductor material 40. As a result, AlN layer 20 is formed on SiC base substrate 10.

[0045] In this crystal growth step S20, an inert gas or a doping gas may be introduced into the source material transport space 31 to control the doping concentration and growth environment of the AlN layer 20. In addition, in the crystal growth step S20, it is preferable to introduce nitrogen gas so that the inside of the source material transport space 31 is filled with a nitrogen atmosphere for growth.

[0046] In this embodiment, the AlN layer 20 is formed by the PVT method, but any method that can form the AlN layer 20 can be naturally adopted.

[0047] <Temperature cooling process> The temperature-lowering step S30 is a step of lowering the temperatures of the SiC base substrate 10 and AlN layer 20 that were heated in the crystal growth step S20.

[0048] In the temperature-lowering step S30, the SiC base substrate 10 and the AlN layer 20 contract in accordance with their respective thermal expansion coefficients as the temperature drops. At this time, a difference in contraction rate occurs between the SiC base substrate 10 and the AlN layer 20.

[0049] According to this embodiment, the strength of SiC base substrate 10 is reduced in embrittlement processing step S10, so even if there is a difference in the shrinkage rates between SiC base substrate 10 and AlN layer 20, SiC base substrate 10 will deform or cracks 13 will form (see Figures 2 and 8).

[0050] According to the present invention, by including the embrittlement processing step S10 that reduces the strength of the SiC base substrate 10, stress generated between the SiC base substrate 10 and the AlN layer 20 can be released to the SiC base substrate 10, thereby suppressing the occurrence of cracks in the AlN layer 20. [Example]

[0051] The present invention will be explained more specifically with reference to Example 1 and Comparative Example 1. AlN has a lattice mismatch with SiC of about 1%, and a thermal expansion coefficient difference with SiC of about 23%. In Example 1, the stress caused by this lattice mismatch and thermal expansion coefficient difference is released to the SiC base substrate 10, thereby suppressing the occurrence of cracks in the AlN layer 20.

[0052] Example 1 <Through hole formation step S11> A laser was irradiated onto a SiC base substrate 10 under the following conditions to form through-holes 11.

[0053] (SiC base substrate 10) Semiconductor material: 4H-SiC Board size: 11mm wide x 11mm long x 524μm thick Growth aspect: Si-face Off-axis angle: on-axis

[0054] (Laser processing conditions) Type: Green laser Wavelength: 532nm Spot diameter: 40 μm Average output power: 4W (at 30kHz)

[0055] (Pattern details) 5A and 5B are explanatory diagrams illustrating the pattern of through holes 11 formed in the through hole forming step S11 according to Example 1. Fig. 5A is an explanatory diagram showing an arrangement of a plurality of through holes 11. In Fig. 5A, the black areas indicate the portions of the through holes 11, and the white areas are left as the SiC base substrate 10.

[0056] Fig. 5(b) is an explanatory diagram showing an enlarged view of the through-hole 11 in Fig. 5(a). In Fig. 5(b), the white area indicates the through-hole 11, and the black area is the SiC base substrate 10 that remains. In the pattern of FIG. 5, 80% or more of the effective area of ​​the SiC base substrate 10 is removed, reducing the strength of the SiC base substrate 10.

[0057] (Strained layer removal process S12) FIG. 6 is an explanatory diagram illustrating the strained layer removing step S12 according to the first embodiment. The SiC base substrate 10 in which the through-holes 11 were formed in the through-hole forming step S11 was housed in a SiC container 50, which was then housed in a TaC container 60 and heated under the following conditions.

[0058] (Heating conditions) Heating temperature: 1800℃ Heating time: 2h Etching amount: 8 μm

[0059] (SiC container 50) Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Distance between the SiC substrate 10 and the bottom of the SiC container 50: 2 mm

[0060] (Details of the SiC container 50) 6, the SiC container 50 is a fitting container having an upper container 51 and a lower container 52 that can fit together. A minute gap 53 is formed at the fitting portion between the upper container 51 and the lower container 52, and the SiC container 50 is configured so that the inside of the SiC container 50 can be evacuated (vacuumed) through this gap 53.

[0061] The SiC container 50 has an etching space 54 formed by arranging a part of the SiC container 50 located on the low temperature side of the temperature gradient opposite the SiC base substrate 10, with the SiC base substrate 10 located on the high temperature side of the temperature gradient. This etching space 54 is a space in which Si atoms and C atoms are transported from the SiC base substrate 10 to the SiC container 50, causing etching, using the temperature difference between the SiC base substrate 10 and the bottom surface of the SiC container 50 as a driving force.

[0062] Furthermore, SiC vessel 50 has substrate holder 55 that holds SiC base substrate 10 in the air and forms etching space 54. Note that substrate holder 55 may not be provided depending on the direction of the temperature gradient in the heating furnace. For example, if the heating furnace forms a temperature gradient such that the temperature decreases from lower vessel 52 to upper vessel 51, SiC base substrate 10 may be placed on the bottom surface of lower vessel 52 without providing substrate holder 55.

[0063] (TaC container 60) Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 64 (Si compound): TaSi2

[0064] (Details of TaC container 60) Similar to the SiC container 50, the TaC container 60 is a fitting container having an upper container 61 and a lower container 62 that can fit together, and is configured to be able to house the SiC container 50. A minute gap 63 is formed at the fitting portion between the upper container 61 and the lower container 62, and the TaC container 60 is configured to be able to be evacuated (vacuumed) through this gap 63.

[0065] The TaC container 60 has a Si vapor supply source 64 capable of supplying vapor pressure of a gaseous species containing Si element into the TaC container 60. The Si vapor supply source 64 may be configured to generate vapor pressure of a gaseous species containing Si element inside the TaC container 60 during heat treatment.

[0066] <Crystal growth process S20> FIG. 7 is an explanatory diagram illustrating the crystal growth step S20 according to the first embodiment. The SiC base substrate 10 from which the strained layer 12 had been removed in the strained layer removal step S12 was placed opposite the semiconductor material 40 and placed in the crucible 30, and heated under the following conditions.

[0067] (Heating conditions) Heating temperature: 2040℃ Heating time: 70h Growth thickness: 500 μm N2 gas pressure: 10kPa

[0068] (crucible 30) Material: Tantalum carbide (TaC) and / or tungsten (W) Container size: 10mm x 10mm x 1.5mm Distance between SiC substrate 10 and semiconductor material 40: 1 mm

[0069] (Details of Crucible 30) Crucible 30 has a source material transport space 31 between SiC base substrate 10 and semiconductor material 40. Source material is transported from semiconductor material 40 onto SiC base substrate 10 via source material transport space 31.

[0070] 7(a) shows an example of a crucible 30 used in the crystal growth step S20. Similar to the SiC container 50 and the TaC container 60, this crucible 30 is a fitting container including an upper container 32 and a lower container 33 that can fit together. A minute gap 34 is formed at the fitting portion between the upper container 32 and the lower container 33, and the crucible 30 is configured so that the inside of the crucible 30 can be evacuated (evacuated) through this gap 34.

[0071] Furthermore, crucible 30 has substrate holder 35 that forms raw material transport space 31. Substrate holder 35 is provided between SiC base substrate 10 and semiconductor material 40, and forms raw material transport space 31 by placing semiconductor material 40 on the high-temperature side and SiC base substrate 10 on the low-temperature side.

[0072] Figures 7(b) and 7(c) show other examples of crucible 30 used in crystal growth step S20. The temperature gradient in Figures 7(b) and 7(c) is set to be the opposite of that in Figure 7(a), with SiC base substrate 10 placed on the upper side. That is, similar to Figure 7(a), a raw material transport space 31 is formed with semiconductor material 40 placed on the high-temperature side and SiC base substrate 10 placed on the low-temperature side.

[0073] FIG. 7(b) shows an example in which a source material transport space 31 is formed between the SiC base substrate 10 and the semiconductor material 40 by fixing the SiC base substrate 10 to the upper vessel 32 side. 7(c) shows an example in which a through window is formed in upper vessel 32 and SiC base substrate 10 is placed therein, thereby forming raw material transport space 31 between upper vessel 32 and lower vessel 33. Alternatively, as shown in FIG. 7(c), raw material transport space 31 may be formed by providing intermediate member 36 between upper vessel 32 and lower vessel 33.

[0074] (Semiconductor Materials 40) Material: AlN sintered body Size: Width 20mm x Height 20mm x Thickness 5mm

[0075] (Details of Semiconductor Material 40) The AlN sintered body of the semiconductor material 40 was sintered by the following procedure. The AlN powder was placed in the frame of a TaC block and compressed with a moderate force.The compressed AlN powder and TaC block were then placed in a pyrolytic carbon crucible and heated under the following conditions.

[0076] Heating temperature: 1850℃ N2 gas pressure: 10kPa Heating time: 3h

[0077] <Temperature cooling process> Finally, the SiC base substrate 10 and AlN layer 20 after the crystal growth step S20 were cooled under the following conditions.

[0078] (Temperature-lowering conditions) Substrate temperature before cooling: 2040℃ Substrate temperature after cooling: Room temperature Cooling rate: 128℃ / min

[0079] 7 is an SEM image of the SiC base substrate 10 and AlN layer 20 cooled under the above conditions, observed from the SiC base substrate 10 side. It can be seen that cracks 13 have formed in the SiC base substrate 10.

[0080] A plurality of cracks 13 were observed in the SiC base substrate 10 of the AlN substrate produced in Example 1. On the other hand, no cracks were observed in the AlN layer 20. That is, it was confirmed that there were no cracks in the entire 10 mm × 10 mm area of ​​the AlN crystal growth surface (0001).

[0081] Comparative Example 1 The same SiC base substrate 10 as in Example 1 was subjected to the crystal growth step S20 and the temperature-lowering step S30 under the same conditions as in Example 1. That is, in Comparative Example 1, the embrittlement processing step S10 was not performed, and the crystal growth step S20 was performed.

[0082] No cracks 13 were observed in the SiC base substrate 10 of the AlN substrate manufactured in Comparative Example 1. On the other hand, in the AlN layer 20, cracks 13 were observed in the SiC base substrate 10 of the AlN substrate manufactured in Comparative Example 1. -1 Cracks were observed at a crack linear density of 100 mm. In this specification, the crack linear density refers to the value obtained by dividing the total length of all cracks observed in the measurement area by the measurement area (total crack length (mm) / measurement area (mm -2 ) = crack linear density (mm -1 )).

[0083] From the results of Example 1 and Comparative Example 1, it can be seen that by reducing the strength of the SiC base substrate 10 by the embrittlement processing step S10, the stress generated in the AlN layer 20 can be released to the SiC base substrate 10, thereby suppressing the occurrence of cracks in the AlN layer 20.

[0084] 10 SiC base substrate 11 Through hole 12 Strain layer 13 Crack 20 AlN layer 30 Crucible 31 Raw material transportation space 40 Semiconductor Materials 50 SiC container 60 TaC container S10 Brittle processing process S11 Through-hole formation process S12 Deviated Layer Removal Project S20 Crystallization Growth Project S30 Cooling Project

Claims

1. a brittle processing step for reducing the strength of the silicon carbide substrate; a crystal growth step of forming an aluminum nitride layer on the silicon carbide base substrate; the embrittlement processing step includes a through-hole forming step of forming a through-hole in the silicon carbide base substrate, A method for manufacturing an aluminum nitride substrate, wherein the through-hole forming step is a step of removing 50% or more of the effective area, which is the area of ​​the surface of the silicon carbide base substrate to which the raw material for the aluminum nitride layer adheres in the crystal growth step.

2. A method for manufacturing an aluminum nitride substrate as described in claim 1, further comprising a strain layer removal process for removing the strain layer introduced by the through hole formation process.

3. The method for manufacturing an aluminum nitride substrate according to claim 2 , wherein the through-hole forming step is a step of forming the through-holes by irradiating the silicon carbide base substrate with a laser.

4. 4. The method for producing an aluminum nitride substrate according to claim 2, wherein the strained layer removal step is a step of removing the strained layer of the silicon carbide base substrate by heat treatment.

5. 5. The method for producing an aluminum nitride substrate according to claim 2, wherein the strained layer removal step is a step of etching the silicon carbide base substrate in a silicon atmosphere.

6. 6. The method for producing an aluminum nitride substrate according to claim 1, wherein the crystal growth step is a step of growing the crystal by a physical vapor transport method.

7. a brittle processing step of reducing the strength of the silicon carbide substrate before forming an aluminum nitride layer on the silicon carbide substrate; the embrittlement processing step includes a through-hole forming step of forming a through-hole in the silicon carbide base substrate, A method for suppressing the occurrence of cracks in an aluminum nitride layer, wherein the through-hole forming step is a step of removing 50% or more of the area of ​​the growth surface of the silicon carbide base substrate on which the aluminum nitride layer is to be formed.

8. The method described in claim 7, further comprising a strain layer removal process for removing the strain layer introduced by the through hole formation process.

9. The method of claim 8 , wherein the strained layer removal step is a step of etching the silicon carbide base substrate by heat treatment.

10. 10. The method according to claim 8, wherein the strained layer removal step is a step of etching the silicon carbide base substrate in a silicon atmosphere.

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