Method for manufacturing silicon epitaxial substrate and silicon epitaxial substrate

Abstract

To provide a method for manufacturing a silicon epitaxial substrate, capable of suppressing the occurrence of a stacking fault, and the silicon epitaxial substrate.SOLUTION: A method for manufacturing a silicon epitaxial substrate comprises: the growth step of adding phosphorus as a dopant to grow a silicon single crystal having an electrical resistivity controlled to 0.6-1.0 mΩcm by the Czochralski method; the step of monitoring a transit time at 700-600°C when cooling the silicon single crystal; the step of slicing the silicon single crystal to put the slices into an epitaxial growth furnace; the holding step of maintaining the temperature of the epitaxial growth furnace at 750°C or more and 900°C or less when the transit time at 700-600°C is less than 300 minutes or at 900°C or more and 1000°C or less when the transit time is 300 minutes or more, for 120-300 seconds; and the epitaxial growth step of performing epitaxial growth.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a silicon epitaxial substrate and a silicon epitaxial substrate. [Background technology]

[0002] Epitaxial silicon wafers for power MOSFETs (metal oxide semiconductor field effect transistors) require substrates with low resistivity, and to date, substrates with a resistivity of 1 mΩ·cm or less are known. One method for lowering the substrate resistivity of silicon wafers is to add arsenic (As) or antimony (Sb) as n-type dopants for resistivity adjustment to the molten silicon during the silicon single crystal ingot pulling process. However, because these dopants are highly volatile, it is difficult to increase the dopant concentration in the silicon single crystal, and as a result, the substrate resistivity cannot be sufficiently reduced. For this reason, the n-type dopant species has shifted from As and Sb to phosphorus (P), and the concentration is approximately 1×10 20 It is about atoms / cc.

[0003] However, by adding a high concentration of phosphorus during single crystal ingot growth, If the resistivity is reduced to 1.1 mΩ·cm or less, it is known that when an epitaxial layer is grown on a silicon wafer cut from such a single crystal ingot, numerous stacking faults (hereinafter also referred to as "SFs") occur in the epitaxial layer. These stacking faults appear as steps on the surface of the epitaxial silicon wafer and are detected as an increase in the number of light point defects (LPDs) on the wafer surface.

[0004] For example, Patent Document 1 and Non-Patent Documents 1 and 2 describe a technique for producing silicon single crystals with an electrical resistivity of 0.6 to 1.0 mΩ cm while reducing stacking faults by limiting the time spent at 700 to 600°C during the cooling process during silicon single crystal growth to less than 300 minutes. Patent Document 2 also describes reducing stacking faults by performing a heat treatment at 700 to 1050°C for 30 to 450 seconds before epitaxial growth. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-109807 [Patent Document 2] Japanese Patent Application Publication No. 2019-186449 [Non-patent literature]

[0006] [Non-Patent Document 1] The 78th Autumn Meeting of the Japan Society of Applied Physics "Structural Analysis of Si-P Precipitates in Highly Red Phosphorus-Doped CZ-Si Crystals" (7p-PB6-5) [Non-patent document 2] The 67th Autumn Meeting of the Japan Society of Applied Physics "SiP Precipitate Formation Behavior in Highly Phosphorus-Doped CZ-Si Crystals" (15p-D411-1) Summary of the Invention [Problem to be solved by the invention]

[0007] Incidentally, stacking faults that occur in epitaxial layers are caused by phosphorus and silicon precipitates (Si-P defects) that form during the crystal growth process of the substrate crystal, and these are thought to be the starting points for stacking faults during the epitaxial growth process. Therefore, in order to suppress the occurrence of stacking faults, it is necessary to work together to suppress the occurrence of Si-P defects during the crystal growth process and to prevent Si-P defects from becoming the starting points for stacking faults.

[0008] However, for example, the technology of Patent Document 1 focuses on the crystal growth process, and the technology of Patent Document 2 focuses on the epitaxial growth process, and the crystal growth history is not reflected in the epitaxial growth process.

[0009] In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a silicon epitaxial substrate and a silicon epitaxial substrate that suppresses the occurrence of stacking faults. [Means for solving the problem]

[0010] A method for manufacturing a silicon epitaxial substrate that has been devised to achieve the above object includes the steps of: growing, by the Czochralski method, a silicon single crystal in which phosphorus has been added as a dopant and the electrical resistivity has been adjusted to 0.6 to 1.0 mΩ cm; monitoring the time it takes for the silicon single crystal to pass through a temperature range of 700 to 600°C as it is cooled; slicing the silicon single crystal and placing it in an epitaxial growth furnace; maintaining the furnace temperature of the epitaxial growth furnace at a temperature between 750°C and 900°C for 120 to 300 seconds if the time it takes to pass through the temperature range of 700 to 600°C is less than 300 minutes, or at a temperature between 900°C and 1000°C for 300 minutes or more; and performing epitaxial growth after the maintaining step.

[0011] If Si-P defects formed during cooling of silicon single crystals simultaneously dissolve the contained phosphorus into the surroundings and escape outside the substrate during the epitaxial growth process, it is believed that this will adversely affect (remain or increase) the distortion of the crystal structure caused by the Si-P precipitates. The manufacturing method of silicon epitaxial substrates configured as described above performs the process of dissolving phosphorus (P) from the Si-P precipitates into the surroundings and escaping outside the substrate continuously and steadily, thereby reducing the residual distortion of the crystal structure of the substrate surface. This makes it possible to suppress the occurrence of stacking faults.

[0012] In the holding step, it is preferable to maintain the furnace temperature of the epitaxial growth furnace at 750°C or higher and 875°C or lower for 120 seconds to 300 seconds when the time required for passing through the 700-600°C temperature range is less than 200 minutes, and at 825°C or higher and 900°C or lower for 200 minutes or higher and less than 300 minutes.

[0013] Furthermore, it is preferable to perform hydrogen chloride etching at 1150° C. or higher but lower than 1200° C. between the holding step and the epitaxial growth step, followed by hydrogen heat treatment at 1150° C. or higher but lower than 1200° C. This effectively removes residual silicon lattice distortion and further reduces the occurrence of stacking faults.

[0014] Furthermore, it is preferable to form a chemical oxide film of 0.5 nm or more using ozone water before the low-temperature holding step. In the low-temperature holding step, it is important that the oxide film on the substrate surface is stable, and for this purpose, an ozone oxide film is suitable.

[0015] The length of the tail portion of the ingot produced in the final stage of the growth process is preferably 0 to 50 mm. By setting the length of the tail portion to 0 to 50 mm, the time required to pull up the silicon single crystal at 700 to 600°C, which is the growth temperature of Si-P defects, can be shortened.

[0016] From the viewpoint of the product, the manufacturing method of the silicon epitaxial substrate is to adjust the electrical resistivity to 0.8 to 0.9 mΩ cm and to adjust the density of Si-P precipitates with a maximum side length of 35 nm or more to 3E11 / cm. 3 The silicon epitaxial substrate is obtained by growing a silicon epitaxial layer on a semiconductor substrate having a temperature of 750°C or more and 900°C or less for 120 to 300 seconds before growing the silicon epitaxial layer. [Effects of the Invention]

[0017] According to each aspect of the present invention, it is possible to provide a method for manufacturing a silicon epitaxial substrate that suppresses the occurrence of stacking faults, and a silicon epitaxial substrate. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a schematic diagram of a pulling device for the Czochralski method. [Figure 2] FIG. 2 is a schematic diagram of the epitaxial growth furnace. [Figure 3] FIG. 3 is a graph showing the dependency of stacking faults on the holding temperature when the time spent passing through the temperature range of 700° C. to 600° C. is less than 200 minutes. [Figure 4] FIG. 4 is a graph showing the dependency of stacking faults on the holding temperature when the time required to pass through the temperature range of 700° C. to 600° C. is 200 minutes or more and less than 300 minutes. [Figure 5] FIG. 5 is a graph showing the dependency of stacking faults on the holding temperature when the temperature range from 700° C. to 600° C. is passed for 300 minutes or more. [Figure 6] FIG. 6 is a graph showing the dependence of crystal growth of stacking faults on the time it takes to pass through temperatures between 700°C and 600°C. [Figure 7] FIG. 7 is a graph showing the dependence of the crystal growth of Si—P precipitates on the time of passing through 700-600° C. [Figure 8]FIG. 8 is a graph showing the relationship between the occurrence of stacking faults and the density of Si—P precipitates in the examples. [Figure 9] FIG. 9 is a graph showing the relationship between the occurrence of stacking faults and the density of Si—P precipitates in the comparative example. [Figure 10] FIG. 10 is a flowchart showing a method for manufacturing a silicon epitaxial substrate. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiments described below. In addition, the same or corresponding elements in each drawing are appropriately designated by the same reference numerals. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from those in reality. There may also be parts in which the dimensional relationships and ratios differ between the drawings.

[0020] First, a pulling apparatus and an epitaxial growth furnace used in a method for manufacturing a silicon epitaxial substrate according to an embodiment of the present invention will be described.

[0021] Fig. 1 is a schematic diagram of a pulling apparatus using the Czochralski method. The pulling apparatus shown in Fig. 1 has a rotatable quartz crucible 3 filled with raw material melt 2 installed in the center of a furnace 1. A side heater 4 for heating the quartz crucible 3 from the periphery and a bottom heater 5 for heating the quartz crucible 3 from the bottom are installed around the quartz crucible 3. In addition, a radiation shield 6 is installed above the quartz crucible 3 to control the temperature of the raw material melt 2 in the quartz crucible 3 and the single crystal 9 to be pulled.

[0022] In a single crystal pulling apparatus using the Czochralski method, a seed crystal 8 held at the lower end of a wire 7 is placed on the surface of the raw material melt 2 in a quartz crucible 3, and the wire 7 is pulled up while the quartz crucible 3 and the seed crystal 8 are both rotated, thereby growing a single crystal 9. Here, it is assumed that phosphorus is added as a dopant to the raw material melt 2, and the electrical resistivity is adjusted to 0.6 to 1.0 mΩ cm.

[0023] Fig. 2 is a schematic diagram of an epitaxial growth furnace. As shown in Fig. 2, in an epitaxial growth furnace 10, a semiconductor substrate W is placed on a susceptor 14 installed in a chamber 11. The susceptor 14 and the semiconductor substrate W are then rotated in a predetermined direction around a rotation axis O. A heater outside the chamber 11 heats the semiconductor substrate W to a predetermined temperature, while a reactive gas G is supplied horizontally from a reactive gas supply pipe 12 to an exhaust pipe 13. This causes an epitaxial layer to grow on the surface of the semiconductor substrate W.

[0024] Here, we will explain the process by which Si-P defects become the starting point for stacking faults. Based on this consideration, the present invention suppresses the occurrence of stacking faults.

[0025] In silicon single crystals, the higher the temperature, the higher the concentration of phosphorus that can be dissolved in the silicon single crystal. On the other hand, the lower the temperature, the less phosphorus can be dissolved in the silicon single crystal at a high concentration.

[0026] Therefore, in the process of growing a silicon single crystal by the Czochralski method, even if it is possible to dissolve phosphorus in the raw material melt at a high concentration, phosphorus that does not dissolve in the single crystal 9 forms precipitates during the process of pulling the single crystal 9 from the raw material melt 2. In particular, in the single crystal 9 that is doped with phosphorus at a high concentration to reduce resistivity, the concentration is about 1×10 20 It has been found from Patent Document 1 that the concentration is about atoms / cc, and that precipitates of phosphorus and silicon (Si-P precipitates) are formed particularly when the temperature of the single crystal 9 is in the range of 600°C to 700°C.

[0027] On the other hand, during the epitaxial growth process, the temperature inside the epitaxial growth furnace 10 is 1000°C or higher, so the Si-P precipitates formed during the crystal growth process are re-melted and diffused. However, distortions remain in the crystal structure where the Si-P precipitates were formed, and this is thought to be the starting point for the occurrence of stacking faults.

[0028] Here, if the dissolution of phosphorus contained in the Si-P precipitates into the surroundings and the dissolved phosphorus (P) escaping outside the substrate occur simultaneously, it is thought that this will have an adverse effect (remain or increase) on the distortion of the crystal structure caused by the Si-P precipitates.Therefore, we conducted the following verification experiment based on the hypothesis that the residual distortion of the crystal structure on the surface of the substrate will be reduced by making the process of phosphorus (P) dissolving from the Si-P precipitates into the surroundings and the dissolved phosphorus (P) escaping outside the substrate occur continuously and in a steady state.

[0029] [Verification experiment 1] First, phosphorus-doped silicon single crystals were grown by the Czochralski method with a resistivity of 0.7–0.9 mΩ·cm. The crystal orientation was (001), diameter was 200 mm, and the oxygen concentration was 0.9E18 atoms / cc.

[0030] During this crystal growth, the crystal length and cooling time of the tail portion of the ingot were controlled, and the following three types of passing times from 700°C to 600°C were created. (1) Less than 200 minutes (2) 200 minutes or more but less than 300 minutes (3) 300 minutes or more

[0031] After that, various silicon single crystals were sliced, and a backside oxide film was formed and mirror-finished.Furthermore, these semiconductor substrates were treated with 1 ppm ozone water to form a chemical oxide film 0.7 nm thick on the surface.

[0032] The wafer was then placed in an epitaxial growth furnace, and the occurrence of stacking faults (i.e., the number of light point defects (LPDs)) was measured while varying the temperature conditions prior to epitaxial growth. Figures 3 to 5 are graphs showing the dependence of stacking faults on the holding temperature when the temperature was passed through a range of 700°C to 600°C for (1) less than 200 minutes, (2) 200 to 300 minutes, and (3) 300 minutes or more. The holding times at each temperature were from 120 to 300 seconds, and the left end of the horizontal axis of the graphs shows the case where no low-temperature holding was performed.

[0033] 3 to 5, regardless of the time spent at 700°C to 600°C during crystal growth, the dependence of stacking faults on the holding temperature before epitaxial growth is downward convex. In other words, the optimal holding temperature before epitaxial growth is preferably neither too low nor too high, but within a certain range.

[0034] 3 to 5, the optimum holding temperature in the stage before epitaxial growth shifts to a higher temperature depending on the time spent passing through the 700°C to 600°C range during crystal growth. Specifically, when the time spent passing through the 700°C to 600°C range during crystal growth is (1) less than 200 minutes, the optimum holding temperature in the stage before epitaxial growth is 750°C to 875°C, (2) when the time spent passing through the 700°C to 600°C range during crystal growth is 200 minutes to less than 300 minutes, the optimum holding temperature is 825°C to 900°C, and (3) when the time spent passing through the 700°C to 600°C range is 300 minutes or more, the optimum holding temperature is 900°C to 1000°C.

[0035] Furthermore, as can be seen by comparing the graphs in Figures 3 to 5, the shapes of the graphs differ significantly depending on whether the crystal growth time is between 700°C and 600°C (1) less than 200 minutes, (2) between 200 and 300 minutes, or (3) 300 minutes or more. This is also evident from Figure 6, which is a graph showing the dependency of stacking faults on the time spent growing at 700°C to 600°C. In the graph in Figure 6, solid plots are used for cases where a low-temperature holding time was provided prior to epitaxial growth, and open plots are used for cases where no low-temperature holding time was provided prior to epitaxial growth.

[0036] As can be seen from the graph in Figure 6, the occurrence of stacking faults can be reduced by providing a low-temperature holding time prior to epitaxial growth, but when the time spent at 700°C to 600°C during crystal growth exceeds 300 minutes, the effect of reducing the occurrence of stacking faults decreases.

[0037] Therefore, when a low-temperature holding time is set before epitaxial growth, it is possible to distinguish between cases where the time spent passing through the temperature range of 700°C to 600°C during crystal growth is 300 minutes or more. That is, it is effective to divide the low-temperature holding time before epitaxial growth into cases where the time spent passing through the temperature range of 700°C to 600°C during crystal growth is less than 300 minutes, where the furnace temperature of the epitaxial growth furnace is maintained at 750°C to 900°C for 120 to 300 seconds, and cases where the time spent passing through the temperature range of 700°C to 600°C for 300 minutes or more, where the furnace temperature is maintained at 900°C to 1000°C for 120 to 300 seconds.

[0038] [Verification experiment 2] Next, we investigated the relationship between the Si-P precipitates formed during the crystal growth process and the reduction of stacking faults. Figure 7 is a graph showing the dependence of Si-P precipitates on the time spent at 700-600°C during crystal growth. The horizontal axis of the graph in Figure 7 represents the time spent at 700-600°C during crystal growth, and the vertical axis represents the density ( / cm) of Si-P precipitates larger than 35 nm.

[0039] As can be seen from Figure 7, by setting the time for passing through the temperature range of 700-600°C during crystal growth to less than 300 minutes, the density of Si-P precipitates larger than 35 nm was reduced to 3 × 10 11 In other words, controlling the time spent passing through the 700-600°C temperature range during crystal growth makes it possible to keep the density of Si-P precipitates low from the perspective of the manufacturing method.

[0040] Meanwhile, there is a close relationship between the density of Si-P precipitates and the low-temperature holding condition prior to epitaxial growth. Figures 8 and 9 are graphs showing the relationship between the occurrence of stacking faults and the density of Si-P precipitates, respectively, with and without low-temperature holding condition prior to epitaxial growth. In the graphs shown in Figures 8 and 9, the horizontal axis represents the density ( / cm) of Si-P precipitates larger than 35 nm before epitaxial growth, and the vertical axis represents the occurrence of stacking faults after epitaxial growth, measured as light point defects (LPD).

[0041] As can be seen from Fig. 8, the density of Si-P precipitates larger than 35 nm before epitaxial growth was set to 3 × 10 11 If the thickness is smaller than 100 nm, light point defects (LPD) after epitaxial growth can be further reduced.

[0042] As can be seen from comparing the graphs in Figures 8 and 9, low-temperature holding prior to epitaxial growth results in smaller variance in the relationship between stacking fault occurrence and Si-P precipitate density. This means that stacking fault occurrence can be more effectively reduced by not only controlling the 700-600°C passing time during crystal growth, but also by combining it with low-temperature holding prior to epitaxial growth. Because there is smaller variance in the relationship between stacking fault occurrence and Si-P precipitate density, it is not only possible to reduce stacking fault occurrence, but it is also possible to reduce variation between products.

[0043] [Summary of manufacturing method] Fig. 10 is a flowchart showing a method for manufacturing a silicon epitaxial substrate that reflects the results of the above verification experiment. As shown in Fig. 10, the method for manufacturing a silicon epitaxial substrate includes a single crystal growth step (S1), a monitoring step (S2), a slicing and oxide film formation step (S3), a furnace loading step (S4), a low-temperature holding step (S5), an etching step (S6), and an epitaxial growth step (S7).

[0044] In the single crystal growth step (S1), a silicon single crystal is grown using a pulling device based on the Czochralski method. Here, phosphorus is added as a dopant to the raw material melt, and the electrical resistivity is adjusted to 0.6 to 1.0 mΩ·cm.

[0045] In the monitoring step (S2), the time it takes for the silicon single crystal to pass through the temperature range of 700-600°C as it is cooled is monitored. The length of the tail of the ingot produced at the final stage of the growth step is preferably 0-50 mm. By setting the length of the tail to 0-50 mm, the time it takes to pull the silicon single crystal at the growth temperature of 700-600°C, which is the Si-P defect growth temperature, can be shortened.

[0046] In the slicing and oxide film formation process (S3), the silicon single crystal is sliced, an oxide film is formed on the backside, and then a mirror finish is applied. An oxide film is then formed on the surface of this substrate. Specifically, it is preferable to treat the substrate with ozone water and form a chemical oxide film 0.7 nm thick on the surface. As mentioned above, it is important that the oxide film on the substrate surface is stable in the subsequent low-temperature holding process (S5), and for this purpose, an ozone oxide film is suitable.

[0047] In the furnace loading step (S4), the silicon semiconductor substrate is loaded into an epitaxial growth furnace.

[0048] In the low-temperature holding step (S5), the temperature of the epitaxial growth furnace is raised, but is maintained at a temperature lower than the temperature for epitaxial growth for 120 to 300 seconds. Specifically, if the time it takes for the silicon single crystal to pass through the 700-600°C range during cooling monitored in the monitoring step (S2) is less than 300 minutes, the temperature is preferably set to 750°C or higher but 900°C or lower, and if it takes 300 minutes or longer, the temperature is preferably set to 900°C or higher but 1000°C or lower.

[0049] Furthermore, in the low-temperature holding step (S5), if the time it takes for the silicon single crystal to pass through the temperature range of 700-600°C during cooling monitored in the monitoring step (S2) is less than 200 minutes, it is more preferable to hold the temperature at 750°C or higher and 875°C or lower, and if the time is 200 minutes or higher and less than 300 minutes, it is more preferable to hold the temperature at 825°C or higher and 900°C or lower.

[0050] In the etching step (S6), hydrogen chloride etching is performed at a temperature of 1150°C or higher but lower than 1200°C, followed by hydrogen heat treatment at a temperature of 1150°C or higher but lower than 1200°C. This effectively removes residual silicon lattice distortion and further reduces the occurrence of stacking faults.

[0051] In the epitaxial growth step (S7), a Si epitaxial layer is formed at 1100-1150°C. [Explanation of symbols]

[0052] 1 furnace 2 Raw material melt 3 Quartz crucible 4 Side heater 5 Bottom heater 6 Radiation Shield 7 wire 8 seed crystals 9 crystal 10 Epitaxial growth equipment 11 Chamber 12 Reaction gas supply pipe 13 Exhaust W semiconductor substrate

Claims

1. a growing step of growing a silicon single crystal by the Czochralski method, the silicon single crystal having an electrical resistivity adjusted to 0.6 to 1.0 mΩ cm by adding phosphorus as a dopant; monitoring the time it takes for the silicon single crystal to pass through 700-600°C as it cools; Slicing the silicon single crystal and placing it in an epitaxial growth furnace; a holding step of maintaining the furnace temperature of the epitaxial growth furnace at 750°C or higher but 900°C or lower for 120 seconds to 300 seconds when the time for passing through the 700-600°C temperature range is less than 300 minutes, or at 900°C or higher but 1000°C or lower for 300 minutes or longer; an epitaxial growth step of performing epitaxial growth after the holding step; A method for manufacturing a silicon epitaxial substrate having the above structure.

2. 2. The method for producing a silicon epitaxial substrate according to claim 1, wherein in the holding step, the furnace temperature of the epitaxial growth furnace is maintained at 750°C or higher and 875°C or lower for 120 seconds to 300 seconds when the passage time from 700 to 600°C is less than 200 minutes, or at 825°C or higher and 900°C or lower for 120 seconds to 300 seconds when the passage time from 700 to 600°C is 200 minutes or higher and less than 300 minutes.

3. 3. The method for manufacturing a silicon epitaxial substrate according to claim 1, wherein a hydrogen chloride etching process is performed at a temperature of 1150°C or higher but lower than 1200°C between the holding step and the epitaxial growth step, and a hydrogen heat treatment process is then performed at a temperature of 1150°C or higher but lower than 1200°C.

4. 4. The method for producing a silicon epitaxial substrate according to claim 1, wherein a chemical oxide film having a thickness of 0.5 nm or more is formed using ozone water before the holding step.

5. 5. The method for producing a silicon epitaxial substrate according to claim 1, wherein the length of the tail portion of the ingot produced in the final stage of the growing step is 0 to 50 mm.

Images