circuit board

Abstract

A circuit board according to an embodiment includes a first substrate layer and a second substrate layer disposed on the first substrate layer and including a cavity, the cavity of the second substrate layer including a first part disposed adjacent to an upper surface of the second substrate layer and having a first slope such that its width gradually decreases toward a lower surface of the second substrate layer, and a second part disposed below the first part and adjacent to the lower surface of the second substrate layer and having a second slope such that its width gradually decreases toward the lower surface of the second substrate layer, wherein the first slope of the first part relative to a bottom surface of the cavity is greater than the second slope of the second part relative to the bottom surface of the cavity, and a vertical length of the first part is different from the vertical length of the second part.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board, and more particularly to a circuit board including an antenna pattern and an antenna package substrate. [Background technology]

[0002] Recently, efforts have been made to develop improved 5th generation (5G) or pre-5G communication systems to meet the demand for wireless data traffic.

[0003] To achieve high data transmission rates, 5G communication systems use ultra-high frequency (mmWave) bands (sub 6G (6 GHz), 28G (28 GHz), 38G (38 GHz) or higher frequencies). These high frequency bands are called mm-Wave due to the length of their wavelengths.

[0004] In order to mitigate the path loss of radio waves in the ultra-high frequency band and increase the transmission distance of radio waves, integration technologies such as beamforming, massive MIMO, and array antennas are being developed for 5G communication systems.

[0005] Considering that a wavelength in such a frequency band consists of several hundred active antennas, the antenna system becomes relatively large.

[0006] This means that the multiple boards that make up an active antenna system, namely the antenna board, antenna feed board, transceiver board, and baseband board, must be integrated into one compact unit.

[0007] Therefore, the circuit board applied to the conventional 5G communication system has a structure in which a large number of substrates are integrated as described above, and therefore has a relatively large thickness. Therefore, in the past, the overall thickness of the circuit board was reduced by reducing the thickness of the insulating layer constituting the circuit board.

[0008] However, there is a limit to how thin the insulating layer can be when manufacturing a circuit board, and as the insulating layer becomes thinner, the circuit pattern cannot be stably protected. Summary of the Invention [Problem to be solved by the invention]

[0009] In the embodiments, a circuit board with a new structure and an antenna package substrate including the same are provided.

[0010] Also, the present invention provides a circuit board capable of slimming down the circuit board and an antenna package substrate including the same.

[0011] Furthermore, the embodiments provide a circuit board and an antenna package substrate including the same that can minimize the distance between a signal line on which a driving element is arranged and a signal line on which an antenna pattern is arranged.

[0012] In addition, the present invention provides a circuit board including a cavity in which a driving element is mounted, and an antenna package substrate including the same.

[0013] In addition, the present invention provides a circuit board including a cavity having at least two different slopes, and an antenna package substrate including the same.

[0014] Also, the present invention provides a circuit board and a package substrate including the same that can minimize damage to pads exposed through cavities during a laser process for forming the cavities.

[0015] The technical problems to be solved in the embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the present invention pertains from the following description. [Means for solving the problem]

[0016] A circuit board according to an embodiment includes a first substrate layer and a second substrate layer disposed on the first substrate layer and including a cavity, wherein the cavity of the second substrate layer includes a first part disposed adjacent to an upper surface of the second substrate layer and having a first slope such that its width gradually decreases toward a lower surface of the second substrate layer, and a second part disposed below the first part and adjacent to the lower surface of the second substrate layer and having a second slope such that its width gradually decreases toward the lower surface of the second substrate layer, wherein the first slope of the first part relative to a bottom surface of the cavity is greater than the second slope of the second part relative to the bottom surface of the cavity, and the vertical length of the first part is different from the vertical length of the second part.

[0017] The first inclination of the first part relative to the bottom surface of the cavity ranges from 115 degrees to 150 degrees, and the second inclination of the second part relative to the bottom surface of the cavity ranges from 91 degrees to 120 degrees.

[0018] Furthermore, the vertical length of the first part is shorter than the vertical length of the second part.

[0019] The vertical length of the second part is in the range of 1.5 to 30 times the vertical length of the first part.

[0020] The first substrate layer includes at least one first insulating layer, a first circuit pattern layer disposed on the at least one first insulating layer, and a first through electrode portion that penetrates the at least one first insulating layer, and the second substrate layer includes a plurality of second insulating layers, a second circuit pattern layer disposed on the plurality of second insulating layers, and a second through electrode portion that penetrates at least one of the plurality of second insulating layers.

[0021] In addition, the second circuit pattern layer of the second substrate layer includes a first antenna pattern layer.

[0022] The first substrate layer also includes a first region that vertically overlaps the cavity and a second region other than the first region, and the upper surface of the first region of the first substrate layer has a step with the upper surface of the second region of the first substrate layer, and the bottom surface of the cavity is located lower than the lower surface of the second substrate layer.

[0023] In addition, the first circuit pattern layer formed in the second region of the first substrate layer includes a second antenna pattern layer connected to the first antenna pattern layer.

[0024] The first insulating layer includes a 1-1 insulating layer disposed closest to the second substrate layer, and the upper surface of the 1-1 insulating layer includes a first upper surface vertically overlapping the cavity and a second upper surface excluding the first upper surface, and the first upper surface and the second upper surface have a step.

[0025] The first circuit pattern layer also includes a first circuit pattern arranged on the upper surface of the 1-1 insulating layer, and the first circuit pattern includes a 1-1 pattern arranged on the first upper surface of the 1-1 insulating layer and vertically overlapping the cavity, and a 1-2 pattern arranged on the second upper surface of the 1-1 insulating layer.

[0026] In addition, the upper surface of the 1-1 pattern is located lower than the upper surface of the 1-2 pattern.

[0027] The first circuit pattern layer also includes a 1-3 pattern disposed on the second upper surface of the 1-1 insulating layer adjacent to the cavity, the side surface of which overlaps the cavity in the horizontal direction.

[0028] The cavity also includes a third part having a third slope corresponding to the side surface of the first-third pattern.

[0029] Meanwhile, an antenna package substrate according to an embodiment includes a first substrate layer and a second substrate layer disposed on the first substrate layer, the first substrate layer including at least one first insulating layer and a first circuit pattern layer disposed on the at least one first insulating layer, the second substrate layer including a plurality of second insulating layers and a second circuit pattern layer disposed on the plurality of second insulating layers and constituting an antenna pattern, the second substrate layer including a cavity penetrating the plurality of second insulating layers, and the first insulating layer including a 1-1 insulating layer disposed so as to be closest to the first substrate layer. The first circuit pattern layer includes a first circuit pattern disposed on the upper surface of the 1-1 insulating layer, and the first circuit pattern includes a 1-1 pattern formed in a first region vertically overlapping the cavity and a 1-2 pattern formed in a second region excluding the first region, and the upper surface of the 1-1 pattern includes a circuit board located lower than the upper surface of the 1-2 pattern, a connection portion disposed on the 1-1 pattern of the circuit board, an element mounted on the connection portion, and a molding layer disposed in the cavity while covering the element.

[0030] The cavity further includes a first part disposed adjacent to the upper surface of the second substrate layer and having a first slope such that its width gradually decreases toward the lower surface of the second substrate layer, and a second part disposed adjacent to the upper surface of the first substrate layer and having a second slope such that its width gradually increases toward the upper surface of the first substrate layer, wherein the first slope of the first part relative to the bottom surface of the cavity is greater than the second slope of the second part relative to the bottom surface of the cavity, and the vertical length of the first part is different from the vertical length of the second part.

[0031] The first inclination of the first part relative to the bottom surface of the cavity ranges from 115 degrees to 150 degrees, and the second inclination of the second part relative to the bottom surface of the cavity ranges from 91 degrees to 110 degrees.

[0032] Furthermore, the vertical length of the first part is shorter than the vertical length of the second part. [Effects of the Invention]

[0033] According to the embodiment, the circuit board includes a first substrate layer and a second substrate layer. The second substrate layer includes a cavity. The first substrate layer includes a first region vertically overlapping the cavity and a second region excluding the first region. The second substrate layer also includes a third region corresponding to the cavity and a fourth region excluding the third region. In this embodiment, the third region of the second substrate layer is a region where a driving element is disposed, and the fourth region is a region where an antenna pattern layer is disposed. In the above embodiment, the driving element is disposed using the cavity of the second substrate layer, and the antenna pattern layer is disposed in the fourth region of the second substrate layer horizontally adjacent to the driving element. As a result, in the embodiment, the signal transmission distance between the antenna pattern layer and the driving element can be minimized, thereby minimizing signal transmission loss. For example, in the embodiment, the signal transmission distance can be reduced compared to the comparative example in which a substrate on which a driving element is disposed and a substrate on which an antenna pattern layer is disposed are connected using a separate connection means, thereby reducing signal transmission loss caused by the separate connection means. In addition, in the embodiment, the antenna pattern layer and the driving element are arranged horizontally, so that the second region of the first substrate layer, which vertically overlaps with the fourth region of the second substrate layer, can be utilized as a second antenna pattern layer, thereby enabling antenna pattern radiation and signal reception in different directions with a single circuit pattern.

[0034] In addition, in an embodiment, by locating the driving elements in the cavities of the second substrate layer, the overall thickness of the circuit board can be reduced to correspond to the depth of the cavities.

[0035] In addition, the cavity in the embodiment includes a first part having a first slope and a second part having a second slope different from the first slope. The second slope has a smaller slope angle relative to the bottom surface of the cavity than the first slope. The vertical length of the second part having the second slope in the embodiment is longer than the vertical length of the first part having the first slope. As a result, the space occupied by the cavity in the embodiment can be reduced compared to the comparative example, thereby improving circuit integration. For example, by reducing the space occupied by the cavity in the embodiment, the length of the antenna pattern layer can be increased within a substrate having the same size as the comparative example, thereby improving communication performance.

[0036] In addition, in the embodiment, the first substrate layer includes a 1-1 insulating layer disposed adjacent to the first substrate layer and a first circuit pattern disposed on an upper surface of the 1-1 insulating layer. The first circuit pattern includes a 1-1 pattern formed in a first region vertically overlapping the cavity and a 1-2 pattern formed in a second region excluding the first region, and the upper surface of the 1-1 pattern is located lower than the upper surface of the 1-2 pattern. As a result, in the embodiment, damage to the surface of the 1-1 pattern can be prevented during a laser process for forming the cavity, thereby improving the electrical and physical reliability of the circuit board. [Brief explanation of the drawings]

[0037] [Figure 1a] 10 is a diagram showing a circuit board of a comparative example. [Figure 1b] 1 is a diagram showing an antenna package substrate of a comparative example. [Figure 2] 1 is a diagram showing a circuit board according to an embodiment; [Figure 3a] FIG. 3 is an enlarged view of the cavity region of FIG. 2 according to the first embodiment. [Figure 3b] FIG. 3 is an enlarged view of the cavity region of FIG. 2 according to the second embodiment. [Figure 3c] FIG. 10 is an enlarged view of a cavity region according to a third embodiment. [Figure 4a] 10 is a plan view of the second substrate layer as seen from above. [Figure 4b] 10 is a plan view of the second substrate layer as seen from above. [Figure 5] 1 is a diagram illustrating an antenna package substrate according to an embodiment. [Figure 6a] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6b] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6c] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6d] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6e] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6f] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6g] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6h] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6i] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6j] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6k] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6l] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6m]3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6n] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. [Figure 6o] 3 is a diagram illustrating a method for manufacturing the circuit board according to the embodiment illustrated in FIG. 2 in a process order. DETAILED DESCRIPTION OF THE INVENTION

[0038] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0039] However, the technical concept of the present invention is not limited to the described embodiments, but can be embodied in various forms, and components between the embodiments can be selectively combined or substituted within the scope of the technical concept of the present invention.

[0040] Furthermore, unless otherwise clearly and specifically stated, terms (including technical and scientific terms) used in the embodiments of the present invention shall be interpreted as meanings that are commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs, and commonly used terms, such as terms defined in a dictionary, shall be interpreted in light of the contextual meaning of the relevant technology.

[0041] Furthermore, the terms used in the examples of the present invention are intended to explain the examples and are not intended to limit the present invention. In this specification, the singular form can include the plural form unless otherwise specified, and when it is described as "A and at least one (or one or more) of B and C," it can include one or more of all possible combinations of A, B, and C.

[0042] Furthermore, in describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are used to distinguish the component from other components, and do not limit the nature or order of the components. When a component is described as being "coupled," "coupled," or "connected" to another component, this may include cases where the component is directly coupled or connected to the other component, as well as cases where other components are further "coupled," "coupled," or "connected" between the components.

[0043] Furthermore, when it is stated that something is formed or disposed "above or below" a component, "above or below" does not only mean that the two components are in direct contact with each other, but also means that one or more other components are formed or disposed between the two components. Furthermore, when it is expressed as "above or below," it can mean not only the upper direction but also the lower direction based on one component.

[0044] Before describing the embodiments of the present invention, a circuit board according to a comparative example will be described. Preferably, an antenna circuit board for an antenna package will be described below.

[0045] FIG. 1a is a diagram showing a circuit board of a comparative example, and FIG. 1b is a diagram showing an antenna package substrate of a comparative example.

[0046] FIG. 1a(a) is a diagram showing a first substrate of a comparative example, and FIG. 1a(b) is a diagram showing a second substrate of a comparative example.

[0047] Referring to (a) and (b) of FIG. 1a, the comparative example includes a first substrate 10 and a second substrate 20. As shown in FIG.

[0048] The first substrate 10 can also be referred to as an antenna substrate on which an antenna pattern is arranged. For example, the first substrate 10 can be an antenna package substrate that configures an antenna unit.

[0049] The first substrate 10 includes a plurality of insulating layers.

[0050] For example, the first substrate 10 may have a multi-insulating layer structure to improve the radiation characteristics of the antenna pattern, such as a 1-1 insulating layer 11, a 1-2 insulating layer 12, and a 1-3 insulating layer 13.

[0051] The first substrate 10 includes a first circuit pattern 14 disposed on a plurality of insulating layers. For example, the first circuit pattern 140 may represent an antenna pattern on the first substrate 10 that transmits a signal to the outside or receives a signal transmitted from the outside.

[0052] The first circuit pattern 14 is disposed on the surface of each of a plurality of insulating layers.

[0053] For example, the first circuit pattern 14 is disposed on the lower surface of the 1-1 insulating layer 11. For example, the first circuit pattern 14 is disposed between the upper surface of the 1-1 insulating layer 11 and the lower surface of the 1-2 insulating layer 12. For example, the first circuit pattern 14 is disposed between the upper surface of the 1-2 insulating layer 12 and the lower surface of the 1-3 insulating layer 13. For example, the first circuit pattern 14 is disposed on the upper surface of the 1-3 insulating layer 13.

[0054] The first substrate 10 also includes through electrodes 15. The through electrodes 15 are formed to penetrate a plurality of insulating layers constituting the first substrate 10. For example, the through electrodes 15 are formed to penetrate the 1-1 insulating layer 11, the 1-2 insulating layer 12, and the 1-3 insulating layer 13. Thus, the through electrodes 15 can electrically connect first circuit patterns disposed in different insulating layers to each other.

[0055] The second substrate 20 is manufactured in a separate process from the first substrate 10.

[0056] For example, in the comparative example, the first substrate 10 and the second substrate 20 are manufactured in separate processes, and then a process of bonding them is performed.

[0057] The second substrate 20 includes a second insulating layer 21. At this time, the second insulating layer 21 may have a single layer structure, or alternatively, may have a multi-layer structure.

[0058] The second substrate 20 includes a second circuit pattern 22 disposed on the surface of the second insulating layer 21. For example, the second substrate 20 includes a second circuit pattern disposed on the upper surface of the second insulating layer 21. At this time, the second circuit pattern disposed on the upper surface of the second insulating layer 21 can be used as a mounting pad for mounting a device. The second substrate 20 also includes a second circuit pattern disposed on the lower surface of the second insulating layer 21. At this time, the second circuit pattern disposed on the lower surface of the second insulating layer 21 can function to connect the device and the first substrate 10.

[0059] For example, a first connection portion 24 and a second connection portion 26 are disposed on the second circuit pattern disposed on the upper surface of the second insulating layer 21. The first connection portion 24 and the second connection portion 26 may represent solder balls.

[0060] Also, a driving element 25 is disposed on the first connection portion 24. The driving element 25 may refer to an element for driving an antenna in the antenna device. For example, the driving element 25 may transmit a transmission signal to the first substrate 10, thereby transmitting a radio signal corresponding to the transmission signal to the outside via an antenna pattern. The driving element 25 may also receive a reception signal via the first substrate 10 and analyze the reception signal to confirm reception information.

[0061] In addition, a passive element 25 is disposed on the second connection portion 37. The passive element 25 may be an element for supporting the operation of the driving element 25. For example, the passive element 25 may include a resistor, a capacitor, an inductor, etc.

[0062] The second substrate 20 also includes a second through electrode 23 disposed in the second insulating layer 23. The second through electrode 23 electrically connects second circuit patterns disposed in different layers of the second insulating layer 23. For example, the second through electrode 23 may electrically connect the driving element 25 and the antenna pattern of the first substrate 10 to each other.

[0063] Meanwhile, referring to FIG. 1b, the antenna package substrate of the comparative example has a structure in which the first substrate 10 and the second substrate 20, which are manufactured through separate processes as described above, are joined by solder balls 30.

[0064] At this time, the solder balls 30 are covered with a separate molding layer 40 .

[0065] 1b, the antenna package substrate of the comparative example has a first substrate 10 constituting an antenna pattern and a second substrate 20 including a driving element and a passive element, which are vertically aligned and combined together. The antenna package substrate of the comparative example has a structure in which a separate connecting means (e.g., solder balls 30) is disposed between the first substrate 10 and the second substrate 20, and the first substrate 10 and the second substrate 20 are electrically connected to each other by the connecting means.

[0066] Therefore, in the comparative example, since the first substrate 10 and the second substrate 20 are interconnected by the solder balls 30, the thickness of the antenna package substrate increases by the height of the solder balls 30.

[0067] In addition, in the comparative example, the first substrate 10 and the second substrate 20 are interconnected in a vertically stacked structure by the solder balls 30 as described above, which increases the signal transmission length, and there is a problem that signal loss increases due to the longer transmission length (e.g., signal transmission distance).

[0068] In the comparative example, the first substrate 10 and the second substrate 20 are connected to each other using a separate flexible circuit board (not shown) instead of the solder balls 30. However, when the first substrate 10 and the second substrate 20 are electrically connected to each other using the flexible circuit board, the signal transmission distance increases by the length of the flexible circuit board even though the first substrate and the second substrate have a horizontally arranged structure, which causes a problem of increased signal loss.

[0069] Meanwhile, in the case of an antenna device applied to a 5G communication system, more data is transmitted and received than in existing communication systems, and transmitting and receiving such a large amount of data increases battery consumption and requires a larger battery capacity. In addition, increasing the battery capacity requires a larger battery size, which in turn requires a larger battery installation space.

[0070] As a result, in a typical 5G communication system, the thickness of the antenna package substrate is reduced to increase the size of the battery while maintaining the size of the antenna device (e.g., mobile terminal).

[0071] In order to reduce the thickness of the antenna package substrate, it is necessary to reduce the thickness of the insulating layer and the antenna pattern constituting the antenna package substrate, but there is a limit to how much they can be reduced. Also, if the thickness of the antenna pattern is reduced too much, there is a problem that communication performance is reduced (e.g., the transmission strength of a transmission signal or the reception strength of a reception signal is reduced), and if the thickness of the insulating layer is reduced, there is a problem that the antenna pattern is not stably protected, resulting in communication errors.

[0072] Therefore, in the embodiment, an antenna unit having an antenna pattern and a driving unit having a driving element are formed on a single circuit board, thereby eliminating the need for separate connection means such as solder balls or a flexible circuit board. Also, in the embodiment, a cavity in which a driving element is disposed is formed on the circuit board, and the driving element is disposed in the formed cavity, thereby reducing the overall thickness of the circuit board. Also, in the embodiment, the antenna unit and the driving unit are structured to be arranged horizontally rather than vertically on a single board, thereby maximizing the communication performance of the antenna unit (e.g., enabling transmission signals to be transmitted or reception signals to be received on both sides of the circuit board, respectively). This will be described in more detail below.

[0073] FIG. 2 is a drawing showing a circuit board according to an embodiment, FIG. 3a is an enlarged view of the cavity region of FIG. 2 according to a first embodiment, FIG. 3b is an enlarged view of the cavity region of FIG. 2 according to a second embodiment, and FIG. 3c is an enlarged view of the cavity region according to a third embodiment.

[0074] Hereinafter, the circuit board according to the embodiment will be described in detail with reference to FIGS. 2, 3a, 3b, and 3c.

[0075] First, the basic structure of the circuit board 300 of the embodiment will be briefly described. The circuit board 300 of the embodiment is provided to drive, power, and support the antenna unit. For example, the circuit board 300 may be a printed circuit board (PCB). Such a circuit board 300 has a flat structure. Such a circuit board 300 may have a multi-layer structure in which multiple layers are stacked.

[0076] The circuit board 300 may include a ground layer (not shown) for grounding and a power supply part (not shown) for power supply.

[0077] The circuit board 300 of the embodiment may be divided into an antenna part having a conductive antenna pattern layer formed thereon and a driving part including a driving element for driving the antenna part by the conductive antenna pattern layer in the antenna region. The conductive antenna pattern layer may refer to a circuit pattern described below.

[0078] The conductive antenna pattern layer is provided to transmit and receive signals on the circuit board of the embodiment. For example, the conductive antenna pattern layer can transmit and receive signals in a predetermined resonant frequency band. For example, the conductive antenna pattern layer can operate in the resonant frequency band to transmit and receive electromagnetic waves. The conductive antenna pattern layer can be operated by receiving power from a power supply unit (not shown) of the circuit board 300, and the power supply operation of the power supply unit is controlled by the driver.

[0079] The conductive antenna pattern layer can resonate in multiple resonant frequency bands. For example, the conductive antenna pattern layer may be a dual-resonant antenna that resonates in different resonant frequency bands. For example, the conductive antenna pattern layer may be, but is not limited to, a dual-resonant antenna that resonates in a first frequency band of 24.03 GHz to 25.81 GHz and a second frequency band of 27.07 GHz to 28.80 GHz. The resonant frequency band of the conductive antenna pattern layer is variable depending on the communication standard of the antenna device to which the circuit board is applied.

[0080] The circuit board 300 of the embodiment may include a first substrate layer 200 and a second substrate layer 300 .

[0081] Here, the first substrate layer 200 and the second substrate layer 300 do not mean a plurality of substrates that are manufactured separately and then bonded together by a bonding layer later. For example, the first substrate layer 200 and the second substrate layer 300 are simply a division of a region in which a cavity C is formed in the thickness direction of the circuit board and a region excluding the region in which the cavity C is formed in a single circuit board.

[0082] The first substrate layer 200 may have a single-layer structure or a multi-layer structure. For example, the first substrate layer 200 may include only one insulating layer or two or more insulating layers. However, the first substrate layer 200 is connected to a main board of an antenna device (e.g., a mobile terminal) to which the circuit board is applied, while mounting a driving element (described below) and connecting the mounted driving element to a conductive antenna pattern layer (described below). In this case, if the first substrate layer 200 has a single-layer structure, the horizontal width of the first substrate layer 200 may increase due to the connection between the antenna pattern and the main board. Therefore, the first substrate layer 200 preferably has at least two or more layers to reduce the horizontal width of the circuit board while connecting the conductive antenna pattern layer and the main board, thereby reducing the signal transmission distance. Hereinafter, the first substrate layer 200 will be described as having a two or more layer structure. However, the embodiment is not limited thereto, and the first substrate layer 200 may have a single layer structure.

[0083] The second substrate layer 300 is disposed on the first substrate layer 200. The second substrate layer 300 may have a layer structure of at least two layers.

[0084] The second substrate layer 300 may have a conductive antenna pattern layer disposed thereon and may also have a cavity C in which a driving element is disposed. If the second substrate layer 300 has a single-layer structure, the cavity C in which the driving element is disposed may not have sufficient space (e.g., depth). The second substrate layer 300 also has a region in which a conductive antenna pattern layer is disposed. If the second substrate layer 300 has a single-layer structure, communication performance through the conductive antenna pattern layer may be reduced. For example, the communication performance may increase or decrease in proportion to the length of the conductive antenna pattern layer. If the second substrate layer 300 has a single-layer structure, the width of the remaining region of the second substrate layer 300 excluding the region in which the cavity C is formed may be significantly increased to maintain communication performance above a certain level. Therefore, in this embodiment, the second substrate layer 300 has a layer structure of at least two layers, ensuring the length of the conductive antenna pattern layer sufficient to satisfy the communication performance and the space of the cavity C in which the driving element is mounted.

[0085] Hereinafter, the first substrate layer 200 and the second substrate layer 300 according to the embodiment will be described in detail.

[0086] The first substrate layer 200 may include a first insulating layer, a circuit pattern, and a through electrode, which functions to connect circuit patterns arranged on different layers and may also be called a "via."

[0087] The first substrate layer 200 may include a first insulating layer. The first insulating layer may have a multi-layer structure or may alternatively have a single-layer structure. Although the first insulating layer is illustrated as having a three-layer structure in the drawings, this is not intended to be limiting. For the sake of convenience, the following description will be given assuming that the first insulating layer has a three-layer structure. However, the first insulating layer may have a layer structure of two or less layers, or may alternatively have a layer structure of four or more layers.

[0088] The first insulating layer may include a 1-1 insulating layer 211, a 1-2 insulating layer 212, and a 1-3 insulating layer 213. For example, the first insulating layer may include a 1-1 insulating layer 211, a 1-2 insulating layer 212, and a 1-3 insulating layer 213 from the top.

[0089] The 1-1 insulating layer 211 may refer to an uppermost insulating layer of the first insulating layers that is disposed closest to the second substrate layer 300. The 1-3 insulating layer 213 may refer to a lowermost insulating layer of the first insulating layers that is farthest from the second substrate layer 300. The 1-2 insulating layer 212 may refer to an inner insulating layer that is disposed between the uppermost insulating layer and the lowermost insulating layer.

[0090] The first insulating layer may include a prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, with an epoxy resin or the like, and then performing thermocompression bonding. However, embodiments are not limited thereto, and the prepreg constituting the first insulating layer may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

[0091] The first insulating layer may include a resin and reinforcing fibers disposed within the resin. The resin may be, but is not limited to, an epoxy resin. The resin is not particularly limited to epoxy resin and may, for example, include one or more epoxy groups in the molecule, or alternatively, include two or more epoxy groups, or alternatively, include four or more epoxy groups. The resin of the first insulating layer may also include a naphthalene group, for example, an aromatic amine type, but is not limited thereto. Examples of the resin include bisphenol A-type epoxy resins, bisphenol F-type epoxy resins, bisphenol S-type epoxy resins, phenol novolac-type epoxy resins, alkylphenol novolac-type epoxy resins, biphenol-type epoxy resins, aralkyl-type epoxy resins, dicyclopentadiene-type epoxy resins, naphthalene-type epoxy resins, naphthol-type epoxy resins, epoxy resins obtained by condensation of phenols with aromatic aldehydes having a phenolic hydroxyl group, biphenol aralkyl-type epoxy resins, fluorene-type epoxy resins, xanthene-type epoxy resins, TGIC (triglycidyl isocyanurate), rubber-modified epoxy resins, and phosphorous-based epoxy resins. Examples of the resin include naphthalene-based epoxy resins, bisphenol A-type epoxy resins, phenol novolac epoxy resins, cresol novolac epoxy resins, rubber-modified epoxy resins, and phosphorous-based epoxy resins. The reinforcing fibers may be glass fibers, carbon fibers, aramid fibers (e.g., aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials. The reinforcing fibers are arranged in the resin in a cross-sectional shape.

[0092] Meanwhile, glass fiber, carbon fiber, aramid fiber (for example, aramid-based organic material), nylon, silica-based inorganic material, or titania-based inorganic material can be used.

[0093] However, the embodiment is not limited thereto, and the first insulating layer may be made of an insulating material other than the prepreg.

[0094] Alternatively, at least one of the plurality of insulating layers constituting the first insulating layer may include a prepreg, and another insulating layer may include an insulating material other than the prepreg.

[0095] For example, the first insulating layer may be rigid or flexible. For example, the first insulating layer may include glass or plastic. More specifically, the first insulating layer may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or a reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC), or may include sapphire. For example, the first insulating layer may include an optically isotropic film. For example, the first insulating layer may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the first insulating layer may be made of a material including an inorganic filler and an insulating resin. For example, the first insulating layer may be made of a resin containing a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, and a reinforcing material such as an inorganic filler such as silica or alumina, specifically ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc. As an example, the first insulating layer may be made of RCC (Resin coated copper).

[0096] Each of the insulating layers constituting the first insulating layer may have a thickness in the range of 10 μm to 60 μm. For example, the 1-1 insulating layer 211, the 1-2 insulating layer 212, and the 1-3 insulating layer 213 may each have a thickness in the range of 10 μm to 60 μm. For example, the 1-1 insulating layer 211, the 1-2 insulating layer 212, and the 1-3 insulating layer 213 may each have a thickness in the range of 12 μm to 50 μm. For example, the 1-1 insulating layer 211, the 1-2 insulating layer 212, and the 1-3 insulating layer 213 may each have a thickness in the range of 15 μm to 40 μm.

[0097] If the thickness of the 1-1 insulating layer 211, the 1-2 insulating layer 212, and the 1-3 insulating layer 213 is less than 10 μm, the circuit patterns included in the circuit board will not be stably protected. If the thickness of each of the 1-1 insulating layer 211, the 1-2 insulating layer 212, and the 1-3 insulating layer 213 exceeds 60 μm, the overall thickness of the circuit board will increase. Furthermore, if the thickness of each of the 1-1 insulating layer 211, the 1-2 insulating layer 212, and the 1-3 insulating layer 213 exceeds 60 μm, the thickness of the circuit patterns and vias will also increase correspondingly, resulting in increased loss of signals transmitted through the circuit patterns.

[0098] In the embodiment, the first substrate layer 200 may include a first circuit pattern layer, for example, the first substrate layer 200 may include a first circuit pattern layer disposed on a surface of a first insulating layer.

[0099] For example, the first substrate layer 200 may include a first circuit pattern 221 disposed on an upper surface of the 1-1 insulating layer 211. For example, the first substrate layer 200 may include a second circuit pattern 222 disposed between a lower surface of the 1-1 insulating layer 211 and an upper surface of the 1-2 insulating layer 212. For example, the first substrate layer 200 may include a third circuit pattern 223 disposed between a lower surface of the 1-2 insulating layer 212 and an upper surface of the 1-3 insulating layer 213. For example, the first substrate layer 200 may include a fourth circuit pattern 224 disposed on a lower surface of the 1-3 insulating layer 213.

[0100] The first circuit pattern 221 is embedded in the first insulating layer. For example, the first circuit pattern 221 may have a structure embedded in the upper part of the first insulating layer. For example, the first circuit pattern 221 may be disposed in an insulating layer disposed at the uppermost position of the first insulating layers. The first circuit pattern 221 may refer to the circuit pattern disposed at the uppermost position of the first circuit pattern layers. The first circuit pattern 221 may also be embedded in the uppermost insulating layer disposed at the uppermost position of the first insulating layers. In this case, the embedding of the first circuit pattern 221 may mean that at least a portion of the upper surface of the first circuit pattern 221 does not overlap with the upper surface of the first-first insulating layer 211. Alternatively, it may mean that at least a portion of the side surface and the lower surface of the first circuit pattern 221 are covered by the first-first insulating layer 211.

[0101] Meanwhile, the top surface of the first circuit pattern 221 may have steps (eg, different heights) depending on the position.

[0102] For example, the first substrate layer 200 may be divided into a plurality of regions in the width direction or length direction.

[0103] For example, the first substrate layer 200 may include a first region RB1 that vertically overlaps the cavity C of the second substrate layer 300, and a second region RB2 other than the first region RB1. The first region RB1 may be a region that overlaps the cavity C of the second substrate layer 300. Alternatively, the first region RB1 may be a region that overlaps the lower surface or bottom surface of the cavity C of the second substrate layer 300. That is, the cavity C of the embodiment may have different widths at its upper and lower portions. For example, the cavity C may have a shape in which the width at its upper portion is greater than the width at its lower portion. For example, the cavity C may have a slope in which the width at its upper portion is greater than the width at its lower portion.

[0104] The first circuit pattern 221 includes a first pattern portion disposed on an upper surface of the first region RB1 of the first-1 insulating layer 211 and a second pattern portion disposed on an upper surface of the second region RB2 of the first-1 insulating layer 211. The height of the first pattern portion and the height of the second pattern portion may be different. For example, the first pattern portion may have a step with respect to the second pattern portion. For example, the upper surface of the first pattern portion may be disposed on a different plane from the upper surface of the second pattern portion. For example, the upper surface of the first pattern portion may be positioned lower than the upper surface of the second pattern portion.

[0105] As described above, in the embodiment, the first pattern portion of the first circuit pattern 221 arranged in the first region RB1 is arranged lower than the second pattern portion arranged in the second region RB2, thereby minimizing damage to the first pattern portion that occurs during the process of forming the cavity C. This will be described in more detail below.

[0106] Meanwhile, the first circuit pattern layer may be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit pattern layer may be made of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern layer may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0107] The first circuit pattern layer may have a thickness in the range of 5 μm to 20 μm. For example, the first circuit pattern layer may have a thickness in the range of 6 μm to 17 μm. The first circuit pattern layer may have a thickness in the range of 7 μm to 16 μm. If the thickness of the first circuit pattern layer is less than 5 μm, the resistance of the circuit pattern increases, thereby reducing signal transmission efficiency. For example, if the thickness of the first circuit pattern layer is less than 5 μm, signal transmission loss increases. For example, if the thickness of the first circuit pattern layer exceeds 20 μm, the line width of the circuit pattern increases, thereby increasing the overall volume of the circuit board.

[0108] The first circuit pattern layer can be formed using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0109] Meanwhile, the first substrate layer 200 includes a through electrode. The first through electrode is formed by penetrating a first insulating layer constituting the first substrate layer 200. For example, the first substrate layer 200 may include a first through electrode 231 penetrating the 1-1 insulating layer 211. For example, the first substrate layer 200 may include a first through electrode 231 penetrating an uppermost insulating layer disposed at the uppermost position of the first insulating layers.

[0110] The first through electrode 231 penetrates the 1-1 insulating layer 211 , thereby electrically connecting the first circuit pattern 221 and the second circuit pattern 222 .

[0111] In addition, the first substrate layer 200 may include a second through electrode 232 that penetrates the first-second insulating layer 212 .

[0112] The second through electrode 232 penetrates the first-second insulating layer 212, thereby electrically connecting the second circuit pattern 222 and the third circuit pattern 223.

[0113] In addition, the first substrate layer 200 may include a third through electrode 233 that penetrates the first to third insulating layer 213 .

[0114] The third through electrode 233 penetrates the first-third insulating layer 213, thereby electrically connecting the third circuit pattern 223 and the fourth circuit pattern 224.

[0115] The through electrode is formed by filling a through hole penetrating the first insulating layer with a conductive material. The through hole penetrating the first insulating layer is formed by any one of mechanical, laser, and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When the through hole is formed by laser processing, methods such as UV or CO2 laser can be used. When the through hole is formed by chemical processing, at least one of the insulating layers can be opened using a chemical containing aminosilane, ketones, etc.

[0116] On the other hand, laser processing is a cutting method that focuses optical energy on the surface to melt and vaporize part of the material to create the desired shape. It can easily process complex shapes created by computer programs and can also process composite materials that are difficult to cut using other methods.

[0117] In addition, the laser processing has the advantage that the cutting diameter can be as small as 0.005 mm, and the range of thickness that can be processed is wide.

[0118] The laser drill is preferably a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is capable of processing both the copper foil layer and the insulating layer, while the CO2 laser is capable of processing only the insulating layer.

[0119] After the through holes are formed, the through holes can be filled with a conductive material to form through electrodes. The metal material forming the through electrodes can be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The conductive material can be filled by any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing, or a combination thereof.

[0120] The second substrate layer 300 may have a multi-layer structure. To this end, the second substrate layer 300 may include a plurality of second insulating layers. For example, the second substrate layer 300 may include a 2-1 insulating layer 311, a 2-2 insulating layer 312, a 2-3 insulating layer 313, and a 2-4 insulating layer 314.

[0121] For example, the second substrate layer 300 may include four second insulating layers, but the embodiment is not limited thereto, and the second insulating layers constituting the second substrate layer 300 may include three or less second insulating layers, or may include four or more second insulating layers.

[0122] The 2-1 insulating layer 311 is disposed on the first substrate layer 200. For example, the 2-1 insulating layer 311 is disposed on the upper surface of the 1-1 insulating layer 211 disposed on the uppermost side of the first substrate layer 200.

[0123] The 2-2 insulating layer 312 is disposed on the 2-1 insulating layer 311 .

[0124] Furthermore, the second-third insulating layer 313 is disposed on the second-second insulating layer 312 .

[0125] Furthermore, the second-fourth insulating layer 314 is disposed on the second-third insulating layer 313 .

[0126] The four second insulating layers constituting the second substrate layer 300 may include the same insulating material as the first insulating layer constituting the first substrate layer 200, but are not limited thereto.

[0127] The second substrate layer 300 may include a second circuit pattern layer.

[0128] For example, the second substrate layer 300 may include a fifth circuit pattern 321 disposed on the upper surface of the 2-1 insulating layer 311 .

[0129] For example, the second substrate layer 300 may include a sixth circuit pattern 322 disposed on the upper surface of the second insulating layer 312 .

[0130] For example, the second substrate layer 300 may include a seventh circuit pattern 323 disposed on the upper surface of the second-third insulating layer 313 .

[0131] In addition, the second substrate layer 300 may include an eighth circuit pattern 324 disposed on the upper surface of the second to fourth insulating layer 314 .

[0132] In this case, the second circuit pattern layer constituting the second substrate layer 300 may be a conductive antenna pattern layer. For example, the fifth circuit pattern 321, the sixth circuit pattern 322, the seventh circuit pattern 323, and the eighth circuit pattern 324 may be an antenna part connected to the first substrate layer 200 and functioning as an antenna for transmitting a transmission signal to the outside or receiving a signal transmitted from the outside.

[0133] The conductive antenna pattern layer may be formed in the same process as the first circuit pattern layer constituting the first substrate layer 200 .

[0134] The second substrate layer 300 may include a through electrode.

[0135] For example, the second substrate layer 300 may include a through electrode that penetrates the second insulating layer.

[0136] For example, the second substrate layer 300 may include a fourth through-electrode 331 penetrating the 2-1 insulating layer 311. The fourth through-electrode 331 may electrically connect the first circuit pattern 221 and the fifth circuit pattern 321 of the first substrate layer 200.

[0137] For example, the second substrate layer 300 may include a fifth through-electrode 332 penetrating the 2-2 insulating layer 312. For example, the fifth through-electrode 332 may electrically connect the fifth circuit pattern 321 and the sixth circuit pattern 322.

[0138] For example, the second substrate layer 300 may include a sixth through-electrode 333 penetrating the second-third insulating layer 313. The sixth through-electrode 333 may electrically connect the sixth circuit pattern 322 and the seventh circuit pattern 323.

[0139] For example, the second substrate layer 300 may include a seventh through-hole electrode 334 penetrating the second-fourth insulating layer 314. The seventh through-hole electrode 334 may electrically connect the seventh circuit pattern 323 and the eighth circuit pattern 334.

[0140] Meanwhile, the second substrate layer 300 includes a cavity C.

[0141] Therefore, the second substrate layer 300 may include a region in which the cavity C is formed, for example, a third region RT1 that vertically overlaps the cavity C, and a fourth region RT2 other than the third region RT1.

[0142] The third region RT1 may be a region that vertically overlaps with the first region RB1 of the first substrate layer 200. The fourth region RT2 may be a region that vertically overlaps with the second region RB2 of the first substrate layer 200.

[0143] A cavity C, which provides a mounting space for mounting a driving element and a passive element in an antenna package substrate, is formed in the third region RT1 of the second substrate layer 300. A conductive antenna pattern layer of an antenna portion that functions as an antenna is formed in the fourth region RT2 of the second substrate layer 300.

[0144] For example, the third region RT1 of the second substrate layer 300 is a region where the cavity C is formed, and the fourth region RT2 of the second substrate layer 300 is a region excluding the region where the cavity C is formed. The fourth region RT2 of the second substrate layer 300 is a region where a conductive antenna pattern layer is formed.

[0145] At this time, the respective circuit patterns in the circuit board 100 of the present invention are disposed in the first to fourth regions of the first substrate layer 200 and the second substrate layer 300, respectively, so that the respective regions can perform different functions.

[0146] For example, the first circuit pattern layer constituting the first substrate layer 200 may include a first pattern portion disposed in a first region RB1 of the first substrate layer 200. The first pattern portion may vertically overlap the cavity C. The first pattern portion may function as a mounting pattern on which driving elements and passive elements are disposed, or as a terminal pattern connecting the circuit board 100 to an external board (e.g., a main board of a terminal).

[0147] In addition, the first circuit pattern layer constituting the first substrate layer 200 may include a second pattern portion disposed in the second region RB2 of the first substrate layer 200. The second pattern portion does not need to vertically overlap the cavity C. For example, the second pattern portion may vertically overlap a conductive antenna pattern layer formed in the fourth region RT2 of the second substrate layer 300.

[0148] In this case, in one embodiment, the second pattern portion may function as a terminal pattern together with the first pattern portion. When the second pattern portion functions as a terminal pattern together with the first pattern portion, the circuit board of the embodiment may function as an antenna only in the fourth region RT2 of the second substrate layer 300. For example, when the second pattern portion is not a conductive antenna pattern layer, the circuit board of the embodiment may transmit a transmission signal to the upper side of the fourth region RT2 of the second substrate layer 300 or receive a signal transmitted from the upper side of the fourth region RT2.

[0149] In another embodiment, the second pattern portion may be an additional conductive antenna pattern layer connected to the conductive antenna pattern layer disposed in the fourth region RT2 of the second substrate layer 300.

[0150] For example, the conductive antenna pattern layer disposed in the fourth region RT2 of the second substrate layer 300 may be referred to as a first antenna pattern layer, and the second pattern portion disposed in the second region RB2 of the first substrate layer 200 may be a second antenna pattern layer connected to the first antenna pattern layer.

[0151] In such a case, in the embodiment, signals can be transmitted in both directions of the circuit board, or signals transmitted from both directions of the circuit board can be received. For example, in the embodiment, a signal can be transmitted to the upper side of the first antenna pattern layer, and a signal can be transmitted to the lower side of the second antenna pattern layer. In addition, in the embodiment, a signal transmitted from the upper side of the first antenna pattern layer can be received, and a signal transmitted from the lower side of the second antenna pattern layer can be received.

[0152] Meanwhile, in the embodiment, all of the first pattern portions disposed in the first region RB1 of the first substrate layer 200 function as mounting pads or terminal pads, but this is not limited thereto. For example, some of the first pad portions disposed in the first region RB1 of the first substrate layer 200 may function as mounting pads or terminal pads, and the remaining portion may function as an antenna pattern together with the second antenna pattern layer.

[0153] The structure of the cavity C of the embodiment will be specifically described below.

[0154] 3a, in this embodiment, the cavity C is formed through the second substrate layer 300. For example, the cavity C is formed through a plurality of second insulating layers constituting the second substrate layer 300.

[0155] At this time, the cavity C may include a plurality of parts.

[0156] For example, the cavity C may include a first part P1 adjacent to the upper surface of the second substrate layer 300. Also, the cavity C may include a second part P2 adjacent to the lower surface of the second substrate layer 300 and below the first part P1.

[0157] In this case, the first part P1 may have a first slope in which the width gradually decreases toward the bottom surface of the second substrate layer 300. The first slope may refer to the slope of an inner wall IW1 of the first part P1. For example, the first slope may refer to the slope angle of the inner wall IW1 of the first part P1 with respect to the bottom surface of the cavity C. For example, the first slope may refer to the interior angle between the bottom surface of the cavity C and the inner wall IW1 of the first part P1.

[0158] The first inclination θ1 of the inner wall IW1 of the first part P1 may be in the range of 115 degrees to 150 degrees. For example, the first inclination θ1 of the inner wall IW1 of the first part P1 may be in the range of 118 degrees to 148 degrees. For example, the first inclination θ1 of the inner wall IW1 of the first part P1 may be in the range of 120 degrees to 145 degrees.

[0159] When the first inclination θ1 of the inner wall IW1 of the first part P1 is less than 115 degrees, the process time required to form the cavity C according to the embodiment increases. For example, when the first inclination θ1 of the inner wall IW1 of the first part P1 is less than 115 degrees, it means that the width of the laser beam (e.g., laser mask) used in the process of forming the primary cavity described below is small, and therefore the time required to form the cavity C increases.

[0160] Furthermore, if the first inclination θ1 of the inner wall IW1 of the first part P1 is greater than 150 degrees, the upper width of the cavity C increases, thereby reducing the circuit integration density. For example, the width of the cavity C is determined by determining the lower width of the cavity C to correspond to the arrangement space of the device to be mounted, and the cavity formation process is performed based on the determined lower width. In this case, if the upper width of the cavity C increases, the amount of wasted space increases, and therefore the space available for arranging the antenna pattern layer decreases accordingly. Therefore, in this embodiment, the first inclination θ1 of the inner wall IW1 of the first part P1 is set to be in the range of 115 degrees to 150 degrees.

[0161] Meanwhile, the cavity C of the embodiment includes a second part P2 below the first part P1. The second part P2 may have a second slope θ2 whose width gradually decreases toward the lower surface of the second substrate layer 300. In this case, the second slope θ2 of the second part P2 may be different from the first slope θ1 of the first part P1. For example, the second slope θ2 of the second part P2 may be smaller than the first slope θ1 of the first part P1.

[0162] In this case, the second inclination θ2 may refer to the inclination of the inner wall IW2 of the second part P2. For example, the second inclination θ2 may refer to the inclination of the inner wall IW2 of the second part P2 with respect to the bottom surface of the cavity C. For example, the second inclination θ2 may refer to the interior angle between the bottom surface of the cavity C and the inner wall IW2 of the second part P2.

[0163] The second inclination θ2 of the inner wall IW2 of the second part P2 may be smaller than the first inclination θ1 and may range from 91 degrees to 120 degrees. For example, the second inclination θ2 of the inner wall IW2 of the second part P2 may be smaller than the first inclination θ1 and may range from 95 degrees to 118 degrees. For example, the second inclination θ2 of the inner wall IW2 of the second part P2 may be smaller than the first inclination θ1 and may range from 98 degrees to 115 degrees.

[0164] If the second inclination θ2 of the inner wall IW2 of the second part P2 is less than 91 degrees, the driving element and the passive element cannot be stably disposed in the cavity C. For example, if the second inclination θ2 of the inner wall IW2 of the second part P2 is less than 91 degrees, the second part P2 has a shape in which its width decreases toward the upper surface of the second substrate layer 300, and there is no space in the middle region of the cavity C for disposing the driving element and the passive element. For example, the inner wall in the middle region of the cavity C may come into contact with the driving element and the passive element, which may cause the position of the driving element and the passive element to be misaligned during the mounting process of the driving element and the passive element. That is, as described above, the width of the cavity C is determined by the width of the lower part of the cavity C corresponding to the mounting space of the element. In this case, if the second inclination θ2 of the inner wall IW2 of the second part P2 is less than 91 degrees, the space toward the upper side of the second part P2 becomes narrower than the mounting space of the element, which causes a problem that the passive element and the driving element cannot be stably arranged in the cavity C.

[0165] Furthermore, if the second inclination θ2 of the inner wall IW2 of the second part P2 is greater than 120 degrees, the cavity C is formed with a size larger than the space required for mounting the device. Therefore, if the second inclination θ2 of the inner wall IW2 of the second part P2 is greater than 120 degrees, the area of ​​the space occupied by the cavity C increases even when the same device is arranged, resulting in a decrease in circuit integration density.

[0166] Meanwhile, the lengths of the first part P1 and the second part P2 of the cavity C may be different. For example, the first part P1 of the cavity C may have a first length L1, and the second part P2 may have a second length L2 that is longer than the first length L1. In this case, the first length L1 may refer to the depth of the first part P1. For example, the first length L1 may refer to the vertical distance of the first part P1 in the vertical direction. Furthermore, the second length L2 may refer to the depth of the second part P2. For example, the second length L2 may refer to the vertical distance of the second part P2 in the vertical direction.

[0167] In this case, the second length L2 may be 1.5 times or more the first length L1. For example, the second length L2 may be 3 times or more the first length L1. For example, the second length L2 may be 5 times or more the first length L1. For example, the second length L2 may be 10 times or more the first length L1.

[0168] For example, the second length L2 may be in the range of 1.5 to 30 times the first length L1. For example, the second length L2 may be in the range of 3 to 28 times the first length L1. For example, the second length L2 may be in the range of 5 to 25 times the first length L1. For example, the second length L2 may be in the range of 10 to 20 times the first length L1.

[0169] If the second length L2 is less than 1.5 times the first length L1, the effect caused by the difference between the first slope of the first part P1 and the second slope of the second part P2 becomes insignificant. Also, if the second length L2 is 30 times or more the first length L1, the thickness of the second substrate layer 300 must be increased to satisfy this, which increases the overall thickness of the circuit board.

[0170] Meanwhile, the cavity C in the embodiment may include a third part P3 below the second part P2. The third part P3 may be located lower than the second substrate layer 300. For example, a cavity penetrating the second substrate layer 300 may include the first part P1 and the second part P2, and the third part P3 may be a space formed by removing a part of the first substrate layer 200, not the second substrate layer 300.

[0171] For example, the third part P3 may be a portion formed by removing a stopper layer arranged in an area of ​​the first circuit pattern 221 arranged on the top side of the first substrate layer 200 that vertically overlaps with the cavity C.

[0172] For example, the overall depth of the cavity C may be greater than the overall thickness of the second insulating layer constituting the second substrate layer 300. For example, the depth of the cavity C may be greater than the overall thickness of the second insulating layer by the thickness of the first circuit pattern 221.

[0173] Therefore, the bottom surface of the cavity C may be located lower than the bottom surface of the second substrate layer 300 .

[0174] The third part P3 may have a third slope. The third slope may refer to the slope of an inner wall IW3 of the third part P3. In this case, the inner wall IW1 of the first part P1 and the inner wall IW2 of the second part P2 refer to the inner walls of the second insulating layer constituting the second substrate layer 300. Alternatively, the inner wall IW3 of the third part P3 may refer to the slope of a side surface of a first-third pattern 221-3 in the first circuit pattern 221 of the first substrate layer 200.

[0175] For example, in this embodiment, the first circuit pattern 221 of the first substrate layer 200 includes a 1-3 pattern 221-3 disposed around the bottom of the cavity C. The 1-3 pattern 221-3 is a portion of a stopper layer used in forming the cavity C. For example, the cavity C may be formed with a width corresponding to the stopper layer, and thus the width of the cavity C may be smaller than the width of the stopper layer. As a result, a portion of the stopper layer may vertically overlap the cavity C, and the remaining portion may not vertically overlap the cavity C. In this case, the stopper layer vertically overlapping the cavity C may be removed by etching to form a third part P3 of the cavity C. The stopper layer not vertically overlapping the cavity C may not be removed during the etching process and may remain as the 1-3 pattern 221-3 between the first substrate layer 200 and the second substrate layer 300. An inner wall IW3 of the third part P3 of the cavity C may refer to an inclination angle of the side surface of the first-third pattern 221-3. The third inclination of the inner wall IW3 of the third part P3 is determined by an etching condition of the stopper layer.

[0176] For example, in the first embodiment, the third inclination of the inner wall IW3 of the third part P3 may be perpendicular to the bottom surface of the cavity C.

[0177] Meanwhile, in an embodiment, the top surface of the first substrate layer 200 may have a step. For example, the first substrate layer 200 includes a first insulating layer. The top surface of the first insulating layer may have a step. For example, the first substrate layer 200 includes a plurality of first insulating layers, and the top surface of a 1-1 insulating layer disposed at the top of the plurality of first insulating layers may have a step.

[0178] For example, the top surface of the 1-1 insulating layer 211 may include a first top surface 211T1 vertically overlapping the cavity C and a second top surface 211T2 other than the first top surface 211T1. For example, the first top surface 211T1 of the 1-1 insulating layer 211 may refer to a first region RB1 of the first substrate layer 200. For example, the second top surface 211T2 of the 1-1 insulating layer 211 may refer to a second region RB2 of the first substrate layer 200.

[0179] The first top surface 211T1 of the 1-1 insulating layer 211 may be located lower than the second top surface 211T2 of the 1-1 insulating layer 211. For example, the first top surface 211T1 of the 1-1 insulating layer 211 may be located lower than the second top surface 211T2 due to removal of the stopper layer in a region vertically overlapping the cavity C. For example, the first top surface 211T1 of the 1-1 insulating layer 211 may be located lower than the second top surface 211T2 by the thickness of the stopper layer. In this case, the first top surface 211T1 of the 1-1 insulating layer 211 may refer to the bottom surface of the cavity C.

[0180] Accordingly, the first circuit patterns 221 disposed on the upper surface of the 1-1 insulating layer 211 may have different heights depending on the region. For example, the first circuit patterns 221 may include a 1-1 pattern 221-1 disposed on the first upper surface 211T1 of the 1-1 insulating layer 211. The first circuit patterns 221 may also include a 1-2 pattern 221-2 disposed on the second upper surface 211T2 of the 1-1 insulating layer 211. The 1-1 pattern 221-1 may be positioned lower than the 1-2 pattern 221-2. For example, the upper surface of the 1-1 pattern 221-1 may be positioned lower than the upper surface of the 1-2 pattern 221-2.

[0181] In addition, in the embodiment, the first through electrodes 231 may have different thicknesses depending on their positions. For example, the first through electrodes 231 may include a first through electrode 231-1 that vertically overlaps the first pattern 221-1. The first through electrodes 231 may also include a first through electrode 231-2 that vertically overlaps the first pattern 221-2. The thickness of the first through electrode 231-1 may be thinner than the thickness of the first through electrode 231-2. For example, the thickness of the first through electrode 231-1 may be thinner than the thickness of the first through electrode 231-2 by the thickness of the stopper layer. As a result, in the embodiment, a thin circuit board may be implemented.

[0182] 3b, the cavity C may include a first part P1, a second part P2, and a third part P3a. The cavity of FIG. 3b differs from the cavity of FIG. 3a in the third slope of the third part P3a. For example, the slope of the side surface of the first-third pattern 221-3 in FIG. 3a is substantially perpendicular to the bottom surface of the cavity C. Alternatively, the third slope of the side surface IW3a of the first-third pattern 221-3a in FIG. 3b may have a constant slope with respect to the bottom surface of the cavity. For example, the third slope may be the same as the second slope of the inner wall IW2 of the second part P2. For example, the third slope may be different from the second slope. The third slope may be selectively changed depending on the etching conditions of the stopper layer.

[0183] 3c, the cavity C may include a first part P1, a second part P2, and a third part P3b. In this case, the cavity of FIGS. 3a and 3b has a structure in which the first-third pattern 221-3 is disposed in an area adjacent to the bottom of the cavity C.

[0184] Alternatively, as shown in Fig. 3c, the pattern 1-3 may be completely removed during etching, thereby forming a recess IW3ab recessed away from the cavity C on the inner wall of the third part P3b of the cavity C.

[0185] According to the embodiment, the circuit board includes a first substrate layer and a second substrate layer. The second substrate layer includes a cavity. The first substrate layer includes a first region vertically overlapping the cavity and a second region excluding the first region. The second substrate layer also includes a third region corresponding to the cavity and a fourth region excluding the third region. In this embodiment, the third region of the second substrate layer is a region where a driving element is disposed, and the fourth region is a region where an antenna pattern layer is disposed. In the above embodiment, the driving element is disposed using the cavity of the second substrate layer, and the antenna pattern layer is disposed in the fourth region of the second substrate layer horizontally adjacent to the driving element. As a result, in the embodiment, the signal transmission distance between the antenna pattern layer and the driving element can be minimized, thereby minimizing signal transmission loss. For example, in the embodiment, the signal transmission distance can be reduced compared to the comparative example in which a substrate on which a driving element is disposed and a substrate on which an antenna pattern layer is disposed are connected using a separate connection means, thereby reducing signal transmission loss caused by the separate connection means.

[0186] In addition, in an embodiment, by locating the driving elements in the cavities of the second substrate layer, the overall thickness of the circuit board can be reduced to correspond to the depth of the cavities.

[0187] In addition, the cavity in the embodiment includes a first part having a first slope and a second part having a second slope different from the first slope. The second slope has a smaller slope angle relative to the bottom surface of the cavity than the first slope. The vertical length of the second part having the second slope in the embodiment is longer than the vertical length of the first part having the first slope. As a result, the space occupied by the cavity in the embodiment can be reduced compared to the comparative example, thereby improving circuit integration. For example, by reducing the space occupied by the cavity in the embodiment, the length of the antenna pattern layer can be increased within a substrate having the same size as the comparative example, thereby improving communication performance.

[0188] In addition, in the embodiment, the first substrate layer includes a 1-1 insulating layer disposed adjacent to the first substrate layer and a first circuit pattern disposed on an upper surface of the 1-1 insulating layer. The first circuit pattern includes a 1-1 pattern formed in a first region vertically overlapping the cavity and a 1-2 pattern formed in a second region excluding the first region, and the upper surface of the 1-1 pattern is located lower than the upper surface of the 1-2 pattern. As a result, in the embodiment, damage to the surface of the 1-1 pattern can be prevented during a laser process for forming the cavity, thereby improving the electrical and physical reliability of the circuit board.

[0189] 4a and 4b show plan views of the second substrate layer as seen from above.

[0190] 4a, the second substrate layer 300 includes a third region RT1 and a fourth region RT2. The third region RT1 is a region in which a cavity C penetrating the second substrate layer 300 is formed. The third region RT1 and the fourth region RT2 are formed in the width direction or length direction of the second substrate layer 300, respectively. For example, the third region RT1 is disposed on one side of the fourth region RT2.

[0191] 4b, the third region RT1 is disposed in the center of the second substrate layer 300. The fourth region RT2 is formed to surround the periphery of the third region RT1.

[0192] FIG. 5 is a diagram showing an antenna package substrate according to an embodiment.

[0193] Referring to FIG. 5, the antenna package substrate includes the circuit board 100 shown in FIG.

[0194] The antenna package substrate may include a first protective layer 450 disposed on an upper surface of the second substrate layer 300 of the circuit board 100. The antenna package substrate may also include a second protective layer 460 disposed on a lower surface of the first substrate layer 200 of the circuit board 100.

[0195] The antenna package substrate may also include a first connection portion 410 disposed on a first-1 circuit pattern 221-1, which is disposed in an area of ​​the first circuit pattern 221 of the first substrate layer 200 that vertically overlaps the cavity C. The first connection portion 410 may have a circular planar shape. Alternatively, the first connection portion 410 may have a rectangular planar shape. The first connection portion 410 is disposed on the first-1 circuit pattern 221-1 and may connect the first-1 circuit pattern 221-1 and a terminal 425 of the element 420. The first connection portion 410 may be, for example, a solder ball. The first connection portion 410 may contain a different material component in the solder. The solder may be made of at least one of SnCu, SnPb, and SnAgCu. The heterogeneous material may include any one of Al, Sb, Bi, Cu, Ni, In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe.

[0196] An element 420 is disposed on the first connection portion 410. The element 420 may be a driver element. For example, the element 420 may be a driver element that drives an antenna pattern layer included in the circuit board. Also, although only one element is illustrated as being mounted in the cavity C in the drawings, the present invention is not limited thereto. For example, in addition to the element 420, a passive element (not shown) for operating the element 420 may be additionally mounted in the cavity C.

[0197] Meanwhile, a molding layer 430 is formed in the cavity C to cover the element 420. The molding layer 430 may be, but is not limited to, an EMC (Epoxy Molding Compound).

[0198] The embodiment also includes a second connection part 440 disposed on the underside of a circuit pattern layer disposed on the underside of the first region RB1 of the first substrate layer 200. The second connection part 440 may connect the antenna package substrate to an external substrate (e.g., a main board of a terminal).

[0199] The method for manufacturing a circuit board according to the embodiment will be described below in the order of steps.

[0200] In this case, the circuit board in this embodiment may have a coreless structure as shown in FIG.

[0201] However, the embodiments are not limited thereto. For example, the circuit board of the embodiments may be a core substrate including a core insulating layer. For example, the circuit board of the embodiments may have an ETS (Embedded Trace Substrate) structure manufactured by an ETS method. However, for the sake of convenience, the embodiments will be described assuming that the circuit board has a coreless substrate structure.

[0202] 6a to 6o are diagrams showing a method for manufacturing the circuit board according to the embodiment shown in FIG. 2 in the order of steps.

[0203] The manufacturing process of the circuit board of the embodiment of the present application can broadly include a first step of manufacturing a portion of a first substrate layer and a portion of a second substrate layer using a carrier board, a step of manufacturing a remaining portion of the first substrate layer and a remaining portion of the second substrate layer above and below the substrate layer manufactured by the first step, a step of forming a cavity in the second substrate layer, and a step of removing a stopper layer in an area vertically overlapping with the cavity.

[0204] First, referring to FIG. 6a, a carrier board, which is a basic material for manufacturing a circuit board according to an embodiment, can be prepared.

[0205] The carrier board may include a carrier insulating layer 510 and a carrier copper foil layer 520 disposed on one surface of the carrier insulating layer 510 .

[0206] The carrier copper foil layer 520 may be disposed on one side of the carrier insulating layer 510, or may be disposed on both sides. When the carrier copper foil layer 520 is disposed on both sides of the carrier insulating layer 510, a circuit board manufacturing process may be performed on both sides of the carrier board before the carrier board is removed in the following process.

[0207] The carrier copper foil layer 520 may be formed by electroless plating on the surface of the carrier insulating layer 510. Alternatively, the carrier insulating layer 510 and the carrier copper foil layer 520 may be a copper clad laminate (CCL).

[0208] In this case, the carrier board may include a first region RB1 and a second region RB2 of the first substrate layer 200.

[0209] Next, in this embodiment, a process of forming a mask 530 on the lower surface of the carrier copper foil layer 520 may be performed. At this time, a process of forming an opening 540 in the mask 530 may be performed. The opening 540 of the mask 530 may vertically overlap an area of ​​the lower surface of the carrier copper foil layer 520 where the fifth circuit pattern 321 is to be formed.

[0210] Next, as shown in FIG. 6b, electrolytic plating may be performed using the carrier copper foil layer 520 as a seed layer to form a fifth circuit pattern 321 that fills the openings 540 of the mask 530.

[0211] In the embodiment, after the fifth circuit pattern 321 is formed, a process of removing the mask 530 may be performed. Next, in the embodiment, a process of forming a part of the second insulating layer of the second substrate layer 300, a 2-1 insulating layer 311, on the lower surface of the carrier copper foil layer 520 and the lower surface of the fifth circuit pattern 321 by removing the mask 530 may be performed.

[0212] 6c, in an embodiment, a process of forming a through hole (not shown) penetrating the 2-1 insulating layer 311 may be performed. Next, in an embodiment, a process of forming a fourth through electrode 331 filling the through hole of the 2-1 insulating layer 311 and a part of the first circuit pattern 221 of the first substrate layer 200 on the lower surface of the 2-1 insulating layer 311 may be performed.

[0213] In this case, the first circuit pattern 221 may include a first pattern 221-2 that vertically overlaps the second region RB2 and a stopper layer 221-3 that vertically overlaps the first region RB1 on the lower surface of the second-first insulating layer 311. The stopper layer 221-3 is formed in a region that vertically overlaps a region where a cavity is to be formed on the lower surface of the second-first insulating layer.

[0214] Next, in this embodiment, as shown in FIG. 6d, a process of forming a 1-1 pattern 221-1, which is a remaining part of the first circuit pattern 221, on the lower surface of the stopper layer 221-3 may be performed.

[0215] At this time, the 1-1 pattern 221-1 is disposed on the underside of the stopper layer 221-3, and thus may have a step (e.g., different heights) with the 1-2 pattern 221-2 formed in the second region RB2 on the underside of the 2-1 insulating layer 311.

[0216] Next, as shown in FIG. 6e, in this embodiment, a process of removing the carrier insulating layer 510 and the carrier copper foil layer 520 may be performed.

[0217] Hereinafter, in an embodiment, a process for manufacturing a portion of the second substrate layer 300 and a portion of the first substrate layer 200 may be performed above and below the 2-1 insulating layer 311, respectively. For example, in an embodiment, a process for forming a 1-1 insulating layer 211 on the lower surface of the 2-1 insulating layer 311, a first through electrode 231 penetrating the 1-1 insulating layer 211, and a second circuit pattern 222 on the lower surface of the 1-1 insulating layer 211 may be performed. In this case, the first through electrode 231 may include a 1-1 through electrode 231-1 connected to the 1-1 pattern 221-1 and a 1-2 through electrode 231-2 connected to the 1-2 pattern 221-2. The 1-1 through electrode 231-1 and the 1-2 through electrode 231-2 may have different thicknesses. Specifically, the 1-1 pattern 221-1 is positioned lower than the 1-2 pattern 221-2. Therefore, the first through-hole electrode 231-1 may have a thickness thinner than the second through-hole electrode 231-2. For example, the lower surface of the first through-hole electrode 231-1 may be flush with the lower surface of the second through-hole electrode 231-2. Conversely, the upper surface of the first through-hole electrode 231-1 may be lower than the upper surface of the second through-hole electrode 231-2.

[0218] In addition, in the embodiment, a process can be performed in which a 2-2 insulating layer 312 is formed on the upper surface of the 2-1 insulating layer 311, and a 5th through-electrode 332 penetrating the 2-2 insulating layer 312 and a 6th circuit pattern 322 are formed on the upper surface of the 2-2 insulating layer 312.

[0219] 6g, in an embodiment, a process of forming a first-second insulating layer 212 on the lower surface of the first-first insulating layer 211 may be performed. In an embodiment, a process of forming a second through electrode 232 penetrating the first-second insulating layer 212 and a third circuit pattern 223 on the lower surface of the first-second insulating layer 212 may be performed.

[0220] In addition, in the embodiment, a process of forming a 2-3 insulating layer 313 on an upper surface of the 2-2 insulating layer 312 may be performed. In addition, in the embodiment, a process of forming a sixth through electrode 333 penetrating the 2-3 insulating layer 313 and a seventh circuit pattern 323 on an upper surface of the 2-3 insulating layer 313 may be performed.

[0221] 6h, in an embodiment, a process of forming a first-third insulating layer 213 on the lower surface of the first-second insulating layer 212 may be performed. Also, in an embodiment, a process of forming a third through electrode 233 penetrating the first-third insulating layer 213 and a fourth circuit pattern 224 on the lower surface of the first-third insulating layer 213 may be performed.

[0222] In addition, in the embodiment, a process of forming a 2-4 insulating layer 314 on the upper surface of the 2-3 insulating layer 313 may be performed. Next, in the embodiment, a process of forming a seventh through electrode 334 penetrating the 2-4 insulating layer 314 and an eighth circuit pattern 324 on the 2-4 insulating layer 314 may be performed.

[0223] In this embodiment, this completes the manufacturing of the circuit board 100 including the first substrate layer 200 and the second substrate layer 300 before the cavity C is formed.

[0224] Meanwhile, in the embodiment, as shown in FIG. 6i, in the process of forming the eighth circuit pattern 324, a portion of the seed layer of the eighth circuit pattern 324 is left unremoved so that it can be used as a mask in the process of forming the cavity C.

[0225] 6j, in the manufacturing process of the eighth circuit pattern 324, a seed layer 324-1 for forming the eighth circuit pattern 324 is located on the upper surface of the second to fourth insulating layer 314. The seed layer 324-1 can be used as a seed layer for electroplating the eighth circuit pattern 324.

[0226] Next, as shown in FIG. 6k, in an embodiment, since the eighth circuit pattern 324 is formed, a process of removing a region of the seed layer 324-1 that does not vertically overlap the eighth circuit pattern 324 may be performed. At this time, in an embodiment, a region 324-1a of the seed layer 324-1 adjacent to the region where the cavity C is to be formed is left unremoved. Then, in an embodiment, in a cavity formation process described below, the region 324-1a of the seed layer 324-1 may be used as a laser mask to perform a cavity formation process only on a portion corresponding to the third region RT1. At this time, the region RB1 of the seed layer 324-1 may cover a portion of the third region RT1, where the cavity C is to be formed. This is to take into consideration undercutting due to process deviations that occur during the laser formation process.

[0227] Next, as shown in FIG. 6l, in an embodiment, a process may be performed to form a first cavity C1 penetrating the second insulating layer of the second substrate layer 300 using the region RB1 of the seed layer 324-1. The first cavity C1 may be formed up to the top surface of the stopper layer 221-3, which is part of the first circuit pattern 221 of the first substrate layer 200. An inner wall IW1 of the first cavity C1 may have a first slope. For example, in an embodiment, a first cavity process may be performed. In this case, a laser mask used in the first cavity process may have a first width. The laser mask determines the width of a laser beam in a laser device. In this case, in an embodiment, the first cavity process may be performed using a first laser beam having a relatively large width to completely open the region where the cavity will be formed. As a result, the inner wall IW1 of the first cavity C1 formed by the first cavity process may have a first slope corresponding to the first laser beam.

[0228] Next, as shown in FIG. 6m, in this embodiment, a second cavity process may be performed on the first cavity C1 to form a second cavity C2. At this time, the width of the laser mask used in the second cavity process may have a second width smaller than the first width. The second cavity process is performed only on a portion corresponding to the inner wall of the first cavity C1 formed in the first cavity process. Because the width of the laser mask used in the second cavity process has a second width smaller than the first width, the inner wall of the second cavity C2 may have multiple slopes. For example, the inner wall of the second cavity C2 may include a first slope formed by the first cavity process and a second slope formed by the second cavity process.

[0229] For example, referring to FIG. 6n, in an embodiment, a process of forming the first cavity C1 may be performed by irradiating a first laser beam L1 corresponding to a mask having a first width of 280 μm. Thereafter, in an embodiment, a process of forming the second cavity C2 may be performed by irradiating a second laser beam L2 corresponding to a mask having a second width of 100 μm, which is smaller than the first width. Thus, the cavity in this embodiment includes a first slope corresponding to the first laser beam L1 and a second slope corresponding to the second laser beam L2. In this case, the overall slope of the cavity may have the second slope, but the first laser beam L1 penetrates the underside of region RB1 of the seed layer 324-1 during the first cavity formation process, resulting in an undercut region. The portion of the cavity C corresponding to the first slope may correspond to the undercut region formed during the first cavity process.

[0230] Next, as shown in Figure 6o, the stopper layer 221-3 exposed by the second cavity process may be removed to form a third part of the cavity C. At this time, the inner wall of the third part is the side of the first-third pattern 221-3. At this time, the third part of the cavity C may be formed to have the shape shown in any one of Figures 3a to 3c.

[0231] According to the embodiment, the circuit board includes a first substrate layer and a second substrate layer. The second substrate layer includes a cavity. The first substrate layer includes a first region vertically overlapping the cavity and a second region excluding the first region. The second substrate layer also includes a third region corresponding to the cavity and a fourth region excluding the third region. In this embodiment, the third region of the second substrate layer is a region where a driving element is disposed, and the fourth region is a region where an antenna pattern layer is disposed. In the above embodiment, the driving element is disposed using the cavity of the second substrate layer, and the antenna pattern layer is disposed in the fourth region of the second substrate layer horizontally adjacent to the driving element. As a result, in the embodiment, the signal transmission distance between the antenna pattern layer and the driving element can be minimized, thereby minimizing signal transmission loss. For example, in the embodiment, the signal transmission distance can be reduced compared to the comparative example in which a substrate on which a driving element is disposed and a substrate on which an antenna pattern layer is disposed are connected using a separate connection means, thereby reducing signal transmission loss caused by the separate connection means.

[0232] In addition, in an embodiment, by locating the driving elements in the cavities of the second substrate layer, the overall thickness of the circuit board can be reduced to correspond to the depth of the cavities.

[0233] In addition, the cavity in the embodiment includes a first part having a first slope and a second part having a second slope different from the first slope. The second slope has a smaller slope angle relative to the bottom surface of the cavity than the first slope. The vertical length of the second part having the second slope in the embodiment is longer than the vertical length of the first part having the first slope. As a result, the space occupied by the cavity in the embodiment can be reduced compared to the comparative example, thereby improving circuit integration. For example, by reducing the space occupied by the cavity in the embodiment, the length of the antenna pattern layer can be increased within a substrate having the same size as the comparative example, thereby improving communication performance.

[0234] In addition, in the embodiment, the first substrate layer includes a 1-1 insulating layer disposed adjacent to the first substrate layer and a first circuit pattern disposed on an upper surface of the 1-1 insulating layer. The first circuit pattern includes a 1-1 pattern formed in a first region vertically overlapping the cavity and a 1-2 pattern formed in a second region excluding the first region, and the upper surface of the 1-1 pattern is located lower than the upper surface of the 1-2 pattern. As a result, in the embodiment, damage to the surface of the 1-1 pattern can be prevented during a laser process for forming the cavity, thereby improving the electrical and physical reliability of the circuit board.

[0235] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in another embodiment by a person skilled in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0236] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. A person skilled in the art to which the embodiments pertain may make various modifications and applications not exemplified above within the scope of the essential characteristics of the embodiments. For example, each component specifically presented in the embodiments may be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer; a second insulating layer disposed on the first insulating layer and including a first through hole; a third insulating layer disposed on the second insulating layer and including a second through hole; a circuit portion disposed on the second insulating layer; a protective insulating layer disposed on the third insulating layer; an electronic element disposed inside the first through hole, the first through-hole overlaps the second through-hole in a vertical direction; the second insulating layer forms the first through hole and includes a first inner wall having a first inclination angle with respect to an upper surface of the first insulating layer; the third insulating layer forms the second through hole and includes a second inner wall having a second inclination angle with respect to the top surface of the first insulating layer that is greater than the first inclination angle; the circuit portion includes a wiring portion that does not overlap the first inner wall in the horizontal direction and overlaps the second inner wall along the horizontal direction, the electronic element overlaps the wiring portion and the contact portion where the first inner wall and the second inner wall are in contact with each other in a horizontal direction; A circuit board, wherein a vertical thickness of a portion of the second insulating layer having the first tilt angle is greater than a vertical thickness of a portion of the third insulating layer having the second tilt angle.

2. further comprising a metal layer disposed between the first insulating layer and the second insulating layer; The circuit board according to claim 1 , wherein the metal layer extends horizontally outside the first inner wall.

3. The circuit board according to claim 2 , wherein the metal layer overlaps the second through-hole in a vertical direction.

4. 4. The circuit board according to claim 1, wherein the first insulating layer, the second insulating layer, and the third insulating layer are made of the same material.

5. 4. The circuit board according to claim 1, wherein the electronic element overlaps the first inner wall and the second inner wall along the horizontal direction.

6. The circuit board according to claim 5 , wherein the electronic element is spaced apart from the first inner wall and the second inner wall in the horizontal direction.

7. The circuit board according to claim 6 , further comprising a buried insulating layer that embeds the first through-hole, the second through-hole, and the electronic element.

8. The circuit board according to claim 7 , wherein the buried insulating layer is made of a different material than the first insulating layer, the second insulating layer, and the third insulating layer.

9. The circuit unit includes: a first via electrode that penetrates at least a portion of the second insulating layer and is connected to a lower surface of the wiring portion; a second via electrode connected to an upper surface of the wiring portion and penetrating at least a portion of the third insulating layer, 4. The circuit board according to claim 1, wherein at least a portion of the first via electrode and the second via electrode overlaps with the electronic element along the horizontal direction.

10. the first tilt angle has a range between 91 degrees and 110 degrees; The circuit board according to any one of claims 1 to 3, wherein the second tilt angle has a range between 115 degrees and 150 degrees.

11. A circuit board described in any one of claims 1 to 3, wherein the vertical length of the first inner wall having the first inclination angle is greater than the vertical length of the second inner wall having the second inclination angle.

12. 4. The circuit board according to claim 1, wherein the vertical thickness of the portion of the second insulating layer having the first tilt angle is between 1.5 and 30 times the vertical thickness of the portion of the third insulating layer having the second tilt angle.

13. a metal layer disposed inside the first through-hole between the first insulating layer and the electronic element; 4. The circuit board according to claim 1, further comprising an adhesive member disposed between the metal layer and the electronic element.

14. 4. The circuit board according to claim 1, wherein the first and second through holes have horizontal widths that gradually decrease toward the first insulating layer.

15. a first insulating layer; a second insulating layer disposed on the first insulating layer and including a first through hole; a third insulating layer disposed on the second insulating layer and including a second through hole; a circuit layer disposed between the second insulating layer and the third insulating layer; an electronic element disposed inside the first through hole, the first through-hole overlaps the second through-hole in a vertical direction; the second insulating layer forms the first through hole and includes a first inner wall having a first inclination angle with respect to an upper surface of the first insulating layer; the third insulating layer forms the second through hole and includes a second inner wall having a second inclination angle with respect to the top surface of the first insulating layer, the second inclination angle being different from the first inclination angle; the electronic element overlaps the circuit layer and a contact portion where the first inner wall and the second inner wall are in contact with each other along a horizontal direction; A circuit board, wherein a vertical thickness of a portion of the second insulating layer having the first tilt angle is greater than a vertical thickness of a portion of the third insulating layer having the second tilt angle.

16. The circuit board of claim 15 , wherein the first tilt angle is less than the second tilt angle.

17. the first tilt angle has a range between 91 degrees and 110 degrees; 17. The circuit board of claim 16, wherein the second tilt angle has a range between 115 degrees and 150 degrees.

18. The circuit board according to claim 16 , wherein the electronic element overlaps the first inner wall, the second inner wall, and the circuit layer along the horizontal direction.

19. A circuit board as described in claim 16, wherein the vertical length of the first inner wall having the first inclination angle is greater than the vertical length of the second inner wall having the second inclination angle.

20. further comprising a metal layer disposed between the first insulating layer and the second insulating layer; The circuit board according to claim 18 , wherein the metal layer extends along the horizontal direction outside the first inner wall.

Images