Anomaly detection device

Abstract

A first detection circuit (11) and a second detection circuit (12) output a first signal when a corresponding abnormal state is detected. A first register (21) and a second register (22) store data that correspond to the first signal inputted from the corresponding detection circuit from among the first detection circuit (11) and the second detection circuit (12), and output a second signal. A first selection circuit (31) and a second selection circuit (32) select whether to output a third signal in response to the second signal inputted from the corresponding register from among the first register (21) and the second register (22). An exclusive OR circuit (41) outputs a fourth signal in response to the third signal inputted from the first selection circuit (31) and the second selection circuit (32). A single output terminal outputs, as an abnormality detection signal, the fourth signal outputted from the exclusive OR circuit (41).

Description

[Technical Field]

[0001] The present disclosure relates to an anomaly detection device. [Background technology]

[0002] A conventional device for detecting an abnormal state of a semiconductor device provided in various electronic devices is an interrupt signal generating device that includes a detection unit that detects various abnormal states, such as an abnormal state of a power supply, and an output terminal that outputs an interrupt signal when an abnormality is detected by the detection unit (Patent Document 1). In such an interrupt signal generating device, the interrupt signal is output from the output terminal to an internal bus of the device.

[0003] A semiconductor device is required to detect an abnormal condition inside the semiconductor device and output a detection signal indicating the detected abnormal condition to an external device. Such a semiconductor device has an abnormality detection device that includes a plurality of detection circuits that detect various abnormal conditions, a plurality of registers that are provided corresponding to the plurality of detection circuits and that store data of the detection signals output from the corresponding detection circuits, and a plurality of output terminals that are provided corresponding to the plurality of registers and that output the detection signals read from the corresponding registers to an external device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-55830 Summary of the Invention [Problem to be solved by the invention]

[0005] However, as mentioned above, in conventional abnormality detection devices that are provided with multiple output terminals corresponding to the number of detection circuits that detect abnormal conditions, there was a risk that the area of ​​the semiconductor substrate used to output the abnormality detection signal would become excessively large due to the excessive number of output terminals.

[0006] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide an abnormality detection device that can suppress the expansion of the area of ​​a semiconductor substrate used to output an abnormality detection signal. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, an abnormality detection device is capable of detecting multiple abnormal states that may occur in a semiconductor device, and includes multiple detection circuits, multiple registers, multiple selection circuits, an OR circuit, and one output terminal. The multiple detection circuits are provided corresponding to multiple abnormal states, respectively, and output a first signal when a corresponding abnormal state is detected. The multiple registers are provided corresponding to the multiple detection circuits, respectively, and store data corresponding to the first signal input from the corresponding detection circuit, and output a second signal according to the stored data. The multiple selection circuits are provided corresponding to the multiple registers, respectively, and select whether to output a third signal according to the second signal input from the corresponding register. The OR circuit can input the third signal from the multiple selection circuits, and outputs a fourth signal according to the input third signal. The one output terminal outputs the fourth signal output from the OR circuit as an abnormality detection signal indicating that an abnormal state has been detected.

[0008] According to another aspect of the present disclosure, an abnormality detection device is capable of detecting multiple abnormal states that may occur in a semiconductor device, and includes multiple detection circuits, multiple registers, multiple selection circuits, an OR circuit, a bypass circuit, an exclusive OR circuit, and one output terminal. The multiple detection circuits are provided corresponding to multiple abnormal states, respectively, and output a first signal when a corresponding abnormal state is detected. The multiple registers are provided corresponding to the multiple detection circuits, respectively, and store data corresponding to the first signal input from the corresponding detection circuit, and output a second signal corresponding to the stored data. The multiple selection circuits are provided corresponding to the multiple registers, respectively, and select whether to output a third signal depending on the second signal input from the corresponding register. The OR circuit can input the third signal from the multiple selection circuits, and outputs a fourth signal depending on the input third signal. The bypass circuit outputs a fifth signal corresponding to the first signal output from a detection circuit selected from the multiple detection circuits, bypassing the corresponding register and selection circuit. The exclusive OR circuit can receive the fourth signal output from the OR circuit and the fifth signal output from the bypass circuit, and outputs a sixth signal in response to the fourth and fifth signals. One output terminal outputs the sixth signal output from the exclusive OR circuit as an abnormality detection signal indicating that an abnormal state has been detected. The bypass circuit includes a plurality of selection switches provided corresponding to the plurality of detection circuits and capable of selecting a corresponding detection circuit, and a pulse generation circuit that outputs a fifth signal consisting of a one-shot pulse signal in response to the first signal output from the detection circuit selected by the plurality of selection switches. [Effects of the Invention]

[0009] According to an aspect of the present disclosure, an abnormality detection device uses a plurality of selection circuits to select whether to output a third signal in accordance with a second signal input from a corresponding register, thereby narrowing down the number of third signals input to an OR circuit. In the OR circuit, a fourth signal output in accordance with the input third signal is output as an abnormality detection signal from one output terminal, thereby reducing the number of output terminals that output abnormality detection signals. By reducing the number of output terminals that output abnormality detection signals, the area of ​​a semiconductor substrate used to output the abnormality detection signals can be reduced.

[0010] According to another aspect of the present disclosure, an abnormality detection device includes a plurality of selection circuits that select whether to output a third signal in response to a second signal input from a corresponding register, thereby narrowing down the number of third signals input to the OR circuit. The OR circuit outputs a fourth signal in response to the input third signal, and the exclusive OR circuit outputs a sixth signal in response to the fourth signal output from the OR circuit and a fifth signal output from the bypass circuit from a single output terminal as an abnormality detection signal. This reduces the number of output terminals that output abnormality detection signals, thereby reducing the area of ​​a semiconductor substrate used to output the abnormality detection signals. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a circuit diagram of an abnormality detection device according to a first embodiment. [Figure 2] FIG. 10 is a circuit diagram of an abnormality detection device according to a second embodiment. [Figure 3] FIG. 2 is a circuit diagram of a pulse generating circuit. [Figure 4] 4 is a timing chart showing signal levels at various points in a pulse generating circuit. [Figure 5] 1 is a truth table showing the relationship between the input and output of an exclusive OR circuit. [Figure 6]10 is a timing chart showing a first example of determining an abnormal state based on an output signal of an exclusive OR circuit. [Figure 7] 10 is a timing chart showing a second example of determining an abnormal state based on an output signal of an exclusive OR circuit. [Figure 8] FIG. 10 is a diagram showing an example of a circuit area and an output terminal pad area in the first to third embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. While multiple embodiments will be described below, it is anticipated from the beginning that the configurations described in each embodiment will be appropriately combined. Note that identical or corresponding parts in the drawings will be designated by the same reference numerals, and their description will not be repeated.

[0013] [Embodiment 1] (Configuration of the abnormality detection device 10) FIG. 1 is a circuit diagram of an abnormality detection device 10 according to the first embodiment.

[0014] 1, the abnormality detection device 10 is included in a semiconductor device 100. The abnormality detection device 10 includes an abnormality detection circuit 1, an abnormality storage register 2, an abnormality selection circuit 3, a logic circuit 4, a bypass circuit 5, and an output terminal 6. The abnormality detection device 10 further includes a first determination value storage circuit 7 and a second determination value storage circuit 8.

[0015] The semiconductor device 100 is a semiconductor device constituting a current sensor that detects a predetermined current and outputs a signal indicating the detected current value. Note that the semiconductor device 100 may be a semiconductor device constituting any electronic device.

[0016] The abnormality detection circuit 1 is a circuit that detects multiple abnormal states in the semiconductor device 100 and outputs a detection signal. The abnormality storage register 2 is a register that stores the abnormal states detected by the abnormality detection circuit 1, stores the detection signal output from the abnormality detection circuit 1, and outputs a corresponding signal to the abnormality selection circuit 3. The abnormality selection circuit 3 is a circuit that outputs a signal selected from the signals output from the abnormality storage register 2 to the logic circuit 4. The logic circuit 4 is a circuit that performs a logical operation according to the signal output from the abnormality selection circuit 3, and outputs a signal indicating the operation result to an output terminal 6.

[0017] The output terminal 6 is a terminal that outputs the signal output from the logic circuit 4 as an abnormality detection signal by the abnormality detection device 10. The output terminal 6 passes through a signal path provided in the semiconductor device 100 and is output to the outside of the semiconductor device 100 via an external output terminal provided in the semiconductor device 100.

[0018] In addition, the output terminal 6 may itself have the function of an external output terminal that outputs a signal to the outside of the semiconductor device 100. In this case, the signal output via the output terminal 6 provided in the abnormality detection device 10 is output to the outside of the semiconductor device 100 as an abnormality detection signal indicating that an abnormal state has been detected in the semiconductor device 100.

[0019] Outside the semiconductor device 100, there is a system that uses various signals output from the semiconductor device 100. If the semiconductor device 100 is, for example, a current sensor, a current detection signal output from the semiconductor device 100 is output to a system that uses a current value detected by the semiconductor device 100. An abnormality detection signal indicating that an abnormal state has been detected in the semiconductor device 100 is also output to a system that uses a current value detected by the semiconductor device 100.

[0020] The abnormality detection circuit 1 includes a first detection circuit 11 and a second detection circuit 12 provided to correspond to a plurality of abnormal states. The abnormality storage register 2 includes a first register 21 and a second register 22. The abnormality selection circuit 3 includes a first selection circuit 31 and a second selection circuit 32. The logic circuit 4 includes a logical OR circuit 41. The bypass circuit 5 includes a first selection switch 51 and a second selection switch 52.

[0021] In the abnormality storage register 2, a first register 21 is provided corresponding to the first detection circuit 11. In the abnormality storage register 2, a second register 22 is provided corresponding to the second detection circuit 12.

[0023] In the abnormality selection circuit 3, a first selection circuit 31 is provided corresponding to the first register 21. In the abnormality selection circuit 3, a second selection circuit 32 is provided corresponding to the second register 22. The first selection circuit 31 is a logical product circuit having two input terminals, a first input terminal and a second input terminal, and one output terminal, and outputs an output signal from the output terminal at a level corresponding to the logical product of the input signals from the first input terminal and the second input terminal. The second selection circuit 32 is a logical product circuit similar to the first selection circuit 31.

[0024] The semiconductor device 100 is provided with a voltage monitor circuit 101. The voltage monitor circuit 101 converts a current value detected by the semiconductor device 100, which constitutes a current sensor, into a voltage value, and outputs the voltage value as a monitor voltage VM.

[0025] The first judgment value storage circuit 7 stores an upper limit voltage VH, which is the upper limit of the monitor voltage, as a first judgment value. The first judgment value storage circuit 7 outputs the stored upper limit voltage VH. The second judgment value storage circuit 8 stores a lower limit voltage VL, which is the lower limit of the monitor voltage, as a second judgment value. The second judgment value storage circuit 8 outputs the stored lower limit voltage VL.

[0026] The first detection circuit 11 and the second detection circuit 12 are comparators. The first detection circuit 11 receives a monitor voltage VM and an upper limit voltage VH. When an abnormal state occurs in which the monitor voltage VM is higher than the upper limit voltage VH, the output signal of the first detection circuit 11 becomes H level. The second detection circuit 12 receives a monitor voltage VM and a lower limit voltage VL. When an abnormal state occurs in which the monitor voltage VM is lower than the lower limit voltage VL, the output signal of the second detection circuit 12 becomes H level. In this way, the first detection circuit 11 and the second detection circuit 12 are provided to correspond to a plurality of types of abnormal states.

[0027] The signal output from the first detection circuit 11 is output to the first register 21 and the first selection switch 51. When the signal output from the first detection circuit 11 is at an H level, the first register 21 stores the H-level signal state.

[0028] The signal output from the second detection circuit 12 is output to the second register 22 and the second selection switch 52. When the signal output from the second detection circuit 12 is at an H level, the second register 22 stores the H-level signal state.

[0029] The output signal of the first register 21 is input to the first selection circuit 31 from a first input terminal of the first selection circuit 31. The output signal of the second register 22 is input to the second selection circuit 32 from a first input terminal of the second selection circuit 32. The first selection circuit 31 and the second selection circuit 32 are both configured by logical AND circuits.

[0030] The mask register 33 is a register that enables selection of either the first selection circuit 31 or the second selection circuit 32, which circuit outputs a signal corresponding to the signal input from the corresponding register.

[0031] The mask register 33 selects a circuit from among the multiple circuits of the first selection circuit 31 and the second selection circuit 32 that outputs a signal by always setting the signal level of the second input terminal of that circuit to an H level.

[0032] The mask register 33 does not select any of the multiple circuits in the first selection circuit 31 and the second selection circuit 32 that do not want to output a signal by always setting the signal level of the second input terminal of that circuit to an L level.

[0033] In the abnormality selection circuit 3, due to the function of the mask register 33, among the multiple circuits of the first selection circuit 31 and the second selection circuit 32, the circuit whose second input terminal signal level is set to H level is selected as the circuit that outputs a signal corresponding to the signal input from the corresponding register.

[0034] The signal output from the first selection circuit 31 and the signal output from the second selection circuit 32 are input to an OR circuit 41 .

[0035] When the first selection circuit 31 is selected as the circuit to output a signal, when the first detection circuit 11 detects an abnormal state and the output signal becomes H level, the signal input to the corresponding first register 21 and the logical OR circuit 41 via the first selection circuit 31 becomes H level.

[0036] When the second selection circuit 32 is selected as the circuit to output a signal, when the second detection circuit 12 detects an abnormal state and the output signal becomes H level, the signal input to the corresponding second register 22 and the logical OR circuit 41 via the second selection circuit 32 becomes H level.

[0037] In the abnormality selection circuit 3, a user of the abnormality detection device 10 can adjust the signals output from the mask register 33 to the first selection circuit 31 and the second selection circuit 32 as needed, thereby selecting a selection circuit that outputs a signal corresponding to a signal indicating a detected abnormal state. Therefore, in the abnormality selection circuit 3, both the first selection circuit 31 and the second selection circuit 32 can be made to output a signal corresponding to a signal indicating a detected abnormal state, or either the first selection circuit 31 or the second selection circuit 32 can be made to output a signal corresponding to a signal indicating a detected abnormal state. This allows the user of the abnormality detection device 10 to output a signal corresponding to a signal indicating a detected abnormal state of the type required by the user of the abnormality detection device 10. In this way, the abnormality selection circuit 3 can narrow down the number of signals input to the OR circuit.

[0038] In the bypass circuit 5, when the first selection switch 51 is in the ON state, the output signal of the first detection circuit 11 passes through a signal path in the bypass circuit 5, bypassing the corresponding first register 21 and first selection circuit 31, and is input to the OR circuit 41. For example, when the first selection switch 51 is in the ON state, if the first detection circuit 11 detects an abnormal state and its output signal becomes H level, the signal input to the OR circuit 41 via the first selection switch 51 and the signal path in the bypass circuit 5 becomes H level.

[0039] In the bypass circuit 5, when the second selection switch 52 is in the ON state, the output signal of the second detection circuit 12 passes through a signal path in the bypass circuit 5, bypassing the corresponding second register 22 and second selection circuit 32, and is input to the OR circuit 41. For example, when the second selection switch 52 is in the ON state, if the second detection circuit 12 detects an abnormal state and its output signal becomes H level, the signal input to the OR circuit 41 via the second selection switch 52 and the signal path in the bypass circuit 5 becomes H level.

[0040] The OR circuit 41 outputs a signal indicating the logical sum of the signal input from the first selection circuit 31, the signal input from the second selection circuit 32, and the signal input from the bypass circuit 5. The signal output from the OR circuit 41 is output via the output terminal 6. When the signal output from the OR circuit 41 is at an H level, the signal output via the output terminal 6 is an abnormality detection signal indicating that an abnormal state has been detected.

[0041] In the bypass circuit 5, the output signal of the first detection circuit 11 and the output signal of the second detection circuit 12 are input to the logical OR circuit 41, bypassing the abnormality memory register 2 and the abnormality selection circuit 3. Therefore, the output signal of the first detection circuit 11 and the output signal of the second detection circuit 12 are input to the logical OR circuit 41 at a higher speed than when they pass through the normal signal path that inputs them to the logical OR circuit 41 via the abnormality memory register 2 and the abnormality selection circuit 3.

[0042] For example, the user of the abnormality detection device 10 sets the corresponding switch of the first selection switch 51 and the second selection switch 52 to the on state for a special abnormal state that requires an emergency response when detected among the multiple types of abnormal states. Of the multiple types of abnormal states, abnormal states other than the special abnormal state may be called standard abnormal states.

[0043] As a result, when an abnormal state is detected in which the corresponding switch of the first selection switch 51 or the second selection switch 52 is set to the on state, the detection signal is input to the logical sum circuit 41 via the bypass circuit 5, and an abnormality detection signal is output via the output terminal 6 at an earlier timing than when the detection signal is input to the logical sum circuit 41 via the normal signal path.

[0044] As an example, if a user of the abnormality detection device 10 needs to deal with an abnormal state detected by the first detection circuit 11 when the monitor voltage VM output from the voltage monitor circuit 101 becomes higher than the upper limit voltage VH more urgently than an abnormal state detected by the second detection circuit 12 when the monitor voltage VM becomes lower than the lower limit voltage VL, the user sets the first selection switch 51 to the on state.

[0045] When the first selection switch 51 is set to the on state in this way, the first selection circuit 31 may be set to be able to output a signal or may be set to be unable to output a signal. Similarly, when the second selection switch 52 is set to the on state, the second selection circuit 32 may be set to be able to output a signal or may be set to be unable to output a signal.

[0046] For example, when the first selection switch 51 is set to the off state and the second selection circuit 32 is set to be able to output a signal, when the second detection circuit 12 detects an abnormal state in which the monitor voltage VM has become lower than the lower limit voltage VL, an abnormality detection signal corresponding to the signal output from the second detection circuit 12 passes through the second register 22, the second selection circuit 32, and the logical sum circuit 41 and is output from the output terminal 6 at a first timing.

[0047] For example, when the first selection switch 51 is set to an on state and the first selection circuit 31 is set to be able to output a signal, when an abnormal state occurs in which the monitor voltage VM becomes higher than the upper limit voltage VH, an abnormality detection signal corresponding to the signal output from the first detection circuit 11 passes through the first register 21, the first selection circuit 31, and the logical sum circuit 41 and is output from the output terminal 6 at a first timing, before the abnormality detection signal corresponding to the signal output from the first detection circuit 11 passes through the first selection switch 51 and the logical sum circuit 41 of the bypass circuit 5 and is output from the output terminal 6 at a second timing earlier than the first timing.

[0048] The first embodiment described above can achieve the following technical effects. Regarding the detection signals output from the first detection circuit 11 and the second detection circuit 12, the first selection circuit 31 and the second selection circuit 32, which are multiple selection circuits, select whether or not to output a signal in accordance with the signals input from the corresponding registers, the first register 21 and the second register 22. This makes it possible to narrow down the number of signals input to the OR circuit 41. In the OR circuit 41, a signal output in accordance with the input signal is output as an abnormality detection signal from one output terminal 6. This makes it possible to reduce the number of output terminals that output abnormality detection signals. By reducing the number of output terminals 6 that output abnormality detection signals, it is possible to reduce the area of ​​the semiconductor substrate used to output the abnormality detection signals.

[0049] Furthermore, the bypass circuit 5 allows the signals output from the first detection circuit 11 and the second detection circuit 12, which are detection circuits selected by the first selection switch 51 and the second selection switch 52, which are multiple selection switches, to be input to the logical sum circuit 41, bypassing normal signal paths such as the corresponding registers and selection circuits. Therefore, an abnormality detection signal can be output via the output terminal 6 at an earlier timing than when the detection signals from the first detection circuit 11 and the second detection circuit 12 are input to the logical sum circuit 41 via the normal signal path.

[0050] 1 may be configured without the bypass circuit 5. Even with such a configuration, the area of ​​the semiconductor substrate used to output the abnormality detection signal can be reduced.

[0051] [Embodiment 2] (Configuration of the abnormality detection device 10a) 2 is a circuit diagram of an abnormality detection device 10a according to embodiment 2. The abnormality detection device 10a will be described mainly with respect to differences in configuration from the abnormality detection device 10 according to embodiment 1.

[0052] The abnormality detection device 10a shown in Fig. 2 differs from the abnormality detection device 10 shown in Fig. 1 in the configurations of the logic circuit 40 and the bypass circuit 50. The logic circuit 40 includes an exclusive OR circuit 42 in addition to a logical OR circuit 41. The bypass circuit 50 includes a pulse generation circuit 53 in addition to a first selection switch 51 and a second selection switch 52.

[0053] The OR circuit 41 receives the signal output from the first selection circuit 31 and the signal output from the second selection circuit 32. The OR circuit 41 outputs a signal indicating the logical sum of the signal input from the first selection circuit 31 and the signal input from the second selection circuit 32. The signal output from the OR circuit 41 is input to an exclusive OR circuit 42.

[0054] In the bypass circuit 50, the signal output from the first selection switch 51 and the signal output from the second selection switch 52 are input to the pulse generation circuit 53. The pulse generation circuit 53 generates a one-shot pulse signal in accordance with the signal input from the first selection switch 51 and the signal input from the second selection switch 52. The one-shot pulse signal output from the pulse generation circuit 53 is input to the exclusive OR circuit 42.

[0055] The exclusive OR circuit 42 outputs a signal indicating the exclusive OR of the signal input from the OR circuit 41 and the signal input from the pulse generating circuit 53. The signal output from the OR circuit 41 is output via the output terminal 6. The signal output from the exclusive OR circuit 42 is an abnormality detection signal that indicates that an abnormal state has been detected in accordance with the change in the signal, as shown in FIGS. 5 to 7.

[0056] (Configuration of pulse generating circuit 53) 3 is a circuit diagram of the pulse generating circuit 53. When the input voltage Vin at the input terminal 530 becomes H level, the pulse generating circuit 53 outputs a one-shot pulse signal that causes the output voltage Vout at the output terminal 535 to become H level for a predetermined time.

[0057] The pulse generating circuit 53 includes a resistor 531, a capacitor 532, an inverter circuit 533, and a logical product circuit 534. A first input terminal of the logical product circuit 534 is connected to the input terminal 530.

[0058] A resistor 531 and a capacitor 532 are connected in series between the input terminal 530 and ground 536. An inverting circuit 533 is connected between a connection point 537 of the resistor 531 and the capacitor 532 and a second input terminal of the AND circuit 534.

[0059] The voltage at connection point 537 of the RC circuit formed by resistor 531 and capacitor 532 becomes the input voltage V1 of inverter circuit 533. The output voltage V2 of inverter circuit 533 becomes the input voltage to the second input terminal of AND circuit 534. The output voltage Vout of AND circuit 534 becomes the input voltage to the input terminal of exclusive OR circuit 42.

[0060] Fig. 4 is a timing chart showing the signal levels of each part in the pulse generating circuit 53. Fig. 4 shows the relationship between the voltage Vin, the voltage V1, the voltage V2, and the voltage Vout.

[0061] 4, for example, when the first selection switch 51 is set to the ON state, if the detection signal of the first detection circuit 11 changes from L level to H level, the voltage Vin changes from L level to H level. When the voltage Vin changes to H level, the voltage V1 changes from L level to H level with a timing delayed by a delay period t determined by the time constant of the RC circuit.

[0062] When the voltage V1 changes to the H level, the voltage V2, whose level has been inverted by the inverting circuit 533, changes from the H level to the L level. The AND circuit 534 has a first input terminal that is the voltage Vin and a second input terminal that is the voltage V2. Before the voltage Vin changes to the H level, the output voltage Vout of the AND circuit 534 is the sum of the voltages Vin and V 1is at L level, and becomes H level during a period t corresponding to the delay period t from when voltage Vin changes to H level until voltage V2 changes to L level with a delay, and then becomes L level.

[0063] With this configuration, the voltage out output from the AND circuit 534, i.e., the voltage Vout at the output terminal 535, becomes a one-shot pulse signal that becomes H level during the period t when the voltage V1 changes from L level to H level. Therefore, the pulse generating circuit 53 outputs a one-shot pulse signal when the input signal becomes H level.

[0064] As the pulse generating circuit 53, a pulse generating circuit other than the circuit shown in FIG. 3 may be used as long as it is a circuit that outputs a one-shot pulse signal.

[0065] (Relationship between input and output of exclusive OR circuit 42) Next, the relationship between the input and output of the exclusive OR circuit 42 will be explained.

[0066] Fig. 5 is a truth table showing the relationship between the input and output of the exclusive OR circuit 42. Fig. 5 shows the relationship between the input signal X from the OR circuit 41 to the exclusive OR circuit 42, the input signal Y from the pulse generating circuit 53 to the exclusive OR circuit 42, and the output signal Z from the exclusive OR circuit 42. Fig. 5 also shows the relationship between the states of the input signals X, Y and output signal Z and the detection state of an abnormal state.

[0067] When input signal X and input signal Y are at L level, output signal Z is at L level. If this relationship exists, no abnormal condition has been detected. If input signal X is at H level and input signal Y is at L level, output signal Z is at H level. If this relationship exists, a standard abnormal condition has been detected.

[0068] When input signal X is at L level and input signal Y is at H level, output signal Z is at H level. When this relationship exists, it means that a special abnormal condition has been detected. When input signal X and input signal Y are at H level, output signal Z is at L level. When this relationship exists, it means that a standard abnormal condition and a special abnormal condition have been detected simultaneously.

[0069] (Example of Determining Abnormal State Based on Output Signal of Exclusive OR Circuit 42) Next, an example of determining an abnormal state based on the output signal of the exclusive OR circuit 42 will be described. Fig. 6 is a timing chart showing a first example of determining an abnormal state based on the output signal of the exclusive OR circuit 42. Fig. 6 shows an example in which a standard abnormal state occurs after a special abnormal state is detected.

[0070] 6, when a special abnormal state is detected at timing Ta, a one-shot pulse signal is input from pulse generating circuit 53 of bypass circuit 50 to exclusive OR circuit 42 at timing Ta, and therefore the output signal of exclusive OR circuit 42 becomes H level during period t from timing Ta to Tb. Thereafter, when a standard abnormal state is detected during period Tc to Td, a H level signal is input from OR circuit 41 during period Tc to Td, and therefore the output signal of exclusive OR circuit 42 becomes H level during period Tc to Td.

[0071] In the first example shown in Fig. 6, when the output signal of the exclusive OR circuit 42 becomes H level with a one-shot pulse as in timing Ta to Tb, it can be determined that a special abnormal state has been detected. In the first example shown in Fig. 6, when the output signal of the exclusive OR circuit 42 becomes H level for a period longer than the H level period t of the one-shot pulse as in timing Tc to Td, it can be determined that a standard abnormal state has been detected.

[0072] 7 is a timing chart showing a second example of determining an abnormal state based on the output signal of the exclusive OR circuit 42. In FIG. 7, an example is shown in which a special abnormal state is detected when a standard abnormal state has been detected.

[0073] 7, when a standard abnormal state is detected at timing Te, an H-level signal is input from the OR circuit 41 during the period from timing Te to Th. As a result, the output signal of the exclusive OR circuit 42 is basically H-level during the period from timing Te to Th. When a special abnormal state is detected at timing Tf within the period from timing Te to Th, a one-shot pulse signal is input from the pulse generating circuit 53 of the bypass circuit 50 to the exclusive OR circuit 42 at timing Tf. As a result, the output signal of the exclusive OR circuit 42 changes from H-level to L-level during the period t from timing Tf to Tg due to the relationship shown in FIG.

[0074] 7, when the output signal of the exclusive OR circuit 42 remains at H level for a period longer than the H level period t of the one-shot pulse, such as from timing Te to Th, it can be determined that a standard abnormal state has been detected. When the output signal changes from H level to L level during period t, such as from timing Tf to Tg, it can be determined that a special abnormal state has been detected during the period Tf to Tg.

[0075] In addition to the effects achieved by the abnormality detection device 10 of the first embodiment, the abnormality detection device 10a of the second embodiment has the following configuration. As described with reference to Figures 6 and 7, the abnormality detection device 10a can indicate whether or not a special abnormal condition has been detected, and can also indicate that a standard abnormal condition has been detected, based on the change in the signal output from the exclusive OR circuit 42. Therefore, by checking the change in the signal output from the output terminal 6, the abnormality detection device 10a can indicate whether or not a special abnormal condition has been detected, and can also indicate that a standard abnormal condition has been detected.

[0076] [Embodiment 3] (Another setting example of the abnormality selection circuit 3 when outputting a signal in response to the detection of a special abnormality state) In embodiment 3, other setting examples of the abnormality selection circuit 3 are described when the first selection switch 51 and the second selection switch 52 are used to set the bypass circuits 5, 50 to output a signal indicating that a special abnormality state has been detected.

[0077] In the above-described first and second embodiments, an example has been described in which, even when the first selection switch 51 or the second selection switch 52 is set to the on state, the first selection circuit 31 and the second selection circuit 32 corresponding to the first detection circuit 11 and the second detection circuit 12 corresponding to the first selection switch 51 and the second selection switch 52 are set by the mask register 33 so as to output signals in accordance with signals input from the corresponding first register 21 and second register 22.

[0078] However, this is not limited to this, and when the first selection switch 51 or the second selection switch 52 is set to the on state, the first selection circuit 31 or the second selection circuit 32 corresponding to the first detection circuit 11 or the second detection circuit 12 corresponding to the selection switch other than the first selection switch 51 or the second selection switch 52 may be set by the mask register 33 so as not to output a signal in response to the signal input from the corresponding first register 21 or second register 22.

[0079] With such a setting, if an abnormal condition is detected and does not require urgent action, a signal indicating the detection of an abnormal condition is not output. Therefore, it is possible to narrow down the abnormal conditions to be addressed from the abnormal conditions indicated by the signal output from the OR circuit 41 via the output terminal 6, and it becomes possible to quickly take action against abnormal conditions that require urgent action.

[0080] [Example of Circuit Area and Output Terminal Pad Area in Embodiments 1 to 3] Next, an example of the circuit area and the pad area for the output terminal in the first to third embodiments is shown in FIG. 8 This is explained using visual images.

[0081] 1 and 2, in order to output the abnormality detection signal output from the output terminal 6 to the outside of the semiconductor device 100, it is necessary to provide pads, which are electrodes made of a metal film for signal output, on the semiconductor substrate on which the semiconductor device 100 is provided. One pad must be provided for each output terminal. Therefore, it is necessary to provide the same number of pads as the number of output terminals.

[0082] 8 is a diagram showing an example of the area of ​​the circuit and the area of ​​the pad for signal output in the first to third embodiments. Referring to FIG. 8, in a semiconductor substrate on which the semiconductor device 100 shown in FIGS. 1 and 2 is provided, the chip area of ​​the circuit region 61 on which the circuits constituting the abnormality detection devices 10 and 10a are provided is, for example, 36 μm 2 This is because the circuit constituting the abnormality detection device 10, 10a is composed of approximately 600 transistors, and the chip area on which each transistor is provided is 0.06 μm 2 This is an example of a case where:

[0083] 8, the chip area of ​​pad region 62 in which pads for signal output are provided in a semiconductor substrate provided with a semiconductor device such as semiconductor device 100 shown in FIGS. 1 and 2 is, for example, 60 μm×60 μm=360 μm per pad region 62. 2 8, the chip area of ​​the circuit region 61 and the chip area of ​​the pad region 62 are shown so as to be comparable.

[0084] As shown in Fig. 8, the chip area of ​​pad region 62 requires an area that is approximately 100 times larger than the chip area of ​​circuit region 61. Therefore, when an output terminal is provided for each of a plurality of abnormality detection signals as in the conventional case, for example, in the case of five output terminals, the chip area of ​​the pad region requires five times the chip area of ​​one pad region 62 shown in Fig. 8, which clearly results in an excessive increase in the area of ​​the semiconductor substrate, as is clear from a comparison of circuit region 61 and pad region 62 in Fig. 8. In contrast, in abnormality detection devices 10 and 10a shown in embodiments 1 to 3, there is only one output terminal 6 that outputs an abnormality detection signal, and therefore the area of ​​the semiconductor substrate used to output the abnormality detection signal can be reduced.

[0085] [Other variations] Next, other modifications of the embodiment of the present disclosure will be described.

[0086] (1) In the first to third embodiments, the case where there is one type of voltage as an example of the monitor voltage has been described, but the monitor voltage may be any of various voltages, such as the power supply voltage of the semiconductor device 100, the internal regulator voltage, the output voltage, the voltage of the temperature sensor, and the differential voltage of the redundant temperature sensor.

[0087] (2) In the first to third embodiments, an example has been shown in which two detection circuits, namely, first detection circuit 11 and second detection circuit 12, are provided as detection circuits for detecting an abnormality corresponding to one type of monitor voltage. However, three or more detection circuits may be provided as detection circuits included in abnormality detection circuit 1 in accordance with one type of monitor voltage. In that case, the number of registers in abnormality storage register 2, the number of selection circuits in abnormality selection circuit 3, and the number of selection switches in bypass circuits 5 and 50 are provided in a manner corresponding to the number of detection circuits.

[0088] (3) In the first to third embodiments, two detection circuits are provided corresponding to one type of monitor voltage. However, this is not limiting, and when one type of abnormal state is to be detected from one type of monitor voltage, one detection circuit may be provided corresponding to one type of monitor voltage. In this case, the registers of the abnormality storage register 2, the selection circuits of the abnormality selection circuit, and the selection switches of the bypass circuits 5 and 50 are provided in numbers corresponding to the number of detection circuits.

[0089] (4) In the bypass circuit 5 of the first embodiment, an example has been shown in which one signal path is provided corresponding to a plurality of selection switches, such as the first selection switch 51 and the second selection switch 52. However, this is not limiting, and a plurality of signal paths may be provided corresponding to a plurality of selection switches, and signals may be input to the OR circuit 41 from the plurality of selection switches via the plurality of signal paths.

[0090] [Note] Next, features of the embodiments of the present disclosure will be summarized.

[0091] <1> An abnormality detection device (abnormality detection device 10) capable of detecting a plurality of abnormal states that may occur in a semiconductor device (semiconductor device 100), the abnormality detection device including a plurality of detection circuits (first detection circuit 11, second detection circuit 12) that are provided corresponding to the plurality of abnormal states, respectively, and that output a first signal when the corresponding abnormal state is detected; and a plurality of registers (first register 21, second register 22) that are provided corresponding to the plurality of detection circuits (first detection circuit 11, second detection circuit 12), respectively, that store data corresponding to the first signal input from the corresponding detection circuit, and that output a second signal according to the stored data. ), a plurality of selection circuits (first selection circuit 31, second selection circuit 32) respectively provided corresponding to the plurality of registers (first register 21, second register 22) and selecting whether or not to output a third signal in accordance with a second signal input from the corresponding register, a logical sum circuit (logical sum circuit 41) to which the third signal can be input from the plurality of selection circuits and which outputs a fourth signal in accordance with the input third signal, and one output terminal (output terminal 6) which outputs the fourth signal output from the logical sum circuit as an abnormality detection signal indicating that an abnormal state has been detected (see FIG. 1 ).

[0092] <2> The abnormality detection device (abnormality detection device 10) according to <1>, further comprising: a bypass circuit (bypass circuit 5) that includes a plurality of selection switches (first selection switch 51, second selection switch 52) that are provided corresponding to the plurality of detection circuits (first detection circuit 11, second detection circuit 12) and that can select the corresponding detection circuit; the bypass circuit (bypass circuit 5) that causes a first signal output from a detection circuit selected by the plurality of selection switches (first selection switch 51, second selection switch 52) to be input to the OR circuit (OR circuit 41) bypassing a corresponding register and selection circuit; and the OR circuit (OR circuit 41) outputs the fourth signal in response to the first signal input from the bypass circuit (bypass circuit 5) and a third signal that can be input from the plurality of selection circuits (see FIG. 1).

[0093] <3> An abnormality detection device (abnormality detection device 10) capable of detecting a plurality of abnormal states that may occur in a semiconductor device (semiconductor device 100), the abnormality detection device including: a plurality of detection circuits (first detection circuit 11, second detection circuit 12) provided corresponding to the plurality of abnormal states, each outputting a first signal when detecting a corresponding abnormal state; and a plurality of registers (registers) provided corresponding to the plurality of detection circuits (first detection circuit 11, second detection circuit 12), each storing data corresponding to the first signal input from the corresponding detection circuit, and outputting a second signal corresponding to the stored data. a plurality of selection circuits (first selection circuit 31, second selection circuit 32) provided corresponding to the plurality of registers (first register 21, second register 22) and selecting whether to output a third signal in response to a second signal input from the corresponding register; a logical OR circuit (logical OR circuit 41) to which the third signal can be input from the plurality of selection circuits and which outputs a fourth signal in response to the input third signal; and a fifth signal in response to the first signal output from a detection circuit selected from the plurality of detection circuits and which outputs a fifth signal in response to the first signal output from the corresponding register and and a bypass circuit (bypass circuit 50) that bypasses the selection circuit and outputs the signal; an exclusive OR circuit (exclusive OR circuit 42) that can receive the fourth signal output from the OR circuit (OR circuit 41) and the fifth signal output from the bypass circuit (bypass circuit 50) and that outputs a sixth signal in response to the fourth signal and the fifth signal that are input; and one output terminal (output terminal 6) that outputs the sixth signal output from the exclusive OR circuit (exclusive OR circuit 42) as an abnormality detection signal indicating that the abnormal state has been detected. The bypass circuit (bypass circuit 50) is provided corresponding to each of the plurality of detection circuits (first detection circuit 11, second detection circuit 12), and includes a plurality of selection switches (first selection switch 51, second selection switch 52) that can select the corresponding detection circuit, and a pulse generation circuit (pulse generation circuit 53) that outputs the fifth signal consisting of a one-shot pulse signal in response to a first signal output from a detection circuit selected by the plurality of selection switches (first selection switch 51, second selection switch 52) (see Figures 2 to 4).

[0094] <4> The sixth signal can indicate whether or not an abnormal state has been detected by the detection circuit selected by the plurality of selection switches (first selection switch 51, second selection switch 52) according to the change in signal level (see Figures 6 and 7), in the abnormality detection device (abnormality detection device 10a) described in <3>.

[0095] <5> An abnormality detection device according to any one of <2> to <4>, wherein the selection circuit corresponding to the detection circuit not selected by the plurality of selection switches (first selection switch 51, second selection switch 52) is configured not to output a third signal in response to the second signal from the corresponding register (see embodiment 3).

[0096] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0097] 100 semiconductor device, 10, 10a abnormality detection device, 11 first detection circuit, 12 second detection circuit, 21 first register, 22 second register, 31 first selection circuit, 32 second selection circuit, 41 logical sum circuit, 6 output terminal, 51 first selection switch, 52 second selection switch, 5, 50 bypass circuit, 42 exclusive logical sum circuit.

Claims

1. An abnormality detection device capable of detecting a plurality of abnormal states that may occur in a semiconductor device, a plurality of detection circuits provided corresponding to the plurality of abnormal states, each of which outputs a first signal when detecting a corresponding abnormal state; a plurality of registers provided corresponding to the plurality of detection circuits, each register storing data corresponding to a first signal input from the corresponding detection circuit, and outputting a second signal corresponding to the stored data; a plurality of selection circuits provided corresponding to the plurality of registers, each selecting whether to output a third signal in response to a second signal input from the corresponding register; a logical OR circuit to which third signals can be input from the plurality of selection circuits and which outputs a fourth signal in response to the input third signals; an output terminal that outputs the fourth signal output from the OR circuit as an abnormality detection signal indicating that an abnormal state has been detected.

2. a bypass circuit including a plurality of selection switches respectively provided corresponding to the plurality of detection circuits and capable of selecting a corresponding detection circuit, and causing a first signal output from a detection circuit selected by the plurality of selection switches to bypass a corresponding register and selection circuit and input to the OR circuit; 2. The abnormality detection device according to claim 1, wherein the OR circuit outputs the fourth signal in response to a first signal input from the bypass circuit and a third signal that can be input from the plurality of selection circuits.

3. An abnormality detection device capable of detecting a plurality of abnormal states that may occur in a semiconductor device, a plurality of detection circuits provided corresponding to the plurality of abnormal states, each of which outputs a first signal when detecting a corresponding abnormal state; a plurality of registers provided corresponding to the plurality of detection circuits, each register storing data corresponding to a first signal input from the corresponding detection circuit, and outputting a second signal corresponding to the stored data; a plurality of selection circuits provided corresponding to the plurality of registers, each selecting whether to output a third signal in response to a second signal input from the corresponding register; a logical OR circuit to which third signals can be input from the plurality of selection circuits and which outputs a fourth signal in response to the input third signals; a bypass circuit that outputs a fifth signal corresponding to a first signal output from a detection circuit selected from the plurality of detection circuits, bypassing a corresponding register and a selection circuit; an exclusive OR circuit to which the fourth signal output from the OR circuit and the fifth signal output from the bypass circuit can be input, and which outputs a sixth signal in response to the fourth signal and the fifth signal input; an output terminal that outputs the sixth signal output from the exclusive OR circuit as an abnormality detection signal indicating that the abnormal state has been detected; The bypass circuit is a plurality of selection switches provided corresponding to the plurality of detection circuits, each of which can select a corresponding detection circuit; a pulse generating circuit that outputs the fifth signal, which is a one-shot pulse signal, in response to a first signal output from a detection circuit selected by the plurality of selection switches.

4. 4. The abnormality detection device according to claim 3, wherein the sixth signal is capable of indicating whether or not an abnormal state has been detected by a detection circuit selected by the plurality of selection switches, depending on a change in signal level.

5. The abnormality detection device according to any one of claims 2 to 4, wherein a selection circuit corresponding to a detection circuit not selected by the plurality of selection switches is configured not to output a third signal in response to a second signal from a corresponding register.

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