Nanosheet metal oxide semiconductor field-effect transistors with asymmetric threshold voltages

Abstract

The semiconductor structure and method of forming the semiconductor structure include an internal spacer positioned between channel nanosheets on a semiconductor substrate, a first portion of the internal spacer positioned on a first side of the semiconductor structure and a second portion of the internal spacer positioned on a second side opposite the first side, the first portion of the internal spacer on the first side including a protruding region extending outwardly from a central top surface of the first portion of the internal spacer, and a metal gate stack in direct contact with the internal spacer, the first portion of the internal spacer including the protruding region that pinches off the metal gate stack to increase a threshold voltage of the first side.

Description

[Technical Field]

[0001] The present invention relates generally to the field of complementary metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and more particularly to nanosheet MOSFETs with asymmetric threshold voltages. [Background technology]

[0002] In recent semiconductor device fabrication processes, numerous semiconductor devices, such as field-effect transistors (FETs), are assembled on a single wafer. Nonplanar device architectures, including nanosheet FETs, offer higher device density and performance than planar devices. In contrast to conventional FETs, in nanosheet FETs, the gate stack wraps around the entire periphery of each nanosheet, enabling more complete depletion of the channel region and reducing short-channel effects. The wrap-around gate structure used in nanosheet devices can also enable better management of leakage current in the active region, even at increased drive currents. However, the lateral asymmetric channel (LAC) doping profile used in planar FETs to improve electrical performance can be difficult to achieve in stacked nanosheet FETs. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a semiconductor structure includes an inner spacer located between channel nanosheets on a semiconductor substrate, wherein a first portion of the inner spacer is located on a first side of the semiconductor structure and a second portion of the inner spacer is located on a second side opposite the first side, and the first portion of the inner spacer on the first side includes a protruding region extending outward from a central top surface of the first portion of the inner spacer; and a metal gate stack in direct contact with the inner spacer, wherein the first portion of the inner spacer includes the protruding region that pinches off the metal gate stack to increase the threshold voltage of the first side.

[0004] According to another embodiment of the present disclosure, a semiconductor structure includes a plurality of channel nanosheets above an isolation region on a semiconductor substrate, and an internal spacer positioned between each of the plurality of channel nanosheets, wherein a first portion of the internal spacer is positioned on a first side of the semiconductor structure and a second portion of the internal spacer is positioned on a second side opposite the first side, the first portion of the internal spacer on the first side including a protruding region extending outward from a central top surface of the first portion of the internal spacer. The semiconductor structure further includes a metal gate stack separated by the first portion of the internal spacer from a source region located along a sidewall of the plurality of channel nanosheets on the first side, the metal gate stack separated by the second portion of the internal spacer from a drain region located along an opposite sidewall of the plurality of channel nanosheets on the second side, the protruding region of the first portion of the internal spacer pinching off the metal gate stack to increase the threshold voltage of the first side.

[0005] According to yet another embodiment of the present disclosure, a method of forming a semiconductor structure includes forming a nanosheet stack on a semiconductor substrate, wherein a dummy gate is located above the nanosheet stack adjacent to an offset spacer, the nanosheet stack including an alternating sequence of sacrificial nanosheets and channel nanosheets, the sacrificial nanosheet including a second nanosheet located between a first nanosheet and a third nanosheet, the first nanosheet and the third nanosheet having a first germanium concentration lower than a second germanium concentration of the second nanosheet, and selectively etching the sacrificial nanosheet, wherein the lower first germanium concentration causes the first nanosheet and the third nanosheet to etch more slowly than the second nanosheet, forming indentation regions on both sides of the nanosheet stack, the indentation regions having a shape that tapers toward the remaining second nanosheet of the sacrificial nanosheets.

[0006] The following detailed description, given by way of example and not limitation, will be best understood in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor structure showing nanosheet stacks formed on a semiconductor substrate according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view of a semiconductor structure after recessing a sacrificial nanosheet according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a cross-sectional view of a semiconductor structure after forming a first inner spacer according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a cross-sectional view of a semiconductor structure after removing remaining portions of a sacrificial nanosheet according to an embodiment of the present disclosure. [Figure 5]FIG. 2 is a cross-sectional view of a semiconductor structure after forming a protective organic planarization layer and removing a portion of a first inner spacer according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a cross-sectional view of a semiconductor structure after removing the protective organic planarization layer and forming a second inner spacer according to an embodiment of the present disclosure. [Figure 7] 2 is a cross-sectional view of a semiconductor structure after forming source and drain regions according to an embodiment of the present disclosure. [Figure 8] FIG. 1B is a cross-sectional view of a semiconductor structure after removing a dummy gate and a sacrificial nanosheet according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a cross-sectional view of a semiconductor structure after removing a remaining portion of a first inner spacer according to an embodiment of the present disclosure. [Figure 10A] FIG. 2 is a cross-sectional view of a semiconductor structure after depositing a gate stack and a metal fill according to an embodiment of the present disclosure. [Figure 10B] FIG. 2 is a cross-sectional view of a semiconductor structure after depositing a gate stack and metal fill according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] The drawings are not necessarily to scale. The drawings are merely schematic and are not intended to depict specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. Like numbers refer to like elements throughout the drawings.

[0009] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. The description may omit details of well-known features and techniques so as not to unnecessarily obscure the present embodiments.

[0010] For purposes of the following description, terms such as "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods as oriented in the drawings. Terms such as "above," "on," "up," "on top," "positioned on," or "positioned on top" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that there may be an intervening element, such as an interface structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0011] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be grouped together for purposes of presentation and illustration, and in some cases may not be described in detail. Also, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on distinctive features or elements of various embodiments of the present invention.

[0012] Although the disclosed embodiments include detailed descriptions of exemplary nanosheet FET architectures having silicon nanosheets and silicon germanium nanosheets, it should be understood that practice of the teachings described herein is not limited to the particular FET architectures described herein. Rather, embodiments of the invention may be practiced with any other type of FET device now known or later developed.

[0013] As integrated circuit fabrication continues to strive to produce smaller, denser integrated circuits, nanosheet FETs present a viable alternative for 5nm node technologies and beyond. As previously mentioned, in particular, the gate stack in nanosheet FETs wraps around the entire periphery of each nanosheet, allowing for more complete depletion of the channel region and reducing short-channel effects. This allows for increased device density and performance compared to planar devices.

[0014] Nanosheet FETs often contain thin, alternating layers (nanosheets) of different semiconductor materials arranged in a stack. The nanosheets are typically patterned into a nanosheet fin. Once the nanosheet fin is patterned, a gate stack is formed over the channel region of the nanosheet fin, and source / drain regions are formed adjacent to the gate stack. In some devices, once the gate stack or source / drain regions are formed, an etching process is performed to selectively remove one nanosheet layer of dissimilar material from the fin. The etching process creates undercuts and suspensions in the layers of the nanosheet fin, forming nanosheets or nanowires that can be used to form gate-all-around devices.

[0015] In conventional MOSFET fabrication, a lateral asymmetric channel (LAC) doping profile technique is implemented to improve the device's electrical characteristics. In an LAC MOSFET, the doping concentration on the source side of the channel region is higher than that on the drain side. Therefore, due to the nonuniform channel doping, the channel potential transition on the source side of the channel region is much steeper than that on the drain side during device operation. This steep potential distribution near the source side of the channel region enhances the lateral channel electric field and therefore carrier mobility. However, implementing a nonuniform channel doping profile in prior art short-channel devices (e.g., nanosheets) can be very challenging due to the small device area. Therefore, alternative designs and techniques are needed to introduce a halo region in a portion of the channel in a self-aligned manner in stacked nanosheet FETs.

[0016] Accordingly, embodiments of the present disclosure provide stacked nanosheet complementary metal oxide semiconductor (CMOS) structures that achieve an asymmetric threshold voltage distribution across the channel region by pinching off the work function metal near the source side of the channel region. The resulting asymmetric work function metal distribution improves device performance by increasing the threshold voltage on the source side of the channel region without the need for metal gate patterning. One method for pinching off the work function metal to achieve an asymmetric threshold voltage distribution across the channel is to form an asymmetric internal spacer. Below, with reference to the accompanying drawings of Figures 1-10B, embodiments in which asymmetric internal spacers can be formed to achieve a stacked nanosheet structure with an asymmetric threshold voltage distribution are described in detail.

[0017] Referring to FIG. 1 , a cross-sectional view of a semiconductor structure 100 including a nanosheet stack 108 according to an embodiment of the present disclosure is shown. The nanosheet stack 108 is formed from an alternating arrangement of silicon germanium (SiGe) sacrificial nanosheets 110, 112, 114 (hereinafter “sacrificial nanosheets”) and silicon (Si) channel nanosheets 120 (hereinafter “channel nanosheets”). The nanosheet stack 108 is formed in an oxide isolation layer 106 formed on a semiconductor substrate 102 (e.g., silicon). For ease of illustration and without any intention of limitation, an arrangement of 15 alternating sacrificial nanosheets 110, 112, 114 and channel nanosheets 120 is shown in FIG. 1 . However, any number of sacrificial nanosheets 110, 112, 114 and channel nanosheets 120 can be formed in the semiconductor structure 100 to meet design requirements.

[0018] In one or more embodiments, the alternating arrangement of sacrificial nanosheets 110, 112, 114 and channel nanosheets 120 is formed by epitaxially growing one layer followed by the next until the desired number and thickness of nanosheets is achieved. The epitaxial material can be grown from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Depending on the type of transistor, epitaxial silicon, silicon-germanium, or carbon-doped silicon (Si:C)-silicon, or a combination thereof, can be doped (in-situ doped) during deposition by adding dopants, i.e., n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium).

[0019] The terms "epitaxial growth and / or epitaxial deposition" and "epitaxially formed and / or epitaxially grown" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), such that the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material (seed material) on the deposition surface. In an epitaxial deposition process, chemical reactants supplied by source gases can be controlled and system parameters are set so that the deposited atoms arrive at the deposition surface with sufficient energy to move around the deposition surface of the semiconductor substrate so that they align with the crystalline arrangement and orientation of the atoms on the deposition surface. Thus, epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which it was formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystal surface will have a {100} orientation. In some embodiments, the epitaxial growth process and / or epitaxial deposition process is selective to formation on semiconductor surfaces and generally does not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0020] In some embodiments, the gas source for depositing the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Meanwhile, an epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0021] According to one embodiment, (first or lower) sacrificial nanosheet 110 and (third or upper) sacrificial nanosheet 114 comprise silicon-germanium (SiGe) having a first germanium (Ge) concentration of approximately 25% Ge, and (second or middle) sacrificial nanosheet 112, located between sacrificial nanosheet 110 and sacrificial nanosheet 114, is formed with a second germanium concentration of approximately 35% Ge. As described in more detail below, the different Ge concentrations can result in different etching rates between sacrificial nanosheets 110, 114 and sacrificial nanosheet 112.

[0022] According to one embodiment, known processing techniques are applied to the alternating arrangement of sacrificial nanosheets 110, 112, 114 and channel nanosheets 120 that form the nanosheet stack 108. For example, known processing techniques can include forming a fin hard mask (not shown) on the nanosheet stack 108. The fin hard mask can be formed by first depositing a hard mask material (e.g., silicon nitride) on the nanosheet stack 108, for example, using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable technique for dielectric deposition. The deposited hard mask material is then patterned into a plurality of individual fin hard masks. The patterning of the hard mask corresponds to the desired footprint and location of the channel nanosheets 120 used to form the channel region of the semiconductor device. According to an exemplary embodiment, reactive ion etching (RIE) is used to etch the alternating array of sacrificial nanosheets 110, 112, 114 and channel nanosheets 120 to form nanosheet stacks 108 as shown in FIG.

[0023] Continuing to refer to FIG. 1 , a dummy gate 130 and a hard mask (HM) 140 are formed on and around the nanosheet stack 108. Specifically, as known to those skilled in the art, the dummy gate 130 is formed on the top and sidewalls (not shown) of the nanosheet stack 108. In one or more embodiments, the dummy gate 130 is formed from amorphous silicon (a-Si), and the hard mask 140 is formed from silicon nitride (SiN), silicon oxide, an oxide / nitride stack, or similar materials and configurations. The hard mask 140 is typically formed on the dummy gate 130 to act as an etch stop.

[0024] As shown, offset spacers 150 are formed along the sidewalls of the dummy gate 130 and the hard mask 140. The offset spacers 150 can be formed using a spacer pull down formation process. The offset spacers 150 can also be formed using a sidewall image transfer (SIT) spacer formation process, which includes deposition of a spacer material followed by directional RIE of the deposited spacer material. The width dimension of the offset spacers 150 is selected such that the offset spacers 150 and the hard mask 140 define an initial width (w).

[0025] As known to those skilled in the art, the offset spacers 150 are used as a mask to recess the portions of the sacrificial nanosheets 110, 112, 114 and channel nanosheet 120 that are not beneath the offset spacers 150 and dummy gate 130, as shown. For example, an RIE process can be used to recess the portions of the sacrificial nanosheets 110, 112, 114 and channel nanosheet 120 that are not beneath the offset spacers 150 and dummy gate 130. Although not shown, the sacrificial nanosheets 110, 112, 114 and channel nanosheet 120 are typically recessed into the oxide isolation layer 106, forming grooves (not shown). Because the fin etch is performed before the dummy gate replacement step (described in more detail below), the semiconductor device fabrication process described herein can be referred to as a fin-first process.

[0026] 2, there is shown a cross-sectional view of the semiconductor structure 100 after recessing the sacrificial nanosheets 110, 112, 114, according to an embodiment of the present disclosure. In this embodiment, an isotropic etching process, such as, for example, a hydrogen chloride (HCl) gas isotropic etch, can be performed on the semiconductor structure 100 to recess the sacrificial nanosheets 110, 112, 114. The isotropic etching process selected is preferably capable of etching silicon germanium without attacking silicon.

[0027] As previously mentioned, the germanium concentration of the sacrificial nanosheets 110, 114 is lower than the germanium concentration of the sacrificial nanosheet 112. Therefore, during the etching process, the sacrificial nanosheet 112 formed with a higher germanium concentration is etched faster than the sacrificial nanosheets 110, 114 formed with a lower germanium concentration. This results in deeper recessed or depressed regions 202 in the sacrificial nanosheet 112, as shown. In other words, because the germanium concentration of the sacrificial nanosheets 110, 114 is lower, these layers are etched more slowly than the sacrificial nanosheet 112, forming depressed regions 202. Note that regions 204 containing remnants of silicon-germanium from the sacrificial nanosheets 110, 114 may still be present in the semiconductor structure 100 after the etching process. Due to the difference in etching rates between sacrificial nanosheets 110, 114 and sacrificial nanosheet 112, recessed region 202 necessarily has a shape that tapers towards sacrificial nanosheet 112 as shown.

[0028] 3, a cross-sectional view of the semiconductor structure 100 is shown after forming a first inner spacer 320 according to an embodiment of the present disclosure. In this embodiment, the first inner spacer 320 may be formed, for example, by conformal deposition of an inner spacer material that pinches off the recessed region 202 (FIG. 2). The inner spacer material forming the first inner spacer 320 may include, for example, silicon dioxide (SiO2).

[0029] An isotropic etch, such as a wet etch, is then performed to recess the first interior spacer 320, as shown. Recessing the first interior spacer 320 exposes the remaining portions of the sacrificial nanosheets 110, 114 (e.g., region 204 in FIG. 2 ) located beneath the offset spacer 150 and above the channel nanosheet 120. Note that excess interior spacer material from other regions of the semiconductor structure 100 may be removed during the isotropic etching process.

[0030] Referring now to FIG. 4, a cross-sectional view of the semiconductor structure 100 is shown after removing the remaining portions of the sacrificial nanosheets 110, 114 below the offset spacer 150 and above the channel nanosheet 120 exposed after recessing the first internal spacer 320, according to an embodiment of the present disclosure.

[0031] As shown, the exposed remaining portions of the sacrificial nanosheets 110, 114 located under the offset spacers 150 and above the channel nanosheet 120 are selectively removed from the semiconductor structure 100 (i.e., from the exposed portions of region 204 in FIG. 2 ) to prevent SiGe release damage to subsequently formed source / drain epi regions. In an exemplary embodiment, an isotropic etching process, such as, for example, a hydrogen chloride (HCl) gas isotropic etch, can be performed to remove the exposed remaining portions of the sacrificial nanosheets 110, 114 located under the offset spacers 150 and above the channel nanosheet 120. As shown, portions of the sacrificial nanosheets 110, 114 may remain in contact with the dummy gate 130, an interior region of the channel nanosheet 120, and the oxide isolation layer 106.

[0032] Referring now to FIG. 5, a cross-sectional view of the semiconductor structure 100 is shown after forming a protective organic planarization layer (OPL) 520 and removing a portion of the first inner spacer 320 from a first side of the semiconductor structure 100 opposite the protective OPL 520, in accordance with an embodiment of the present disclosure.

[0033] The protective OPL 520 is formed by depositing an organic planarizing material that can effectively prevent damage to underlying layers during a subsequent etching process. According to one embodiment, the protective OPL 520 protects a second side of the semiconductor structure 100, opposite the first side, during an etching process used to remove the first inner spacer 320 from the first side of the semiconductor structure 100, as shown. As described below, source and drain regions are formed on the first side of the semiconductor structure 100, and a drain region is formed on the opposite second side of the semiconductor structure 100.

[0034] The protective OPL 520 can include, but is not necessarily limited to, an organic polymer containing C, H, and N. According to certain embodiments, the OPL material can be free of silicon (Si). According to other embodiments, the OPL material can be free of Si and fluorine (F). As described herein, a material is free of atoms when its atomic content is below trace levels detectable by analytical methods available in the art. Non-limiting examples of OPL materials that form the protective OPL 520 include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials. The protective OPL 520 can be deposited, for example, by spin coating, followed by a planarization process such as chemical mechanical polishing (CMP).

[0035] After forming the protective OPL 520, a portion of the first inner spacer 320 is selectively removed using a wet etching process, such as diluted HF. Removing the portion of the first inner spacer 320 from the first side of the semiconductor structure 100 forms a first recess 510. After removing the portion of the first inner spacer 320 from the first side of the semiconductor structure 100, the protective OPL 520 is removed, as shown in FIG.

[0036] 6, there is shown a cross-sectional view of semiconductor structure 100 after removing protective OPL 520 and forming second inner spacers 640 in accordance with an embodiment of the present disclosure. In an embodiment, protective OPL 520 may be removed using, for example, OPL RIE including trace point detection.

[0037] Similar to the first inner spacer 320, the second inner spacer 640 can be formed by conformal deposition of an inner spacer material. According to one embodiment, the inner spacer material forming the second inner spacer 640 can include, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOxNy, and combinations thereof. An etching process, including RIE, wet etching, or isotropic vapor-phase dry etching, can be performed to remove excess inner spacer material from the semiconductor structure 100.

[0038] It should be noted that second interior spacer 640 constitutes the primary interior spacer of semiconductor structure 100. In one or more embodiments, the spacer material forming first interior spacer 320 is selected based on providing etch selectivity relative to the spacer material forming second interior spacer 640. As shown, second interior spacer 640 on the first side of semiconductor structure 100 substantially fills first recess 510 ( FIG. 5 ), which corresponds to recessed region 202 shown in FIG. 2 .

[0039] As shown, the second inner spacer 640 includes a protruding region 612 that extends outward from the central top surface of the inner spacer 640 toward the remaining sacrificial nanosheet 112. The protruding region 612 provides a T-shaped inner spacer formed such that the space between the protruding region 612 and the channel nanosheet 120 is less than twice the thickness of a subsequently formed nitride layer (e.g., the inner nitride layer 1010 shown in FIG. 10A ). The resulting asymmetric shape of the second inner spacer 640 can pinch off a subsequently formed nitride layer on the first or source side of the semiconductor structure 100, as described in more detail below.

[0040] In exemplary embodiments, the thickness of the second internal spacer 640 can vary from about 5 nm to about 10 nm, and can be less than 5 nm and greater than 10 nm thick. The thickness of the protruding region 612 of the second internal spacer 640 can vary from about 2 nm to about 5 nm, and can be less than 2 nm and greater than 5 nm thick.

[0041] Referring now to FIG. 7, a cross-sectional view of the semiconductor structure 100 is shown after forming a source region 720 and a drain region 722 in accordance with an embodiment of the present disclosure.

[0042] During this step of the fabrication process, source and drain regions 720 and 722 are formed at the exposed ends of the channel nanosheet 120 using an epitaxial layer growth process. In-situ or ex-situ doping can be applied to dope the source and drain regions 720 and 722, thereby forming the necessary junctions for the semiconductor device. Nearly all semiconductor transistors are based on the formation of junctions. A junction can block or pass current depending on the applied bias. A junction is typically formed by contacting two semiconductor regions of opposite polarity. The most common junction is the pn junction, which consists of a hole-rich p-type piece of silicon contacting an electron-rich n-type piece of silicon. N-type and p-type FETs are formed by implanting different types of dopants into selected regions of the device to form the necessary junctions. N-type devices can be formed by implanting arsenic (As) or phosphorus (P), and p-type devices can be formed by implanting boron (B).

[0043] It should be understood that the first side of semiconductor structure 100 corresponds to the side where source region 720 is located (i.e., the source side). Similarly, the second side of semiconductor structure 100 (opposite the first side) corresponds to the side where drain region 722 is located (i.e., the drain side).

[0044] After forming the source region 720 and drain region 722, an interlevel dielectric (ILD) layer 730 is formed to fill the gap between the gate structure and other existing devices in the semiconductor structure 100. The ILD layer 730 can be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the ILD layer 730 include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics. After depositing the ILD layer 730, the semiconductor structure 100 is subjected to a CMP process to expose the top surface of the dummy gate 130, as shown.

[0045] Referring now to FIG. 8, a cross-sectional view of the semiconductor structure 100 is shown after removing the dummy gate 130 and the sacrificial nanosheets 110, 114, according to an embodiment of the present disclosure.

[0046] The dummy gate 130 and (SiGe) sacrificial nanosheets 110, 114 can be removed by known etching processes, including, for example, RIE or chemical oxide removal (COR). In a gate-last fabrication process, the removed dummy gate 130 is then replaced with a metal gate (not shown), as known in the art. Note that the dummy gate 130 and sacrificial nanosheets 110, 114 are removed selectively relative to the first interior spacer 320 remaining on the second side of the semiconductor structure 100.

[0047] 9, a cross-sectional view of the semiconductor structure 100 is shown after removing the remaining portion of the first inner spacer 320, according to an embodiment of the present disclosure. In this embodiment, a known etching process, such as, for example, RIE or wet etching, may be used to remove the remaining portion of the first inner spacer 320 from the second or drain side of the semiconductor structure 100. After removing the dummy gate 130 (FIG. 7), the sacrificial nanosheets 110, 114 (FIG. 7), and the first inner spacer 320 (FIG. 8), a second recess 910 is formed in the semiconductor structure 100.

[0048] After removing the remaining portion of the first inner spacer 320 ( FIG. 8 ) from the drain side of the semiconductor structure 100, the asymmetric configuration of the second inner spacer 640 can be visually recognized in the semiconductor structure 100. As shown, the second inner spacer 640 on the first (source) side of the semiconductor structure 100 includes a protruding region 612 that extends toward the second recess 910, while the second inner spacer 640 on the second (drain) side of the semiconductor structure 100 does not have a protruding region 612. As previously mentioned, the protruding region 612 on the source side of the semiconductor structure 100 provides a T-shaped inner spacer configuration that can pinch off a subsequently formed nitride layer, as described in detail below.

[0049] 10A and 10B, cross-sectional views of the semiconductor structure 100 are shown after depositing a gate stack and metal fill according to an embodiment of the present disclosure. As known to those skilled in the art, in a replacement metal gate or gate-last fabrication process, the dummy gate 130 (FIG. 7) is replaced with an n-type or p-type metal gate stack.

[0050] According to one embodiment, Figure 10A shows the semiconductor structure 100 after deposition of a gate dielectric and work function metal suitable for an n-type field effect transistor (NFET) device. For ease of illustration, the gate dielectric is not shown. In this embodiment, a three-layer gate metal stack formed by a doped transition metal layer 1020 located between an inner nitride layer 1010 and an outer nitride layer 1030 is continuously and conformally deposited within the second recess 910 (Figure 9).

[0051] The inner nitride layer 1010 can be conformally formed within the second recess 910 (FIG. 9) using any suitable deposition process. In some embodiments, the inner nitride layer 1010 is conformally deposited using ALD. In some embodiments, the inner nitride layer 1010 comprises titanium nitride (TiN). The thickness of the inner nitride layer 1010 can vary from about 1 nm to about 2 nm.

[0052] A doped transition metal layer 1020 is formed on the inner nitride layer 1010. In some embodiments, the doped transition metal layer 1020 is deposited using ALD. In some embodiments, the doped transition metal layer 1020 comprises an aluminum-doped transition metal carbide. In some embodiments, the doped transition metal layer 1020 is formed using a hybrid ALD / CVD process having alternating pulses of a transition metal-containing precursor and an aluminum carbide-containing precursor. In this embodiment, the doped transition metal layer 1020 is formed from, for example, aluminum-doped titanium carbide (TiAlC). The thickness of the doped transition metal layer 1020 can vary from about 3 nm to about 5 nm.

[0053] As known to those skilled in the art, the presence of aluminum (Al)-containing metals can lower the threshold voltage of a device. By forming the T-shaped second inner spacer 640, the inner nitride layer 1010 is pinched off on the source side of the semiconductor structure 100, thereby preventing deposition of Al-containing metals from the doped transition metal layer 1020. The inner spacer-gate metal stack configuration shown in FIG. 10A therefore provides a lateral asymmetric channel (LAC) structure with an asymmetric work function metal distribution that increases the threshold voltage of the first, or source, side of the semiconductor structure 100. This can improve the short-channel performance of the device without additional metal patterning.

[0054] The outer nitride layer 1030 can be conformally formed on the doped transition metal layer 1020 in a manner similar to that of the inner nitride layer 1010. In some embodiments, the outer nitride layer 1030 is conformally deposited using ALD. In some embodiments, the outer nitride layer 206 comprises titanium nitride (TiN). The thickness of the outer nitride layer 1010 can vary from about 1 nm to about 2 nm.

[0055] In some embodiments, a gate dielectric (not shown) is formed between the channel nanosheet 120 and the inner nitride layer 1010. The gate dielectric can be formed, for example, from silicon oxide, silicon nitride, silicon oxynitride, boron nitride, a high-k material, or any combination of these materials. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material can further include dopants such as lanthanum and aluminum. In some embodiments, the gate dielectric can have a thickness ranging from about 1 nm to about 3 nm.

[0056] According to another embodiment, FIG. 10B illustrates the semiconductor structure 100 after deposition of a work function metal suitable for a p-type field effect transistor (PFET) device. In this embodiment, a nitride layer 1012 is conformally deposited within the second recess 910 (FIG. 9). The nitride layer 1012 can be conformally formed within the recess 910 (FIG. 9) using any suitable deposition process. In some embodiments, the nitride layer 1012 is conformally deposited using ALD. In some embodiments, the nitride layer 1012 comprises titanium nitride (TiN). The thickness of the nitride layer 1012 can vary from about 3 nm to about 5 nm. As described above with reference to FIG. 10A, a gate dielectric (not shown) can be formed between the channel nanosheet 120 and the nitride layer 1012.

[0057] In embodiments in which the semiconductor structure 100 is a PFET device, no aluminum (Al)-containing metal is included in the gate metal stack. Thus, in these embodiments, the asymmetric threshold voltage profile is caused by a difference in effective metal thickness between the source and drain sides of the semiconductor structure 100. In other words, the effective thickness of the (metal) nitride layer 1012 on the source side of the semiconductor structure 100 is less than the effective thickness of the nitride layer 1012 on the drain side of the semiconductor structure 100. This less effective metal thickness on the source side of the semiconductor structure 100 is caused by the protruding region 612 of the second inner spacer 640.

[0058] Thus, a lateral asymmetric channel (LAC) structure with asymmetric work function metal distribution and a high threshold voltage on the (first) source side can be realized in embodiments in which the semiconductor structure 100 is a PFET device. Similar to the NFET device described above in Figure 10A, the short channel performance of the device can be improved without additional metal patterning.

[0059] Continuing to refer together to Figures 10A and 10B, after depositing a corresponding (p-type or n-type) work function metal in the second recess 910 (Figure 9), as known to those skilled in the art, a conductive gate layer 1040 is deposited above the top nitride layer in the semiconductor structure 100, as shown. The conductive gate layer 1040 may be a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au)), a conductive metal compound material (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (RuO), cobalt silicide (CoSi), nickel silicide (NiSi)), a transition metal aluminide (e.g., TiAl, ZrAl), TaC, TaMgC, or any suitable combination of these materials. In various embodiments, the conductive gate layer 1040 can further include dopants that are incorporated during or after deposition. Any known deposition process can be used to form the conductive gate layer 1040. A planarization process, such as CMP, is typically performed on the semiconductor structure 100 after the conductive gate layer 1040 is deposited.

[0060] Finally, the proposed embodiments enable the formation of semiconductor structures with asymmetric threshold voltage profiles between the source and drain regions, which can improve device performance and enable further scaling of nanosheet technology.

[0061] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor structure comprising: an internal spacer located between channel nanosheets on a semiconductor substrate, wherein a first portion of the internal spacer is located on a first side of the semiconductor structure and a second portion of the internal spacer is located on a second side opposite the first side, and the first portion of the internal spacer on the first side includes a protruding region extending outward from a central top surface of the first portion of the internal spacer; a metal gate stack in direct contact with the inner spacer, the first portion of the inner spacer including the protruding region that pinches off the metal gate stack to increase a threshold voltage of the first side; Equipped with the protruding region provides a T-shaped inner spacer, and the space between the protruding region and the channel nanosheet is less than two times the thickness of the inner nitride layer of the metal gate stack. Semiconductor structures.

2. a source region located along a sidewall of the channel nanosheet on the first side, separated from the metal gate stack by the first portion of the inner spacer; a drain region located along an opposite sidewall of the channel nanosheet on the second side, separated from the metal gate stack by the second portion of the inner spacer on the second side; 10. The semiconductor structure of claim 1 further comprising:

3. 10. The semiconductor structure of claim 1 further comprising a metal gate adjacent to an offset spacer and above said metal gate stack.

4. 10. The semiconductor structure of claim 1, wherein said semiconductor structure comprises an NFET device, and said metal gate stack comprises a trilayer gate metal stack formed by a doped transition metal layer situated between said inner and outer nitride layers, said doped transition metal layer comprising an aluminum doped transition metal carbide.

5. 5. The semiconductor structure of claim 4, wherein said protruding region pinches off said inner nitride layer to prevent deposition of said doped transition metal layer on said first side to increase said threshold voltage.

6. 10. The semiconductor structure of claim 1 wherein said semiconductor structure comprises a PFET device and said metal gate stack comprises said inner nitride layer.

7. 7. The semiconductor structure of claim 6, wherein said protruding region pinches off said inner nitride layer to reduce an effective metal thickness of said inner nitride layer on said first side to increase a threshold voltage.

8. 10. The semiconductor structure of claim 1 wherein said channel nanosheet comprises silicon and said interior spacer comprises at least one of SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, and SiOxNy.

9. 1. A semiconductor structure comprising: a plurality of channel nanosheets above a separation region on a semiconductor substrate; an internal spacer between each of the plurality of channel nanosheets, wherein a first portion of the internal spacer is located on a first side of the semiconductor structure and a second portion of the internal spacer is located on a second side opposite the first side, and the first portion of the internal spacer on the first side includes a protruding region extending outward from a central top surface of the first portion of the internal spacer; a metal gate stack separated by the first portion of the internal spacer from a source region located along a sidewall of the plurality of channel nanosheets on the first side, the metal gate stack being separated by the second portion of the internal spacer from a drain region located along an opposite sidewall of the plurality of channel nanosheets on the second side, the protruding region of the first portion of the internal spacer pinching off the metal gate stack to increase a threshold voltage of the first side; Equipped with the protruding region provides a T-shaped inner spacer, and the space between the protruding region and the channel nanosheet is less than two times the thickness of the inner nitride layer of the metal gate stack. Semiconductor structures.

10. 10. The semiconductor structure of claim 9 further comprising a metal gate adjacent to an offset spacer and above said metal gate stack.

11. 10. The semiconductor structure of claim 9, wherein said semiconductor structure comprises an NFET device, and said metal gate stack comprises a trilayer gate metal stack formed by a doped transition metal layer situated between said inner and outer nitride layers, said doped transition metal layer comprising an aluminum doped transition metal carbide.

12. 12. The semiconductor structure of claim 11, wherein said protruding region pinches off said inner nitride layer to prevent deposition of said doped transition metal layer on said first side to increase said threshold voltage.

13. 10. The semiconductor structure of claim 9 wherein said semiconductor structure comprises a PFET device and said metal gate stack comprises said inner nitride layer.

14. 14. The semiconductor structure of claim 13, wherein said protruding region pinches off said inner nitride layer to reduce an effective metal thickness of said inner nitride layer on said first side to increase said threshold voltage.

15. 10. The semiconductor structure of claim 9 wherein said plurality of channel nanosheets comprise silicon and said interior spacer comprises at least one of SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, and SiOxNy.

16. 1. A method of forming a semiconductor structure, comprising: forming a nanosheet stack on a semiconductor substrate, wherein a dummy gate is located above the nanosheet stack adjacent to an offset spacer, the nanosheet stack including an alternating arrangement of sacrificial nanosheets and channel nanosheets, the sacrificial nanosheet including a second nanosheet located between a first nanosheet and a third nanosheet, the first nanosheet and the third nanosheet having a first germanium concentration lower than a second germanium concentration of the second nanosheet; selectively etching the sacrificial nanosheets, wherein the lower germanium concentration in the first nanosheet causes the first nanosheet and the third nanosheet to etch more slowly than the second nanosheet, forming recessed regions on either side of the nanosheet stack, the recessed regions having a shape that tapers toward the remaining second nanosheet of the sacrificial nanosheets; Including, forming first internal spacers on either side of the sacrificial nanosheet, the first internal spacers substantially filling the recessed regions; selectively removing a first portion of the first inner spacer located on a first side of the semiconductor structure to form a first recess, wherein a second portion of the first inner spacer remains on a second side of the semiconductor structure opposite the first side; forming second internal spacers on both sides of the sacrificial nanosheet and in direct contact with the channel nanosheet, wherein a first portion of the second internal spacer substantially fills the first recess on the first side, and the first portion of the second internal spacer on the first side has a protruding region extending from a central top surface of the first portion of the second internal spacer toward a remaining second layer of the sacrificial nanosheet; further comprising: method.

17. 17. The method of claim 16, further comprising forming a source region on the first side along a sidewall of the channel nanosheet and the second internal spacer, and forming a drain region on the second side along an opposite sidewall of the channel nanosheet and the second internal spacer.

18. removing the dummy gate and the sacrificial nanosheet; removing a remaining portion of the first inner spacer from the second side, the removing forming a second recess by removing the dummy gate, the sacrificial nanosheet, and the remaining portion of the first inner spacer; conformally depositing a gate dielectric and a work function metal into the second recess, wherein the protruding region of the second inner spacer pinches off a portion of the work function metal located on the first side to form an asymmetric work function metal distribution that increases a threshold voltage on the first side; 20. The method of claim 17, further comprising:

19. forming a protective organic planarization layer on the second side; removing the first inner spacer from the first side; removing the protective organic planarization layer from the second side; 20. The method of claim 18, further comprising:

20. 17. The method of claim 16, wherein the channel nanosheet comprises silicon, the first nanosheet, the second nanosheet, and the third nanosheet comprise silicon germanium, the first germanium concentration in the first nanosheet and the third nanosheet comprises 25% germanium, and the second germanium concentration in the second nanosheet comprises 35% germanium.

21. 17. The method of claim 16, wherein the second inner spacer comprises at least one of SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, and SiOxNy.

22. 20. The method of claim 18, wherein the protruding region provides a T-shaped internal spacer, and the space between the protruding region and the channel nanosheet is less than twice the thickness of the work function metal nitride layer.

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