Segmented focus ring for plasma semiconductor processing and processing tool configured to use a segmented focus ring

Abstract

The present disclosure relates to plasma semiconductor processes and processing tools for such processes. In one embodiment, the processing tool includes a chamber, a substrate support, and a focus ring (FR) translation assembly. The substrate support is disposed within the chamber and has a support surface. The FR translation assembly is disposed within the chamber and includes a frame and a segment support mechanically coupled to the frame. Each segment support is configured to support a respective individual segment of the focus ring. The FR translation assembly is configured to support the individual segments disposed laterally surrounding the support surface. The FR translation assembly is further configured to (i) translate the segment supports in a plane of the support surface and in a direction parallel to a radial direction from a center, and / or (ii) tilt the segment supports about respective axes parallel to the support surface.

Description

[Background technology]

[0001] Plasma processing is widespread in the semiconductor industry. Plasma semiconductor processes have been used for material etching, material deposition, and more. Such plasma processes have been found to improve the quality of the processing or resulting properties on semiconductor substrates. For example, plasma-enhanced chemical vapor deposition (PECVD) has been found to offer advantages over conventional chemical vapor deposition (CVD), such as lower deposition temperatures, increased material purity, and improved step coverage. However, the introduction of plasma has brought various challenges. Summary of the Invention [Means for solving the problem]

[0002] One embodiment of the present disclosure provides a processing tool for semiconductor processing. The processing tool includes a chamber, a substrate support, and a focus ring translation assembly. The chamber has an internal volume therein. The substrate support is disposed within the chamber. The substrate support has a support surface configured to support a semiconductor substrate. The focus ring translation assembly is disposed within the chamber. The focus ring translation assembly includes a frame and a plurality of segment supports mechanically coupled to the frame. Each segment support of the plurality of segment supports is configured to support a respective individual segment of a focus ring. The focus ring includes a plurality of individual segments. The focus ring translation assembly is configured to support the plurality of individual segments arranged to laterally surround the support surface. The focus ring translation assembly is configured to translate the plurality of segment supports in respective first directions. Each of the respective first directions is within the plane of the support surface and parallel to a respective radial direction from a center of the support surface.

[0003] Another embodiment of the present disclosure provides a processing tool for semiconductor processing. The processing tool includes a chamber, a substrate support, and a focus ring movement assembly. The chamber has an internal volume therein. The substrate support is disposed within the chamber. The substrate support has a support surface configured to support a semiconductor substrate. The focus ring movement assembly is disposed within the chamber. The focus ring movement assembly includes a frame and a plurality of segment supports mechanically coupled to the frame. Each segment support of the plurality of segment supports is configured to support a respective individual segment of a focus ring. The focus ring includes a plurality of individual segments. The focus ring movement assembly is configured to support the plurality of individual segments arranged to laterally surround the support surface. The focus ring movement assembly is configured to tilt the plurality of segment supports about respective axes, each axis of the respective axes being parallel to the support surface.

[0004] Another embodiment of the present disclosure provides a method for semiconductor processing. The method includes moving multiple ring segments of a focus ring to respective positions relative to a semiconductor substrate. The semiconductor substrate is positioned on a support surface of a substrate support. The substrate support is positioned within a chamber of a processing tool. The multiple ring segments of the focus ring laterally surround the semiconductor substrate. Moving the multiple ring segments includes translating the multiple ring segments in respective first directions, each of which is in a plane of the support surface and parallel to a respective radial direction from a center of the support surface. The method includes generating a plasma in a processing volume of the chamber. The semiconductor substrate is exposed to the plasma while the multiple ring segments are at their respective positions relative to the semiconductor substrate.

[0005] Another embodiment of the present disclosure provides a method for semiconductor processing. The method includes moving multiple ring segments of a focus ring to respective positions relative to a semiconductor substrate. The semiconductor substrate is positioned on a support surface of a substrate support. The substrate support is positioned within a chamber of a processing tool. The multiple ring segments of the focus ring laterally surround the semiconductor substrate. Moving the multiple ring segments includes tilting the multiple ring segments about respective axes, each of which is parallel to the support surface. The method includes generating a plasma within a processing volume of the chamber. The semiconductor substrate is exposed to the plasma while the multiple ring segments are at their respective positions relative to the semiconductor substrate.

[0006] Another embodiment of the present disclosure provides a method for semiconductor processing. The method includes using a processing tool to perform a plasma semiconductor process having first process conditions on a first plurality of substrates. A plurality of individual segments of a focus ring laterally surround the substrates during the plasma semiconductor process. The first process conditions correspond to respective positions of the individual segments disposed at respective first radial distances from the substrates during the plasma semiconductor process on the first plurality of substrates. The method includes measuring a first characteristic of each of the first plurality of substrates proximate a center of each of the first plurality of substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates proximate an edge of each of the first plurality of substrates. The second characteristic is formed by the plasma semiconductor process. The method includes determining, by a processor-based system, second process conditions to be applied during the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to respective positions of the plurality of individual segments disposed at respective second radial distances from the substrates during the plasma semiconductor process on the second plurality of semiconductor substrates. The method includes performing a plasma semiconductor process having the second process conditions on the second plurality of substrates using the processing tool.

[0007] Another embodiment of the present disclosure provides a method for semiconductor processing. The method includes using a processing tool to perform a plasma semiconductor process having first process conditions on a first plurality of substrates. A plurality of individual segments of a focus ring laterally surround the substrates during the plasma semiconductor process. The first process conditions correspond to respective positions of the individual segments disposed at respective tilt angles with respect to upper surfaces of the substrates during the plasma semiconductor process on the first plurality of substrates. The method includes measuring a first characteristic of each of the first plurality of substrates proximate a center of each of the first plurality of substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates proximate an edge of each of the first plurality of substrates. The second characteristic is formed by the plasma semiconductor process. The method includes determining, by a processor-based system, second process conditions to be applied during the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to respective positions of the individual segments disposed at respective tilt angles with respect to upper surfaces of the substrates during the plasma semiconductor process on the second plurality of substrates. The method includes performing a plasma semiconductor process having second process conditions on a second plurality of substrates using the processing tool.

[0008] The foregoing summary has outlined, rather broadly, various features of embodiments of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of such embodiments are described below. The described embodiments may be readily utilized as a basis for modifying or designing other embodiments within the scope of the appended claims. [Brief explanation of the drawings]

[0009] For a more detailed understanding of the above-described features, reference is now made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] [Figure 1] 1 is a schematic diagram of a processing tool for semiconductor processing according to some embodiments of the present disclosure. [Figure 2A] 1A and 1B are layout and cross-sectional views of a segmented focus ring in accordance with some embodiments of the present disclosure. [Figure 2B] 1A and 1B are layout and cross-sectional views of a segmented focus ring in accordance with some embodiments of the present disclosure. [Figure 3A] 1A and 1B are layout and cross-sectional views of a segmented focus ring in accordance with some embodiments of the present disclosure. [Figure 3B] 1A and 1B are layout and cross-sectional views of a segmented focus ring in accordance with some embodiments of the present disclosure. [Figure 4] FIG. 1C is a layout diagram of a segmented focus ring illustrating lateral and radial translation of focus ring segments in accordance with some embodiments of the present disclosure. [Figure 5] FIG. 2 is a simplified cross-sectional view of a focus ring radial translation assembly in accordance with some embodiments of the present disclosure. [Figure 6] FIG. 1 is a perspective view of a focus ring radial translation assembly in accordance with some embodiments of the present disclosure. [Figure 7] 5 and 6 illustrate lateral and radial translation of focus ring segments by the focus ring radial translation assembly of FIGS. [Figure 8] 5 and 6 illustrate lateral and radial translation of focus ring segments by the focus ring radial translation assembly of FIGS. [Figure 9] 10 illustrates how a gap between a focus ring segment and the edge of a semiconductor substrate can contribute to plasma control, according to some embodiments of the present disclosure. [Figure 10] 10 illustrates how a gap between a focus ring segment and the edge of a semiconductor substrate can contribute to plasma control, according to some embodiments of the present disclosure. [Figure 11] 1A-1C are cross-sectional views of focus ring segments of a segmented focus ring illustrating tilt of the focus ring segments in accordance with some embodiments of the present disclosure. [Figure 12] FIG. 1 is a simplified cross-sectional view of a focus ring tilt assembly according to some embodiments of the present disclosure. [Figure 13A] FIG. 1 is a perspective view of a focus ring tilt assembly according to some embodiments of the present disclosure. [Figure 13B] FIG. 13B is a perspective view of a portion of the focus ring tilt assembly of FIG. 13A according to some embodiments of the present disclosure. [Figure 14] 13 illustrates tilting of focus ring segments by the focus ring tilt assembly of FIG. 12. [Figure 15] 13 illustrates tilting of focus ring segments by the focus ring tilt assembly of FIG. 12. [Figure 16] 10 illustrates how tilting focus ring segments can contribute to plasma control, in accordance with some embodiments of the present disclosure. [Figure 17] 10 illustrates how tilting focus ring segments can contribute to plasma control, in accordance with some embodiments of the present disclosure. [Figure 18] 1 illustrates a focus ring translation assembly including a focus ring radial translation subassembly and a focus ring tilt subassembly, according to some embodiments of the present disclosure. [Figure 19] 1A-1C are simplified cross-sectional views of respective focus ring movement assemblies including a focus ring vertical translation subassembly, according to some embodiments of the present disclosure. [Figure 20] 1A-1C are simplified cross-sectional views of respective focus ring movement assemblies including a focus ring vertical translation subassembly, according to some embodiments of the present disclosure. [Figure 21]1A-1C are simplified cross-sectional views of respective focus ring movement assemblies including a focus ring vertical translation subassembly, according to some embodiments of the present disclosure. [Figure 22] 10 illustrates how vertical translation of focus ring segments can contribute to plasma control, in accordance with some embodiments of the present disclosure. [Figure 23] 10 illustrates how vertical translation of focus ring segments can contribute to plasma control, in accordance with some embodiments of the present disclosure. [Figure 24] 2 is a schematic diagram of a radio frequency (RF) power system of the processing tool of FIG. 1 according to some embodiments of the present disclosure. [Figure 25] FIG. 2 is a schematic diagram of an RF power system that may be implemented with the processing tool of FIG. 1 in accordance with some embodiments of the present disclosure. [Figure 26] 1 is a processor-based system according to some embodiments of the present disclosure. [Figure 27] 1 is a flowchart of a semiconductor processing method according to some embodiments of the present disclosure. [Figure 28] 1 is a flowchart of a method for semiconductor processing according to some embodiments of the present disclosure.

[0011] The drawings and the accompanying detailed description are provided to provide an understanding of the features of various examples and are not intended to limit the scope of the appended claims. The embodiments illustrated in the drawings and described in the accompanying detailed description may be readily utilized as a basis for modifying or designing other embodiments within the scope of the appended claims. Wherever possible, the same reference numerals may be used to designate identical elements common to the drawings. The figures are drawn to clearly illustrate associated elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0012] Various features are described below with reference to the figures. An embodiment may not have all aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in other embodiments even if not so shown or explicitly described. Furthermore, while methods described herein may be described with a particular order of operations, other methods according to other embodiments may be implemented with more or fewer operations and in various other orders (e.g., including different sequential or parallel execution of various operations).

[0013] The present disclosure relates to plasma semiconductor processes, as well as components and processing tools for plasma semiconductor processes. Some embodiments of the present disclosure described herein include a segmented focus ring composed of multiple individual focus ring segments. Generally, the focus ring segments can be translated in respective lateral and radial directions and / or tilted at respective tilt angles. Additionally, in some embodiments of the present disclosure, the focus ring segments can be translated in respective vertical directions. The movement and / or positioning of the focus ring segments can contribute to plasma control at the edge of a semiconductor substrate. Various other examples described herein include processing tools including a focus ring movement assembly configured to move and / or position the focus ring segments. Further examples described herein include, for example, semiconductor processing methods using such segmented focus rings and processing tools. Further examples include methods for semiconductor processing that determine the position of focus ring segments to be performed in subsequent processing of a semiconductor substrate based on results of previous processing of the semiconductor substrate.

[0014] Additionally, in some embodiments of the present disclosure, the focus ring segments may include respective electrodes to which respective voltages, such as radio frequency (RF) signals, may be applied. In some embodiments of the present disclosure, the focus ring segments may include respective heating elements to which respective voltages may be applied. The processing tool may include components for applying such voltages to the focus ring segments. The plasma semiconductor process may include applying such voltages to the focus ring segments.

[0015] Plasma non-uniformity in semiconductor processes can result in defects in the integrated circuit (IC) dies being fabricated. Plasma non-uniformity has been observed between the center of a semiconductor substrate (e.g., a wafer) and portions near the edge of the semiconductor substrate. Because a significant number of IC dies are fabricated near the edge of the semiconductor substrate, plasma non-uniformity at the edge of the semiconductor substrate can result in significant yield loss.

[0016] Structural differences at the edge of a semiconductor substrate compared to the center of the semiconductor substrate can contribute to plasma non-uniformity between the center and edge of the semiconductor substrate. For example, the structure containing or defining the plasma at the edge of the semiconductor substrate may be different from that at the center of the semiconductor substrate. At the center, the plasma is contained or defined by the flat lateral surfaces of the semiconductor surface, while the edge, with its vertical sides, structurally differs from the flat lateral surfaces. To mitigate such structural differences, a focus ring surrounding the semiconductor substrate is sometimes used, but a gap may exist between the focus ring and the semiconductor substrate due to manufacturing tolerances. The plasma sheath of the plasma may bend around the edge and enter the gap, which can result in ion bombardment near the edge of the semiconductor substrate at a different angle than at the center of the semiconductor substrate.

[0017] Furthermore, the physical structure of the processing tool can at least partially determine the electromagnetic field used to generate the plasma. The structure between the electrodes where the plasma is generated can determine the electromagnetic field. At the center of the electrode, the electromagnetic field can be modeled as arising from an infinite plane, with no or little edge effects. Near the edge of the electrode, edge effects become more pronounced and can reduce and / or change the directionality of the electromagnetic field. As a result, the plasma density at the edge of the semiconductor substrate can be different compared to the center of the substrate. Furthermore, the edge of the electrode is closer to the wall of the processing tool's chamber, which can create low-resistance electromagnetic loops that can result in plasma density and ion energy differences between the center and the edge.

[0018] Some embodiments of the present disclosure can address and / or mitigate some of these challenges associated with plasma semiconductor processing. By adjusting the position of the focus ring segments, the plasma sheath can be tailored to cause a more uniform angle of ion bombardment at the edges relative to the center of the semiconductor substrate. Furthermore, by applying voltages to focus ring electrodes, the electromagnetic field can be locally controlled to promote plasma uniformity, or by applying voltages to focus ring heating elements, the plasma energy can be locally controlled to promote plasma uniformity. Other advantages or benefits can be achieved using various aspects described herein.

[0019] For brevity and convenience, similar components shown in the figures may be individually or collectively referred to by the same base reference number. In the figures, instances of such components may be labeled with the base reference number appended with a respective instance identifier (in the form "-#"). For example, a description may refer to x widgets ZZZ, with the instances in the figures being labeled ZZZ-1, ZZZ-2, ... ZZZ-x. A reference in the description to a particular instance of a component includes a reference to the base reference number and the corresponding instance identifier (e.g., an instance of widget ZZZ-2).

[0020] FIG. 1 is a schematic diagram of a processing tool 100 for semiconductor processing in accordance with some embodiments of the present disclosure. FIG. 1 includes X, Y, and Z axes to facilitate the illustration of various orientations, and such axes are reproduced accordingly in other figures. The processing tool 100 in FIG. 1 is depicted in a simplified manner so as not to obscure various aspects described herein. Those skilled in the art will readily appreciate other aspects of the processing tool 100. The processing tool 100 is depicted in this example as a capacitively coupled plasma (CCP) processing tool. In other examples, the processing tool 100 can be configured as an inductively coupled plasma (ICP) processing tool, an electron cyclotron resonance (ECR) processing tool, or other processing tools. Those skilled in the art will readily appreciate that aspects described herein are also applicable to such other processing tools. The processing tool 100 may be for performing plasma semiconductor processes such as sputtering, physical vapor deposition (PVD), modified double plasma (MDP), plasma enhanced chemical vapor deposition (PECVD), ion beam etching (IBE), reactive ion etching (RIE), and other semiconductor processes.

[0021] The processing tool 100 includes a chamber 102. The chamber 102 has an interior volume 104 defined by the interior walls of the chamber 102. The processing tool 100 includes a substrate support 106 disposed in the interior volume 104 of the chamber 102. The substrate support 106 includes an electrostatic chuck (ESC) 108, a midplate 110, and a baseplate 112. In the illustrated configuration, the midplate 110 is disposed above the baseplate 112, and the ESC 108 is disposed above the midplate 110. The substrate support 106 is disposed on and supported by a pedestal 114. The baseplate 112 is disposed on the pedestal 114.

[0022] The substrate support 106 has a support surface 116 configured to support a semiconductor substrate 120 during semiconductor processing. During semiconductor processing, the semiconductor substrate 120 is disposed on the support surface 116 of the substrate support 106. In the illustrated example, the support surface 116 is the top surface of the ESC 108. In the illustrated example of FIG. 1, the support surface 116 lies in the xy plane.

[0023] The ESC 108 includes a chucking electrode 122 configured to have a direct current (DC) voltage applied to it to chuck the semiconductor substrate 120 on the support surface 116. The ESC 108 may include a dielectric material coating the chucking electrode 122 to electrically insulate it from direct contact with the chucking electrode 122. The dielectric material may be or include any non-conductive material, such as aluminum oxide (Al2O3), yttrium oxide (YO3), silicon oxide (SiO2), or the like, or a combination thereof. In some embodiments of the present disclosure, the ESC 108 may include a resistive heating element configured to have an electric current flow therethrough, thereby generating thermal energy that is conducted to the semiconductor substrate 120.

[0024] The midplate 110 includes n RF electrodes 132. The RF electrodes 132 are configured to have a voltage (e.g., an RF signal) applied to them to generate and / or control a plasma. The RF electrodes 132 can have any arrangement and any number of electrodes. By including multiple RF electrodes 132, localized control of the plasma within the chamber 102 can be achieved. The RF electrodes 132 may have a dielectric material thereon to electrically insulate them from direct electrical contact with other components. In some embodiments of the present disclosure, the midplate 110 includes a fluid channel configured to have a fluid (e.g., a liquid) flowing therethrough to remove and dissipate thermal energy from the semiconductor substrate 120. The fluid channel may also be referred to as a cooler.

[0025] The base plate 112 includes n bias electrodes 136. The bias electrodes 136 are configured to have a bias voltage (e.g., an RF signal) applied to them to enhance the driveability of the RF electrodes 132. The bias electrodes 136 can have any arrangement and any number of electrodes. In some embodiments of the present disclosure, the number and arrangement of the bias electrodes 136 correspond to the number and arrangement of the RF electrodes 132. In some embodiments of the present disclosure, the base plate 112 has one bias electrode 136. The bias electrode 136 may have a dielectric material thereon to electrically insulate the bias electrode 136 from direct electrical contact with other components.

[0026] Processing tool 100 includes a focus ring translation assembly. As generally shown in FIG. 1 , focus ring translation assembly includes frame 138, which, in the illustrated example, projects laterally from pedestal 114. Frame 138 is configured to support a segmented focus ring that laterally surrounds semiconductor substrate 120 disposed on support surface 116. As shown in FIG. 1 , the segmented focus ring is supported by focus ring translation assembly and includes m focus ring segments 140 that laterally surround semiconductor substrate 120. As described in more detail below, in various embodiments, frame 138 can be movable or stationary, and further, can be separate from substrate support 106 or can be attached to, fixed to, and / or integral with substrate support 106 (e.g., ESC 108). In various embodiments, the focus ring translation assembly is configured to (i) laterally, radially translate focus ring segment 140 (e.g., in an x-y plane parallel to support surface 116), (ii) tilt focus ring segment 140 (e.g., at a respective angle relative to an axis perpendicular to support surface 116), or (iii) a combination thereof. In various embodiments, the focus ring translation assembly may be further configured to translate focus ring segment 140 vertically (e.g., in a z-direction perpendicular to support surface 116). Additional details of the focus ring translation assembly are described below.

[0027] The processing tool 100 further includes a gas distribution plate 142 and a gas showerhead 144 disposed within the interior volume 104 of the chamber 102. The gas distribution plate 142 has an opening, and the gas showerhead 144 has an opening. The gas distribution plate 142 and the gas showerhead 144 are electrically coupled to a ground node (e.g., electrically grounded). The chamber 102 has a gas inlet 146 fluidly coupled to a gas supply system 148 and a gas outlet 150 fluidly coupled to an exhaust system 152. The gas distribution plate 142 and the gas showerhead 144 are disposed within the interior volume 104 of the chamber 102 relative to the substrate support 106 such that, during semiconductor processing, gas flows from the gas supply system 148, through the gas inlet 146, through the openings through the gas distribution plate 142, through the openings through the gas showerhead 144, and into a processing volume 154 within the interior volume 104. The process volume 154 is located between the gas showerhead 144 and the substrate support 106 and is typically where a plasma is generated (using gases flowed into the process volume 154) during semiconductor processing. A semiconductor substrate 120 disposed on the support surface 116 of the substrate support 106 is exposed to the plasma in the process volume 154 during semiconductor processing. The gases then flow through a gas outlet 150 to an exhaust system 152 where they can be exhausted from the interior volume 104 of the chamber 102.

[0028] The processing tool 100 includes a DC power supply 160 and an isolation filter 162. The DC power supply 160 is configured to generate and output a DC voltage. Output nodes (e.g., a positive output node and a negative output node) of the DC power supply 160 are electrically coupled to input nodes of the isolation filter 162, and the output nodes of the isolation filter 162 are electrically coupled to the respective chucking electrodes 122. The isolation filter 162 may be, for example, a low-pass filter. The DC power supply 160 can be selectively turned on and off to chuck and release the semiconductor substrate 120.

[0029] The processing tool 100 includes an RF power source 164 and n signal control circuits 166. The RF power source 164 may include an RF power generator and an RF matching network and is configured to generate and output an RF voltage (e.g., an RF signal, which may be a continuous RF signal and / or a pulsed RF signal) at an output node of the RF power source 164. The output node of the RF power source 164 is electrically coupled to respective input nodes of the signal control circuits 166. The signal control circuits 166 are individually controllable to generate respective regulated RF voltages based on the RF voltage received from the RF power source 164. The regulated RF voltages generated by each signal control circuit 166 may have an regulated amplitude of the received RF voltage (e.g., may have a magnitude greater than, equal to, or less than 1, depending on the gain of the signal control circuit 166) and / or may have a phase offset from the received RF voltage. The gain and / or phase offset may each be selectable from a set of gains and / or phase offsets that the signal control circuit 166 is configured to implement. Each signal control circuit 166 has an output node electrically coupled to a corresponding RF electrode 132 of the midplate 110. Each signal control circuit 166 is configured to output a respective regulated RF voltage to the output node, such that the regulated RF voltage can be applied to a respective RF electrode 132. The RF voltage output by each signal control circuit 166 can be used to generate and / or control (e.g., locally generate and / or control) a plasma within the process volume 154.

[0030] The processing tool 100 includes an RF power supply 168 and n signal control circuits 172. The RF power supply 168 may include an RF power generator and an RF matching network and is configured to generate and output an RF voltage (e.g., an RF signal, which may be a continuous RF signal and / or a pulsed RF signal) at an output node of the RF power supply 168. The output node of the RF power supply 168 is electrically coupled to respective input nodes of the signal control circuits 172. Similar to the signal control circuits 166, the signal control circuits 172 are individually controllable to generate regulated RF voltages based on RF voltages received from the signal control circuits 172. The regulated RF voltages generated by each signal control circuit 172 may have an regulated amplitude of the received RF voltage (e.g., may have a magnitude greater than, equal to, or less than 1, depending on the gain of the signal control circuit 172) and / or may have a phase offset from the received RF voltage. The gain and / or phase offset may each be selectable from a set of gains and / or phase offsets that each signal control circuit 172 is configured to implement. Each signal control circuit 172 has an output node electrically coupled to a corresponding bias electrode 136 of the base plate 112. In examples where the base plate 112 has a single bias electrode 136, the signal control circuit 172 similarly has an output node electrically coupled to the single bias electrode 136 (e.g., the additional signal control circuit 172 may be omitted).

[0031] The base plate 112 may be strongly capacitively coupled to the RF electrode 132 in the mid-plate 110 in this example. Thus, according to some embodiments of the present disclosure, the base plate 112 is biased by RF voltages output by the signal control circuitry 172 to improve the driving capability of the RF electrode 132 to generate plasma. In operation, the signal control circuitry 172 outputs respective RF voltages having respective target amplitudes and respective target phase offsets relative to the RF voltages applied to the corresponding RF electrodes 132. Such RF voltages are applied to the bias electrode 136 of the base plate 112 to improve the driving capability of the RF electrode 132 to generate and control plasma.

[0032] The processing tool 100 includes an RF power source 180 and m signal control circuits 182. The RF power source 180 may include an RF power generator and an RF matching network and is configured to generate and output an RF voltage (e.g., an RF signal, which may be a continuous RF signal and / or a pulsed RF signal) at an output node of the RF power source 180. The output node of the RF power source 180 is electrically coupled to a respective input node of the signal control circuit 182. Each of the signal control circuits 182 is individually controllable to generate a regulated RF voltage based on the RF voltage received from the RF power source 180. The regulated RF voltage generated by each signal control circuit 182 may have an regulated amplitude of the received RF voltage (e.g., may have a magnitude greater than, equal to, or less than 1, depending on the gain of the signal control circuit 182) and / or may have a phase offset from the received RF voltage. The gain and / or phase offset may each be selectable from a set of gains and / or phase offsets that each signal control circuit 182 is configured to implement. Each signal control circuit 182 has an output node electrically coupled to an external electrical connector 186 of a corresponding focus ring segment 140 of the segmented focus ring. Each signal control circuit 182 is configured to output a regulated RF voltage at the output node, thereby applying the regulated RF voltage to each focus ring segment 140. The RF voltage output by signal control circuit 182 can be used to control a plasma in process volume 154 proximate an edge of semiconductor substrate 120.

[0033] The processing tool 100 includes a controller 190. The controller 190 can be or include any processor-based system, which may be or include a hardened processor architecture, a soft processor (e.g., implemented on the programmable fabric of a Field Programmable Gate Array (FPGA)), or a combination thereof. For example, the controller 190 can be or include a computer, a server, a Programmable Logic Controller (PLC), or the like, or a combination thereof. The controller 190 can control the operation of the processing tool 100 and can be programmed to implement the operation of the processing tool 100 as described herein. Among other things, the controller 190 is communicatively coupled to the signal control circuits 166, 172, 182. The controller 190 can be programmed to implement various set points for controlling the signal control circuits 166, 172, 182. The set points may be implemented in the signal control circuits 166, 172, 182 to implement and / or selectively configure the respective control circuits to achieve the corresponding gain and / or phase offset.

[0034] 1 is described as being implemented to control a plasma in chamber 102, segmented focus rings may also be implemented in other processing tools, such as ICP processing tools. The aspects described herein are applicable to other tools and configurations for controlling a plasma.

[0035] 2A and 2B are a layout diagram and a cross-sectional view, respectively, of segmented focus ring 200 according to some embodiments of the present disclosure. FIG. 2A shows cross section 2B-2B shown in FIG. 2B. Segmented focus ring 200 includes, in this example, 12 focus ring segments 240 (e.g., corresponding to focus ring segments 140 in FIG. 1). In other examples, other numbers of focus ring segments may be implemented.

[0036] Each focus ring segment 240 includes a respective electrode 250. The electrodes 250 of the focus ring segments 240 are electrically coupled to respective external electrical connectors 186, which are configured to be electrically coupled to the signal control circuitry 182. A dielectric material 252 covers the electrodes 250. The dielectric material 252 can electrically insulate the electrodes 250 from direct electrical contact with other components, including the electrodes 250 of adjacent focus ring segments 240. Exemplary dielectric materials 252 include any non-conductive material, such as aluminum oxide (Al2O3), yttrium oxide (YO3), silicon oxide (SiO2), or a combination thereof. The electrodes 250 can be formed of any conductive material (e.g., metal), such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), or a combination thereof.

[0037] Respective RF voltages can be applied to electrodes 250 of focus ring segments 240 to control the electromagnetic field proximate the edge of semiconductor substrate 120 during plasma semiconductor processing. Using multiple focus ring segments 240 allows for localized control of the electromagnetic field proximate each focus ring segment 240. Controlling the electromagnetic field allows for localized control of the plasma at the edge of semiconductor substrate 120, which can promote plasma uniformity.

[0038] 3A and 3B are a layout diagram and a cross-sectional view, respectively, of a segmented focus ring 300 according to some embodiments of the present disclosure. FIG. 3A shows cross section 3B-3B shown in FIG. 3B. Segmented focus ring 300 includes, in this example, 12 focus ring segments 340 (e.g., corresponding to focus ring segments 140 in FIG. 1). In other examples, other numbers of focus ring segments may be implemented.

[0039] Each focus ring segment 340 includes a respective resistive heating element 350. The resistive heating element 350 of a focus ring segment 340 is electrically coupled between two nodes of a respective external electrical connector 186, which is configured to be electrically coupled to signal control circuitry 182. The resistive heating element 350 is configured such that an electrical current flows through the resistive heating element 350 and generates thermal energy when electrically coupled between the two nodes of the respective external electrical connector 186. The resistive heating elements 350 are arranged in a serpentine configuration within each focus ring segment 340. A dielectric material 352 covers the resistive heating elements 350. The dielectric material 352 can electrically insulate the resistive heating elements 350 from direct electrical contact with other components, including the resistive heating elements 350 of adjacent focus ring segments 340.

[0040] Generating thermal energy by focus ring segment 240 can vary the energy of the plasma proximate the edge of semiconductor substrate 120 during plasma semiconductor processing. RF voltage applied to resistive heating element 350 of focus ring segment 340 can increase the energy of the plasma proximate that focus ring segment 340. Using multiple focus ring segments 340, the thermal energy of the plasma can be locally controlled proximate each focus ring segment 340. Controlling the thermal energy can locally control the plasma at the edge of semiconductor substrate 120, promoting plasma uniformity.

[0041] In some embodiments of the present disclosure, the focus ring translation assembly is a focus ring radial translation assembly configured to laterally and radially translate the focus ring segments 140 (e.g., in an x-y plane parallel to the support surface 116). FIG. 4 is a layout diagram of a segmented focus ring (comprising focus ring segments 140) illustrating the lateral and radial translation of the focus ring segments 140, according to some embodiments of the present disclosure. Each focus ring segment 140 can be translated along a respective lateral and radial direction 402 (e.g., in an x-y plane parallel to the support surface 116 and / or the top surface of the semiconductor substrate 120) from a center 404 of the segmented focus ring. Each focus ring segment 140 can be positioned at a proximal position 410 closest to the support surface 116 and / or the semiconductor substrate 120. At the proximal position 410, each focus ring segment 140 can have a minimum lateral and radial gap 412 between the inner sidewall surface of the respective focus ring segment 140 and the edge of the semiconductor substrate 120. Each focus ring segment 140 can be positioned at a distal position 420 farthest from support surface 116 and / or semiconductor substrate 120. At distal position 420, each focus ring segment 140 can have a maximum lateral and radial gap 422 between the inner sidewall surface of each focus ring segment 140 and the edge of semiconductor substrate 120. A focus ring radial translation assembly can laterally and radially translate the focus ring segments to any respective position between their respective proximal positions 410 and their respective distal positions 420.

[0042] FIG. 5 is a simplified cross-sectional view of a focus ring radial translation assembly according to some embodiments of the present disclosure, and FIG. 6 is a perspective view of the focus ring radial translation assembly. In this example, the focus ring radial translation assembly is configured to support and move six focus ring segments 140. In other examples, the focus ring radial translation assembly may be configured to support any number of focus ring segments 140. Semiconductor substrate 120, focus ring segments 140, ESC 108, pedestal 114, and controller 190 are shown in FIG. 5 for context.

[0043] The focus ring radial translation assembly includes a motor 502 having a drive shaft 504, a frame 506 having a vertical bracket 508, a lateral translation guide track 510, segment supports 512, and a linkage 514. The motor 502 is configured to extend and retract the drive shaft 504 vertically (e.g., along the Z direction). In some embodiments of the present disclosure, the motor 502 is a stepper motor (e.g., a helical stepper motor), a pneumatic motor, or a linear actuator / drive motor; in other examples, the motor 502 may be another type of motor. The motor 502 is communicatively coupled to a controller 190, which is configured to control the operation of the motor 502.

[0044] The motor 502 is shown mounted on and supported by a frame 506. In other embodiments, the motor 502 and frame 506 may be separate and relatively fixed. For example, the frame 506 may be attached to or integral with the substrate support 106, and the motor 502 may be fixedly mounted to the pedestal 114.

[0045] The frame 506 has vertical brackets 508 disposed at respective positions along the edge of the frame 506. The vertical brackets 508 protrude vertically (e.g., in the Z direction) from the frame 506. A respective lateral translation guide track 510 is disposed on each vertical bracket 508 (e.g., on an upper portion of the vertical bracket 508 adjacent the support surface 116). A respective segment support 512 is mechanically coupled or attached to each lateral translation guide track 510. The lateral translation guide tracks 510 are positioned to enable lateral, radial translation of each segment support 512 along their respective lateral translation guide tracks 510 and are mechanically coupled to each segment support 512.

[0046] Each linkage 514 is mechanically coupled between a respective segment support 512 and drive shaft 504. Linkages 514 are mechanically coupled to segment supports 512 and drive shaft 504 via pins 516 or other hinge connections. As shown, a first end of linkage 514 is mechanically coupled to a respective segment support 512 via pin 516, and a second end (e.g., opposite the respective first end) is mechanically coupled to drive shaft 504 via pin 516. Linkages 514 (and pins 516) are configured to translate vertical translation of drive shaft 504 (e.g., along the z-direction) into lateral, radial translation of focus ring segment 140 (e.g., in the x-y plane radially from the center of the segmented focus ring).

[0047] 7 and 8 illustrate the lateral and radial translation of focus ring segments 140 by the focus ring radial translation assembly of FIGS. 5 and 6. Referring to FIG. 7, drive shaft 504 is in a position protruding from motor 502, which causes segment supports 512 (via linkages 514) to assume their respective distal lateral and radial positions. The distal lateral and radial positions of segment supports 512 result in maximum lateral and radial gaps 422 between focus ring segments 140 and the edges of semiconductor substrate 120, respectively.

[0048] 8 , drive shaft 504 is moved vertically 802 to a retracted position by actuation of motor 502, which causes segment supports 512 (via links 514) to assume their respective proximal lateral and radial positions. The proximal lateral and radial positions of segment supports 512 create respective minimum lateral and radial gaps 412 between focus ring segments 140 and the edges of semiconductor substrate 120.

[0049] Generally, when motor 502 operates to move drive shaft 504 to the extended position of FIG. 7 , linkage 514 translates the vertical movement (e.g., upward movement) of drive shaft 504 into outward lateral, radial translation of segment supports 512 translating along their respective lateral translation guide tracks 510. Thus, motor 502 moving drive shaft 504 toward the extended position operates to increase the gap between focus ring segments 140 and semiconductor substrate 120. When motor 502 operates to move drive shaft 504 to the retracted position of FIG. 8 , linkage 514 translates the vertical movement (e.g., downward movement) of drive shaft 504 into inward lateral, radial translation of segment supports 512 translating along their respective lateral translation guide tracks 510. Thus, motor 502 moving drive shaft 504 toward the retracted position operates to reduce the gap between focus ring segments 140 and semiconductor substrate 120 .

[0050] 9 and 10 illustrate how a gap between focus ring segment 140 and the edge of semiconductor substrate 120 can contribute to plasma control, according to some embodiments of the present disclosure. FIGS. 9 and 10 are cross-sectional views of semiconductor substrate 120 and focus ring segment 140 (as disposed in processing tool 100 of FIG. 1 ). In FIG. 9 , a lateral and radial gap 902 is between semiconductor substrate 120 and focus ring segment 140, while in FIG. 10 , a lateral and radial gap 1002 is between semiconductor substrate 120 and focus ring segment 140. Lateral and radial gap 902 in FIG. 9 is larger than lateral and radial gap 1002 in FIG. 10 . In FIG. 9 , plasma sheath 912 is recessed into radial gap 902, while in FIG. 10 , plasma sheath 1012 is recessed into radial gap 1002. The plasma sheath 912 is recessed into the radial gap 902 in Figure 9 more than the plasma sheath 1012 is recessed into the radial gap 1002 in Figure 10. In Figures 9 and 10, the plasma sheaths 912, 1012 are generally flat at the center of the semiconductor substrate 120, so ion bombardment 914, 1014 from the plasma on the center of the semiconductor substrate 120 may be generally normal to the top surface of the semiconductor substrate 120. In Figure 9, at the edge of the semiconductor substrate 120, the plasma sheath 912 curves as the plasma sheath 912 is recessed into the radial gap 902, so ion bombardment 916 from the plasma at the edge of the semiconductor substrate 120 may be generally off-normal (e.g., at an angle from normal) to the top surface of the semiconductor substrate 120. 10 , at the edge of the semiconductor substrate 120, because the plasma sheath 1012 is slightly recessed into the radial gap 1002, the curvature of the plasma sheath 1012 is less severe, and therefore, the ion bombardment 1016 from the plasma at the edge of the semiconductor substrate 120 can be approximately normal to the top surface of the semiconductor substrate 120. Therefore, the ion bombardment 1014 at the center of the semiconductor substrate 120 and the ion bombardment 1016 at the edge of the semiconductor substrate 120 can both be approximately normal to the top surface of the semiconductor substrate 120.Therefore, by adjusting the gap between the edge of semiconductor substrate 120 and focus ring segment 140, the curvature of the plasma sheath and the resulting angle of ion bombardment on semiconductor substrate 120 can be controlled.

[0051] The processing tool 100 includes an RF power source 168 and n signal control circuits 172. The RF power source 168 may include an RF power generator and an RF matching network and is configured to generate and output an RF voltage (e.g., an RF signal, which may be a continuous RF signal and / or a pulsed RF signal) at an output node of the RF power source 168. The output node of the RF power source 168 is electrically coupled to a respective input node of the signal control circuit 172. Similar to the signal control circuit 166, the signal control circuit 172 RF power supply 168 Each signal control circuit 172 can be individually controllable to generate a regulated RF voltage based on the RF voltage received from the base plate 112. The regulated RF voltage generated by each signal control circuit 172 may have an regulated amplitude of the received RF voltage (e.g., may have a magnitude greater than, equal to, or less than 1, depending on the gain of the signal control circuit 172) and / or may have a phase offset from the received RF voltage. The gain and / or phase offset may each be selectable from a set of gains and / or phase offsets that the respective signal control circuit 172 is configured to implement. Each signal control circuit 172 has an output node electrically coupled to a corresponding bias electrode 136 of the base plate 112. In examples where the base plate 112 has a single bias electrode 136, the signal control circuit 172 similarly has an output node electrically coupled to the single bias electrode 136 (e.g., the additional signal control circuit 172 may be omitted).

[0052] FIG. 12 is a simplified cross-sectional view of a focus ring tilt assembly according to some embodiments of the present disclosure. In this example, the focus ring tilt assembly is configured to support and move six focus ring segments 140. In other examples, the focus ring tilt assembly may be configured to support any number of focus ring segments 140. In FIG. 12, semiconductor substrate 120, focus ring segments 140, ESC 108, pedestal 114, and controller 190 are shown for context.

[0053] The focus ring tilt assembly includes a motor 1202 having a drive shaft 1204, a fixed frame 1206 having a vertical bracket 1208, a segment support 1210, a hinge 1212, a movable frame 1214, and a lift pin 1216. The motor 1202 is configured to extend and retract the drive shaft 1204 vertically (e.g., along the Z direction). In some embodiments of the present disclosure, the motor 1202 is a stepper motor (e.g., a helical stepper motor), a pneumatic motor, or a linear actuator / drive motor; in other examples, the motor 1202 may be another type of motor. The motor 1202 is communicatively coupled to a controller 190, which is configured to control the operation of the motor 1202.

[0054] 12, the motor 1202 is disposed on and supported by a stationary frame 1206. In other embodiments, the motor 1202 and the stationary frame 1206 may be separate and relatively fixed. For example, the stationary frame 1206 may be attached to or integral with the substrate support 106, and the motor 1202 may be fixedly disposed on the pedestal 114.

[0055] The fixed frame 1206 has vertical brackets 1208 disposed at respective positions along the edge of the fixed frame 1206. The vertical brackets 1208 protrude vertically (e.g., in the Z direction) from the fixed frame 1206. Each segment support 1210 is mechanically coupled to a respective one or more vertical brackets 1208. The segment supports 1210 may be mechanically coupled to the one or more vertical brackets 1208 by any coupling that allows the segment supports 1210 to tilt, such as by hinges 1212.

[0056] The movable frame 1214 is mechanically attached to the drive shaft 1204. The movable frame 1214 extends laterally beyond (e.g., through) the vertical bracket 1208. The lift pins 1216 are mechanically attached to the movable frame 1214 and protrude vertically (e.g., in the Z direction) from the movable frame 1214. One or more of the lift pins 1216 contact the underside of a respective segment support 1210. The location at which the lift pins 1216 contact the underside of the segment support 1210 is laterally and radially more distal from the center of the segmented focus ring than the location at which the hinges 1212 are located, in this example. Because the hinges 1212 are located closer to the support surface 116 and thus the semiconductor substrate 120, tilting movement of the segment supports 1210 can result in the focus ring segments 140 remaining closer to the support surface 116 and thus the semiconductor substrate 120.

[0057] FIG. 13A is a perspective view of a focus ring tilt assembly according to some embodiments of the present disclosure, and FIG. 13B is a perspective view of a portion of the focus ring tilt assembly of FIG. 13A. The focus ring tilt assembly of FIGS. 13A and 13B is generally the focus ring tilt assembly of FIG. 12, and therefore a description of similar components will not be repeated here. FIGS. 13A and 13B show a stationary frame 1306 that is attached to or integral with the substrate support 106. Lift pins 1216 extend vertically through the stationary frame 1306 (e.g., through respective openings 1316). In FIGS. 13A and 13B, two lift pins 1216 contact the underside of each segment support 1210.

[0058] 14 and 15 illustrate tilting of focus ring segment 140 by the focus ring tilt assembly of FIG. 12. Referring to FIG. 14, drive shaft 1204 is in a first position from motor 1202, which causes segment supports 1210 to have their respective top surfaces parallel to support surface 116. Axis 1402 perpendicular to the top surfaces of focus ring segment 140 is parallel to an axis perpendicular to support surface 116 (e.g., in the z-direction).

[0059] 15, operation of the motor 1202 causes the drive shaft 1204 to move 1502 vertically to a second (e.g., extended) position, which causes the lift pins 1216 to move vertically. The vertical movement of the lift pins 1216 pushes radially distal portions of the segment supports 1210 vertically. The hinges 1212 mechanically couple the segment supports 1210, and the lift pins 1216 pushing against the segment supports 1210 causes the segment supports 1210 to tilt (e.g., rotate somewhat about their respective hinges 1212). The tilt of the segment supports 1210 is due to the angle 1504 of the axes 1402 in the position of FIG. 15 relative to the axes 1402 in the position of FIG. 14.

[0060] Generally, when motor 1202 operates to move drive shaft 1204 to a more retracted position, lift pins 1216 are lowered, causing segment support 1210, and focus ring segment 140 thereon, to rotate about their respective hinges in a rotational direction away from support surface 116 and / or semiconductor substrate 120. When motor 1202 operates to move drive shaft 1204 to a more protruding position, lift pins 1216 are raised, causing segment support 1210, and focus ring segment 140 thereon, to rotate about their respective hinges in a rotational direction toward support surface 116 and / or semiconductor substrate 120.

[0061] FIGS. 16 and 17 illustrate how tilting focus ring segment 140 can contribute to plasma control, according to some embodiments of the present disclosure. FIGS. 16 and 17 are cross-sectional views of semiconductor substrate 120 and focus ring segment 140 (as positioned in processing tool 100 of FIG. 1 ). In FIG. 16 , focus ring segment 140 has an upper surface parallel to the upper surface of the semiconductor substrate, while in FIG. 17 , focus ring segment 140 is tilted somewhat toward semiconductor substrate 120 (e.g., rotated toward semiconductor substrate 120). In FIG. 16 , plasma sheath 1612 is recessed into the gap between the edge of semiconductor substrate 120 and focus ring segment 140, while in FIG. 17 , plasma sheath 1712 is not recessed significantly into the gap and outlines the tilted focus ring segment 140. 16 and 17, the plasma sheath 1612, 1712 is generally flat at the center of the semiconductor substrate 120, so ion bombardment 1614, 1714 from the plasma on the center of the semiconductor substrate 120 may be generally normal to the top surface of the semiconductor substrate 120. In FIG. 16, at the edges of the semiconductor substrate 120, the plasma sheath 1612 curves as the plasma sheath 1612 recesses into the gap, so ion bombardment 1616 from the plasma at the edges of the semiconductor substrate 120 may be generally off-normal (e.g., at an angle from normal) to the top surface of the semiconductor substrate 120. Referring to FIG. 17, at the edges of the semiconductor substrate 120, the plasma sheath 1712 curves less severely because the plasma sheath 1712 recesses slightly into the gap, so ion bombardment 1716 from the plasma at the edges of the semiconductor substrate 120 may be generally closer to normal to the top surface of the semiconductor substrate 120. Thus, ion bombardment 1714 at the center of semiconductor substrate 120 and ion bombardment 1716 at the edge of semiconductor substrate 120 can both be approximately normal to the top surface of semiconductor substrate 120. Thus, by adjusting the tilt of focus ring segment 140, the curvature of the plasma sheath and the resulting angle of ion bombardment on semiconductor substrate 120 can be controlled.

[0062] In some embodiments of the present disclosure, the focus ring translation assembly includes a focus ring radial translation subassembly and a focus ring tilt subassembly. FIG. 18 shows an example of such a focus ring translation assembly. In general, as is apparent from FIG. 18, the focus ring radial translation subassembly includes similar components to the focus ring radial translation assembly of FIG. 5, and the focus ring tilt subassembly includes similar components to the focus ring tilt assembly of FIG. 12. Some components of the focus ring translation assembly of FIG. 18 may be considered to be components of both the focus ring radial translation subassembly and the focus ring tilt subassembly.

[0063] The focus ring movement assembly includes motors 502, 1202 with respective drive shafts 504, 1204, a frame 506 with a vertical bracket 508, a lateral translation guide track 510, a linkage 514, a movable bracket 1808, a vertical translation guide track 1810, a segment support 1210, a frame 1814 with an extendable arm 1816, and a lift pin 1216. The motors 502, drive shafts 504, frame 506, vertical bracket 508, and lateral translation guide track 510 are generally configured as described with respect to FIG. 5. Each movable bracket 1808 is mechanically coupled or attached to a respective lateral translation guide track 510. The lateral translation guide tracks 510 are positioned to enable lateral, radial translation of each movable bracket 1808 along its respective lateral translation guide track 510 and are mechanically coupled to each movable bracket 1808. Each segment support 1210 is mechanically coupled to a respective movable bracket 1808. The segment supports 1210 may be mechanically coupled to the movable brackets 1808 by any coupling that allows the segment supports 1210 to tilt, such as by hinges 1212.

[0064] Each linkage 514 is mechanically coupled between a respective movable bracket 1808 and drive shaft 504. Linkages 514 are mechanically coupled to movable bracket 1808 and drive shaft 504 via pins 516 or other hinge connections. Linkages 514 (and pins 516) are configured to translate vertical translation of drive shaft 504 (e.g., along the z-direction) into lateral, radial translation of focus ring segments 140 (e.g., in the x-y plane radially from the center of the segmented focus ring).

[0065] The motor 1202 is disposed on and supported by the drive shaft 504. A frame 1814 is mechanically attached to the drive shaft 1204 of the motor 1202. The telescoping arms 1816 are mechanically attached to the frame 1814. A radially outer portion (e.g., a tube) of the telescoping arms 1816 is configured to translate radially relative to a radially inner portion of the telescoping arms 1816 that is mechanically attached to the frame 1814. The radially outer portion of the telescoping arms 1816 is mechanically coupled to the vertical translation guide track 1810. A lift pin 1216 is mechanically attached to each radially outer portion of the telescoping arms 1816 and protrudes vertically (e.g., in the Z direction) from the telescoping arms 1816. The telescoping arms 1816 and vertical translation guide tracks 1810 are configured to maintain the positioning of the lift pins 1216 relative to their respective segment supports 1210 as the moveable bracket 1808 moves radially and laterally along the lateral translation guide tracks 510. The vertical translation guide tracks 1810 generally do not allow lateral movement of the radially outer portions of the telescoping arms 1816 relative to their respective moveable brackets 1808. Thus, as the moveable bracket 1808 moves laterally and radially, the respective telescoping arms 1816 retract or extend correspondingly to the movement of the moveable bracket 1808.

[0066] Generally, when motor 502 operates to move drive shaft 504 vertically 1830, linkage 514 translates the vertical 1830 movement of drive shaft 504 into lateral, radial translation of movable bracket 1808 (and thus segment supports 1210), which translates along their respective lateral translation guide tracks 510. Thus, motor 502 moving drive shaft 504 vertically 1830 also operates to move segment supports 1210 laterally, radially 1832, thereby adjusting the gap between focus ring segment 140 and semiconductor substrate 120. Generally, when motor 1202 operates to move drive shaft 1204 vertically 1834, telescoping arm 1816 translates vertically along vertical translation guide track 1810, thereby moving lift pins 1216 vertically. Vertical movement of the lift pins 1216 causes the segment supports 1210 , and the respective focus ring segments 140 thereon, to tilt 1836 about their respective hinges 1212 .

[0067] In the illustrated embodiment, the motor 1202 is disposed on and supported by the drive shaft 504, so that when the motor 502 is operated to move the drive shaft 504, the motor 1202 can, in some cases, operate reciprocally or in conjunction with the operation of the motor 502. For example, when the motor 502 operates to move the segment support 1210 laterally, the movement of the drive shaft 504 moves the motor 1202 and drive shaft 1204 vertically, causing vertical movement of the lift pins 1216. In such a situation, to maintain the tilt of the segment support 1210 with radial and lateral movement, the drive shaft 1204 will move in the opposite direction with an equal movement distance from the drive shaft 504. A controller 190 communicatively coupled to the motors 502, 1202 can control and coordinate such movement of the drive shafts 504, 1204 in addition to general control of the motors 502, 1202.

[0068] In some embodiments of the present disclosure, the focus ring translation assembly includes a focus ring vertical translation subassembly in addition to a focus ring radial translation subassembly and / or a focus ring tilt subassembly. FIGS. 19, 20, and 21 are simplified cross-sectional views of respective focus ring translation assemblies including a focus ring vertical translation subassembly, according to some embodiments of the present disclosure. The focus ring vertical translation subassembly includes a motor 1902 having a drive shaft 1904 and includes a frame 1906. The frame 1906 is mechanically attached to the drive shaft 1904. The motor 1902 is communicatively coupled to a controller 190, which is configured to control the operation of the motor 1902.

[0069] Referring to FIG. 19 , the focus ring translation assembly includes a focus ring vertical translation subassembly in addition to the focus ring radial translation subassembly. The focus ring radial translation subassembly is the focus ring radial translation assembly of FIG. 5 . Frame 506 is mechanically attached to and supported by frame 1906. As described with respect to FIG. 5 , vertical movement 1920 of drive shaft 504 by motor 502 causes lateral, radial translation 1922 of segment support 512. Vertical movement 1910 of drive shaft 1904 causes vertical movement of the focus ring radial translation subassembly, which in turn causes vertical movement 1912 of segment support 512.

[0070] Referring to FIG. 20 , the focus ring translation assembly includes a focus ring vertical translation subassembly in addition to a focus ring tilt subassembly. The focus ring tilt subassembly is the focus ring tilt assembly of FIG. 12 . Fixed frame 1206 is mechanically attached to and supported by frame 1906. As described with respect to FIG. 12 , vertical movement 2020 of drive shaft 1204 by motor 1202 causes tilt 2022 of segment support 1210. Vertical movement 1910 of drive shaft 1904 causes vertical movement of the focus ring tilt subassembly, which in turn causes vertical movement 1912 of segment support 1210.

[0071] Referring to FIG. 21 , the focus ring translation assembly includes a focus ring vertical translation subassembly in addition to a focus ring radial translation subassembly and a focus ring tilt subassembly. The focus ring radial translation subassembly and focus ring tilt subassembly are as shown in and described with respect to FIG. 18 . Frame 506 is mechanically attached to and supported by frame 1906. As described with respect to FIG. 18 , vertical movement 1830 of drive shaft 504 by motor 502 causes lateral, radial translation 1832 of segment support 1210, and vertical movement 1834 of drive shaft 1204 by motor 1202 causes tilt 1836 of segment support 1210. Vertical movement 1910 of drive shaft 1904 causes vertical movement of the focus ring radial translation subassembly and focus ring tilt subassembly, thereby causing vertical movement 1912 of segment support 1210.

[0072] 22 and 23 illustrate how vertical translation of focus ring segment 140 can contribute to plasma control, according to some embodiments of the present disclosure. FIGS. 22 and 23 are cross-sectional views of semiconductor substrate 120 and focus ring segment 140 (as disposed in processing tool 100 of FIG. 1 ). In FIG. 22 , focus ring segment 140 is in a first vertical position, and in FIG. 23 , focus ring segment 140 is in a second vertical position that is higher than the first vertical position. In FIG. 22 , plasma sheath 2212 is recessed into the gap between the edge of semiconductor substrate 120 and focus ring segment 140, and in FIG. 23 , plasma sheath 2312 contours to focus ring segment 140. 22 and 23 , plasma sheath 2212, 2312 is generally flat at the center of semiconductor substrate 120, so ion bombardment 2214, 2314 from the plasma on the center of semiconductor substrate 120 may be generally normal to the top surface of semiconductor substrate 120. In FIG. 22 , at the edge of semiconductor substrate 120, plasma sheath 2212 curves as plasma sheath 2212 recesses into the gap, so ion bombardment 2216 from the plasma at the edge of semiconductor substrate 120 may be generally off-normal (e.g., at an angle from normal) to the top surface of semiconductor substrate 120. Referring to FIG. 23 , at the edge of semiconductor substrate 120, plasma sheath 2312 curves less severely as plasma sheath 2312 contours to focus ring segment 140, so ion bombardment 2316 from the plasma at the edge of semiconductor substrate 120 may be generally closer to normal to the top surface of semiconductor substrate 120. Thus, ion bombardment 2314 at the center of semiconductor substrate 120 and ion bombardment 2316 at the edge of semiconductor substrate 120 can both be approximately normal to the top surface of semiconductor substrate 120. Thus, by adjusting the vertical position of focus ring segment 140, the curvature of the plasma sheath and the resulting angle of ion bombardment on semiconductor substrate 120 can be controlled.

[0073] 24 is a schematic diagram of an RF power system 2400 of processing tool 100 in accordance with some embodiments of the present disclosure. RF power system 2400 includes an RF power source 2402, s signal control circuits 2404, and s electrodes 2406. RF power source 2402 can be RF power sources 164, 168, 180 (each of which can include an RF power generator and an RF matching network), signal control circuit 2404 can be signal control circuit 166, 172, 182, and electrode 2406 can be RF electrode 132, bias electrode 136, and / or electrode 250 and / or resistive heating element 350 of focus ring segment 140.

[0074] Each signal control circuit 2404 includes a respective voltage / power control circuit 2412 and a respective phase control circuit 2414. For example, signal control circuit 2404-1 includes a voltage / power control circuit 2412-1 and a phase control circuit 2414-1, and signal control circuit 2404-s includes a voltage / power control circuit 2412-s and a phase control circuit 2414-s. Each voltage / power control circuit 2412 has an input node that is the input node of the respective signal control circuit 2404 and is electrically coupled to an output node of RF power supply 2402. Each voltage / power control circuit 2412 has an output node that is electrically coupled to the input node of the respective phase control circuit 2414. Each phase control circuit 2414 has an output node that is the output node of the respective signal control circuit 2404 that is electrically coupled to the respective electrode 2406. The voltage / power control circuit 2412 and phase control circuit 2414 of each signal control circuit 2404 are communicatively coupled to, for example, controller 190 to receive one or more set points for the respective signal control circuit 2404. The setpoint(s) are digital numbers or codes that selectively set the gain of the voltage / power control circuit 2412 and the phase offset of the phase control circuit 2414 .

[0075] In some embodiments of the present disclosure, the voltage / power control circuit 2412 may include an amplifier and a selectively configurable impedance network configured to receive an RF voltage and output an RF voltage with a gain adjusted relative to the received RF voltage. The selectively configurable impedance network may include, for example, several switched resistors connected in parallel. For example, the switched resistor may include a resistor electrically connected in series with a channel of a transistor. For example, a signal, which may be a bit of a setting value or a bit resulting from decoding the setting value, may be applied to the gate of the transistor to selectively place the channel of the transistor in a conductive or non-conductive state. The gain of the voltage / power control circuit 2412 may be selectively configured by selectively electrically connecting and / or disconnecting resistors in parallel. Those skilled in the art will readily understand the configuration of the voltage / power control circuit 2412 and how such a voltage / power control circuit 2412 may be selectively configurable to achieve different gains. This may be done by using any combination of impedance elements, such as resistors, capacitors, and / or inductors.

[0076] Similarly, in some embodiments of the present disclosure, the phase control circuit 2414 may include an amplifier and a selectively configurable impedance network configured to receive an RF voltage and output an RF voltage with a phase offset adjusted relative to the received RF voltage. The selectively configurable impedance network may include several parallel-connected switched impedance elements, including, for example, resistors, capacitors, and / or inductors. For example, a signal, which may be a bit of a set value or a bit resulting from decoding the set value, may be applied to the gate of a transistor to selectively place the transistor channel in a conductive or non-conductive state. Selectively electrically connecting and / or disconnecting the impedance elements in parallel may selectively configure the phase offset of the phase control circuit 2414. Those skilled in the art will readily appreciate the configuration of the phase control circuit 2414 and how such a phase control circuit 2414 may be selectively configurable to achieve different phase offsets.

[0077] FIG. 25 is a schematic diagram of an RF power system 2500 that may be implemented with processing tool 100 according to some embodiments of the present disclosure. RF power system 2500 of FIG. 25 is an improvement over RF power system 2400 of FIG. 24. RF power system 2400 is a multi-frequency RF power system. RF power system 2400 includes t RF power sources 2402. Each RF power source 2402 is configured to generate an RF voltage at a target frequency, and the target frequencies of the RF power sources 2402 may be different. For example, the target frequency of RF power source 2402-1 may be 13.56 MHz, and the target frequency of RF power source 2402-t may be 60 MHz.

[0078] The RF power system 2500 includes s signal control circuits 2404 for each RF power source 2402. In total, the RF power system 2500 includes (s x t) signal control circuits 2404. In the figure, each signal control circuit 2404 is appended with "-ij", where i indicates which electrode 2406 a given signal control circuit 2404 is associated with and j indicates which RF power source 2402 a given signal control circuit 2404 is associated with. Each signal control circuit 2404 includes a voltage / power control circuit 2412 and a phase control circuit 2414, and is configured as described above with respect to FIG. 24 .

[0079] For each RF power supply 2402, the output node of the respective RF power supply 2402 is electrically coupled to input nodes of one of the signal control circuits 2404 associated with that RF power supply 2402. Each signal control circuit 2404 has an output node electrically coupled to an input node of a respective RF isolation filter 2502 (named similarly to the signal control circuit 2404). Each RF isolation filter 2502 is configured to pass an RF voltage having a target frequency of the RF voltage generated by the associated RF power supply 2402. Each RF isolation filter 2502 can remove or attenuate signals at frequencies that are somewhat below the target frequency. For example, the RF isolation filter 2502 can be a bandpass filter centered at the frequency of the RF voltage generated by the associated RF power supply 2402.

[0080] The RF power system 2500 includes s analog summer / summing circuits 2504. Each analog summer / summing circuit 2504 has t input nodes and is associated with a respective electrode 2406. The output node of each RF isolation filter 2502 associated with a given electrode 2406 is electrically coupled to a respective input node of the analog summer / summing circuit 2504 associated with that given electrode 2406. Each analog summer / summing circuit 2504 is configured to sum the t RF voltages received from its respective RF isolation filter 2502 to generate an RF voltage. Each analog summer / summing circuit 2504 has an output node electrically coupled to the electrode 2406 with which it is associated. The RF voltage generated by the analog summer / summing circuit 2504 is output to the electrode 2406 at the output node. By having multiple RF sources 2402 generating RF voltages at different frequencies, the RF voltage can include multiple RF components applied to the electrode 2406. Other aspects of RF power system 2500 will be apparent to those skilled in the art in light of the foregoing description, including the description of RF power system 2400 of FIG.

[0081] 26 illustrates a processor-based system 2600 according to some embodiments of the present disclosure. The processor-based system 2600 may be or include a computer, a server, a PLC, etc., or a combination thereof. The processor-based system 2600 may be implemented as the controller 190 or other processor-based system for performing any of the operations described herein. The processor-based system 2600 includes one or more processors 2602, a memory system 2612, a communication bus 2622, one or more input / output (I / O) interfaces 2632, and a network interface 2642.

[0082] Each processor 2602 may include one or more processor cores 2604. Each processor 2602 and / or processor core 2604 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), a hardened processor such as an application specific integrated circuit (ASIC), or a combination thereof, or a soft processor implemented on programmable logic such as an FPGA.

[0083] The memory system 2612 includes one or more memory controllers 2614 and memories 2616. The memory controller 2614 is configured to control read and / or write access to a particular memory 2616 or a subset of the memory 2616. The memory 2616 may include main memory, disk storage, or any suitable combination thereof. The memory 2616 may include any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state storage, etc. The memory 2616 is a non-transitory machine-readable storage medium. Instructions 2618 are stored in the memory 2616. The instructions 2618 may be machine-executable code (e.g., machine code) and may be comprised of firmware, software, a program, an application, or other machine-executable code. The instructions 2618 may embody, for example, software modules 2620 that, when executed by the one or more processors 2602, perform various functionality and operations described herein.

[0084] The one or more I / O interfaces 2632 are configured to be electrically and / or communicatively coupled to one or more I / O devices 2634. The I / O devices 2634 include the signal control circuits 166, 172, 182 and the motors 502, 1202, 1902. The signal control circuits 166, 172, 182 and the motors 502, 1202, 1902 can receive their respective setting values ​​via the I / O interfaces 2632. Other exemplary I / O devices 2634 include a keyboard, a mouse, a display device, a printer, etc. The one or more I / O interfaces 2632 can include connectors or coupling circuits such as an industrial application connection, a Universal Serial Bus (USB) connection, a High-Definition Multimedia Interface (HDMI®) connection, a Bluetooth® circuit, etc.

[0085] The network interface 2642 is configured to be communicatively coupled to a network 2644. The network interface 2642 can include circuitry for wired communication, such as an Ethernet connection, and / or can include circuitry for wireless communication, such as circuitry for Wi-Fi® communication. For example, one or more computers and / or servers communicatively coupled to the network 2644 can communicate recipes, process conditions, etc. to the processor-based system 2600 via the network 2644 and the network interface 2642.

[0086] The communication bus 2622 is communicatively coupled to the one or more processors 2602, the memory system 2612, the one or more I / O interfaces 2632, and the network interface 2642. The various components may communicate with one another via the communication bus 2622. The communication bus 2622 may control the flow of communication, such as by including an arbiter for arbitrating communications.

[0087] FIG. 27 is a flowchart of a method 2700 of semiconductor processing according to some embodiments of the present disclosure. Method 2700 can be implemented using the processing tool 100 described above. Operation of method 2700 can be initiated and / or controlled by controller 190 (e.g., by execution of instructions 2618 by one or more processors 2602). In block 2702, a semiconductor substrate 120 is transferred into chamber 102 of processing tool 100 and placed on a substrate support 106 (e.g., ESC 108) within chamber 102. A segmented focus ring (including focus ring segments 140) can be positioned on a focus ring movement assembly as semiconductor substrate 120 is transferred into chamber 102. Semiconductor substrate 120 can be secured to ESC 108 by applying a DC voltage to chucking electrode 122 (e.g., chucking semiconductor substrate 120). The DC voltage can be generated by DC power supply 160 and applied to chucking electrode 122. With semiconductor substrate 120 transferred into chamber 102 and positioned on support surface 116 , a segmented focus ring is positioned to laterally surround semiconductor substrate 120 .

[0088] In block 2704, the focus ring segments 140 of the segmented focus ring are moved to their respective positions relative to the semiconductor substrate 120. The focus ring segments 140 can be moved by lateral or radial translation to adjust the gap between the semiconductor substrate 120 and the focus ring segments 140. The focus ring segments 140 can be moved by tilting or rotating to adjust the angle of the top surface of the focus ring segments 140 relative to the top surface of the semiconductor substrate 120. Additionally, the focus ring segments 140 can be moved by vertical translation. As previously described, any combination or permutation of movements can be implemented. The focus ring segments 140 can be moved by a focus ring movement assembly, which can be one of the focus ring movement assemblies previously described or other assemblies. The controller 190 can cause the respective motors 502, 1202, 1902 to move the focus ring segments 140, as previously described.

[0089] At block 2706, a plasma semiconductor process is performed in the chamber 102 of the processing tool 100. The plasma semiconductor process may be, for example, an etch process, a deposition process, or other applicable process. Examples of plasma semiconductor processes include sputtering, PVD, MDP, PECVD, IBE, and RIE. Block 2706 includes, at block 2708, generating a plasma in the processing volume 154 of the chamber 102. The semiconductor substrate 120 may be exposed to the plasma in the processing volume 154. The plasma may be generated by flowing gas into the chamber 102 (e.g., from the gas supply system 148 and through the gas inlet 146, gas distribution plate 142, and gas showerhead 144) and applying an RF voltage to each of the RF electrodes 132. The plasma may be generated as a result of the RF voltage on the RF electrodes 132 and the gas showerhead 144 being grounded.

[0090] Block 2706 further includes, in block 2710, controlling the plasma at the periphery of semiconductor substrate 120. While described separately for simplicity, blocks 2708 and 2710 can be performed in the same operation(s). The plasma can be controlled at the periphery of semiconductor substrate 120 by an RF voltage applied to RF electrode 132. The plasma can be controlled at the periphery using a segmented focus ring including focus ring segments 140.

[0091] In an example where focus ring segment 140 includes respective electrodes 250, as in FIGS. 2A and 2B, plasma can be controlled peripherally by applying respective RF voltages (e.g., RF signals) to electrodes 250 of focus ring segment 140 to control the electromagnetic field at the periphery. In an example where focus ring segment 140 includes respective resistive heating elements 350, as in FIGS. 3A and 3B, plasma can be controlled peripherally by applying respective RF voltages (e.g., RF signals) to resistive heating elements 350 of focus ring segment 140 to pass current through resistive heating elements 350 and generate thermal energy. Voltage to either electrode 250 or resistive heating element 350 can be supplied via RF power supply 180 and signal control circuitry 182, which can be controlled by controller 190, for example, as described above.

[0092] The plasma can be controlled at the periphery of semiconductor substrate 120 by the respective positions of focus ring segments 140 relative to semiconductor substrate 120. As previously described, the lateral, radial distance, tilt, and / or vertical positioning of focus ring segments 140 can control the plasma at the periphery. Any combination or permutation of positioning can be implemented. Positioning can be achieved by movement of focus ring segments 140 in block 2704.

[0093] Additionally, biasing of the bias electrode 136 may be performed during blocks 2708, 2710. The biasing may include applying an RF bias voltage to the bias electrode 136.

[0094] At block 2712, the plasma semiconductor process is terminated and semiconductor substrate 120 is unloaded from chamber 102 of processing tool 100. At the end of the plasma semiconductor process, RF voltages may be stopped from RF electrode 132 and bias electrode 136 (e.g., RF power supplies 164, 168 are turned off). Additionally, voltages may be stopped from electrode 250 or resistive heating element 350 of focus ring segment 140 (e.g., RF power supply 180 is turned off). Gases may be stopped from being delivered into chamber 102 and may be evacuated from chamber 102. Next, focus ring movement assembly may move focus ring segment 140 to a position to provide clearance for transferring semiconductor substrate 120. DC voltages may also be stopped (e.g., by turning off DC power supply 160) to release semiconductor substrate 120 from ESC 108. Semiconductor substrate 120 may then be unloaded from chamber 102.

[0095] FIG. 28 is a flowchart of a method 2800 for semiconductor processing according to some embodiments of the present disclosure. In block 2802, a plasma semiconductor process, such as that described with reference to FIG. 27, is performed on a first plurality of semiconductor substrates (e.g., one or more lots of semiconductor substrates) using processing tool 100. The plasma semiconductor process is performed under first process conditions. The first process conditions may include, where applicable, setpoints for signal control circuits 166, 172, 182 and motors 502, 1202, 1902. Based on the respective setpoints, an RF voltage is applied to RF electrode 132, an RF voltage is applied to bias electrode 136, an RF voltage (e.g., an RF signal) is applied to electrode 250 or resistive heating element 350 of focus ring segment 140, and focus ring segment 140 is positioned according to a lateral, radial, tilt, and / or vertical position.

[0096] In block 2804, a first property of each of the first plurality of semiconductor substrates is measured near a center of each of the first plurality of substrates, and in block 2806, a second property of each of the first plurality of semiconductor substrates is measured near an edge of each of the first plurality of substrates. The first property and the second property may be the same feature or component. The use of “first” and “second” is for ease of reference. The measurements may be performed with a metrology tool. In some embodiments of the present disclosure, the first and second properties may be or include a profile angle of a recess etched by a plasma semiconductor process. In some embodiments of the present disclosure, the first and second properties may be or include a depth of a recess etched by a plasma semiconductor process. In some embodiments of the present disclosure, the first and second properties may be or include a thickness of a film deposited by a plasma semiconductor process. Other properties may also be measured. Variation between the first property and the second property may indicate plasma non-uniformity in the plasma semiconductor process when the first plurality of substrates is processed.

[0097] In block 2808, one or more processor-based systems are used to determine second process conditions to be applied in the processing tool while the plasma semiconductor process is performed on the second plurality of semiconductor substrates. The second process conditions are determined based on the first and second characteristics measured in blocks 2804 and 2806, such as a difference between the first and second characteristics. The second process conditions are the same type of process conditions as the first process conditions, but the values ​​or data of the first and second process conditions may be different. As an example, a processor-based system running an Advanced Process Control (APC) algorithm may determine the RF voltages (e.g., RF signals that may include their respective amplitudes and phases) to be applied to RF electrode 132 and bias electrode 136, may determine the RF voltages (e.g., RF signals that may include their respective amplitudes and phases) to be applied to electrode 250 or resistive heating element 350 of focus ring segment 140, and may determine the positioning of focus ring segment 140, including its lateral, radial, tilt, and / or vertical position. The processor-based system running the APC algorithm may then determine the setpoints to set signal control circuits 166, 172, 182 and motors 502, 1202, 1902, if applicable.

[0098] In block 2810, second process conditions are applied to a processing tool for a plasma semiconductor process. For example, a processor-based system running an APC algorithm may communicate the second process conditions to controller 190 (e.g., via network 2644). Controller 190 may reset a recipe for the plasma semiconductor process to have the second process conditions and may communicate the second process conditions (e.g., setpoints) to signal control circuits 166, 172, 182, which may selectively configure signal control circuits 166, 172, 182 based on the second process conditions and to motors 502, 1202, 1902, which may responsively position focus ring segment 140.

[0099] At block 2812, a plasma semiconductor process is performed on a second plurality of semiconductor substrates using processing tool 100. The plasma semiconductor process is performed at second process conditions. Based on the setpoints of the second process conditions, RF voltages are applied and motors 502, 1202, 1902 position focus ring segment 140 during the plasma semiconductor process.

[0100] A first embodiment is a processing tool for semiconductor processing. The processing tool includes a chamber, a substrate support, and a focus ring translation assembly. The chamber has an internal volume therein. The substrate support is disposed within the chamber. The substrate support has a support surface configured to support a semiconductor substrate. A focus ring translation assembly is disposed within the chamber. The focus ring translation assembly includes a frame and a plurality of segment supports mechanically coupled to the frame. Each segment support of the plurality of segment supports is configured to support a respective individual segment of a focus ring. The focus ring includes a plurality of individual segments. The focus ring translation assembly is configured to support the plurality of individual segments arranged to laterally surround the support surface. The focus ring translation assembly is configured to translate the plurality of segment supports in respective first directions. Each first direction of the respective first directions is within the plane of the support surface and parallel to a respective radial direction from a center of the support surface.

[0101] In the processing tool of the first embodiment, the frame may include a plurality of lateral translation guide tracks. Each segment support of the plurality of segment supports may be mechanically coupled to a respective one of the plurality of lateral translation guide tracks, and each segment support may be configured to translate laterally along its respective lateral translation guide track. The focus ring movement assembly may further include a drive motor including a drive shaft and a plurality of linkages. Each linkage of the plurality of linkages may have a first end mechanically coupled to a respective one of the plurality of segment supports and a second end mechanically coupled to the drive shaft. The drive motor may be configured to cause movement of the drive shaft and the plurality of linkages, and movement of the drive shaft and the plurality of linkages may translate the plurality of segment supports in their respective first directions.

[0102] In the processing tool of the first embodiment, the focus ring movement assembly may be further configured to tilt the plurality of segment supports about respective axes, each of the respective axes being parallel to the support surface.

[0103] In the processing tool of the first embodiment, the focus ring movement assembly may be further configured to translate the plurality of segment supports in respective second directions parallel to the direction perpendicular to the support surface.

[0104] The processing tool of the first embodiment may further include a plurality of focus ring electrical connectors, each of which may be configured to electrically connect to and supply a voltage to an electrode of a respective individual segment of the focus ring.

[0105] The processing tool of the first embodiment may further include a plurality of focus ring electrical connectors, wherein each pair of focus ring electrical connectors may be configured to electrically connect to and provide electrical current to the resistive thermal element of a respective individual segment of the focus ring.

[0106] The processing tool of the first embodiment may further include a power supply and a plurality of control circuits. The power supply may be configured to output a voltage at an output node of the power supply. Each control circuit of the plurality of control circuits may have an input node electrically coupled to the output node of the power supply and an output node configured to be electrically coupled to a respective individual segment of the focus ring. Each control circuit of the plurality of control circuits may be controllable to adjust the amplitude, phase, or a combination thereof of the voltage and output a corresponding adjusted voltage at the output node of the respective control circuit. Furthermore, the processing tool may further include a controller. The controller may include one or more processors and non-transitory memory. The non-transitory memory may include stored instructions that, when executed by the one or more processors, cause the one or more processors to control the plurality of control circuits to adjust their respective amplitudes, their respective phases, or a combination thereof.

[0107] A second embodiment is a processing tool for semiconductor processing. The processing tool includes a chamber, a substrate support, and a focus ring movement assembly. The chamber has an internal volume therein. The substrate support is disposed in the internal volume of the chamber. The substrate support has a support surface configured to support a semiconductor substrate. The focus ring movement assembly is disposed in the internal volume of the chamber. The focus ring movement assembly includes a frame and a plurality of segment supports mechanically coupled to the frame. Each segment support of the plurality of segment supports is configured to support a respective individual segment of the focus ring. The focus ring includes a plurality of individual segments. The focus ring movement assembly is configured to support the plurality of individual segments arranged to laterally surround the support surface. The focus ring movement assembly is configured to tilt the plurality of segment supports about respective axes, each axis of the respective axes being parallel to the support surface.

[0108] In the processing tool of the second embodiment, the focus ring movement assembly may further include a drive motor including a drive shaft and a plurality of lift pins. Each lift pin of the plurality of lift pins may be mechanically coupled to the drive shaft and configured to contact a respective individual segment of the focus ring. The drive motor may be configured to cause movement of the drive shaft and the plurality of lift pins, such that movement of the drive shaft and the plurality of lift pins tilts the plurality of segment supports about their respective axes.

[0109] In the processing tool of the second embodiment, the focus ring movement assembly may be further configured to translate the plurality of segment supports in respective directions, each of which may be parallel to a respective radial direction in the plane of the support surface from a center of the support surface.

[0110] In the processing tool of the second embodiment, the focus ring movement assembly may be further configured to translate the plurality of segment supports in respective directions parallel to the direction perpendicular to the support surface.

[0111] The processing tool of the second embodiment may further include a plurality of focus ring electrical connectors, each of which may be configured to electrically connect to and supply a voltage to an electrode of a respective individual segment of the focus ring.

[0112] The processing tool of the second embodiment may further include a plurality of focus ring electrical connectors, wherein each pair of focus ring electrical connectors may be configured to electrically connect to and provide electrical current to the resistive thermal element of a respective individual segment of the focus ring.

[0113] The processing tool of the second embodiment may further include a power supply and a plurality of control circuits. The power supply may be configured to output a voltage at an output node of the power supply. Each control circuit of the plurality of control circuits may have an input node electrically coupled to the output node of the power supply and an output node configured to be electrically coupled to a respective individual segment of the focus ring. Each control circuit of the plurality of control circuits may be controllable to adjust the amplitude, phase, or a combination thereof of the voltage and output a corresponding adjusted voltage at the output node of the respective control circuit. Furthermore, the processing tool may further include a controller. The controller may include one or more processors and non-transitory memory. The non-transitory memory may include stored instructions that, when executed by the one or more processors, cause the one or more processors to control the plurality of control circuits to adjust their respective amplitudes, their respective phases, or a combination thereof.

[0114] A third embodiment is a method for semiconductor processing. The method includes moving multiple ring segments of a focus ring to respective positions relative to a semiconductor substrate. The semiconductor substrate is positioned on a support surface of a substrate support. The substrate support is positioned within a chamber of a processing tool. The multiple ring segments of the focus ring laterally surround the semiconductor substrate. Moving the multiple ring segments includes translating the multiple ring segments in respective first directions, each of which is in a plane of the support surface and parallel to a respective radial direction from a center of the support surface. The method includes generating a plasma in a processing volume of the chamber. The semiconductor substrate is exposed to the plasma while the multiple ring segments are at their respective positions relative to the semiconductor substrate.

[0115] In a third embodiment, moving the plurality of ring segments may further include tilting the plurality of ring segments about respective axes, each of which may be parallel to the support surface.

[0116] In a third embodiment, moving the plurality of ring segments may further include translating the plurality of ring segments in respective second directions parallel to a direction perpendicular to the support surface.

[0117] The third embodiment may further include providing a respective current to each ring segment of the plurality of ring segments. Each ring segment of the plurality of ring segments may include a resistive heating element. The respective current may flow through the resistive heating element.

[0118] The method of the third embodiment may further include applying a respective voltage to each ring segment of the plurality of ring segments. Each ring segment of the plurality of ring segments may include a segment electrode.

[0119] A fourth embodiment is a method for semiconductor processing. The method includes moving multiple ring segments of a focus ring to respective positions relative to a semiconductor substrate. The semiconductor substrate is positioned on a support surface of a substrate support. The substrate support is positioned within a chamber of a processing tool. The multiple ring segments of the focus ring laterally surround the semiconductor substrate. Moving the multiple ring segments includes tilting the multiple ring segments about respective axes, each of which is parallel to the support surface. The method includes generating a plasma in a processing volume of the chamber. The semiconductor substrate is exposed to the plasma while the multiple ring segments are at their respective positions relative to the semiconductor substrate.

[0120] In a fourth embodiment, moving the plurality of ring segments may further include translating the plurality of ring segments in respective directions parallel to a direction perpendicular to the support surface.

[0121] The method of the fourth embodiment may further include providing a respective current to each ring segment of the plurality of ring segments. Each ring segment of the plurality of ring segments may include a resistive heating element. The respective current may flow through the resistive heating element.

[0122] The method of the fourth embodiment may further include applying a respective voltage to each ring segment of the plurality of ring segments. Each ring segment of the plurality of ring segments may include a segment electrode.

[0123] A fifth embodiment is a method for semiconductor processing. The method includes using a processing tool to perform a plasma semiconductor process having first process conditions on a first plurality of substrates. A plurality of individual segments of a focus ring laterally surround the substrates during the plasma semiconductor process. The first process conditions correspond to respective positions of the plurality of individual segments disposed at respective first radial distances from the substrates during the plasma semiconductor process on the first plurality of substrates. The method includes measuring a first characteristic of each of the first plurality of substrates proximate a center of each of the first plurality of substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates proximate an edge of each of the first plurality of substrates. The second characteristic is formed by the plasma semiconductor process. The method includes determining, by a processor-based system, second process conditions to be applied during the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to respective positions of the plurality of individual segments disposed at respective second radial distances from the substrates during the plasma semiconductor process on the second plurality of semiconductor substrates. The method includes performing a plasma semiconductor process having second process conditions on a second plurality of substrates using the processing tool.

[0124] In a fifth embodiment, the first process conditions may further correspond to respective positions of the plurality of individual segments disposed at respective tilt angles relative to the upper surface of the substrate during the plasma semiconductor process on the first plurality of substrates, and the second process conditions may further correspond to respective positions of the plurality of individual segments disposed at respective tilt angles relative to the upper surface of the substrate during the plasma semiconductor process on the second plurality of substrates.

[0125] In a fifth embodiment, the first process conditions may further correspond to respective positions of a plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor process on the first plurality of substrates, and the second process conditions may further correspond to respective positions of a plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor process on the second plurality of substrates.

[0126] In a fifth embodiment, the first characteristic may include, for each substrate of the first plurality of substrates, a first profile angle of a recess etched into the respective substrate proximate a respective center of the respective substrate, and the second characteristic may include, for each substrate of the first plurality of substrates, a second profile angle of a recess etched into the respective substrate proximate a respective edge of the respective substrate.

[0127] In a fifth embodiment, the first characteristic may include, for each substrate of the first plurality of substrates, a first depth of a recess etched into the respective substrate proximate a respective center of the respective substrate, and the second characteristic may include, for each substrate of the first plurality of substrates, a second depth of a recess etched into the respective substrate proximate a respective edge of the respective substrate.

[0128] In a fifth embodiment, the first characteristic may include, for each substrate of the first plurality of substrates, a first thickness of the film deposited on the respective substrate proximate a center of the respective substrate, and the second characteristic may include, for each substrate of the first plurality of substrates, a second thickness of the film proximate an edge of the respective substrate.

[0129] A sixth embodiment is a method for semiconductor processing. The method includes using a processing tool to perform a plasma semiconductor process having first process conditions on a first plurality of substrates. A plurality of individual segments of a focus ring laterally surround the substrates during the plasma semiconductor process. The first process conditions correspond to respective positions of the plurality of individual segments disposed at respective tilt angles with respect to upper surfaces of the substrates during the plasma semiconductor process on the first plurality of substrates. The method includes measuring a first characteristic of each of the first plurality of substrates proximate a center of each of the first plurality of substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a second characteristic of each of the first plurality of substrates proximate an edge of each of the first plurality of substrates. The second characteristic is formed by the plasma semiconductor process. The method includes determining, by a processor-based system, second process conditions to be applied during the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic. The second process conditions correspond to respective positions of the plurality of individual segments disposed at respective tilt angles with respect to upper surfaces of the substrates during the plasma semiconductor process on the second plurality of substrates. The method includes performing a plasma semiconductor process having second process conditions on a second plurality of substrates using the processing tool.

[0130] In a sixth embodiment, the first process conditions may further correspond to respective positions of a plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor process on the first plurality of substrates, and the second process conditions may further correspond to respective positions of a plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor process on the second plurality of substrates.

[0131] In a sixth embodiment, the first characteristic may include, for each substrate of the first plurality of substrates, a first profile angle of a recess etched into the respective substrate proximate a respective center of the respective substrate, and the second characteristic may include, for each substrate of the first plurality of substrates, a second profile angle of a recess etched into the respective substrate proximate a respective edge of the respective substrate.

[0132] In a sixth embodiment, the first characteristic may include, for each substrate of the first plurality of substrates, a first depth of a recess etched into the respective substrate proximate a respective center of the respective substrate, and the second characteristic may include, for each substrate of the first plurality of substrates, a second depth of a recess etched into the respective substrate proximate a respective edge of the respective substrate.

[0133] In a sixth embodiment, the first characteristic may include, for each substrate of the first plurality of substrates, a first thickness of the film deposited on the respective substrate proximate a center of the respective substrate, and the second characteristic may include, for each substrate of the first plurality of substrates, a second thickness of the film proximate an edge of the respective substrate.

[0134] Although various embodiments have been described in detail, it should be understood that various changes, substitutions, and alterations can be made thereto without departing from the scope defined by the appended claims.

Claims

1. 1. A processing tool for semiconductor processing, comprising: a chamber; a substrate support disposed within the chamber, the substrate support having a support surface configured to support a semiconductor substrate; a focus ring translation assembly disposed within the chamber, the focus ring translation assembly comprising: a frame; and a plurality of segment supports mechanically coupled to the frame, each segment support of the plurality of segment supports configured to support a respective individual segment of a focus ring, the focus ring comprising a plurality of individual segments, the focus ring translation assembly supporting the plurality of individual segments arranged laterally around the support surface, and configured to translate the plurality of segment supports in respective first directions, each first direction being parallel to a respective radial direction from a center of the support surface within the plane of the support surface; the frame includes a plurality of lateral translation guide tracks, each segment support of the plurality of segment supports being mechanically coupled to a respective lateral translation guide track of the plurality of lateral translation guide tracks, each segment support being configured to translate laterally along its respective lateral translation guide track; The focus ring moving assembly includes: a drive motor including a drive shaft; a plurality of linkages, each linkage having a first end mechanically coupled to a respective segment support of the plurality of segment supports and a second end mechanically coupled to the drive shaft, the drive motor configured to move the drive shaft and the plurality of linkages, the movement of the drive shaft and the plurality of linkages translating the plurality of segment supports in the respective first directions. Processing tools.

2. 10. The processing tool of claim 1, wherein the focus ring movement assembly is further configured to tilt the plurality of segment supports about respective axes, each of the respective axes being parallel to the support surface.

3. 10. The processing tool of claim 1, wherein the focus ring translation assembly is further configured to translate the plurality of segment supports in respective second directions parallel to a direction perpendicular to the support surface.

4. 10. The processing tool of claim 1, further comprising a plurality of focus ring electrical connectors, each focus ring electrical connector of the plurality of focus ring electrical connectors configured to electrically connect to and supply a voltage to an electrode of a respective individual segment of the focus ring.

5. 10. The processing tool of claim 1, further comprising a plurality of focus ring electrical connectors, each pair of focus ring electrical connectors of the plurality of focus ring electrical connectors configured to electrically connect to and supply electrical current to a resistive thermal element of a respective individual segment of the focus ring.

6. a power supply configured to output a voltage at an output node of the power supply; a plurality of control circuits, each control circuit of the plurality of control circuits having an input node electrically coupled to the output node of the power supply and an output node configured to be electrically coupled to a respective individual segment of the focus ring, each control circuit of the plurality of control circuits being controllable to adjust the amplitude, phase, or a combination thereof of the voltage and output a corresponding regulated voltage at the output node of the respective control circuit. The processing tool of claim 1 .

7. one or more processors; a non-transitory memory containing instructions stored therein that, when executed by the one or more processors, cause the one or more processors to control the plurality of control circuits to adjust the respective amplitudes, the respective phases, or a combination thereof; and a controller comprising: The processing tool of claim 6 , further comprising:

8. 1. A processing tool for semiconductor processing, comprising: a chamber; a substrate support disposed within the chamber, the substrate support having a support surface configured to support a semiconductor substrate; a focus ring translation assembly disposed within the chamber, the focus ring translation assembly comprising: a frame; and a plurality of segment supports mechanically coupled to the frame, each segment support of the plurality of segment supports configured to support a respective individual segment of a focus ring, the focus ring comprising a plurality of individual segments, each including an electrode; the focus ring translation assembly supporting the plurality of individual segments arranged laterally surrounding the support surface, and configured to tilt the plurality of segment supports about respective axes to control curvature of the plasma sheath and an angle of ion bombardment on the semiconductor substrate, each of the respective axes being parallel to the support surface; Processing tools.

9. The focus ring moving assembly includes: a drive motor including a drive shaft; 10. The processing tool of claim 8, further comprising: a plurality of lift pins, each lift pin mechanically coupled to the drive shaft and configured to contact a respective individual segment of the focus ring; the drive motor configured to move the drive shaft and the plurality of lift pins, the movement of the drive shaft and the plurality of lift pins tilting the plurality of segment supports about the respective axes.

10. 9. The processing tool of claim 8, wherein the focus ring translation assembly is further configured to translate the plurality of segment supports in respective directions, each of the respective directions being parallel to a respective radial direction in a plane of the support surface from a center of the support surface.

11. 9. The processing tool of claim 8, wherein the focus ring translation assembly is further configured to translate the plurality of segment supports in respective directions parallel to a direction perpendicular to the support surface.

12. 10. The processing tool of claim 8, further comprising a plurality of focus ring electrical connectors, each focus ring electrical connector of the plurality of focus ring electrical connectors configured to electrically connect to and supply a voltage to the electrode of a respective individual segment of the focus ring.

13. 10. The processing tool of claim 8, further comprising a plurality of focus ring electrical connectors, wherein each pair of focus ring electrical connectors of the plurality of focus ring electrical connectors is configured to electrically connect to and supply electrical current to a resistive thermal element in a respective individual segment of the focus ring.

14. a power supply configured to output a voltage at an output node of the power supply; a plurality of control circuits, each control circuit of the plurality of control circuits having an input node electrically coupled to the output node of the power supply and an output node configured to be electrically coupled to a respective individual segment of the focus ring, each control circuit of the plurality of control circuits being controllable to adjust the amplitude, phase, or a combination thereof of the voltage and output a corresponding regulated voltage at the output node of the respective control circuit. The processing tool of claim 8 .

15. one or more processors; a non-transitory memory containing instructions stored therein that, when executed by the one or more processors, cause the one or more processors to control the plurality of control circuits to adjust the respective amplitudes, the respective phases, or a combination thereof; and a controller comprising: The processing tool of claim 14 further comprising:

16. 1. A method for semiconductor processing, comprising: moving multiple ring segments of a focus ring to respective positions relative to a semiconductor substrate, the semiconductor substrate being disposed on a support surface of a substrate support, the substrate support being disposed within a chamber of a processing tool, the multiple ring segments of the focus ring laterally surrounding the semiconductor substrate, and moving the multiple ring segments includes translating the multiple ring segments in respective first directions, each first direction being parallel to a respective radial direction from a center of the support surface within a plane of the support surface; generating a plasma in the chamber, the semiconductor substrate being exposed to the plasma while the plurality of ring segments are in their respective positions relative to the semiconductor substrate; Including, The method, wherein moving the plurality of ring segments further comprises tilting the plurality of ring segments about respective axes, each axis of the respective axes being parallel to the support surface.

17. 17. The method of claim 16, wherein moving the plurality of ring segments further comprises translating the plurality of ring segments in respective second directions parallel to a direction perpendicular to the support surface.

18. 17. The method of claim 16, further comprising supplying a respective current to each ring segment of the plurality of ring segments, each ring segment of the plurality of ring segments including a resistive heating element, the respective current flowing through the resistive heating element.

19. The method of claim 16 , further comprising applying a respective voltage to each ring segment of the plurality of ring segments, each ring segment of the plurality of ring segments comprising a segment electrode.

20. 1. A method for semiconductor processing, comprising: moving a plurality of ring segments of a focus ring to respective positions relative to a semiconductor substrate, the semiconductor substrate being disposed on a support surface of a substrate support, the substrate support being disposed within a chamber of a processing tool, the plurality of ring segments of the focus ring each including an electrode and laterally surrounding the semiconductor substrate, and moving the plurality of ring segments includes tilting the plurality of ring segments about respective axes to control a curvature of a plasma sheath and an angle of ion bombardment on the semiconductor substrate, each axis of the axes being parallel to the support surface; generating a plasma in the chamber, the semiconductor substrate being exposed to the plasma while the plurality of ring segments are in their respective positions relative to the semiconductor substrate; Including, method.

21. 21. The method of claim 20, wherein moving the plurality of ring segments further comprises translating the plurality of ring segments in respective directions parallel to a direction normal to the support surface.

22. 21. The method of claim 20, further comprising supplying a respective current to each ring segment of the plurality of ring segments, each ring segment of the plurality of ring segments including a resistive heating element, the respective current flowing through the resistive heating element.

23. 21. The method of claim 20, further comprising applying a respective voltage to each ring segment of the plurality of ring segments, each ring segment of the plurality of ring segments comprising a segment electrode.

24. 1. A method for semiconductor processing, comprising: using a processing tool to perform a plasma semiconductor process having first process conditions on a first plurality of substrates, wherein a plurality of individual segments of a focus ring laterally surround the substrates during the plasma semiconductor process, the first process conditions corresponding to respective positions of the plurality of individual segments disposed at respective first radial distances from the substrates during the plasma semiconductor process on the first plurality of substrates; measuring a first characteristic of each of the first plurality of substrates proximate a center of each of the first plurality of substrates, the first characteristic being formed by the plasma semiconductor process; measuring a second characteristic of each of the first plurality of substrates proximate an edge of each of the first plurality of substrates, the second characteristic being formed by the plasma semiconductor process; and determining, by a processor-based system, second process conditions to be applied during performing the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic, the second process conditions corresponding to positions of each of the plurality of individual segments disposed at respective second radial distances from a substrate during the plasma semiconductor process on the second plurality of substrates; performing the plasma semiconductor process having the second process conditions on the second plurality of substrates using the processing tool; Including, the first process condition further corresponds to a position of each of the plurality of individual segments disposed at a respective tilt angle relative to an upper surface of a substrate during the plasma semiconductor process on the first plurality of substrates; The method, wherein the second process conditions further correspond to respective positions of the plurality of individual segments disposed at respective tilt angles relative to an upper surface of a substrate during the plasma semiconductor processing on the second plurality of substrates.

25. the first process conditions further correspond to respective positions of the plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor processing on the first plurality of substrates; the second process conditions further correspond to respective positions of the plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor processing on the second plurality of substrates.

25. The method of claim 24.

26. the first characteristic includes, for each substrate of the first plurality of substrates, a first profile angle of a recess etched into the respective substrate proximate a respective center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second profile angle of a recess etched into the respective substrate proximate a respective edge of the respective substrate; 25. The method of claim 24.

27. the first characteristic includes, for each substrate of the first plurality of substrates, a first depth of a recess etched into the respective substrate proximate a respective center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second depth of a recess etched into the respective substrate proximate a respective edge of the respective substrate; 25. The method of claim 24.

28. the first characteristic includes, for each substrate of the first plurality of substrates, a first thickness of a film deposited on the respective substrate proximate a center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second thickness of the film proximate each edge of the respective substrate; 25. The method of claim 24.

29. 1. A method for semiconductor processing, comprising: using a processing tool to perform a plasma semiconductor process having first process conditions on a first plurality of substrates, wherein a plurality of individual focus ring segments laterally surround the substrates during the plasma semiconductor process, the first process conditions corresponding to respective positions of the plurality of individual segments including electrodes positioned at respective oblique angles with respect to upper surfaces of the substrates during the plasma semiconductor process on the first plurality of substrates, the positions controlling a curvature of a plasma sheath and an angle of ion bombardment on the substrates; measuring a first characteristic of each of the first plurality of substrates proximate a center of each of the first plurality of substrates, the first characteristic being formed by the plasma semiconductor process; measuring a second characteristic of each of the first plurality of substrates proximate an edge of each of the first plurality of substrates, the second characteristic being formed by the plasma semiconductor process; and determining, by a processor-based system, second process conditions to be applied during performing the plasma semiconductor process on a second plurality of substrates based on the first characteristic and the second characteristic, the second process conditions corresponding to positions of each of the plurality of individual segments disposed at respective tilt angles with respect to an upper surface of the substrate during the plasma semiconductor process on the second plurality of substrates, the positions controlling a curvature of a plasma sheath and an angle of ion bombardment on the substrate; performing the plasma semiconductor process having the second process conditions on the second plurality of substrates using the processing tool; A method comprising:

30. the first process conditions further correspond to respective positions of the plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor processing on the first plurality of substrates; the second process conditions further correspond to respective positions of the plurality of individual segments disposed at respective vertical positions relative to the substrates during the plasma semiconductor processing on the second plurality of substrates.

30. The method of claim 29.

31. the first characteristic includes, for each substrate of the first plurality of substrates, a first profile angle of a recess etched into the respective substrate proximate a respective center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second profile angle of a recess etched into the respective substrate proximate a respective edge of the respective substrate; 30. The method of claim 29.

32. the first characteristic includes, for each substrate of the first plurality of substrates, a first depth of a recess etched into the respective substrate proximate a respective center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second depth of a recess etched into the respective substrate proximate a respective edge of the respective substrate; 30. The method of claim 29.

33. the first characteristic includes, for each substrate of the first plurality of substrates, a first thickness of a film deposited on the respective substrate proximate a center of the respective substrate; the second characteristic includes, for each substrate of the first plurality of substrates, a second thickness of the film proximate each edge of the respective substrate; 30. The method of claim 29.

34. A processing tool for semiconductor processing, comprising: a chamber; a substrate support disposed within the chamber, the substrate support having a support surface configured to support a semiconductor substrate; a focus ring translation assembly disposed within the chamber, the focus ring translation assembly comprising: a frame; and a plurality of segment supports mechanically coupled to the frame, each segment support of the plurality of segment supports configured to support a respective individual segment of a focus ring, the focus ring comprising a plurality of individual segments, the focus ring translation assembly supporting the plurality of individual segments arranged laterally around the support surface, and configured to translate the plurality of segment supports in respective first directions, each first direction being parallel to a respective radial direction from a center of the support surface within the plane of the support surface; The focus ring movement assembly is further configured to tilt the plurality of segment supports about respective axes, each axis of the respective axes being parallel to the support surface. Processing tools.

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