Power supply device

Abstract

To provide a power supply device capable of suppressing cyclic current of an input side circuit.SOLUTION: A power supply device comprises: a first bridge circuit; a transformer to whose first coil an AC voltage outputted from the first bridge circuit is inputted, and from whose second coil an induced AC voltage is outputted; a second bridge circuit that converts the AC voltage outputted from the second coil of the transformer into a DC voltage and outputs the resultant to a load; and a controller that controls a phase difference between a first drive pulse to be outputted to switch elements in the first bridge circuit and a second drive pulse to be outputted to switch elements in the second bridge circuit to control the DC voltage to be outputted from the second bridge circuit. The controller performs control of increasing or decreasing a duty ratio of the first drive pulse to be larger or lower than a standard value on the basis of a first voltage inputted to the first bridge circuit and a second voltage of the load.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power supply device. [Background technology]

[0002] A DC-DC converter of the DAB (Dual Active Bridge) type is described in Patent Document 1. The DAB is capable of isolation, and is easily capable of step-up / step-down operation and bidirectional power conversion.

[0003] However, DAB has a characteristic that when the voltage difference between the input side (primary side) and the output side (secondary side) is large, the current circulating in the input side circuit increases. This characteristic does not decrease even if the phase difference between the input side and the output side, which is the command value for the output current, is set to 0°.

[0004] Therefore, under conditions where a significant difference in input / output voltage occurs, such as output droop (short circuit), the current increases beyond the normal operating range in almost all elements through which current flows, causing problems such as a significant increase in circuit stress and loss.

[0005] Patent Document 2 describes a switching power supply device that solves the above problem by controlling the phase of the switch elements in the arms (phase between phases). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 5,027,264 [Patent Document 2] Japanese Patent Application Publication No. 2018-26961 Summary of the Invention [Problem to be solved by the invention]

[0007] In a three-phase power supply device, the phase difference between the three phases is fixed at 120°, so the switching power supply device described in Patent Document 2 cannot be applied to three-phase cases.

[0008] An object of the present invention is to provide a power supply device that can suppress circulating current in an input side circuit. [Means for solving the problem]

[0009] A power supply device according to one aspect of the present invention comprises: a first bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, and converting a DC voltage into an AC voltage and outputting the AC voltage; a transformer including a first winding and a second winding, the AC voltage output from the first bridge circuit being input to the first winding and the AC voltage induced in the transformer being output from the second winding; a second bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, converting the AC voltage output from the second winding of the transformer into a DC voltage and outputting the DC voltage to a load; a control unit that outputs a plurality of first drive pulses to the switch elements in the first bridge circuit to cause the switch elements in the first bridge circuit to perform a switching operation, outputs a plurality of second drive pulses to the switch elements in the second bridge circuit to cause the switch elements in the second bridge circuit to perform a switching operation, and controls a phase difference between the plurality of first drive pulses and the plurality of second drive pulses to control a DC voltage output from the second bridge circuit; Equipped with The control unit performing control to make the duty ratio of the plurality of first drive pulses smaller or larger than a standard value based on a first voltage input to the first bridge circuit and a second voltage of the load; It is characterized by:

[0010] In the power supply device, The control unit and performing control to make the duty ratio smaller or larger than the standard value based on a value of the ratio of the second voltage to the first voltage. It is characterized by:

[0011] In the power supply device, The control unit The smaller the value of the ratio, the smaller or larger the duty ratio is controlled to be than the standard value. It is characterized by:

[0012] In the power supply device, The control unit When the value of the ratio is within a predetermined range including 1, control is performed to maintain the duty ratio at the standard value. It is characterized by:

[0013] In the power supply device, The control unit performing control to adjust the duty ratio in accordance with the phase difference; It is characterized by:

[0014] In the power supply device, each of the first bridge circuit and the second bridge circuit is a three-phase bridge circuit; the transformer is a three-phase transformer; The control unit Control is performed to fix the phase difference between three arms of the first bridge circuit and between three arms of the second bridge circuit to 120°. It is characterized by: [Effects of the Invention]

[0015] The power supply device according to one aspect of the present invention has an effect of suppressing circulating current in an input side circuit. [Brief explanation of the drawings]

[0016] [Figure 1]FIG. 1 is a diagram showing the configuration of a power supply device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing waveforms at various parts on the primary side of the power supply device of the comparative example. [Figure 3] FIG. 3 is a diagram illustrating functional blocks of the control unit of the power supply device according to the embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of the duty ratio when the phase difference is 0° in the power supply device according to the embodiment. [Figure 5] FIG. 5 is a diagram illustrating an example of the duty ratio when the phase difference is 0° in the power supply device according to the embodiment. [Figure 6] FIG. 6 is a diagram showing waveforms at various parts on the primary side of the power supply device according to the embodiment. [Figure 7] FIG. 7 is a diagram showing the relationship between the duty ratio and the effective value of the output AC voltage of the first bridge circuit according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A power supply device according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0018] <Embodiment> (Overall composition) 1 is a diagram showing the configuration of a power supply device according to an embodiment. Power supply device 1 is a DAB (Dual Active Bridge) type bidirectional DC-DC converter. In this embodiment, power supply device 1 receives a DC voltage Vin that is output from a power supply 2 and smoothed by a capacitor 3, and outputs a DC voltage Vout to a load 4.

[0019] The voltage Vin corresponds to an example of a "first voltage" in the present disclosure, and the voltage Vout corresponds to an example of a "second voltage" in the present disclosure.

[0020] The power supply device 1 includes a first voltage sensor 11, a first bridge circuit 12 on the primary side, a reactor 13, a transformer 14, a second bridge circuit 15 on the secondary side, a capacitor 16, a second voltage sensor 17, and a control unit 18.

[0021] The first voltage sensor 11 detects the voltage Vin and outputs it to the control unit 18.

[0022] The first bridge circuit 12 is a single-phase full-bridge circuit including transistors Tr1 to Tr4.

[0023] In the embodiment, the first bridge circuit 12 is a single-phase full-bridge circuit, but the present disclosure is not limited to this. The first bridge circuit 12 may be a three-phase bridge circuit including three arms.

[0024] In the present disclosure, each transistor is described as a MOSFET, but is not limited to this. Each transistor may be a silicon power device, a GaN power device, a SiC power device (for example, an IGBT (Insulated Gate Bipolar Transistor)), or the like.

[0025] Each transistor has a parasitic diode (body diode) that can actively conduct current, or has a diode connected in anti-parallel: the pn junction between the back gate and the source and drain of the MOSFET.

[0026] The source of transistor Tr1 is electrically connected to the drain of transistor Tr2. The drain of transistor Tr1 is electrically connected to the drain of transistor Tr3. The source of transistor Tr3 is electrically connected to the drain of transistor Tr4. The source of transistor Tr2 is electrically connected to the source of transistor Tr4.

[0027] Each of the transistors Tr1 to Tr4 corresponds to an example of a "switch element" in the present disclosure.

[0028] Each of the transistors Tr1 and Tr3 corresponds to an example of a "high-side switching element" in the present disclosure. Each of the transistors Tr2 and Tr4 corresponds to an example of a "low-side switching element" in the present disclosure.

[0029] The transistors Tr1 and Tr2 correspond to an example of an "arm" in the present disclosure. Similarly, the transistors Tr3 and Tr4 correspond to an example of an "arm" in the present disclosure.

[0030] The connection point between the drain of the transistor Tr1 and the drain of the transistor Tr3 is one input terminal 12a of the first bridge circuit 12. The connection point between the source of the transistor Tr2 and the source of the transistor Tr4 is the other input terminal 12b of the first bridge circuit 12.

[0031] The connection point between the source of the transistor Tr1 and the drain of the transistor Tr2 is one output terminal 12c of the first bridge circuit 12. The connection point between the source of the transistor Tr3 and the drain of the transistor Tr4 is the other output terminal 12d of the first bridge circuit 12.

[0032] The input terminal 12a is electrically connected to one end (high potential end) of the capacitor 3. The input terminal 12b is electrically connected to the other end (low potential end) of the capacitor 3.

[0033] A voltage Vin is supplied between the input terminal 12a and the input terminal 12b.

[0034] One end of reactor 13 is electrically connected to output terminal 12c. In the embodiment, reactor 13 is arranged on the primary side, but the present disclosure is not limited to this. Reactor 13 may be arranged on the secondary side, or on both the primary side and the secondary side.

[0035] The transformer 14 includes a first winding 14a, a second winding 14b, and a core 14c. The first winding 14a and the second winding 14b are wound around the core 14c.

[0036] The transformer 14 corresponds to an example of a "transformer" in the present disclosure.

[0037] In the embodiment, the transformer 14 is a single-phase transformer, but the present disclosure is not limited to this. When the first bridge circuit 12 and the second bridge circuit 15 are three-phase bridge circuits, the transformer 14 may be a three-phase transformer.

[0038] The turns ratio between the first winding 14a and the second winding 14b is 1:1, for example, but the present disclosure is not limited to this.

[0039] One end of the first winding 14a is electrically connected to the other end of the reactor 13. The other end of the first winding 14a is electrically connected to the output terminal 12d.

[0040] The first bridge circuit 12 outputs a voltage Vin or a voltage −Vin between an output terminal 12c and an output terminal 12d.

[0041] For example, when the transistors Tr1 and Tr4 are controlled to be in the on state and the transistors Tr2 and Tr3 are controlled to be in the off state, the first bridge circuit 12 outputs the voltage Vin between the output terminals 12c and 12d.

[0042] Furthermore, for example, when the transistors Tr1 and Tr4 are controlled to be in the off state and the transistors Tr2 and Tr3 are controlled to be in the on state, the first bridge circuit 12 outputs a voltage −Vin between the output terminals 12c and 12d.

[0043] The second bridge circuit 15 is a single-phase full-bridge circuit including transistors Tr5 to Tr8.

[0044] In the embodiment, the second bridge circuit 15 is a single-phase full-bridge circuit, but the present disclosure is not limited to this. The second bridge circuit 15 may be a three-phase bridge circuit including three arms.

[0045] The source of transistor Tr5 is electrically connected to the drain of transistor Tr6. The drain of transistor Tr5 is electrically connected to the drain of transistor Tr7. The source of transistor Tr7 is electrically connected to the drain of transistor Tr8. The source of transistor Tr6 is electrically connected to the source of transistor Tr8.

[0046] Each of the transistors Tr5 to Tr8 corresponds to an example of a "switch element" in the present disclosure.

[0047] Each of the transistors Tr5 and Tr7 corresponds to an example of a "high-side switch element" in the present disclosure. Each of the transistors Tr6 and Tr8 corresponds to an example of a "low-side switch element" in the present disclosure.

[0048] The transistors Tr5 and Tr6 correspond to an example of an "arm" in the present disclosure. Similarly, the transistors Tr7 and Tr8 correspond to an example of an "arm" in the present disclosure.

[0049] The connection point between the source of transistor Tr5 and the drain of transistor Tr6 is one input terminal 15a of the second bridge circuit 15. The connection point between the source of transistor Tr7 and the drain of transistor Tr8 is the other input terminal 15b of the second bridge circuit 15.

[0050] The connection point between the drain of transistor Tr5 and the drain of transistor Tr7 is one output terminal 15c of the second bridge circuit 15. The connection point between the source of transistor Tr6 and the source of transistor Tr8 is the other output terminal 15d of the second bridge circuit 15.

[0051] Input terminal 15a is electrically connected to one end of second winding 14b, and input terminal 15b is electrically connected to the other end of second winding 14b.

[0052] The output terminal 15c is electrically connected to one end (high potential end) of the capacitor 16. The output terminal 15d is electrically connected to the other end (low potential end) of the capacitor 16.

[0053] The voltage of capacitor 16 is voltage Vout. One end (high potential end) of capacitor 16 is electrically connected to one end (high potential end) of load 4. The other end (low potential end) of capacitor 16 is electrically connected to the other end (low potential end) of load 4.

[0054] The second voltage sensor 17 detects the voltage Vout and outputs it to the control unit 18.

[0055] The control unit 18 controls the first bridge circuit 12 and the second bridge circuit 15.

[0056] For example, the control unit 18 controls the switching frequencies of the transistors Tr1 to Tr8 to be the same and the duty ratio to be 0.5.

[0057] The duty ratio is the ratio of the on-time (or off-time) of the switch element to one control cycle. In the present disclosure, the duty ratio is defined as the on-time of the high-side transistors Tr1 and Tr3 (the off-time of the low-side transistors Tr2 and Tr4) to one control cycle.

[0058] In the DAB, the phase difference between the input bridge circuit and the output bridge circuit is the command value for the output current. Therefore, the control unit 18 controls the phase difference between the first bridge circuit 12 and the second bridge circuit 15 to control the output current (power).

[0059] (Control of Comparative Example) In Patent Document 1, the duty ratio of the drive pulse (gate signal) is set to 0.5 (hereinafter referred to as the "standard value").

[0060] Fig. 2 is a diagram showing waveforms at various parts on the primary side of a power supply device of a comparative example. Fig. 2 is a diagram showing waveforms at various parts on the primary side of power supply device 1 when load 4 is short-circuited (voltage Vout is 0V) and the duty ratios of transistors Tr1 to Tr8 are standard values. Note that when load 4 is short-circuited, the results will not change regardless of the state of the gate signals of transistors Tr5 to Tr8 (no voltage is generated on the input terminal 15a and input terminal 15b sides), so illustration and description will be omitted.

[0061] Waveform 101 represents a drive pulse input to the gate of transistor Tr1. Waveform 102 represents a drive pulse input to the gate of transistor Tr2. Waveform 103 represents a drive pulse input to the gate of transistor Tr3. Waveform 104 represents a drive pulse input to the gate of transistor Tr4. Waveform 105 represents a voltage applied to reactor 13. Waveform 106 represents a current flowing through reactor 13.

[0062] In FIG. 2, the dead time is omitted.

[0063] The period from timing t0 to timing t2 is one control cycle. Since the duty ratios of transistors Tr1 to Tr8 are standard values, the period from timing t0 to timing t1 and the period from timing t1 to timing t2 are the same length.

[0064] At timing t0, a high-level drive pulse is input to the gate of transistor Tr1, as shown by waveform 101. A low-level drive pulse is input to the gate of transistor Tr2, as shown by waveform 102. A low-level drive pulse is input to the gate of transistor Tr3, as shown by waveform 103. A high-level drive pulse is input to the gate of transistor Tr4, as shown by waveform 104.

[0065] At this time, as shown by a waveform 105, a voltage Vin is applied to the reactor 13. Therefore, as shown by a waveform 106, the reactor current flowing through the reactor 13 increases linearly.

[0066] At timing t1, a low-level drive pulse is input to the gate of transistor Tr1, as shown by waveform 101. A high-level drive pulse is input to the gate of transistor Tr2, as shown by waveform 102. A high-level drive pulse is input to the gate of transistor Tr3, as shown by waveform 103. A low-level drive pulse is input to the gate of transistor Tr4, as shown by waveform 104.

[0067] At this time, as shown by a waveform 105, a voltage −Vin is applied to the reactor 13. Therefore, as shown by a waveform 106, the reactor current flowing through the reactor 13 decreases linearly.

[0068] In the comparative example, when the ratio of voltage Vout to voltage Vin is small (or when the voltage difference between voltage Vin and voltage Vout is large), voltage is applied to reactor 13 over the entire period, as shown by waveform 105. Therefore, in the comparative example, a large reactor current (circulating current) flows through reactor 13, as shown by waveform 106.

[0069] (Control of the embodiment) In the embodiment, the control unit 18 reduces or increases the duty ratio of the drive pulses applied to the primary side transistors Tr1 to Tr4 based on the ratio of the voltage Vout to the voltage Vin (hereinafter, sometimes referred to as the "input / output voltage ratio").

[0070] Note that making the duty ratio of the drive pulse smaller than the standard value is equivalent to making it larger than the standard value in terms of the period during which voltage is applied to reactor 13. For example, setting the duty ratio of the drive pulse to 0.9 is equivalent to setting the duty ratio of the drive pulse to 0.1, because the period during which voltage is applied to reactor 13 is the same.

[0071] FIG. 3 is a diagram illustrating functional blocks of the control unit of the power supply device according to the embodiment.

[0072] The control unit 18 includes a deviation calculation unit 21, a phase difference calculation unit 22, a duty ratio calculation unit 23, a signal output unit 24, a pulse generation unit 25, a primary side pulse drive unit 26, and a secondary side pulse drive unit 27.

[0073] The deviation calculation unit 21 calculates the deviation ε between the voltage command value Vcom and the voltage Vout by subtracting the voltage Vout from the voltage command value Vcom.

[0074] Based on the deviation ε, the phase difference calculation unit 22 calculates the phase difference φ between the first bridge circuit 12 on the primary side and the second bridge circuit 15 on the secondary side. As described above, in DAB, the voltage Vout and the output current Iout are controlled by the phase difference φ between the first bridge circuit 12 on the primary side and the second bridge circuit 15 on the secondary side.

[0075] The duty ratio calculation unit 23 calculates the duty ratio based on the voltage Vin and the voltage Vout, taking into account the phase difference φ.

[0076] 4 and 5 are diagrams showing an example of the duty ratio when the phase difference is 0° in the power supply device according to the embodiment.

[0077] 4, waveform 111 shows an example of the relationship between the input / output voltage ratio and the duty ratio when the duty ratio of the drive pulses input to primary-side transistors Tr1 to Tr4 is set smaller than the standard value, and waveform 112 shows an example of the relationship between the input / output voltage ratio and the duty ratio when the duty ratio of the drive pulses input to primary-side transistors Tr1 to Tr4 is set larger than the standard value.

[0078] As shown by waveforms 111 and 112, the duty ratio calculation section 23 may set a dead band 113 when the input / output voltage ratio is between 1.0 and 0.9.

[0079] For example, the duty ratio calculation unit 23 sets the duty ratio to 0.5 (standard value) when the input / output voltage ratio is between 1.0 and 0.9.

[0080] As shown by waveform 111, the duty ratio calculation unit 23 reduces the duty ratio as the input / output voltage ratio becomes smaller than 0.9.

[0081] As shown by the waveform 111, the duty ratio calculation section 23 linearly decreases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation section 23 monotonically decreases the duty ratio.

[0082] As shown by the waveform 112, the duty ratio calculation unit 23 increases the duty ratio as the input / output voltage ratio becomes smaller than 0.9.

[0083] As shown by the waveform 112, the duty ratio calculation section 23 linearly increases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation section 23 monotonically increases the duty ratio.

[0084] 5, waveform 116 shows an example of the relationship between the input / output voltage ratio and the duty ratio when the duty ratio of the drive pulses input to primary-side transistors Tr1 to Tr4 is set smaller than the standard value, and waveform 117 shows an example of the relationship between the input / output voltage ratio and the duty ratio when the duty ratio of the drive pulses input to primary-side transistors Tr1 to Tr4 is set larger than the standard value.

[0085] As shown by waveform 116, the duty ratio calculation unit 23 reduces the duty ratio as the input / output voltage ratio becomes smaller than 1.0.

[0086] As shown by the waveform 116, the duty ratio calculation section 23 linearly decreases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation section 23 monotonically decreases the duty ratio.

[0087] As shown by waveform 117, the duty ratio calculation unit 23 increases the duty ratio as the input / output voltage ratio becomes smaller than 1.0.

[0088] As shown by waveform 117, the duty ratio calculation section 23 linearly increases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation section 23 monotonically increases the duty ratio.

[0089] As shown by waveforms 116 and 117, the duty ratio calculation section 23 may eliminate the dead zone 113 (see FIG. 4).

[0090] Incidentally, when the phase difference φ is not 0°, it is required to output power to the load 4 side.

[0091] Therefore, the duty ratio calculation section 23 may add a value according to the phase difference φ to the waveform 111 or 116 to adjust the duty ratio in a direction approaching the standard value (see arrow 114 in FIG. 4 and arrow 118 in FIG. 5).

[0092] Furthermore, the duty ratio calculation section 23 may subtract a value according to the phase difference φ from the waveform 112 or 117 to adjust the duty ratio in a direction approaching the standard value (see arrow 115 in FIG. 4 and arrow 119 in FIG. 5).

[0093] 3, the signal output unit 24 outputs a first signal S1 and a second signal S2, each having a duty ratio calculated by the duty ratio calculation unit 23 and having a phase difference φ between them. The first signal S1 is a reference signal that forms the basis of drive pulses input to the gates of primary-side transistors Tr1 to Tr4. The second signal S2 is a reference signal that forms the basis of drive pulses input to the gates of secondary-side transistors Tr5 to Tr8.

[0094] The pulse generating unit 25 generates a first pulse group S3 including four pulses each having a waveform input to the gates of the primary-side transistors Tr1 to Tr4 based on the first signal S1. The pulse generating unit 25 generates a second pulse group S4 including four pulses each having a waveform input to the gates of the secondary-side transistors Tr5 to Tr8 based on the second signal S2.

[0095] The primary pulse driver 26 converts the voltage level of the first pulse group S3 to generate a first drive pulse group S5, and outputs the first drive pulse group S5 to the gates of the transistors Tr1 to Tr4.

[0096] The secondary pulse driver 27 outputs a second driving pulse group S6 obtained by converting the voltage level of the second pulse group S4 to the gates of the transistors Tr5 to Tr8.

[0097] Fig. 6 is a diagram showing waveforms at various parts on the primary side of the power supply device according to the embodiment. Fig. 6 is a diagram showing waveforms at various parts on the primary side of the power supply device when the load 4 is short-circuited (voltage Vout is 0V) and the duty ratio of transistors Tr1 to Tr8 is 0.9 (equivalent to 0.1). Note that when the load 4 is short-circuited, the results will not change regardless of the state of the gate signals of transistors Tr5 to Tr8 (no voltage is generated on the input terminal 15a and input terminal 15b sides), so illustration and description thereof will be omitted.

[0098] Waveform 121 represents a drive pulse input to the gate of transistor Tr1. Waveform 122 represents a drive pulse input to the gate of transistor Tr2. Waveform 123 represents a drive pulse input to the gate of transistor Tr3. Waveform 124 represents a drive pulse input to the gate of transistor Tr4. Waveform 125 represents a voltage applied to reactor 13. Waveform 126 represents a current flowing through reactor 13.

[0099] In FIG. 6, the dead time is omitted.

[0100] Timing t 10 From timing t 14 The period from this point onwards is one control cycle.

[0101] 6, the phases of waveforms 121 to 124 remain unchanged from the comparative example. However, the present disclosure is not limited to this. The phases of waveforms 121 to 124 may be changed.

[0102] Timing t 10 In this example, as shown by waveform 121, a high-level drive pulse is input to the gate of transistor Tr1. As shown by waveform 122, a low-level drive pulse is input to the gate of transistor Tr2. As shown by waveform 123, a high-level drive pulse is input to the gate of transistor Tr3. As shown by waveform 124, a low-level drive pulse is input to the gate of transistor Tr4.

[0103] At this time, as shown by waveform 125, no voltage is applied to reactor 13. Therefore, as shown by waveform 126, the reactor current flowing through reactor 13 neither increases nor decreases.

[0104] Timing t 11 In this example, as shown by waveform 121, a high-level drive pulse is input to the gate of transistor Tr1. As shown by waveform 122, a low-level drive pulse is input to the gate of transistor Tr2. As shown by waveform 123, a low-level drive pulse is input to the gate of transistor Tr3. As shown by waveform 124, a high-level drive pulse is input to the gate of transistor Tr4.

[0105] At this time, as shown by a waveform 125, a voltage Vin is applied to the reactor 13. Therefore, as shown by a waveform 126, the reactor current flowing through the reactor 13 increases linearly.

[0106] Timing t 12 In this example, as shown by waveform 121, a high-level drive pulse is input to the gate of transistor Tr1. As shown by waveform 122, a low-level drive pulse is input to the gate of transistor Tr2. As shown by waveform 123, a high-level drive pulse is input to the gate of transistor Tr3. As shown by waveform 124, a low-level drive pulse is input to the gate of transistor Tr4.

[0107] At this time, as shown by waveform 125, no voltage is applied to reactor 13. Therefore, as shown by waveform 126, the reactor current flowing through reactor 13 neither increases nor decreases.

[0108] Timing t 13In this example, as shown by waveform 121, a low-level drive pulse is input to the gate of transistor Tr1. As shown by waveform 122, a high-level drive pulse is input to the gate of transistor Tr2. As shown by waveform 123, a high-level drive pulse is input to the gate of transistor Tr3. As shown by waveform 124, a low-level drive pulse is input to the gate of transistor Tr4.

[0109] At this time, as shown by a waveform 125, a voltage −Vin is applied to the reactor 13. Therefore, as shown by a waveform 126, the reactor current flowing through the reactor 13 decreases linearly.

[0110] The power supply device 1 of the embodiment applies a voltage to the reactor 13 for only two-tenths of one cycle, as shown by waveform 125. That is, the power supply device 1 of the embodiment can reduce the period during which a voltage is applied to the reactor 13, compared to the comparative example (see waveform 106 in FIG. 2). Therefore, the power supply device 1 of the embodiment can reduce the reactor current flowing through the reactor 13, as shown by waveform 126, compared to the comparative example.

[0111] 7 is a diagram showing the relationship between the duty ratio and the effective value of the output AC voltage of the first bridge circuit in the embodiment. The effective value of the output AC voltage of the first bridge circuit 12 on the primary side is normalized by setting the value of the output AC voltage when the duty ratio is the standard value (0.5) to 1.

[0112] As shown by waveform 131, the effective value of the output AC voltage of the first bridge circuit 12 on the primary side decreases as the duty ratio increases or decreases from the standard value. In other words, the effective value of the voltage applied to the reactor 13 is suppressed as the duty ratio increases or decreases from the standard value. Therefore, the reactor current flowing through the reactor 13 is suppressed.

[0113] As described above, the power supply device 1 according to the embodiment can suppress the circulating current in the primary side circuit when the input / output voltage ratio is small.

[0114] As a result, the power supply device 1 according to the embodiment can suppress a significant increase in stress and loss in the primary side circuit.

[0115] Note that the control unit 18 may decrease or increase the duty ratio from the standard value based on the input / output voltage difference, which is the difference between the voltage Vin and the voltage Vout, instead of the input / output voltage ratio. In other words, the control unit 18 may decrease or increase the duty ratio from the standard value as the input / output voltage difference increases.

[0116] Furthermore, the present disclosure does not require changing the phases of the drive pulses input to transistors Tr1 to Tr4, and only the duty ratio needs to be changed. Therefore, the present disclosure is also applicable to a three-phase DAB in which the phase difference between the three arms of the first bridge circuit 12 and the three arms of the second bridge circuit 15 is fixed at 120°.

[0117] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0118] 1 Power supply 2 Power supply 3, 16 Capacitor 4. Load 11 First voltage sensor 12 First bridge circuit 13 Reactor 14 Transformer 15 Second bridge circuit 17 Second voltage sensor 18 Control Unit 21 Deviation calculation section 22 Phase difference calculation section 23 Duty ratio calculation section 24 Signal output section 25 Pulse generation unit 26 Primary side pulse drive unit 27 Secondary side pulse drive unit

Claims

1. a first bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, and converting a DC voltage into an AC voltage and outputting the AC voltage; a transformer including a first winding and a second winding, the AC voltage output from the first bridge circuit being input to the first winding and the AC voltage induced in the transformer being output from the second winding; a second bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, converting the AC voltage output from the second winding of the transformer into a DC voltage and outputting the DC voltage to a load; a control unit that outputs a plurality of first drive pulses to the switch elements in the first bridge circuit to cause the switch elements in the first bridge circuit to perform a switching operation, outputs a plurality of second drive pulses to the switch elements in the second bridge circuit to cause the switch elements in the second bridge circuit to perform a switching operation, and controls a phase difference between the plurality of first drive pulses and the plurality of second drive pulses to control a DC voltage output from the second bridge circuit; Equipped with The control unit performing control to make a duty ratio of the plurality of first drive pulses smaller or larger than a standard value based on a first voltage input to the first bridge circuit and a second voltage of the load; The standard value is 0.5, which is used when the input / output voltage ratio is within a predetermined range including 1; A power supply device comprising:

2. The control unit and performing control to make the duty ratio smaller or larger than the standard value based on a value of the ratio of the second voltage to the first voltage.

2. The power supply device according to claim 1 .

3. The control unit The smaller the value of the ratio, the smaller or larger the duty ratio is controlled to be than the standard value.

3. The power supply device according to claim 2, wherein:

4. The control unit When the value of the ratio is within a predetermined range including 1, control is performed to maintain the duty ratio at the standard value.

4. The power supply device according to claim 2 or 3.

5. The control unit performing control to adjust the duty ratio in accordance with the phase difference; 5. The power supply device according to claim 2, wherein the power supply device is a power supply having a first resistance and a second resistance.

6. each of the first bridge circuit and the second bridge circuit is a three-phase bridge circuit; the transformer is a three-phase transformer; The control unit a control is performed to fix the phase difference between three arms of the first bridge circuit and three arms of the second bridge circuit to 120°; 6. The power supply device according to claim 1, wherein the power supply device comprises:

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