Semiconductor substrate and manufacturing method thereof

Abstract

This semiconductor substrate (1) is provided with: an SiC single crystal substrate (10SB); a first graphene layer (11GR1) that is arranged on an Si surface of the SiC single crystal substrate 10SB; an SiC epitaxial growth layer (12RE) that is formed above the SiC single crystal substrate, with the first graphene layer being interposed therebetween; and a second graphene layer (11GR2) that is arranged on an Si surface of the SiC epitaxial growth layer. This semiconductor substrate is also provided with an SiC polycrystalline substrate (16P) that is provisionally bonded onto the SiC epitaxial growth layer, with the second graphene layer being interposed therebetween. The SiC single crystal substrate is able to be reused by being separated from the SiC epitaxial growth layer. This semiconductor substrate is also provided with an SiC polycrystalline growth layer (18PC) that is CVD grown on the C-plane of the SiC epitaxial growth layer; and the SiC epitaxial growth layer is transferred to the SiC polycrystalline growth layer. Consequently, the present invention provides a semiconductor substrate which is improved in terms of the productivity, reliability and mass productivity.

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor substrate and a manufacturing method thereof. [Background technology]

[0002] In recent years, silicon carbide (SiC) semiconductors have been attracting attention due to their wider bandgap energy and high electric field withstand voltage performance compared to Si and GaAs semiconductors, which allows them to achieve higher withstand voltages, larger currents, lower on-resistance, higher efficiency, lower power consumption, and faster switching.

[0003] Methods for forming SiC wafers include, for example, a method in which a SiC epitaxial growth layer is formed by chemical vapor deposition (CVD) on a SiC single crystal substrate formed by sublimation, and a method in which a SiC single crystal substrate is attached to a SiC CVD polycrystalline substrate by sublimation, and then a SiC epitaxial growth layer is formed on the SiC single crystal substrate by CVD.

[0004] Conventionally, SiC devices such as Schottky barrier diodes (SBDs), metal oxide semiconductor field effect transistors (MOSFETs), and insulated gate bipolar transistors (IGBTs) have been provided for power control applications. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6206786 [Patent Document 2] Japanese Patent Application Publication No. 2019-210161 [Patent Document 3] U.S. Patent No. 8,916,451 [Patent Document 4] International Publication No. 2017 / 044577 Summary of the Invention [Problem to be solved by the invention]

[0006] The SiC semiconductor substrates on which such SiC-based devices are formed have sometimes been fabricated by bonding a single-crystal SiC semiconductor substrate to a polycrystalline SiC semiconductor substrate in order to reduce manufacturing costs and provide desired physical properties.

[0007] In the technology for bonding a single-crystal SiC semiconductor substrate to a polycrystalline SiC semiconductor substrate, a high-quality single-crystal SiC semiconductor substrate must be bonded to the polycrystalline SiC semiconductor substrate without any defects in order to grow an epitaxial layer on the single-crystal SiC semiconductor substrate bonded to the polycrystalline SiC semiconductor substrate. However, the polishing process required to ensure the surface roughness required for bonding the single-crystal SiC semiconductor substrate to the polycrystalline SiC semiconductor substrate by room-temperature bonding or diffusion bonding is costly, and defects occurring at the bonding interface can reduce yields.

[0008] The use of the above technology presupposes that SiC devices are formed on the Si surface of SiC, and therefore, processes such as temporary bonding, peeling, transportation, and transfer are unavoidable, and each of these processes presents challenges. Furthermore, attaching a single crystal to a polycrystal poses issues such as the generation of voids at the interface and increased interface resistance. Furthermore, it is necessary to transfer a thin film several micrometers thick, which poses challenges in selecting a temporary bonding material, thin film transfer technology, and technology for bonding the thin film to the substrate.

[0009] The present embodiment provides a semiconductor substrate and a manufacturing method thereof that can improve productivity, reliability, and mass productivity. [Means for solving the problem]

[0010] According to one aspect of the present disclosure, there is provided a semiconductor substrate comprising: a SiC single crystal substrate; a first graphene layer disposed on a Si face of the SiC single crystal substrate; an epitaxial growth layer disposed above the SiC single crystal substrate with the first graphene layer interposed therebetween; and a second graphene layer disposed on a Si face of the epitaxial growth layer.

[0011] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor substrate, the method including: forming a first graphene layer on a Si-face of a base single crystal substrate; epitaxially growing a first layer formed of a single crystal SiC semiconductor on the first graphene layer; forming a second graphene layer on the Si-face of the first layer; forming a polycrystalline SiC semiconductor substrate on the second graphene layer; peeling the base single crystal substrate from the first graphene layer; removing the first graphene layer to expose a C-face of the first layer; forming a SiC polycrystalline growth layer on the C-face of the first layer; peeling off the polycrystalline SiC semiconductor substrate; and removing the second graphene layer. [Effects of the Invention]

[0012] According to this embodiment, it is possible to provide a semiconductor substrate and a manufacturing method thereof that can improve productivity, reliability, and mass productivity. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 2A is a first cross-sectional view of a semiconductor substrate according to an embodiment, and FIG. 2B is a second cross-sectional view of a semiconductor substrate according to an embodiment. [Figure 2] FIG. 3 is a third cross-sectional view of the semiconductor substrate according to the embodiment. [Figure 3] 6A is a fourth cross-sectional view of the semiconductor substrate according to the embodiment; FIG. 6B is a fifth cross-sectional view of the semiconductor substrate according to the embodiment; [Figure 4] 6A is a fifth cross-sectional view of the semiconductor substrate according to the embodiment; FIG. 6B is a sixth cross-sectional view of the semiconductor substrate according to the embodiment; [Figure 5]FIG. 7 is a seventh cross-sectional view of the semiconductor substrate according to the embodiment. [Figure 6] 10A is an eighth cross-sectional view of the semiconductor substrate according to the embodiment; FIG. 10B is a ninth cross-sectional view of the semiconductor substrate according to the embodiment; [Figure 7] FIG. 2A is a first cross-sectional view of a semiconductor substrate according to a comparative example, and FIG. 2B is a second cross-sectional view of the semiconductor substrate according to the comparative example. [Figure 8] 1A is a third cross-sectional view of a semiconductor substrate according to a comparative example; FIG. 1B is a fourth cross-sectional view of a semiconductor substrate according to a comparative example; and FIG. 1C is a fifth cross-sectional view of a semiconductor substrate according to a comparative example. [Figure 9] 1 is a schematic diagram of a manufacturing apparatus for a sintered SiC substrate applicable to a manufacturing method for a semiconductor substrate according to an embodiment. [Figure 10] 1 is a bird's-eye view of an example of a graphene layer that can be applied to a method for manufacturing a semiconductor substrate according to an embodiment, the graphene layer having a structure in which multiple layers are stacked. [Figure 11] 1 is a cross-sectional view of a Schottky barrier diode manufactured using a semiconductor substrate according to an embodiment. [Figure 12] 1 is a cross-sectional view of a trench gate MOSFET fabricated using a semiconductor substrate according to an embodiment. [Figure 13] 1 is a cross-sectional view of a planar gate MOSFET manufactured using a semiconductor substrate according to an embodiment. [Figure 14] (a) Plan view illustrating the crystal plane of SiC, (b) Side view illustrating the crystal plane of SiC. [Figure 15] 1 is a bird's-eye view of a semiconductor substrate (wafer) according to an embodiment. [Figure 16] (a) Bird's-eye view of a unit cell of a 4H—SiC crystal applicable to a SiC epitaxial substrate of a semiconductor substrate according to an embodiment, (b) a structural diagram of a two-layer portion of the 4H—SiC crystal, and (c) a structural diagram of a four-layer portion of the 4H—SiC crystal. [Figure 17] A structural diagram of the unit cell of the 4H—SiC crystal shown in Figure 16(a) viewed from directly above the (0001) plane. DETAILED DESCRIPTION OF THE INVENTION

[0014] Next, embodiments will be described with reference to the drawings. In the drawings described below, identical or similar parts are designated by identical or similar reference numerals. The drawings are schematic. Furthermore, the embodiments shown below are intended to exemplify devices and methods for embodying technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of parts. Various modifications can be made to the embodiments.

[0015] In the following description of the embodiments, [C] indicates the C-face of SiC, and [S] indicates the Si-face of SiC.

[0016] (semiconductor substrate) As shown in FIG. 1(b), the semiconductor substrate according to this embodiment includes a SiC single crystal substrate (SiC-SB) 10SB, a first graphene layer (GR1) 11GR1 disposed on the Si surface of the SiC single crystal substrate 10SB, an epitaxial growth layer (SiC-epi) 12RE disposed above the SiC single crystal substrate 10SB via the first graphene layer 11GR1, and a second graphene layer (GR2) 11GR2 formed on the Si surface of the epitaxial growth layer 12RE.

[0017] As shown in FIG. 2, the semiconductor substrate according to this embodiment further includes a SiC polycrystalline substrate (SiC-polySB) 16P temporarily bonded onto the epitaxially grown layer via a second graphene layer 11GR2.

[0018] The epitaxially grown layer 12RE is formed on the SiC single crystal substrate 10SB via the first graphene layer 11GR1 by remote epitaxial growth.

[0019] The SiC polycrystalline substrate 16P includes a sintered SiC substrate or a CVD substrate.

[0020] The SiC single crystal substrate 10SB can be reused by separating it from the epitaxial growth layer 12RE.

[0021] As shown in FIG. 4(b), the semiconductor substrate according to this embodiment further includes a SiC polycrystalline growth layer (SiC-polyCVD) 18PC grown by CVD on the C-face of the epitaxial growth layer 12RE, and the epitaxial growth layer 12RE is transferred to the SiC polycrystalline growth layer 18PC.

[0022] (Method of manufacturing semiconductor substrate) A method for manufacturing a semiconductor substrate according to this embodiment will be described.

[0023] (A) First, as shown in FIG. 1(a), a first graphene layer (GR1) 11GR1 is formed on the Si surface of a SiC single crystal substrate (SiCSB) 10SB, and then a SiC epitaxial growth layer (SiC-epi) 12RE is formed. Here, the SiC epitaxial growth layer 12RE is formed on the Si surface of the SiC single crystal substrate 10SB via the first graphene layer 11GR1 using a remote epitaxial growth technique. By using the remote epitaxial growth technique, the surface of the SiC epitaxial growth layer 12RE in contact with the first graphene layer 11GR1 becomes the C-plane, and the surface of the SiC epitaxial growth layer 12RE becomes the Si-plane. Furthermore, the first graphene layer 11GR1 may be formed as a single layer, or may be formed by stacking several layers, such as two or three layers. The first graphene layer 11GR1 can be formed on the Si surface of the SiC single crystal substrate 10SB by thermal decomposition, for example, by annealing the SiC single crystal substrate 10SB at approximately 1300°C to 1700°C. Alternatively, the first graphene layer 11GR1 may be formed by stacking on the SiC single crystal substrate 10SB by CVD. The SiC single crystal substrate 10SB is, for example, a 4H—SiC substrate, and has a thickness of, for example, approximately 300 μm to 600 μm.

[0024] (B) Next, as shown in FIG. 1(b), a second graphene layer (GR2) 11GR2 is formed on the Si surface of the SiC epitaxial growth layer 12RE. Similar to the first graphene layer 11GR1, the second graphene layer 11GR2 can be formed on the SiC epitaxial growth layer 12RE by thermal decomposition, for example, by annealing the SiC epitaxial growth layer 12RE at approximately 1300°C to 1700°C. Alternatively, the second graphene layer 11GR2 may be formed by stacking on the SiC epitaxial growth layer 12RE by CVD.

[0025] (C) Next, as shown in FIG. 2, an inexpensive SiC polycrystalline substrate (SiC-polySB) 16P is attached to the second graphene layer 11GR2. The second graphene layer 11GR2 and the SiC polycrystalline substrate (SiC-polySB) 16P can be easily bonded together if the average surface roughness Ra of the second graphene layer 11GR2 is 1 nm or less. If the surface of the second graphene layer 11GR2 is rough, pressure may be applied between the second graphene layer 11GR2 and the SiC polycrystalline substrate (SiC-polySB) 16P. The SiC polycrystalline substrate 16P may be a sintered SiC substrate. Alternatively, a CVD SiC substrate may be used as the SiC polycrystalline substrate 16P. The thickness of the SiC polycrystalline substrate 16P is, for example, approximately 300 μm to 600 μm. The SiC polycrystalline substrate 16P serves as a substrate layer for the device, and therefore is related to the on-resistance in a vertically structured device. Reducing the thickness of the SiC polycrystalline substrate 16P reduces the series resistance and the on-resistance. Therefore, the thickness of the SiC polycrystalline substrate 16P may be set to approximately 100 μm.

[0026] (D) Next, as shown in FIG. 3(a), the SiC single crystal substrate 10SB is peeled off. Specifically, the SiC polycrystalline substrate 16P / second graphene layer 11GR2 / SiC epitaxial growth layer 12RE / first graphene layer 11GR1 are fixed together and a force is applied in the shear direction, thereby peeling off the SiC single crystal substrate 10SB. Because the first graphene layer 11GR1 is bonded to the surface of the SiC single crystal substrate 10SB by van der Waals forces, it can be easily peeled off by applying a force in the shear direction. FIG. 3(b) is a cross-sectional view of the peeled SiC single crystal substrate 10SB. The surface of the peeled SiC single crystal substrate 10SB has an Si-face, and the back surface has a C-face. The SiC single crystal substrate 10SB can be easily peeled off from the first graphene layer 11GR1. The surface of the peeled SiC single crystal substrate 10SB has a clean Si-face. Therefore, the separated SiC single crystal substrate 10SB can be reused as the SiC single crystal substrate (SiCSB) 10SB shown in FIG. 1(a).

[0027] (E) Next, as shown in FIG. 4(a), the first graphene layer 11GR1 is removed by etching. In the etching process of the first graphene layer 11GR1, for example, a plasma asher using oxygen plasma can be used. Since the C-plane of the SiC epitaxial growth layer 12RE, from which the first graphene layer 11GR1 has been etched using oxygen plasma, is oxidized and uneven, wet etching using HF is performed. Here, the average surface roughness Ra of the C-plane of the SiC epitaxial growth layer 12RE is, for example, approximately 1 nm or less after the wet etching process.

[0028] (F) Next, as shown in FIG. 4(b), a SiC polycrystalline growth layer (SiC-polyCVD) 18PC is formed on the C-plane of the SiC epitaxial growth layer 12RE. The SiC polycrystalline growth layer 18PC can be formed, for example, by CVD technology. The SiC polycrystalline growth layer 18PC has a 3C (cubic) structure. Here, the thickness of the SiC polycrystalline growth layer 18PC is, for example, about 200 μm to about 500 μm, and the thickness of the SiC epitaxial growth layer 12RE is, for example, about 4 μm to about 100 μm. By forming the SiC polycrystalline growth layer 18PC on the C-plane of the SiC epitaxial growth layer 12RE, a substrate layer of the device wafer structure is formed. Since the C-plane of the SiC epitaxial growth layer 12RE becomes the backside of the device wafer structure, surface flatness is not required. Therefore, the SiC polycrystalline growth layer 18PC can be formed by a simple polishing process.

[0029] (G) As shown in Fig. 5, a heavily doped layer 12REN may be formed on the C-face of the SiC epitaxial growth layer 12RE. The heavily doped layer 12REN suppresses the expansion of a depletion layer in the SiC epitaxial growth layer 12RE and facilitates the formation of an ohmic contact with the SiC polycrystalline growth layer (CVD) 18PC formed on the C-face of the SiC epitaxial growth layer 12RE.

[0030] The heavily doped layer 12REN can be formed, for example, by using a high-dose ion implantation technique. For example, in the case of an n-type semiconductor, the heavily doped layer 12REN is formed by high-dose phosphorus (P) ion implantation. When formed by P ion implantation, the crystallinity of the P ion-implanted C-face of the SiC epitaxial growth layer 12RE is affected, but the Si-face that becomes the device surface has already been formed, and the crystallinity of the Si-face is preserved.

[0031] On the other hand, the heavily doped layer 12REN may be formed by forming a heavily nitrogen (N) doped epitaxial growth layer in the early stages of forming the SiC epitaxial growth layer (SiC-epi) 12RE shown in Fig. 1(a). Although the heavily nitrogen (N) doped epitaxial growth layer affects the crystallinity due to lattice constant mismatch, the process is simple because it is formed by autodoping in the early stages of epitaxial growth.

[0032] (H) Next, as shown in FIG. 6(a), in the structure shown in FIG. 4(b), the second graphene layer 11GR2 / SiC epitaxial growth layer 12RE / SiC polycrystalline growth layer 18PC side is fixed, and the SiC polycrystalline substrate 16P is peeled off. The SiC polycrystalline substrate 16P can be easily peeled off because it is bonded to the SiC epitaxial growth layer 12RE via the second graphene layer 11GR2. The second graphene layer 11GR2 can be easily peeled off by applying a force in the shear direction because it is bonded to the surface of the SiC polycrystalline substrate 16P by van der Waals forces.

[0033] (I) Next, as shown in FIG. 6(b), the second graphene layer 11GR2 formed on the S-plane of the SiC epitaxial growth layer 12RE is removed by etching. For example, oxygen plasma can also be used in the etching process of the second graphene layer 11GR2. Since the S-plane of the SiC epitaxial growth layer 12RE etched by oxygen plasma is oxidized and becomes uneven, wet etching using HF is performed. Here, the surface roughness Ra of the S-plane of the SiC epitaxial growth layer 12RE is, for example, approximately 1 nm or less after the wet etching process.

[0034] Through the above steps, the semiconductor substrate 1 according to this embodiment can be formed.

[0035] As shown in FIG. 6(b), the semiconductor substrate 1 according to this embodiment includes an SiC epitaxial growth layer 12RE and an SiC polycrystalline growth layer 18PC formed on the C-plane of the SiC epitaxial growth layer 12RE.

[0036] According to this embodiment, even if the remote epitaxial growth technology is applied to the formation of the Si surface required for SiC-based devices, the steps of peeling, transferring, and bonding can be eliminated.

[0037] According to the method for manufacturing a semiconductor substrate according to this embodiment, thin film transfer technology is not required, and temporary bonding materials for thin film transfer are not required, which allows for cost reduction.

[0038] According to this embodiment, since no substrate bonding technique is applied, it is possible to improve the interface reliability due to voidlessness.

[0039] The method for manufacturing a semiconductor substrate according to the present embodiment is effective in reusing the seed substrate, and can provide a semiconductor substrate with high substrate quality when reused, and a method for manufacturing the same.

[0040] According to the method for manufacturing a semiconductor substrate according to this embodiment, the number of times the seed substrate can be reused can be increased, and costs can be reduced.

[0041] (Comparative Example) A semiconductor substrate and a manufacturing method thereof according to a comparative example will be described.

[0042] (A) First, as shown in FIG. 7(a), a graphene layer (GR) 11GR is formed on the Si surface of a SiC single crystal substrate (SiCSB) 10SB.

[0043] (B) Next, as shown in FIG. 7(b), a SiC epitaxial growth layer (SiC-epi) 12 is formed on the graphene layer 11GR. Here, the SiC epitaxial growth layer 12 is formed on the Si surface of the SiC single crystal substrate 10SB via the graphene layer 11GR using a remote epitaxial growth technique. By using the remote epitaxial growth technique, the surface of the SiC epitaxial growth layer 12 in contact with the graphene layer 11GR becomes the C-plane, and the surface of the SiC epitaxial growth layer 12 becomes the Si-plane.

[0044] (C) Next, as shown in FIG. 8(a), a handling layer (HL) 13 is formed on the SiC epitaxial growth layer 12, and then the SiC epitaxial growth layer 12 is peeled off.

[0045] (D) The peeled substrate includes a SiC single crystal substrate 10SB and a graphene layer (GR) 11GR disposed on the SiC single crystal substrate 10SB, as shown in Fig. 8(b). Therefore, the peeled substrate can be reused as an initial substrate, as shown in Fig. 7(a).

[0046] (E) Next, the SiC epitaxial growth layer 12 and the handling layer (HL) 13 are transported, and as shown in FIG. 8(c), the handling layer (HL) is transferred to an inexpensive host wafer (HW) 15. Specifically, the host wafer (HW) 15 is attached to the C-face of the SiC epitaxial growth layer 12 shown in FIG. 8(a), and then the handling layer (HL) 13 is peeled off from the SiC epitaxial growth layer 12. As a result, the semiconductor substrate 1A according to the comparative example includes the host wafer 15 and the SiC epitaxial growth layer 12 disposed on the host wafer (HW) 15. The surface of the SiC epitaxial growth layer 12 that contacts the host wafer (HW) 15 is the C-face, and the surface of the SiC epitaxial growth layer 12 is the Si-face.

[0047] In the semiconductor substrate manufacturing method according to the comparative example, the SiC epitaxial growth layer 12RE must be handled through processes such as temporary bonding, peeling, transporting, and transferring, which poses problems in productivity, reliability, and mass production. In particular, since SiC devices are generally formed on the Si surface, these processes cannot be avoided.

[0048] On the other hand, in the method for manufacturing a semiconductor substrate according to the present embodiment, after forming the second graphene layer 11GR2 on the Si face of the SiC epitaxial growth layer 12RE, a temporary SiC polycrystalline substrate 16P is formed, and then the SiC single crystal substrate 10SB is peeled off to make the SiC single crystal substrate 10SB reusable. Also, a SiC polycrystalline growth layer 18PC is formed on the C face of the SiC epitaxial growth layer 12RE, and the epitaxial growth layer 12RE is transferred to the SiC polycrystalline growth layer 18PC.

[0049] (SiC sintered body manufacturing equipment) In the method for manufacturing a semiconductor substrate according to the embodiment, the SiC polycrystalline substrate 16P can be formed of a sintered SiC substrate.

[0050] A manufacturing apparatus 500 for a sintered SiC substrate applicable to the manufacturing method for a semiconductor substrate according to the embodiment is shown schematically in Fig. 9. An interior 500A of the manufacturing apparatus 500 is a vacuum atmosphere of about several Pa or an Ar / N2 gas atmosphere.

[0051] The manufacturing apparatus 500 employs a solid compression sintering method using hot press sintering (HP). A graphite die 900, a sintering mold made of graphite and filled with powder or solid SiC polycrystalline material, is heated while being pressurized. A thermocouple or radiation thermometer 920 is housed in the graphite die 900.

[0052] The graphite die 900 is connected to the pressure shafts 600A and 600B via graphite bunches 800A and 800B and graphite spacers 700A and 700B. The SiC polycrystalline material is pressurized and heated by applying pressure between the pressure shafts 600A and 600B. The heating temperature is, for example, up to about 1500°C, and the pressing pressure P is, for example, up to about 280 MPa. In addition to hot press sintering (HP), spark plasma sintering (SPS), for example, may also be applied.

[0053] The manufacturing apparatus 500 limits the heating range, allowing for more rapid heating and cooling (several minutes to several hours) than atmospheric heating in an electric furnace or the like. By applying pressure and rapidly heating, it is possible to produce dense SiC sintered bodies with suppressed grain growth. Furthermore, the method can be applied not only to sintering but also to sinter-bonding, porous body sintering, and other processes.

[0054] The graphene layers 11GR1, 11GR2, etc. applicable to the method for manufacturing a semiconductor substrate 1 according to the embodiment may have a single layer structure or a multi-layer laminated structure. A bird's-eye view of an example of a graphene layer applicable to the method for manufacturing a semiconductor substrate according to the embodiment and having a multi-layer laminated structure is shown in FIG.

[0055] The graphene layer 11GF having a multi-layered structure has a layered structure of graphite sheets GS1·GS2·GS3·...·GSn, as shown in Fig. 10. The graphite sheets GS1·GS2·GS3·...·GSn on each side, which are made up of n layers, have many hexagonal carbon (C) covalent bonds within a single layered crystal structure, and the graphite sheets GS1·GS2·GS3·...·GSn on each side are bonded by van der Waals forces.

[0056] The semiconductor substrate 1 according to the embodiment can be used, for example, to manufacture various SiC semiconductor devices. Examples of such devices will be described below, including a SiC-SBD, a SiC trench gate (T: Trench) MOSFET, and a SiC planar gate MOSFET.

[0057] (SiC-SBD) As shown in FIG. 11 , a semiconductor device fabricated using a semiconductor substrate according to the embodiment includes a SiC-SBD 21. The semiconductor substrate 1 includes a SiC polycrystalline growth layer (CVD) 18PC and a SiC epitaxial growth layer 12RE. A heavily doped layer 12REN may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12RE. The heavily doped layer 12REN suppresses the expansion of a depletion layer in the SiC epitaxial growth layer 12RE and facilitates the formation of an ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-face of the SiC epitaxial growth layer 12RE. The SiC epitaxial growth layer 12RE serves as a drift layer, the heavily doped layer 12REN serves as a buffer layer, and the SiC polycrystalline growth layer 18PC serves as a substrate layer.

[0058] The SiC polycrystalline growth layer 18PC is + type (impurity density is, for example, about 1 × 10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 12RE is doped with n - type (impurity density is, for example, about 5 × 10 14 cm -3 ~Approx. 5×10 16 cm -3 The heavily doped layer 12REN is doped to a higher concentration than the SiC epitaxial growth layer 12RE.

[0059] The SiC epitaxial growth layer 12RE may have any one of the crystal structures of 4H—SiC, 6H—SiC, and 2H—SiC.

[0060] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0061] As the p-type doping impurity, for example, B (boron), Al (aluminum), TMA, etc. can be used.

[0062] The back surface ((000-1)C surface) of the SiC polycrystalline growth layer 18PC is provided with a cathode electrode 22 so as to cover the entire area thereof.

[0063] In addition, the surface 100 (e.g., the (0001) Si surface) of the SiC epitaxial growth layer 12 has a contact hole 24 that exposes a portion of the SiC epitaxial growth layer 12RE as an active region 23, and a field insulating film 26 is formed in a field region 25 surrounding the active region 23.

[0064] The field insulating film 26 is made of SiO2 (silicon oxide), but may be made of other insulators such as silicon nitride (SiN). An anode electrode 27 is formed on the field insulating film 26 and is connected to an anode terminal A.

[0065] A p-type JTE (Junction Termination Extension) structure 28 is formed in the vicinity of the surface 100 (surface layer portion) of the SiC epitaxial growth layer 12 so as to be in contact with the anode electrode 27. The JTE structure 28 is formed along the contour of the contact hole 24 in the field insulating film 26 so as to straddle the inside and outside of the contact hole 24.

[0066] (SiC-TMOSFET) As shown in FIG. 12, a trench-gate MOSFET 31, a semiconductor device fabricated using the semiconductor substrate according to the embodiment, includes a semiconductor substrate 1 including a SiC polycrystalline growth layer 18PC and a SiC epitaxial growth layer 12RE. A heavily doped layer 12REN may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12RE. The heavily doped layer 12REN suppresses the expansion of a depletion layer in the SiC epitaxial growth layer 12RE and facilitates the formation of an ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-face of the SiC epitaxial growth layer 12RE. The SiC epitaxial growth layer 12RE serves as a drift layer, the heavily doped layer 12REN serves as a buffer layer, and the SiC polycrystalline growth layer 18PC serves as a substrate layer.

[0067] The SiC polycrystalline growth layer 18PC is + type (impurity density is, for example, about 1 × 10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 12RE is doped with n - type (impurity density is, for example, about 5 × 10 14 cm -3 ~Approx. 5×10 16 cm -3 The heavily doped layer 12REN is doped to a higher concentration than the SiC epitaxial growth layer 12RE.

[0068] The SiC epitaxial growth layer 12RE may have any one of the crystal structures of 4H—SiC, 6H—SiC, and 2H—SiC.

[0069] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0070] As the p-type doping impurity, for example, B (boron), Al (aluminum), TMA, etc. can be used.

[0071] The back surface ((000-1)C surface) of the SiC polycrystalline growth layer 18PC is provided with a drain electrode 32 so as to cover the entire area thereof.

[0072] In the vicinity (surface layer portion) of the surface 100 ((0001) Si surface) of the SiC epitaxial growth layer 12RE, a p-type impurity (impurity density is, for example, about 1×10 16 cm -3 ~Approx. 1×10 19 cm -3 In the SiC epitaxial growth layer 12RE, the portion on the SiC polycrystalline growth layer 18PC side with respect to the body region 33 is maintained in the state of the SiC epitaxial growth layer RE, and n - The drain region 34 (12RE) is of the same type.

[0073] A gate trench 35 is formed in the SiC epitaxial growth layer 12RE. The gate trench 35 penetrates from the surface 100 of the SiC epitaxial growth layer 12RE through the body region 33, and its deepest portion reaches the drain region 34 (12RE).

[0074] A gate insulating film 36 is formed on the inner surface of the gate trench 35 and on a surface 100 of the SiC epitaxial growth layer 12RE so as to cover the entire inner surface of the gate trench 35. The inside of the gate insulating film 36 is filled with, for example, polysilicon, thereby embedding a gate electrode 37 in the gate trench 35. A gate terminal G is connected to the gate electrode 37.

[0075] The surface layer of the body region 33 is provided with n-type GaN films that form part of the side surfaces of the gate trenches 35. + A source region 38 is formed.

[0076] The SiC epitaxial growth layer 12 also has p-type junctions extending from its surface 100 through the source region 38 and connected to the body region 33. + type (impurity density is, for example, about 1 × 10 18 cm -3~Approx. 1×10 21 cm -3 ) a body contact region 39 is formed.

[0077] An interlayer insulating film 40 made of SiO2 is formed on the SiC epitaxial growth layer 12RE. A source electrode 42 is connected to the source region 38 and the body contact region 39 via a contact hole 41 formed in the interlayer insulating film 40. A source terminal S is connected to the source electrode 42.

[0078] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 37 while a predetermined potential difference is generated between the source electrode 42 and the drain electrode 32 (between the source and drain), a channel can be formed in the body region 33 near the interface with the gate insulating film 36 due to the electric field from the gate electrode 37. This allows a current to flow between the source electrode 42 and the drain electrode 32, turning the SiC-TMOSFET 31 on.

[0079] (SiC planar gate MOSFET) As shown in FIG. 13, a planar-gate MOSFET 51 is a semiconductor device fabricated using the semiconductor substrate 1 according to the embodiment. The semiconductor substrate 1 includes a SiC polycrystalline growth layer 18PC and a SiC epitaxial growth layer 12RE. A heavily doped layer 12REN may be interposed between the SiC polycrystalline growth layer 18PC and the SiC epitaxial growth layer 12RE. The heavily doped layer 12REN suppresses the expansion of a depletion layer in the SiC epitaxial growth layer 12RE and facilitates the formation of an ohmic contact with the SiC polycrystalline growth layer 18PC formed on the C-face of the SiC epitaxial growth layer 12RE. The SiC epitaxial growth layer 12RE serves as a drift layer, the heavily doped layer 12REN serves as a buffer layer, and the SiC polycrystalline growth layer 18PC serves as a substrate layer.

[0080] The SiC polycrystalline growth layer 18PC is + type (impurity density is, for example, about 1 × 1018 cm -3 ~Approx. 1×10 21 cm -3 ), and the SiC epitaxial growth layer 12 is doped with n - type (impurity density is, for example, about 5 × 10 14 cm -3 ~Approx. 5×10 16 cm -3 ) is doped.

[0081] The SiC epitaxial growth layer 12 may have any of the crystal structures of 4H—SiC, 6H—SiC, and 2H—SiC.

[0082] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0083] As the p-type doping impurity, for example, B (boron), Al (aluminum), TMA, etc. can be used.

[0084] A drain electrode 52 is formed on the back surface ((000-1) C surface) of the SiC single crystal substrate 10SB so as to cover the entire area, and a drain terminal D is connected to the drain electrode 52.

[0085] In the vicinity (surface layer portion) of the surface 100 ((0001) Si surface) of the SiC epitaxial growth layer 12RE, a p-type impurity (impurity density is, for example, about 1×10 16 cm -3 ~Approx. 1×10 19 cm -3 The body region 53 of the SiC epitaxial growth layer 12RE is formed in a well shape. The portion of the SiC epitaxial growth layer 12RE facing the SiC single crystal substrate 10SB relative to the body region 53 is maintained in the state after epitaxial growth, i.e., n - The drain region 54 (12RE) is of the same type.

[0086] The surface layer of the body region 53 is + A source region 55 is formed around the periphery of the body region 53 and spaced apart from the periphery.

[0087] Inside the source region 55, p + type (impurity density is, for example, about 1 × 10 18 cm -3 ~Approx. 1×10 21 cm -3 ) is formed in the body contact region 56. The body contact region 56 penetrates the source region 55 in the depth direction and is connected to the body region 53.

[0088] A gate insulating film 57 is formed on the surface 100 of the SiC epitaxial growth layer 12RE. The gate insulating film 57 covers the portion of the body region 53 surrounding the source region 55 (the peripheral portion of the body region 53) and the outer periphery of the source region 55.

[0089] A gate electrode 58 made of, for example, polysilicon is formed on the gate insulating film 57. The gate electrode 58 faces the peripheral edge of the body region 53 across the gate insulating film 57. A gate terminal G is connected to the gate electrode 58.

[0090] An interlayer insulating film 59 made of SiO2 is formed on the SiC epitaxial growth layer 12RE. A source electrode 61 is connected to the source region 55 and the body contact region 56 via a contact hole 60 formed in the interlayer insulating film 59. A source terminal S is connected to the source electrode 61.

[0091] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 58 while generating a predetermined potential difference between the source electrode 61 and the drain electrode 52 (between the source and drain), a channel can be formed in the body region 53 near the interface with the gate insulating film 57 due to the electric field from the gate electrode 58. This allows a current to flow between the source electrode 61 and the drain electrode 52, turning the planar gate MOSFET 51 on.

[0092] Although the present embodiment has been described above, it is possible to carry out the present invention in other forms.

[0093] Furthermore, for example, although not shown, a MOS capacitor can also be manufactured using the semiconductor substrate 1 according to the embodiment. In the case of a MOS capacitor, the yield and reliability can be improved.

[0094] Although not shown, the semiconductor substrate 1 according to the embodiment can also be used to manufacture a bipolar transistor. The semiconductor substrate 1 according to the embodiment can also be used to manufacture SiC-pn diodes, SiCIGBTs, SiC complementary MOSFETs, etc. The semiconductor substrate 1 according to the present embodiment can also be applied to other types of devices, such as LEDs (light emitting diodes) and semiconductor optical amplifiers (SOAs).

[0095] (crystal face) Figure 14 is a diagram illustrating the crystal planes of SiC. The plan view of Figure 14(a) shows a Si surface 211 of a SiC wafer 200 on which a primary orientation flat 201 and a secondary orientation flat 202 are formed. In the side view of Figure 14(b) seen from the [-1100] orientation, the Si surface 211 with a

[0001] orientation is formed on the top surface, and the C surface 212 with a [000-1] orientation is formed on the bottom surface.

[0096] As shown in FIG. 15, a schematic bird's-eye view of a semiconductor substrate (wafer) 1 according to an embodiment of the present invention is as follows: The semiconductor device includes a SiC polycrystalline growth layer 18PC and a SiC epitaxial growth layer 12RE.

[0097] The thickness of the SiC polycrystalline growth layer 18PC is, for example, about 200 μm to about 500 μm, and the thickness of the SiC epitaxial growth layer 12RE is, for example, about 4 μm to about 100 μm.

[0098] (Example of crystal structure) A schematic bird's-eye view of the unit cell of a 4H—SiC crystal applicable to the SiC epitaxial growth layer 12RE is shown in FIG. 16(a), a schematic configuration of a two-layer portion of the 4H—SiC crystal is shown in FIG. 16(b), and a schematic configuration of a four-layer portion of the 4H—SiC crystal is shown in FIG. 16(c).

[0099] Moreover, the schematic configuration of the unit cell of the 4H—SiC crystal structure shown in FIG. 16(a) viewed from directly above the (0001) plane is shown in FIG.

[0100] As shown in Figures 16(a) to 16(c), the crystal structure of 4H-SiC can be approximated by a hexagonal system, with four C atoms bonded to one Si atom. The four C atoms are located at the four vertices of a regular tetrahedron with the Si atom at the center. Of these four C atoms, one Si atom is located on the

[0001] axis side relative to the C atom, and the other three C atoms are located on the [000-1] axis side relative to the Si atom. In Figure 16(a), the off-angle θ is, for example, approximately 4 degrees or less.

[0101] The

[0001] and [000-1] axes are aligned along the axial direction of the hexagonal prism, and the plane normal to the

[0001] axis (top surface of the hexagonal prism) is the (0001) plane (Si plane). On the other hand, the plane normal to the [000-1] axis (bottom surface of the hexagonal prism) is the (000-1) plane (C plane).

[0102] Furthermore, the directions perpendicular to the

[0001] axis and passing through non-adjacent vertices of the hexagonal prism when viewed from directly above the (0001) plane are the a1 axis [2-1-10], a2 axis [-12-10], and a3 axis [-1-120], respectively.

[0103] As shown in Figure 17, the direction passing through the vertex between the a1 axis and the a2 axis is the [11-20] axis, the direction passing through the vertex between the a2 axis and the a3 axis is the [-2110] axis, and the direction passing through the vertex between the a3 axis and the a1 axis is the [1-210] axis.

[0104] Between each of the six axes passing through each vertex of the hexagonal prism, the axes that are inclined at an angle of 30° to the axes on both sides and that are normal to each side of the hexagonal prism are, in clockwise order from the a1 axis and the [11-20] axis, the [10-10] axis, the [1-100] axis, the [0-110] axis, the [-1010] axis, the [-1100] axis, and the [01-10] axis. Each face (side face of the hexagonal prism) having these axes as its normal is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

[0105] The SiC epitaxial growth layer 12RE may include at least one or more types selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0106] Furthermore, the SiC single crystal substrate 10SB and the SiC epitaxial growth layer 12RE may be made of any one of 4H—SiC, 6H—SiC, and 2H—SiC materials.

[0107] Furthermore, the SiC single crystal substrate 10SB and the SiC epitaxial growth layer 12RE may contain at least one material selected from the group consisting of GaN, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite, other than SiC.

[0108] The semiconductor device including the semiconductor substrate according to the embodiment may include any of GaN-based, AlN-based, and gallium oxide-based IGBTs, diodes, MOSFETs, and thyristors other than SiC-based.

[0109] A semiconductor device including a semiconductor substrate according to an embodiment may have any of the following configurations: a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

[0110] According to the semiconductor substrate according to the embodiment, for example, a low-cost SiC polycrystalline growth layer can be used as the substrate material instead of a high-cost SiC single crystal substrate.

[0111] [Other embodiments] Although several embodiments have been described above, the descriptions and drawings forming part of the disclosure are illustrative and should not be understood as limiting. From this disclosure, various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art.

[0112] As such, this embodiment includes various embodiments not described here. [Industrial Applicability]

[0113] The semiconductor substrate of the present embodiment and a semiconductor device including this semiconductor substrate can be used in various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules (SiC, GaN, AlN, gallium oxide), and can be used in a wide range of application fields such as power modules for inverter circuits that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert power generated by solar cells, wind power generators, and other power generation devices (especially private power generation devices) into power from a commercial power source. [Explanation of symbols]

[0114] 1...Semiconductor substrate 10SB...SiC single crystal substrate 11GR1, 11GR2, 11GF...graphene layers 12RE...SiC epitaxial growth layer (first layer) 12REN...Highly doped layer 16P…SiC polycrystalline substrate 18PC…SiC polycrystalline growth layer (CVD) (2nd layer) 21...Semiconductor device (SiC-SBD) 31...Semiconductor device (SiC-TMOSFET) 51...Semiconductor device (SiC-MOSFET) 200...SiC wafer 201...1st Orientation Flat 202...Secondary Orientation Flat 211, [S]...Si surface 212, [C]…C side 500...Manufacturing equipment GS1, GS2, GS3, ..., GSn... graphite sheets S: Source terminal D: Drain terminal G...Gate terminal A...Anode terminal K: Cathode terminal

Claims

1. a SiC single crystal substrate; a first graphene layer disposed on the Si face of the SiC single crystal substrate; an epitaxially grown layer disposed above the SiC single crystal substrate via the first graphene layer; a second graphene layer disposed on the Si face of the epitaxially grown layer; A semiconductor substrate comprising:

2. The semiconductor wafer of claim 1 , further comprising a SiC polycrystalline substrate temporarily bonded onto the epitaxially grown layer via the second graphene layer.

3. The semiconductor substrate according to claim 1 , wherein the first graphene layer has a single-layer structure or a multi-layer stacked structure of graphene.

4. The semiconductor substrate of claim 2 , wherein the SiC polycrystalline substrate comprises a sintered SiC substrate or a CVD substrate.

5. 5. The semiconductor substrate according to claim 1, wherein the SiC single crystal substrate is reusable by being peeled off from the epitaxial growth layer.

6. a SiC polycrystalline growth layer grown by CVD on a C-plane of the epitaxial growth layer; 6. The semiconductor substrate according to claim 1, wherein the epitaxial growth layer is transferred to the SiC polycrystalline growth layer.

7. 7. The semiconductor substrate according to claim 1, wherein the SiC single crystal substrate has a crystal structure of any one of 4H—SiC, 6H—SiC, and 2H—SiC.

8. The semiconductor substrate according to claim 6 , wherein the epitaxial growth layer has a layer having a higher impurity concentration than the epitaxial growth layer on a C-plane that is in contact with the SiC polycrystalline growth layer.

9. forming a first graphene layer on the Si-face of a base single crystal substrate; epitaxially growing a first layer formed of a single-crystal SiC semiconductor on the first graphene layer; forming a second graphene layer on a Si-face of the first layer; forming a polycrystalline SiC semiconductor substrate via the second graphene layer; delaminating the underlying single crystal substrate from the first graphene layer; removing the first graphene layer to expose a C-plane of the first layer; forming a second layer on the C-plane of the first layer by CVD growth; peeling off the polycrystalline SiC semiconductor substrate; removing the second graphene layer; A method for manufacturing a semiconductor substrate, comprising:

10. 10. The method of claim 9, wherein epitaxially growing the first layer comprises growing the first layer on the underlying single crystal substrate by remote epitaxy.

11. 11. The method for manufacturing a semiconductor substrate according to claim 9, wherein the surface of the first layer is a Si-face of 4H—SiC with a [0001] orientation, and the C-face of the first layer is a face of 4H—SiC with a [000-1] orientation.

12. The step of growing the second layer by CVD includes growing the second layer formed of a polycrystalline SiC semiconductor. The method for manufacturing a semiconductor substrate according to any one of claims 9 to 11, comprising the step of forming a semiconductor substrate.

13. 13. The method for manufacturing a semiconductor substrate according to claim 9, further comprising, after the step of exposing the C-face of the first layer, forming a layer having a higher impurity concentration than the first layer on the C-face of the first layer.

14. 13. The method for manufacturing a semiconductor substrate according to claim 9, wherein the step of epitaxially growing a first layer formed of a single-crystal SiC semiconductor via the first graphene layer includes the step of forming a layer having a higher impurity concentration than the first layer in an initial stage of epitaxial growth.

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