System and method for handling floating-point hardware exceptions

Abstract

To provide a method that includes receiving input data in an FP arithmetic unit that performs floating point (FP) arithmetic operations on the input data.SOLUTION: A method for efficiently processing FP hardware exceptions includes a step of receiving input data; and a step of determining whether the received input data generates a FP hardware exception in response to an FP arithmetic operation on the input data, The step of determining is performed prior to performing the FP arithmetic operation. The method also includes a step of converting a value of the received input data to a modified value in response to determining that the received input data generates the FP hardware exception. Conversion eliminates generation of the FP hardware exception responsive to the FP arithmetic operation on the input data.SELECTED DRAWING: Figure 4

Description

Related Applications

[0001] This application is a U.S. non-provisional patent application claiming the benefit of and priority to U.S. Provisional Patent Application No. 62 / 950,626, filed December 19, 2019, which is incorporated herein by reference in its entirety. [Background technology]

[0002] Machine learning (ML) systems are typically computationally intensive and typically perform a large number of floating-point (FP) operations. FP arithmetic operators for FP operations typically conform to the IEEE-754 standard. FP hardware exceptions are generated when the input to and / or output from an FP arithmetic operator is one of positive infinity, negative infinity, signaling NaN (SNAN), etc. A large number of resources are typically required to handle the large number of FP hardware exceptions generated from the large number of FP operations in an ML system. Furthermore, additional resources are required to handle situations where the input to or output from an FP arithmetic operator is a denormalized number, or when the input is a quiet NaN (QNAN), SNAN, infinity, etc. A denormalized number refers to a non-zero number in floating-point arithmetic whose magnitude is less than the minimum normalized number.

[0003] Currently, additional data paths are often required for each FP arithmetic operator to handle input or output values ​​involving denormalized numbers, QNANs, SNANs, infinity, etc. These additional data paths result in a larger footprint, higher power consumption, and increased complexity of the ML system.

[0004] The foregoing examples of the related art and limitations associated therewith are intended to be illustrative, not exhaustive. Other limitations of the related art will become apparent upon reading the specification and studying the drawings. [Brief explanation of the drawings]

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are drawn not to scale. In fact, dimensions of various features may be arbitrarily increased or decreased for clarity of illustration.

[0006] [Figure 1] 1 illustrates an illustrative example of an architecture configured to efficiently handle FP hardware exceptions, according to an aspect of the present embodiments.

[0007] [Figure 2] 1 illustrates an illustrative example of a programmable architecture configured to efficiently handle FP hardware exceptions, according to an aspect of the present embodiments.

[0008] [Figure 3] 1 illustrates an illustrative example of an architecture configured to efficiently handle FP hardware exceptions and their tracking, according to an aspect of the present embodiment.

[0009] [Figure 4] 1 illustrates an illustrative example of a method for efficiently handling FP hardware exceptions according to an aspect of the present embodiment.

[0010] [Figure 5] 10 illustrates an illustrative example of another method for efficiently handling FP hardware exceptions according to an aspect of the present embodiment.

[0011] [Figure 6] 1 shows an illustrative example of a block diagram depicting an example of a suitable computer system for efficient handling of FP hardware exceptions, in accordance with one aspect of the present embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the present subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and / or structures described.

[0013] Before various embodiments are described in more detail, it should be understood that the embodiments are not limiting, as the elements of such embodiments may vary. It should also be understood that the specific embodiments described and / or illustrated herein have elements that can be easily separated from the specific embodiment and, optionally, combined with any of several other embodiments or substituted for elements in any of several other embodiments described herein. It should also be understood that the terminology used herein is for the purpose of describing certain concepts and is not intended to be limiting. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood in the art to which the embodiments belong.

[0014] According to some embodiments, input data to FP arithmetic operators of an ML system is modified to avoid generating one or more FP hardware exceptions. For non-limiting examples, the value of the input data (i.e., operand) for an FP arithmetic operator is replaced with the system's maximum or minimum supported number when the input data is positive infinity or negative infinity, respectively. Furthermore, when the input data for an FP arithmetic operator is a SNAN, the input data may be replaced with zero. As such, the input data when modified will not generate an FP hardware exception resulting from its original value, e.g., positive infinity, negative infinity, SNAN, etc. Furthermore, the input data may be manipulated to handle other situations, such as denormalized numbers, QNAN inputs, which do not cause FP hardware exceptions but may still require an additional data path for each FP arithmetic operator to handle the situation. In some non-limiting examples, input data inputs that are denormalized numbers or QNANs may be replaced with zeros. Thus, eliminating the need for an additional data path for each FP arithmetic operator to handle FP hardware exceptions or to handle denormalized or QNAN inputs.

[0015] In some embodiments, the outputs of FP arithmetic operators, such as addition, subtraction, sum of addition, multiplication, negation, maximum, minimum, sum of maximum, sum of minimum, division, FPx to FPy (x>y), FPx to FPy (x<y), FP to integer (Int), etc., are similarly monitored and replaced to avoid additional data paths for each FP arithmetic operator. For non-limiting examples, even when the input data to the FP arithmetic operator does not cause an FP hardware exception or special situation handling, the output may still require special processing. As an illustration, although the two input operands are each within the supported number range, when added, they may become larger than the maximum supported number, thereby generating infinity and requiring special processing or generating an FP hardware exception. Therefore, when the FP operator results in positive infinity, the output of the FP operator can be replaced with the maximum supported number. Similarly, when the FP operator results in negative infinity, the output of the FP operator can be replaced with the minimum supported number.

[0016] It will be appreciated that in some non-limiting examples, the number of FP hardware exceptions generated is reduced. In non-limiting examples, when the output is a denormalized number, the output of the FP operator can be replaced with zero. It will be understood that the description of the operations related to addition is for illustrative purposes only and should not be construed as limiting the scope of the embodiments. For example, similar processing may occur for other operations such as subtraction, sum of addition, multiplication, negation, maximum, minimum, sum of maximum, sum of minimum, division, FPx to FPy (x>y), FPx to FPy (x<y), FP to Int, etc.

[0017] Thus, the need for additional data paths for each FP arithmetic operator is eliminated to handle FP hardware exceptions or to handle denormalized, infinite, SNAN or QNAN inputs. Therefore, the hardware footprint, power consumption, and complexity are reduced.

[0018] FIG. 1 shows an exemplary example of an architecture configured to efficiently process FP hardware exceptions according to one aspect of the present embodiment. In some embodiments, memory 110 is coupled to logic engine 120, the logic engine is coupled to converter engine 130, and the converter engine is further coupled to arithmetic logic unit (ALU) 140. ALU 140 is an FP arithmetic operator / arithmetic unit configured to perform one or more FP arithmetic operations for ML operations, such as addition, subtraction, sum of additions, multiplication, negation, maximum, minimum, sum of maxima, sum of minima, division, from FPx to FPy (x>y), from FPx to FPy (x<y), from FP to Int, etc. According to some embodiments, memory 110 stores data, such as numerical data, non-numerical numbers, etc. In some embodiments, one or more operands related to FP arithmetic operations are stored in memory 110. It is understood that the operands related to FP arithmetic operations can be fetched and transmitted as input data 112. Logic engine 120 receives input data 112. Logic engine 120 is configured to parse input data 112 to determine whether input data 112 will result in the generation of an FP hardware exception previously calculated by ALU 140 when received. For a non-limiting example, logic engine 120 is configured to determine whether input data 112 is positive infinity, negative infinity, SNAN, etc. In other words, logic engine 120 is configured to determine whether an FP hardware exception will be generated before the FP arithmetic operator operates on the input data (i.e., determined a priori). Further, logic engine 120 may be configured to determine whether input data 112 requires special processing previously calculated by ALU 140, such as QNAN, denormalized numbers, etc. It is understood that logic engine 120 may be implemented by software according to one non-limiting example. However, it is understood that logic engine 120 may be implemented in hardware in some embodiments. As such, the description of embodiments related to software implementation is for illustrative purposes only and should not be construed as limiting the scope of the embodiments.

[0019] In some embodiments, logic engine 120 may send the result of its decision 122 to transformer engine 130. For non-limiting examples, logic engine 120 may send whether input data 112 generates an FP hardware exception or whether input data 112 requires special processing previously computed by an FP arithmetic operator. It is understood that in some non-limiting examples, decision 122 may further include input data 112. However, it is understood that decision 122 including input data 112 is for illustrative purposes, and that transformer engine 130 may independently receive input data 112, for example, from memory 110. Transformer engine 130, responsive to the decision by logic engine 120, may modify the value or content of input data 112. In some non-limiting examples, input data 112 is modified to the maximum or minimum supported number of the system when input data 112 is positive infinity or negative infinity, respectively. Additionally, when input data 112 is a SNAN, the input data may be replaced with zero. As such, input data 112, when modified by transformer engine 130, will not generate FP hardware exceptions resulting from its original value, such as positive infinity, negative infinity, or SNAN. Additionally, input data 112 may be manipulated to handle other conditions, such as denormalized numbers, QNAN inputs, which do not generate FP hardware exceptions but may still require an additional data path for each FP arithmetic operator to handle the condition. In some non-limiting examples, if input data 112 is a denormalized number or QNAN, transformer engine 130 replaces input data 112 with zero. It is understood that transformer engine 130 may leave input data 112 unchanged if input data 112 is neither QNAN nor SNAN, positive infinity, negative infinity, or a denormalized number.

[0020] In some embodiments, transformer engine 130 outputs data 132 to ALU 140. It is understood that data 132 can be the same as input data 112 if it is unchanged or if, when modified by transformer engine 130, it is a modified version of input data 112. In some embodiments, ALU 140 is configured to perform FP arithmetic operations on received data 132. It is understood that, because input data 112 is modified to avoid the generation of FP hardware exceptions or the need for special handling, no FP hardware exceptions are generated from input data 112 that are positive infinity, negative infinity, and SNAN, and no special handling is required for input data 112 that is either QNAN or a denormalized number. However, even if the input to ALU 140 may be a significant number, the output may still generate an exception or require special handling. For a non-limiting example, two significant numbers may produce a denormalized number when added to each other, or may result in positive or negative infinity when added to each other. Thus, the output of ALU 140 is monitored for a denormalized number or positive or negative infinity. Output 142 of ALU 140 is input to logic engine 120, which is configured to determine whether output 142 is a denormalized number or whether it is positive or negative infinity. If logic engine 120 determines that output 142 is neither a denormalized number nor positive or negative infinity, then logic engine 120 outputs content 124 without needing to modify its value. In other words, content 124 has the same value as output 142 from ALU 140. On the other hand, if logic engine 120 determines that content 142 is either a denormalized number or positive or negative infinity, then content 142 is sent as content 126 to converter engine 130 to modify the content. For example, if content 126 is a denormalized number, then converter engine 130 modifies the value to zero and outputs the modified value as output 134.In contrast, if content 126 is positive or negative infinity, then transformer engine 130 systemically changes the value to a maximum supported number or a minimum supported number and outputs it as content 134. It is understood that the process is repeated for each input data (i.e., operand) for the FP arithmetic operator and its output. It is further understood that for illustrative purposes, content 126 is passed from logic engine 120 to transformer engine 130, and the embodiments should not be construed as limiting in scope. For example, in some embodiments, transformer engine 130 may receive content 126 directly from logic engine 120. In one non-limiting example, transformer engine 130 may receive data directly from ALU 140.

[0021] For example, if logic engine 120 determines that content 142 is either a denormal number or positive infinity or negative infinity, then ALU 140 may be signaled to send content 142 from ALU 140 to transform engine 130 to modify the content. It is understood that the processing is repeated for each input data (i.e., operand) and its output for the FP arithmetic operator. It is understood that in some non-limiting examples, logic engine 120 and transform engine 130 may be integrated within the same processing block. It is further understood that communication between the integrated processing block and ALU 140 may be bidirectional. It is further understood that in a non-limiting example, logic engine 120, transform engine 130, and ALU 140 may be integrated within the same processing block, thereby eliminating the need for data communication between different engine blocks.

[0022] It will be appreciated that the input and output data are modified to avoid the need for FP hardware exception generation or special handling, thereby reducing the amount of resources required, power consumption, and complexity.

[0023] FIG. 2 shows an illustrative example of a programmable architecture configured to efficiently handle FP hardware exceptions in FP arithmetic operations according to one aspect of the present embodiment. FIG. 2 is substantially similar to FIG. 1. However, it is understood that in this embodiment, rules engine 210 may be used to program logic engine 120 and / or transformer engine 130. In other words, the circumstances under which input data for an FP arithmetic operator or its output data are modified may be user-programmable. Rules engine 210 allows additional FP hardware exceptions or special handling to be modified or added for other circumstances.

[0024] FIG. 3 shows an illustrative example of an architecture configured to efficiently handle FP hardware exceptions and their tracking, according to one aspect of the present embodiment. FIG. 3 is substantially similar to FIG. 2. In this embodiment, however, memory 310 may be used for tracking when input data for an FP arithmetic operator or its output is modified. For example, when input data 112 or output 142 of ALU 140 is a denormalized number, positive infinity, or negative infinity, a bounds-crossing flag 128 may be generated and stored in memory 310. In some examples, when input data 112 is either a QNAN or an SNAN, an uninitialized flag 128 may be generated and stored in memory 310. When the dividend of a division operation is non-zero and the divisor is zero, the generated flag may be a divide-by-zero flag.

[0025] For illustrative purposes, which should not be construed as limiting the scope of the embodiments, various input data for FP arithmetic operators such as those described above, e.g., addition, subtraction, and summation, are shown below, along with their modifications to the input and its output. [Table 1]

[0026] For illustrative purposes, which should not be construed as limiting the scope of the embodiments, various input data for FP arithmetic operators such as those described above, eg, negation, are shown below. [Table 2]

[0027] For illustrative purposes, which should not be construed as limiting the scope of the embodiments, various input data for an FP arithmetic operator such as that described above, eg, multiplication, are shown below. [Table 3]

[0028] It is understood that while a multiplication operation may have 32-bit input / output, the operation may be performed as a 16-bit floating point. In other words, the 32-bit floating point data is converted to a 16-bit floating point number, and the value may be clipped to a maximum, minimum, or zero. The conversion may result in an out-of-bounds exception, which is handled by the embodiment, as described above.

[0029] For illustrative purposes, which should not be construed as limiting the scope of the embodiments, various input data for FP arithmetic operators such as those described above, e.g., maximum, minimum, maximum sum, minimum sum, are shown below. [Table 4]

[0030] For illustrative purposes, which should not be construed as limiting the scope of the embodiments, various input data for an FP arithmetic operator such as that described above, eg, division, are shown below. [Table 5] [Table 6]

[0031] As described above, it is understood that a division operation can have 32-bit input / output similar to multiplication. In other words, the operation can be performed as 16-bit floating point. In other words, 32-bit floating point data is converted to 16-bit floating point numbers, and the values can be clipped to maximum, minimum, or zero. As described above, the conversion can cause boundary-crossing exceptions or division-by-zero exceptions to be processed by the embodiments.

[0032] For illustrative purposes not to be construed as limiting the scope of the embodiments, various input data for FP arithmetic operators as described above, e.g., from FPx to FPy (x > y), are shown below. [Table 7]

[0033] For illustrative purposes not to be construed as limiting the scope of the embodiments, various input data for FP arithmetic operators as described above, e.g., from FPx to FPy (x < y), are shown below. [Table 8]

[0034] For illustrative purposes not to be construed as limiting the scope of the embodiments, various input data for FP arithmetic operators as described above, e.g., from FPx to Int, are shown below. [Table 9]

[0035] It is understood that a floating-point to integer operation may have a 16-bit input, and as such, it does not require a 32-bit to 16-bit conversion. In other words, the operation may be performed as a 16-bit floating point, which may be converted to an integer, e.g., INT9 (as described in patent application No. (TBD), filed on 2011 / 02 / 06, entitled "System and Method for INT9 Quantization," and incorporated by reference in its entirety). The value may be clipped to a maximum or minimum integer, which may trigger an out-of-bounds exception that is handled by embodiments as described above.

[0036] Figure 4 shows an example of a method for efficiently handling FP hardware exceptions according to one aspect of the present embodiment. At stage 410, input data, such as FP numbers, QNANs, SNANs, denormalized numbers, etc., as described above in relation to FIGS. 1 to 3, is received. At stage 420, it is determined whether the received input data generates an FP hardware exception in response to an FP arithmetic operation on the input data. The determination is understood to be made before performing the FP arithmetic operation. For example, as described above in relation to FIGS. 1 to 3, it is determined whether the input data is a positive infinity, a negative infinity, a SNAN, etc. Further, as described above in relation to FIGS. 1 to 3, it is determined whether the input data requires special processing, for example, whether the input data is a denormalized number, whether the input data is a QNAN, etc. In response to a determination that an FP hardware exception will be generated when the input data is operated on by an FP arithmetic operator, the input data is changed at stage 430. In non-limiting examples, as described above in relation to FIGS. 1 to 3, if the input data is a positive infinity, then the value of the input data is changed to the maximum supported number by the system, if the input data is a negative infinity, then the value of the input data is changed to the minimum supported number by the system, if the input data is a SNAN, then the input data is changed to a zero value, etc. Thus, the change in the value of the input data eliminates the generation of an FP hardware exception that would have been generated if the input data was previously operated on by an FP arithmetic operator. In some embodiments, also, when the value of the input data requires special processing, the value of the input data is changed. In non-limiting examples, if the input data is a denormalized number, then the value of the input data is changed to zero, if the input data is a QNAN, then the value of the input data is changed to zero, etc. At stage 440, as described in FIGS. 1 to 3, the input data (i.e., the changed value or the original value) is operated on by an FP arithmetic operator. The FP arithmetic operation can be an addition operation, a subtraction operation, an add-total operation, a multiplication operation, a negation operation, a maximum operation, a minimum operation, a max-total operation, a min-total operation, a division operation, an FP x to FP y (x>y) operation, an FP x to FP y (x<y) operation, an FP to Int operation, etc.

[0037] In step 450, before an FP hardware exception is generated, it is determined whether the output result of the FP arithmetic operation will generate an FP hardware exception. For example, if the output result of the FP arithmetic operator is positive infinity, negative infinity, etc., then it is determined whether the output result will generate an FP hardware exception, as described in Figures 1-3. In step 460, in response to determining that the output result will generate an FP hardware exception, the value of the output result is modified. For example, positive infinity is modified to the maximum number supported by the system, negative infinity is modified to the minimum number supported by the system, etc. It is further understood that in some embodiments, if the output result is a denormalized number, the value of the output result is modified to zero.

[0038] It is understood that in stage 470, a flag is optionally generated, such as when the input data is determined to generate an FP hardware exception (before the FP hardware exception is generated), or when the input data requires special handling (i.e., QNAN, a denormalized number, etc.), or when the output result of the FP arithmetic operator generates an FP hardware exception (before the FP hardware exception is generated), or when the output result requires special handling (i.e., the output result is a denormalized number). If the value is positive infinity, negative infinity, a denormalized number, etc., the generated flag may be an out-of-bounds flag. If the data is QNAN or SNAN, the generated flag may be an uninitialized flag. If the dividend of a division operation is non-zero and the divisor is zero, the generated flag may be a divide-by-zero flag.

[0039] FIG. 5 shows an example of another method for efficiently handling FP hardware exceptions in FP arithmetic operations according to one aspect of the present embodiment. At stage 510, as described in FIGS. 1 to 3, the first and second input data are received for FP arithmetic operations such as addition, subtraction, sum of addition, multiplication, negation, maximum, minimum, sum of maximum, sum of minimum, division, from FPx to FPy (x>y), from FPx to FPy, (x<y), from FP to Int, etc. At stage 520, as described in FIGS. 1 to 3, when the first / second input data are denormalized numbers, QNAN, SNAN, etc., the first / second input data are set to zero. At stage 530, when the first / second input data are positive infinity, the first / second input data are set to the maximum supported number, and when the first / second input data are negative infinity, they are set to the minimum supported number. It is understood that if any of the input data is SNAN, QNAN, denormalized, positive infinity, or negative infinity, then an FP hardware exception will be generated when operated on by an FP arithmetic operator. At stage 540, as described in FIGS. 1 to 3, the first and second input data (i.e., the modified value or the original value) are operated on by an FP arithmetic operator. At stage 550, it is determined whether the output result of the FP arithmetic operation generates an FP hardware exception before the FP hardware exception is generated. In non-limiting examples, when the output result of the FP arithmetic operator is positive infinity, negative infinity, etc., then it is determined whether the output result generates an FP hardware exception as described in FIGS. 1 to 3. At stage 560, in response to the determination that the output result generates an FP hardware exception, the value of the output result is modified. For example, positive infinity is modified to the maximum supported number by the system, negative infinity is modified to the minimum supported number by the system, etc. It is further understood that in some embodiments, when the output result is a denormalized number, the value of the output result is modified to zero.

[0040] It is understood that in step 570, a flag is optionally generated, such as when it is determined that the first or second input data will generate an FP hardware exception (before the FP hardware exception is generated), or when the first or second input data requires special processing (i.e., QNAN, denormalized number, etc.), or when the output result of the FP arithmetic operator generates an FP hardware exception (before the FP hardware exception is generated), or when the output result requires special processing (i.e., the output result is a denormalized number). If the value is positive infinity, negative infinity, denormalized number, etc., the generated flag may be an out-of-bounds flag. If the input data is QNAN or SNAN, the generated flag may be an uninitialized flag. If the dividend of a division operation is non-zero and the divisor is zero, the generated flag may be a divide-by-zero flag.

[0041] Referring now to FIG. 6 , a block diagram illustrating an example of a computer system suitable for efficient handling of FP hardware exceptions according to some embodiments is shown. In some examples, a computer system 1100 can be used to implement computer programs, applications, methods, processes, or other software to perform the techniques described above and to implement the structures described herein. The computer system 1100 includes a bus 1102 or other communication mechanism for communicating information, which interconnects with subsystems and devices such as a processor 1104, a system memory (“memory”) 1106, a storage device 1108 (e.g., ROM), a disk drive 1110 (e.g., magnetic or optical), a communication interface 1112 (e.g., a modem or Ethernet card), a display 1114 (e.g., CRT or LCD), an input device 1116 (e.g., keyboard), and a pointer cursor control 1118 (e.g., mouse or trackball). In one embodiment, the pointer cursor control 1118 invokes one or more instructions that, for example, modify rules stored in the memory 1106 to define, at least in part, electronic message preview processing.

[0042] According to some examples, computer system 1100 performs particular operations in which processor 1104 executes one or more sequences or instructions stored in system memory 1106. Such instructions can be read into system memory 1106 from another computer-readable medium, such as storage device 1108 or disk drive 1110. In some examples, hard-wired circuitry can be used in place of or in combination with software instructions for implementation. In the illustrated example, system memory 1106 includes an operating system (“O / S”) 1132, modules of instructions executable for implementing an application 1136 (e.g., a host, server, web-services-based, distributed (i.e., enterprise) application programming interface (“API”), program, procedure, or other). Furthermore, application 1136 includes a logic engine 1138 that determines whether input data generates an FP hardware exception when operated on by an FP arithmetic operator or if the input data requires special handling (e.g., a denormalized number, QNAN, etc.), as described above in FIGS. 1 through 5. Application 1136 further includes a transformer engine 1141 that modifies the value of input data or output results of FP arithmetic operators if logic engine 1138 determines that not modifying the value would generate an FP hardware exception or if not modifying the value requires special handling, as described in Figures 1 through 5.

[0043] The term "computer-readable medium," in at least one embodiment, refers to any medium that participates in providing instructions to processor 1104 for execution. Such media may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as disk drive 1110. Volatile media include dynamic memory, such as system memory 1106. Transmission media include coaxial cables, copper wire, and fiber optics, including wires that comprise bus 1102. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0044] Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, other magnetic media, CD-ROMs, other optical media, punch cards, paper tape, other physical media with patterns of holes, RAM, PROM, EPROM, FLASH®-EPROM, other memory chips or cartridges, electromagnetic waveforms, or other media from which a computer can read.

[0045] In some examples, implementation of the sequences of instructions may be performed by a single computer system 1100. According to some examples, two or more computer systems 1100 coupled by a communication link 1120 (e.g., a LAN, a PSTN, or a wireless network) may execute the sequences of instructions in cooperation with one another. The computer system 1100 may send and receive messages, data, and instructions, including program code (i.e., application code), from the communication link 1120 and the communication interface 1112. The received program code may be executed by the processor 1104 as received and / or may be stored on the disk drive 1110 or other non-volatile storage for later execution. In one embodiment, the system 1100 is implemented as a handheld device. However, in other embodiments, the system 1100 may be implemented as a personal computer (i.e., a desktop computer) or other computing device. In at least one embodiment, any of the distribution systems described above may be implemented as a single system 1100 or in a distributed architecture including multiple systems 1100.

[0046] In other examples, the system may be implemented from a personal computer, computing device, mobile device, mobile telephone, facsimile device, personal digital assistant (PDA), or other electronic device, as described above.

[0047] In at least some embodiments, the structure and / or functionality of any of the interfaces and panels described above may be implemented in software, hardware, firmware, circuitry, or combinations thereof. It should be noted that elements of the structures and components shown throughout, as well as their functionality, may be integrated with one or more other structures or elements.

[0048] Alternatively, the elements and their functionality, if any, may be further divided into constituent sub-elements. As software, the techniques described above may be implemented using various types of programming or formatting languages, frameworks, syntaxes, applications, protocols, or techniques, including C, Objective C, C++, C#, Flex®, Fireworks®, Java®, Javascript®, AJAX, COBOL, FORTRAN, ADA, XML, HTML, DHTML, XHTML, HTTP, XMPP, and others, which may vary and are not limited to the examples or descriptions provided.

[0049] The foregoing description of various embodiments of the claimed subject matter has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the claimed subject matter to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain the principles of the invention and its practical application, thereby enabling others skilled in the relevant art to understand the claimed subject matter, various embodiments, and various modifications suitable for the particular application contemplated.

Claims

1. receiving input data at a floating point arithmetic unit, said floating point arithmetic unit configured to perform floating point arithmetic operations on said input data; determining whether the received input data generates a floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the determination being made before performing the floating-point arithmetic operation; converting the value of the received input data to a modified value in response to the determination that the received input data will generate the floating-point hardware exception, the conversion eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the modified value of the input data being a maximum supported number when the input data is positive infinity, and a minimum supported number when the input data is negative infinity; A computer-implemented method comprising:

2. The computer-implemented method of claim 1 , further comprising performing the floating-point arithmetic operation on the input data with modified values ​​to generate an output result.

3. The computer-implemented method of claim 2 , wherein the floating-point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-sum operation.

4. 3. The computer-implemented method of claim 2, further comprising determining whether the output result of the floating-point arithmetic operation generates a floating-point hardware exception.

5. The computer-implemented method of claim 4 , further comprising setting the resulting output value to zero if the resulting output value is a denormalized number.

6. A method of computing a floating-point arithmetic unit comprising: receiving input data at a floating-point arithmetic unit, the floating-point arithmetic unit configured to perform floating-point arithmetic operations on the input data; determining whether the received input data generates a floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the determination being made before performing the floating-point arithmetic operation; responsive to the determination that the received input data will generate the floating-point hardware exception, converting a value of the received input data to a modified value, the conversion eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; performing the floating-point arithmetic operation on the input data with the modified values ​​to generate an output result; determining whether the output result of the floating-point arithmetic operation generates a floating-point hardware exception; If the value of the output result is positive infinity, setting the value of the output result to a maximum supported number; and if the value of the output result is negative infinity, setting the value of the output result to a minimum supported number.

7. The computer-implemented method of claim 1 , further comprising setting the value of the input data to zero if the input data is a denormalized number.

8. The computer-implemented method of claim 7 , further comprising generating a bounds crossing flag associated with the denormalized number.

9. A method of computing a floating-point arithmetic operation, comprising: receiving input data at a floating-point arithmetic unit, said floating-point arithmetic unit configured to perform floating-point arithmetic operations on said input data; determining whether the received input data generates a floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the determination being made before performing the floating-point arithmetic operation; responsive to the determination that the received input data will generate the floating-point hardware exception, converting a value of the received input data to a modified value, the conversion eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; Equipped with The computer-implemented method, wherein the input data is positive infinity and the modified value for the input data is a maximum supported number.

10. The computer-implemented method of claim 9 , further comprising generating a boundary crossing flag associated with the input data.

11. A method of computing a floating-point arithmetic operation, comprising: receiving input data at a floating-point arithmetic unit, said floating-point arithmetic unit configured to perform floating-point arithmetic operations on said input data; determining whether the received input data generates a floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the determination being made before performing the floating-point arithmetic operation; responsive to the determination that the received input data will generate the floating-point hardware exception, converting a value of the received input data to a modified value, the conversion eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; Equipped with The computer-implemented method, wherein the input data is negative infinity and the modified value for the input data is a minimum supported number.

12. The computer-implemented method of claim 11 , further comprising generating a boundary crossing flag associated with the input data.

13. A method of computing a floating-point arithmetic operation, comprising: receiving input data at a floating-point arithmetic unit, said floating-point arithmetic unit configured to perform floating-point arithmetic operations on said input data; determining whether the received input data generates a floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the determination being made before performing the floating-point arithmetic operation; responsive to the determination that the received input data will generate the floating-point hardware exception, converting a value of the received input data to a modified value, the conversion eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; 1. A computer-implemented method comprising: The computer-implemented method further comprising setting the value of the input data to zero if the input data is qnan (quiet NaN).

14. The computer-implemented method of claim 13 , further comprising generating an uninitialized flag associated with the input data.

15. A method of computing a floating-point arithmetic operation, comprising: receiving input data at a floating-point arithmetic unit, said floating-point arithmetic unit configured to perform floating-point arithmetic operations on said input data; determining whether the received input data generates a floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the determination being made before performing the floating-point arithmetic operation; responsive to the determination that the received input data will generate the floating-point hardware exception, converting a value of the received input data to a modified value, the conversion eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; Equipped with A computer-implemented method, wherein the input data is snan (signaling NaN) and the modified value is zero.

16. The computer-implemented method of claim 15 , further comprising generating an uninitialized flag associated with the input data.

17. receiving first input data at a floating point arithmetic unit for floating point arithmetic operations; receiving second input data at the floating point arithmetic unit for the floating point arithmetic operation; setting the first input data to zero if the first input data is a denormalized number, a qnan (quiet NaN), or a snan (signaling NaN); setting the first input data to a maximum supported number if the first input data is positive infinity; setting the first input data to a minimum support number if the first input data is negative infinity; setting the second input data to zero if the second input data is a denormalized number, qnan, or snan; setting the second input data to the maximum supported number if the second input data is positive infinity; If the second input data is negative infinity, setting the second input data to the minimum support number; expunging a floating-point hardware exception in response to the floating-point arithmetic operation on the first input data and the second input data by performing one or more of: A computer-implemented method comprising:

18. 20. The computer-implemented method of claim 17, further comprising performing the floating-point arithmetic operation on the first input data and the second input data or modified values ​​thereof to generate an output result.

19. 20. The computer-implemented method of claim 18, wherein the floating-point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-sum operation.

20. 20. The computer-implemented method of claim 18, further comprising setting the resulting output value to zero if the resulting output value is a denormalized number.

21. 20. The computer-implemented method of claim 18, further comprising: if the value of the resulting output is positive infinity, setting the value of the resulting output to the maximum supported number; and if the value of the resulting output is negative infinity, setting the value of the resulting output to the minimum supported number.

22. 20. The computer-implemented method of claim 17, further comprising generating a bounds crossing flag associated with the denormalized number.

23. 20. The computer-implemented method of claim 17, further comprising generating a boundary crossing flag associated with at least one of the first input data being positive infinity or negative infinity and the second input data being positive infinity or negative infinity.

24. 20. The computer-implemented method of claim 17, further comprising generating an uninitialized flag associated with the qnan input data.

25. 20. The computer-implemented method of claim 17, further generating an uninitialized flag associated with the snan input data.

26. a logic engine configured to receive input data relating to a floating-point arithmetic operation to be performed by a floating-point arithmetic unit, the logic engine configured to determine whether the received input data will generate a floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the determination being made before performing the floating-point arithmetic operation; a transformer engine configured to, in response to the determination that the received input data will generate the floating-point hardware exception, transform the value of the received input data to a modified value, the transformation eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data, the modified value of the input data being a maximum supported number when the input data is positive infinity and a minimum supported number when the input data is negative infinity; A system comprising:

27. 27. The system of claim 26, further comprising an arithmetic floating point unit configured to perform the floating point arithmetic operation on the input data with modified values ​​to generate an output result.

28. 28. The system of claim 27, wherein the floating-point arithmetic operation is selected from one of an addition operation, a subtraction operation, or an add-sum operation.

29. 28. The system of claim 27, wherein the logic engine is further configured to determine whether the output result of the floating-point arithmetic operation generates a floating-point hardware exception.

30. 30. The system of claim 29, wherein the converter engine is further configured to set the resulting output value to zero if the resulting output value is a denormalized number.

31. A logic engine configured to receive input data relating to a floating-point arithmetic operation to be performed by a floating-point arithmetic unit, said logic engine configured to determine whether said received input data will generate a floating-point hardware exception in response to said floating-point arithmetic operation on said input data, said determination being made before performing said floating-point arithmetic operation; a transformer engine configured to, in response to the determination that the received input data will generate the floating-point hardware exception, transform a value of the received input data to a modified value, the transformation eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; an arithmetic floating point unit configured to perform the floating point arithmetic operation on the input data with the modified value to generate an output result; Equipped with the logic engine is further configured to determine whether the output result of the floating-point arithmetic operation generates a floating-point hardware exception; the transformer engine is further configured to set the value of the output result to a maximum supported number if the value of the output result is positive infinity, and the transformer engine is further configured to set the value of the output result to a minimum supported number if the value of the output result is negative infinity.

32. 27. The system of claim 26, wherein the transformer engine is further configured to set the value of the input data to zero if the input data is a denormalized number.

33. 33. The system of claim 32, wherein the logic engine is further configured to generate a bounds crossing flag associated with the denormalized number.

34. A logic engine configured to receive input data relating to a floating-point arithmetic operation to be performed by a floating-point arithmetic unit, said logic engine configured to determine whether said received input data will generate a floating-point hardware exception in response to said floating-point arithmetic operation on said input data, said determination being made before performing said floating-point arithmetic operation; a transformer engine configured to, in response to the determination that the received input data will generate the floating-point hardware exception, transform a value of the received input data to a modified value, the transformation eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; Equipped with The system wherein the input data is positive infinity and the modified value for the input data is a maximum supported number.

35. 35. The system of claim 34, wherein the transformer engine is further configured to generate a boundary crossing flag associated with the input data.

36. A logic engine configured to receive input data relating to a floating-point arithmetic operation to be performed by a floating-point arithmetic unit, said logic engine configured to determine whether said received input data will generate a floating-point hardware exception in response to said floating-point arithmetic operation on said input data, said determination being made before performing said floating-point arithmetic operation; a transformer engine configured to, in response to the determination that the received input data will generate the floating-point hardware exception, transform a value of the received input data to a modified value, the transformation eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; Equipped with The system wherein the input data is negative infinity and the modified value for the input data is a minimum support number.

37. 37. The system of claim 36, wherein the logic engine is further configured to generate a boundary crossing flag associated with the input data.

38. A logic engine configured to receive input data relating to a floating-point arithmetic operation to be performed by a floating-point arithmetic unit, said logic engine configured to determine whether said received input data will generate a floating-point hardware exception in response to said floating-point arithmetic operation on said input data, said determination being made before performing said floating-point arithmetic operation; a transformer engine configured to, in response to the determination that the received input data will generate the floating-point hardware exception, transform a value of the received input data to a modified value, the transformation eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; Equipped with The system, wherein the transformer engine is further configured to set the value of the input data to zero if the input data is qnan (quiet NaN).

39. 39. The system of claim 38, wherein the logic engine is further configured to generate an uninitialized flag associated with the input data.

40. A logic engine configured to receive input data relating to a floating-point arithmetic operation to be performed by a floating-point arithmetic unit, said logic engine configured to determine whether said received input data will generate a floating-point hardware exception in response to said floating-point arithmetic operation on said input data, said determination being made before performing said floating-point arithmetic operation; a transformer engine configured to, in response to the determination that the received input data will generate the floating-point hardware exception, transform a value of the received input data to a modified value, the transformation eliminating the generation of the floating-point hardware exception in response to the floating-point arithmetic operation on the input data; Equipped with A system wherein the input data is snan (signaling NaN) and the modified value is zero.

41. 41. The system of claim 40, wherein the logic engine is configured to generate an uninitialized flag associated with the input data.

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