Automatically assisted circuit verification method

Abstract

The method includes classifying nodes of the fabricated circuit as priority nodes and nodes as subordinate nodes; automatically designating a first priority node for verification and evaluating the first priority node by determining whether a measurement signal from the first priority node meets a pass / fail criterion for the first priority node; if the measurement signal from the first priority node meets the pass / fail criterion, automatically designating a second priority node for verification and evaluating the second priority node by determining whether a measurement signal from the second priority node meets the pass / fail criterion for the second priority node; and if the measurement signal from the first priority node does not meet the pass / fail criterion, automatically designating a first subordinate node for verification and evaluating the first subordinate node by determining whether a measurement signal from the first subordinate node meets the pass / fail criterion for the first subordinate node.

Description

[Technical Field]

[0001] This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 050,053, filed July 9, 2020, which is incorporated herein by reference.

[0002] FIELD OF THE INVENTION This application relates to systems and methods for verifying and debugging electronic circuits. [Background technology]

[0003] Traditionally, verifying and debugging an electronic circuit requires a designer to design the circuit, simulate it, and then manufacture the circuit. Once the circuit is manufactured, the designer must verify the operation of the circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2008 / 0201624 [Patent Document 2] US Patent Application Publication No. 2015 / 0123696 [Patent Document 3] U.S. Patent No. 8,769,360 Summary of the Invention [Problem to be solved by the invention]

[0005] Often, there is a portion of a circuit that does not function as expected. In these cases, a designer or experienced engineer must analyze the circuit and determine, through educated trial and error, which portion of the circuit is malfunctioning or defective. This requires a high level of knowledge about the circuit and its intended operation.

[0006] The disclosed technical arrangements address shortcomings in the prior art. [Means for solving the problem]

[0007] Aspects described herein relate to a method for automated assistance in circuit verification. According to one aspect, a circuit can be verified even when a human operator does not have a high level of knowledge about the circuit or its intended operation. To this end, the described system may automatically select nodes to be tested based on a hierarchy of test nodes, branching analysis, artificial intelligence, or other suitable means.

[0008] Thus, in one embodiment, by way of example, machine learning or automatically generated diagnostic trees are applied to the process of verifying circuit operation. Aspects of the disclosed technology use a circuit diagram and associated circuit node list to apply algorithmic analysis to guide the process of checking circuit operation node by node. In one embodiment, expected and measured waveforms at various locations within the circuit diagram and associated fabricated circuit are used to determine whether the circuit is generating the desired signals at key locations. Depending on the measured circuit nodes and the measurement results, an algorithm suggests new points within the circuit to measure or test. This process is repeated until either proper circuit operation is verified for all parts of the circuit or the most likely location of a faulty component or manufacturing defect has been identified.

[0009] In one form, a circuit schematic is modeled to capture expected signals at critical points in the circuit to determine what the proper behavior of the circuit is. In the exhaustive case, simulation signals are generated at every circuit node in the schematic. The schematic is then analyzed using bifurcation analysis or a suitable artificial intelligence approach to identify the proper sequence for testing the circuit nodes and compare the simulated behavior to determine proper circuit behavior. This analysis can be applied as a batch process at the beginning of circuit verification, or as each node is evaluated to determine where to test next. The goal of this process is to obtain a circuit that operates within an acceptable tolerance of the levels predicted by the simulation model.

[0010] Once a circuit has been evaluated and good and bad signals identified, the faulty component or circuit node is further analyzed to identify the most likely fault. For example, a signal may be present at the input terminal of an active device but not at the output terminal, and power to the active device is present. The circuit node connected to this device or its output terminal is then identified as the most likely location of the fault. Once all of the circuit has been verified and the signals are within tolerance, the circuit is considered verified.

[0011] By automating the process of analyzing a circuit and comparing actual signals with modeled signals, the process of verifying circuit operation and locating faults is simplified and expedited, allowing circuits to be verified by operators who do not have a high level of knowledge of the circuit or its intended operation. [Brief explanation of the drawings]

[0012] [Figure 1] Figure 1 shows an example of the relationship between circuit diagram data, circuit simulation data, and a fabricated circuit. [Figure 2] FIG. 2 is a functional block diagram of an example configuration of components of a system configured for automatic support of circuit verification. [Figure 3] FIG. 3 illustrates an embodiment of an example method for automated assistance in circuit verification according to an example embodiment. [Figure 4] FIG. 4 shows an example of a decision tree in one form. [Figure 5] Figure 5 shows an example of the data flow and process of a batch analysis according to one embodiment. [Figure 6] Figure 6 shows an example of the data flow and process for an iterative analysis according to one example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] FIG. 1 illustrates an example relationship between schematic data 101, circuit simulation data 103, and a fabricated circuit 102. As illustrated, the schematic data 101 may be generated, for example, by a circuit designer, and specifies the functional characteristics of a desired fabricated circuit 102. The schematic data 101 may also be used to generate circuit simulation data 103 (shown in FIG. 1 as appearing in an example display screen). For example, the schematic data 101 may be imported and modeled in a computer-aided analysis tool 202, such as circuit simulation software, to generate the circuit simulation data 103. The circuit simulation data 103 exists as a mathematical model in computer software, modeling the functionality of the physical fabricated circuit 102 or a portion of the fabricated circuit 102. Thus, the circuit simulation data 103 may include a simulated signal for node 105 of the circuit simulation data 103 corresponding to node 104 of the fabricated circuit 102.

[0014] These simulated signals in the circuit simulation data 103 represent expected signals for corresponding nodes 104 of the manufactured circuit 102. These expected signals may then form the basis of pass-fail criteria for the corresponding nodes 104 of the manufactured circuit 102. For example, the pass-fail criteria for a respective node may be met if a given measured signal matches the expected signal for that node or is within a desired tolerance of the expected signal. Similarly, the pass-fail criteria for a respective node may not be met if a given measured signal does not match the expected signal for that node or falls outside the desired tolerance.

[0015] 2 is a functional block diagram of an example configuration of components of a system 200 configured for automated assistance in circuit verification. As shown, the system may include a processor 201, a computer-aided analysis tool 202, a test and measurement device 203, a display device 204, artificial intelligence functionality 205, and an automated probing system 206, each of which is described elsewhere in this disclosure.

[0016] FIG. 3 illustrates an example method 300 for automated support of circuit verification according to an embodiment. As illustrated in FIG. 3, the method for automated support of circuit verification may include a process 301 for classifying one or more nodes 104 of a fabricated circuit 102 as priority nodes and one or more nodes 104 of the fabricated circuit 102 as inferior nodes. Each of the inferior nodes is on the same sub-portion of the fabricated circuit 102 as at least one of the priority nodes. In this context, being "on" the same sub-portion of the fabricated circuit means being logically or functionally related to the same sub-portion of the fabricated circuit, but not necessarily physically adjacent or nearby. Thus, for example, a priority node may be a node related to a distinct functional area of ​​the fabricated circuit 102, while a subordinate node may be a node within a circuit branch of the respective functional area. In one embodiment, the subordinate node provides information to the corresponding priority node. For example, as shown in FIG. 1, node 104 is an example of a priority node, while nodes 106 and 107 are examples of subordinate nodes.

[0017] In some embodiments, a hierarchy may exist between priority nodes. For example, key portions of the manufacturing circuit 102 that are fundamental to the primary operation of the manufacturing circuit may be designated as higher-value priority nodes, while signal paths may be designated as lower-value priority nodes. In some embodiments, this information may be used to generate a diagnostic tree or provided to an artificial intelligence function, as described below.

[0018] Returning to FIG. 3 , the method 300 for automatically assisting circuit verification may further include a process 302 for evaluating the first priority node by automatically designating a first priority node to be verified from among the priority nodes classified in process 301 and then determining whether a signal measured from the first priority node (measured signal) satisfies a pass / fail criterion for the first priority node. For example, several processes (examples of which are described below) may be used to designate a particular priority node from among the multiple priority nodes as the first priority node to be evaluated. The measured signal from the first priority node is then compared with the pass / fail criterion for the first priority node to determine whether the measured signal from the first priority node satisfies the pass / fail criterion for the first priority node. As described above, the pass / fail criterion may be, or may include, whether the measured signal from the first priority node matches or falls within a desired tolerance range for the expected signal for the first priority node, where the expected signal is a simulation signal in the circuit simulation data 103 corresponding to the first priority node.

[0019] In one embodiment, automatically designating a first priority node for verification from among multiple priority nodes includes designating a starting node of a predetermined diagnostic tree as the first priority node. For example, the predetermined diagnostic tree may define a sequence of nodes to be tested, the sequence specifying a starting node (start node) and an order of nodes to be tested after the start node. In one embodiment, the diagnostic tree may be generated using artificial intelligence, branch analysis of previously performed circuit diagram data 101, or other methods to identify an appropriate sequence for testing circuit nodes to determine proper circuit operation. In one embodiment, the order of nodes to be tested may depend on the results of tests at previous nodes in the sequence of nodes, such as whether the previous node passed or failed the test.

[0020] FIG. 4 shows an example diagnostic tree used to explain the concept of a diagnostic tree. As shown in FIG. 4, a predetermined diagnostic tree 400 indicates which node to test next depending on the results of testing the previous node. For example, starting node 401 is shown near the top of FIG. 4. If starting node 401 is tested and meets the pass / fail criteria for starting node 401 (shown as "pass" path 408), diagnostic tree 400 indicates that node 402 is the next node to be tested. In contrast, if starting node 401 is tested and does not meet the pass / fail criteria for starting node 401 (shown as "fail" path 409), diagnostic tree 400 indicates that node 403 is the next node to be tested. This process may be repeated for additional nodes.

[0021] 4, if node 402 is tested and meets the pass / fail criteria for node 402 (shown as "pass" path 410), then diagnosis tree 400 indicates that node 404 is the next node to be tested. However, if node 402 is tested and does not meet the pass / fail criteria for node 402 (shown as "fail" path 410), then diagnosis tree 400 indicates that node 404 is the next node to be tested. path 411), diagnosis tree 400 indicates that node 405 is the next node to be tested.

[0022] 4, if node 403 is tested and meets the pass / fail criteria for node 403 (shown as "pass" path 412), then diagnostic tree 400 indicates that node 406 is the next node to be tested. However, if node 403 is tested and does not meet the pass / fail criteria for node 403 (shown as "fail" path 413), then diagnostic tree 400 indicates that node 407 is the next node to be tested.

[0023] Figure 4 shows an example of a diagnostic tree, but other forms are possible. For example, the next node to be tested can be determined based on the identity of the previous node, including its location in the circuit, regardless of whether the previous node passed or failed the pass / fail criteria. In such a case, the diagnostic tree is simply a list of nodes to be tested in order.

[0024] Returning to FIG. 3 , in one embodiment, the process of automatically designating a first priority node to be verified from among multiple priority nodes includes a process of using the artificial intelligence function 205 to determine a starting node and a process of designating the starting node of the diagnosis tree as the first priority node. For example, the priority may be based on the number of circuit elements to which the node is connected. For example, a power supply may be given a higher priority than an amplifier output terminal that drives only other devices because it contacts many circuit elements. The artificial intelligence function 205 may also repeatedly reevaluate the priority of nodes based on which nodes have passed and failed in the analysis process up to this point.

[0025] In one embodiment, automatically designating a first priority node for verification from among the plurality of priority nodes includes receiving, at the computer-aided analysis tool 202, the circuit diagram data 101 and the circuit simulation data 103. A diagnosis tree may then be generated based on the circuit diagram data 101 and the circuit simulation data 103.

[0026] As mentioned above, in some embodiments, a diagnostic tree may be generated using artificial intelligence, branch analysis, or other methods to identify the appropriate sequence of testing circuit nodes to determine proper circuit operation. Once a diagnostic tree is created, the starting node of the diagnostic tree may be designated as a first priority node.

[0027] In one embodiment, the process of verifying whether the measurement signal from the first priority node meets the pass / fail criteria for the first priority node includes the processes of obtaining the measurement signal from the first priority node, obtaining circuit simulation data 103 including a simulation signal corresponding to the first priority node based on a computer-aided analysis of the manufactured circuit 102, comparing the measurement signal from the first priority node to the simulation signal corresponding to the first priority node, and classifying the measurement signal from the first priority node as pass if the measurement signal from the first priority node falls within the pass / fail criteria for the first priority node based on a maximum desired variance from the simulation signal corresponding to the first priority node, and classifying the measurement signal from the first priority node as fail if the measurement signal from the first priority node does not meet the pass / fail criteria for the first priority node.

[0028] In some embodiments, acquiring the measurement signal from the first priority node may include acquiring the measurement signal from the first priority node using a probe coupled to the test and measurement instrument 203. In such embodiments, the method 300 may further include providing a prompt to a human operator to position the probe coupled to the test and measurement instrument 203 to acquire the measurement signal from the first priority node. The prompt may be, for example, specific instructions for acquiring a signal at a particular location. The prompt may also include an expected result of the measurement signal. For example, the prompt may indicate that the signal should be a sine wave with a frequency of 100 kHz and an amplitude of 1 V p-p. In some embodiments, the prompt to the human operator may be displayed on a screen or other display device, such as the display device 204 shown in FIG. 2 .

[0029] In embodiments using a probe coupled to the test and measurement instrument 203 to obtain the measurement signal from the first priority node, the method 300 may further include having the automated probing system 206 position the probe coupled to the test and measurement instrument 203 to obtain the measurement signal from the first priority node without human intervention. The prompt may include, for example, an identification of the first priority node.

[0030] In one embodiment, evaluating the first priority node further includes comparing the measured signal from the first priority node with the simulated signal corresponding to the first priority node and displaying the comparison result on a user interface, which may be, for example, the display device 204 shown in FIG.

[0031] In some embodiments, the method 300 may further include designating a subsequent node in the diagnosis tree as a second priority node. The subsequent node is later in the sequence of nodes than the first priority node. In some embodiments, the subsequent node is the node that follows the first priority node in the sequence of nodes. For example, in embodiments using a diagnosis tree, the subsequent node is the node identified by the diagnosis tree as the node to test next after the first priority node.

[0032] If the measured signal from the first priority node satisfies the pass / fail criteria for the first priority node, method 300 may further include evaluating the second priority node 303 by automatically designating a second priority node from among the plurality of priority nodes to be verified and determining whether the measured signal from the second priority node satisfies the pass / fail criteria for the second priority node. For example, several processes may be used to designate a particular priority node from among the plurality of priority nodes to be the second priority node to be evaluated. Examples of such processes include a diagnostic tree (such as diagnostic tree 400 in FIG. 4 ) and the artificial intelligence function 205 described above. The measured signal from the second priority node is then compared to the pass / fail criteria for the second priority node to determine whether the measured signal from the second priority node satisfies the pass / fail criteria for the second priority node. As described above, the pass / fail criteria may be or include the measured signal from the second priority node matching or falling within a desired tolerance of the expected signal for the second priority node, where the expected signal is a simulated signal in circuit simulation data 103 corresponding to the second priority node.

[0033] In one embodiment, the process of automatically designating a second priority node to be verified from among the plurality of priority nodes includes a process of designating a next node in a predetermined diagnosis tree as the second priority node.

[0034] In one embodiment, the process of automatically designating a second priority node to be verified from among multiple priority nodes includes a process of using artificial intelligence functionality 205 to determine the next node to be tested, and then designating the next node in the diagnostic tree as the second priority node.

[0035] In one embodiment, the process of verifying whether the measurement signal from the second priority node meets the pass / fail criteria for the second priority node includes the processes of obtaining the measurement signal from the second priority node, obtaining circuit simulation data 103 including a simulation signal corresponding to the second priority node based on a computer-aided analysis of the manufactured circuit 102, comparing the measurement signal from the second priority node to the simulation signal corresponding to the second priority node, and classifying the measurement signal from the second priority node as pass if the measurement signal from the second priority node falls within the pass / fail criteria for the second priority node based on a maximum desired variance from the simulation signal corresponding to the second priority node, and classifying the measurement signal from the second priority node as fail if the measurement signal from the second priority node does not meet the pass / fail criteria for the second priority node.

[0036] In some embodiments, acquiring the measurement signal from the second priority node includes acquiring the measurement signal from the second priority node using a probe coupled to the test and measurement instrument 203. In such embodiments, the method 300 may further include providing a prompt to a human operator to position the probe coupled to the test and measurement instrument 203 to acquire the measurement signal from the second priority node. The prompt may be, for example, as described above with respect to providing a prompt for the first priority node.

[0037] In embodiments using a probe coupled to the test and measurement instrument 203 to obtain the measurement signal from the second priority node, the method 300 may further include causing the automated probing system 206 to position the probe coupled to the test and measurement instrument 203 to obtain the measurement signal from the second priority node. The prompt may be, for example, as described above with respect to providing a prompt for the first priority node.

[0038] In one embodiment, evaluating the second priority node further includes comparing the measured signal from the second priority node with the simulated signal corresponding to the second priority node and displaying the comparison result on a user interface, which may be, for example, the display device 204 shown in FIG.

[0039] If the measurement signal from the first priority node does not meet the pass / fail criteria for the first priority node, method 300 may further include evaluating 304 the first subordinate node by automatically designating a first subordinate node from among the plurality of subordinate nodes for verification and determining whether the measurement signal from the first subordinate node meets the pass / fail criteria for the first subordinate node. The first subordinate node may be on the same subportion of manufacturing circuit 102 as the first priority node. For example, several processes may be used to designate a particular subordinate node from among the plurality of subordinate nodes on the same subportion of manufacturing circuit 102 as the first priority node to be evaluated. Examples of such processes include a diagnosis tree (e.g., diagnosis tree 400 of FIG. 4 ) and artificial intelligence function 205 described above. The measurement signal from the first subordinate node is then compared to the pass / fail criteria for the first subordinate node to determine whether the measurement signal from the first subordinate node meets the pass / fail criteria for the first subordinate node. As described above, the pass / fail criteria may be or may include that the measured signal from the first subnode matches or falls within a desired tolerance for the first subnode, where the expected signal is a simulated signal in the circuit simulation data 103 corresponding to the first subnode.

[0040] In one embodiment, the process of automatically designating a first lower node to be verified from among the plurality of priority nodes includes a process of designating a next node in a predetermined diagnosis tree as the first lower node.

[0041] In one embodiment, the process of automatically designating a first subordinate node to be verified from among a plurality of priority nodes includes a process of determining the next node using artificial intelligence function 205, and a process of designating the next node in the diagnostic tree as the first subordinate node.

[0042] In one embodiment, the process of verifying whether the measurement signal from the first sub-node meets the pass / fail criteria for the first sub-node includes the processes of obtaining the measurement signal from the first sub-node, obtaining circuit simulation data 103 including a simulation signal corresponding to the first sub-node based on a computer-aided analysis of the manufactured circuit 102, comparing the measurement signal from the first sub-node to the simulation signal corresponding to the first sub-node, and classifying the measurement signal from the first sub-node as pass if the measurement signal from the first sub-node falls within the pass / fail criteria for the first sub-node based on a maximum desired variance from the simulation signal corresponding to the first sub-node, and classifying the measurement signal from the first sub-node as fail if the measurement signal from the first sub-node does not meet the pass / fail criteria for the first sub-node.

[0043] In one embodiment, acquiring the measurement signal from the first subordinate node includes acquiring the measurement signal from the first subordinate node using a probe coupled to the test and measurement instrument 203. In such an embodiment, the method 300 may further include providing a prompt to a human operator to position the probe coupled to the test and measurement instrument 203 to acquire the measurement signal from the first subordinate node. The prompt may be, for example, as described above with respect to providing a prompt for the first priority node.

[0044] In embodiments using a probe coupled to the test and measurement instrument 203 to obtain the measurement signal from the first subordinate node, the method 300 may further include causing the automatic probing system 206 to position the probe coupled to the test and measurement instrument 203 to obtain the measurement signal from the first subordinate node. The prompt may be, for example, as described above with respect to providing a prompt for the first priority node.

[0045] In one embodiment, evaluating the first subordinate node further includes comparing the measured signal from the first subordinate node with the simulated signal corresponding to the first subordinate node and displaying the comparison result on a user interface, which may be, for example, display device 204 shown in FIG.

[0046] If the measured signal from the second priority node meets the pass / fail criteria for the second priority node, method 300 may further include evaluating the third priority node by automatically designating a third priority node from among the plurality of priority nodes to be verified and determining whether the measured signal from the third priority node meets the pass / fail criteria for the third priority node. For example, several processes may be used to designate a particular priority node from among the plurality of priority nodes to be the third priority node to be evaluated. Examples of such processes include a diagnostic tree (such as diagnostic tree 400 in FIG. 4 ) and the artificial intelligence function 205 described above. The measured signal from the third priority node is then compared to the pass / fail criteria for the third priority node to determine whether the measured signal from the third priority node meets the pass / fail criteria for the third priority node. As described above, the pass / fail criteria may be or include the measured signal from the third priority node matching or falling within a desired tolerance of the expected signal for the third priority node, where the expected signal is a simulated signal in circuit simulation data 103 corresponding to the third priority node.

[0047] If the measurement signal from the second priority node does not meet the pass / fail criteria for the second priority node, method 300 may further include evaluating 306 the second subordinate node by automatically designating a second subordinate node to verify from among the plurality of subordinate nodes and determining whether the measurement signal from the second subordinate node meets the pass / fail criteria for the second subordinate node. The second subordinate node may be on the same sub-portion of manufacturing circuit 102 as the second priority node.

[0048] In some embodiments, method 300 may further include evaluating each of the preferred nodes when a preceding preferred node meets the pass / fail criteria for that preceding preferred node until evaluation of each preferred node is complete, so that all preferred nodes have been evaluated as long as all preceding preferred nodes have met their respective pass / fail criteria.

[0049] In one embodiment, the method 300 may further include evaluating each child node of each preferred node if the preceding child node meets the pass / fail criteria for the preceding child node until evaluation of each child node of each preferred node is complete.

[0050] Figure 5 illustrates an example data flow and process for batch analysis according to an embodiment. Figure 6 illustrates an example data flow and process for iterative analysis according to an embodiment. The reference numbers identifying the functional blocks in Figures 5 and 6 correspond to the functions and processes described above. Note that some of the processes described above may correspond to more than one functional block in Figures 5 and 6.

[0051] In some embodiments, a processor, such as processor 201 depicted in Figure 2, may be configured to communicate with computer-aided analysis tools 202, test and measurement equipment 203, display devices 204, artificial intelligence functions 205, and automated probing systems 206. In some embodiments, processor 201 may be configured to perform one or more of the operations depicted in Figures 3, 5, or 6, or other operations described in this disclosure.

[0052] Additionally, embodiments may operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The terms "controller" or "processor" herein contemplate microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology may be implemented with computer-usable data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, and the like, which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data formats. Computer-executable instructions may be stored on computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, and the like. Those skilled in the art will appreciate that the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed technology, and such data structures are considered within the scope of the computer-executable instructions and computer-usable data described herein. Example

[0053] The following examples are provided to aid in understanding the technology disclosed herein. Particular aspects of the technology may include one or more of the examples described below, and any combination thereof.

[0054] In a first embodiment, there is a method for automatically assisting circuit verification, the method including: identifying one or more nodes of a manufacturing circuit as priority nodes; and identifying one or more nodes of the manufacturing circuit as inferior nodes on the same subportion of the manufacturing circuit as at least one of the priority nodes. evaluating the first priority node by classifying the first priority node as a subordinate node, automatically designating a first priority node from among the priority nodes for verification, and determining whether a measurement signal from the first priority node satisfies the pass / fail criteria for the first priority node; if the measurement signal from the first priority node satisfies the pass / fail criteria for the first priority node, automatically designating a second priority node from among the priority nodes for verification, and determining whether a measurement signal from the second priority node satisfies the pass / fail criteria for the second priority node; if the measurement signal from the first priority node does not satisfy the pass / fail criteria for the first priority node, automatically designating a first subordinate node from among the subordinate nodes for verification that is on the same subportion of the fabrication circuit as the first priority node, and determining whether a measurement signal from the first subordinate node satisfies the pass / fail criteria for the first subordinate node.

[0055] Example 2 includes the method of Example 1, further comprising: evaluating the third priority node by automatically designating a third priority node from among the priority nodes for verification if the measurement signal from the second priority node satisfies a pass / fail criterion for the second priority node and verifying whether the measurement signal from the third priority node satisfies the pass / fail criterion for the third priority node; and if the measurement signal from the second priority node does not satisfy the pass / fail criterion for the second priority node, evaluating the second lower node by automatically designating a second lower node from among the lower nodes for verification that is on the same sub-portion of the manufacturing circuit as the second priority node and verifying whether the measurement signal from the second lower node satisfies the pass / fail criterion for the second lower node.

[0056] Example 3 is any of the methods of Examples 1 and 2, further comprising a process of evaluating subsequent priority nodes if the preceding priority node satisfies the pass / fail criteria for the preceding priority node until evaluation of each of the priority nodes is complete.

[0057] Example 4 is any of the methods of Examples 1 to 3, further comprising a process of evaluating subsequent subordinate nodes of each of the priority nodes if the preceding subordinate node satisfies the pass / fail criteria for the preceding subordinate node, until evaluation of the subordinate nodes of each of the priority nodes is complete.

[0058] Example 5 is any of the methods of Examples 1 to 4, and the process of automatically designating the first priority node to be verified from among the priority nodes includes a process of designating the starting node of a predetermined diagnostic tree as the first priority node.

[0059] Example 6 is any of the methods of Examples 1 to 5, and the process of automatically designating the first priority node to be verified from among the priority nodes includes a process of determining a start node using an artificial intelligence function, and a process of designating the start node as the first priority node.

[0060] Example 7 is any of the methods of Examples 1 to 6, wherein the process of automatically designating the first priority node to be verified from among the priority nodes includes a process of receiving circuit diagram data and circuit simulation data in a computer-aided analysis tool, a process of generating a diagnostic tree that defines a sequence of nodes based on the circuit diagram data and the circuit simulation data, and a process of designating a starting node in the sequence of nodes in the diagnostic tree as the first priority node.

[0061] Example 8 includes the method of example 7, further comprising designating a successor node of the diagnosis tree as the second priority node, the successor node being later than the first priority node in the sequence of nodes.

[0062] Example 9 includes any of the methods of Examples 1 to 8, wherein the process of verifying whether the measurement signals from each of the first or second priority nodes meet the pass / fail criteria for each of the first or second priority nodes includes: acquiring measurement signals from each of the priority nodes; acquiring circuit simulation data including simulation signals corresponding to each of the priority nodes based on computer-aided analysis of the manufactured circuit; comparing the measurement signals from each of the priority nodes with the simulation signals corresponding to each of the priority nodes; classifying the measurement signals from each of the priority nodes as pass if the measurement signals from each of the priority nodes are within the pass / fail criteria for each of the priority nodes; and classifying the measurement signals from each of the priority nodes as fail if the measurement signals from each of the priority nodes are outside the pass / fail criteria for each of the priority nodes, wherein the pass / fail criteria for each of the priority nodes are based on a maximum desired variance from the simulation signals corresponding to each of the priority nodes.

[0063] Example 10 is the method of Example 9, wherein the process of acquiring the measurement signals from each of the priority nodes includes at least one of the following processes: providing a prompt to a human operator to position a probe coupled to a test and measurement device to acquire the measurement signals from each of the priority nodes; and causing an automated probing system to position the probe coupled to the test and measurement device and acquire the measurement signals from each of the priority nodes.

[0064] Example 11 is any of the methods of Examples 9 to 10, wherein the process of comparing the measurement signals from each of the priority nodes with the simulation signals corresponding to each of the priority nodes produces a comparison result, and the process of evaluating each of the priority nodes further includes a process of displaying the comparison result on a user interface.

[0065] Example 12 is any of the methods of Examples 1 to 11, and the process of automatically designating the second priority node to be verified from among the priority nodes includes a process of designating the next node in a predetermined diagnostic tree as the second priority node.

[0066] Example 13 is any of the methods of Examples 1 to 12, and the process of automatically designating the second priority node to be verified from among the priority nodes includes a process of determining the next node using an artificial intelligence function, and a process of designating the next node as the second priority node.

[0067] Example 14 is any of the methods of Examples 1 to 13, and the process of automatically specifying the first lower node to be verified from the priority node includes a process of specifying the next node in a predetermined diagnostic tree as the first lower node.

[0068] Example 15 is any of the methods of Examples 1 to 14, and the process of automatically designating the first lower node to be verified from among the priority nodes includes a process of determining the next node using an artificial intelligence function, and a process of designating the next node as the first lower node.

[0069] Example 16 includes a non-transitory computer-readable medium having stored thereon computer-executable instructions that, in response to execution by a computing device, cause the computing device to perform a plurality of steps, the plurality of steps including evaluating the first priority node by automatically designating a first priority node to be verified from among the group of priority nodes and verifying whether a measurement signal from the first priority node satisfies a pass / fail criterion for the first priority node; and designating a first priority node to be verified from among the group of priority nodes if the measurement signal from the first priority node satisfies the pass / fail criterion for the first priority node. evaluating the second priority node by automatically designating a second priority node that is on the same subportion of the fabricated circuit as the first priority node and determining whether a measurement signal from the second priority node satisfies a pass / fail criterion for the second priority node; and if the measurement signal from the first priority node does not satisfy the pass / fail criterion for the first priority node, evaluating the first subordinate node by automatically designating a first subordinate node from the group of subordinate nodes that is on the same subportion of the fabricated circuit as the first priority node and determining whether a measurement signal from the first subordinate node satisfies a pass / fail criterion for the first subordinate node.

[0070] Example 17 is the non-transitory computer-readable medium of Example 16, wherein the steps further include: evaluating the third priority node by automatically designating a third priority node from among the group of priority nodes for verification if the measurement signal from the second priority node meets a pass / fail criterion for the second priority node and determining whether the measurement signal from the third priority node meets the pass / fail criterion for the third priority node; and if the measurement signal from the second priority node does not meet the pass / fail criterion for the second priority node, automatically designating a second subordinate node from among the group of subordinate nodes for verification that is on the same subportion of the fabrication circuit as the second priority node and determining whether the measurement signal from the second subordinate node meets the pass / fail criterion for the second subordinate node.

[0071] Example 18 is the non-transitory computer-readable medium of any of Examples 16 to 17, wherein the steps further include, if a preceding preferred node meets the pass / fail criteria for the preceding preferred node, evaluating a subsequent preferred node until evaluation of each of the preferred nodes is complete.

[0072] Example 19 is the non-transitory computer-readable medium of any of Examples 16 to 18, wherein the steps further include, if a preceding subordinate node satisfies a pass / fail criterion for the preceding subordinate node, evaluating a subsequent subordinate node of each of the preferred nodes until evaluation of the subordinate nodes of each of the preferred nodes is complete.

[0073] Example 20 is a non-transitory computer-readable medium of any of Examples 16 to 19, wherein the process of automatically designating the first priority node to be verified from the group of priority nodes includes a process of designating a starting node of a predetermined diagnostic tree as the first priority node.

[0074] Example 21 is a non-transitory computer-readable medium of any of Examples 16 to 20, wherein the process of automatically designating the first priority node to be verified from among the priority nodes includes a process of determining a start node using an artificial intelligence function, and a process of designating the start node as the first priority node.

[0075] Example 22 is the non-transitory computer-readable medium of any of Examples 16 to 21, wherein the process of automatically designating the first priority node to be verified from among the priority nodes includes a process of receiving circuit diagram data and circuit simulation data in a computer-aided analysis tool, a process of generating a diagnostic tree that defines a sequence of nodes based on the circuit diagram data and the circuit simulation data, and a process of designating a starting node in the sequence of nodes in the diagnostic tree as the first priority node.

[0076] Example 23 includes the non-transitory computer-readable medium of Example 22, wherein the steps further include designating a successor node of the diagnosis tree as the second priority node, the successor node being later than the first priority node in the sequence of nodes.

[0077] The above-described versions of the disclosed subject matter have many advantages that have been described or that will be apparent to those skilled in the art. Nevertheless, not all of these advantages or features are required in every version of the disclosed devices, systems, or methods.

[0078] Additionally, the description herein refers to specific features. It should be understood that the technology disclosed herein includes all possible combinations of these specific features. For example, if a specific feature is disclosed in connection with a particular embodiment, that feature can also be used in connection with other embodiments, to the extent possible.

[0079] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, unless the circumstances preclude this possibility.

[0080] Furthermore, the term "comprises" and its grammatical equivalents are used herein to indicate that other components, features, steps, processes, or operations are optionally present. For example, "comprising" components A, B, and C or "something which comprises" components A, B, and C may include only components A, B, and C, or may include components A, B, and C along with one or more other components.

[0081] Although specific examples have been set forth for the convenience of explanation, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for automatic assistance in circuit verification performed by a computing device under program control, comprising: classifying one or more nodes of the manufacturing circuit as priority nodes and one or more nodes of the manufacturing circuit as subordinate nodes that are on the same sub-portion of the manufacturing circuit as at least one of the priority nodes; evaluating the first priority nodes by automatically designating a first priority node to be verified from among the priority nodes and by verifying whether a measurement signal from the first priority node satisfies a pass / fail criterion for the first priority node; a process of evaluating the second priority node by automatically designating a second priority node to be verified from among the priority nodes when the measurement signal from the first priority node satisfies the pass / fail criteria for the first priority node, and a process of checking whether the measurement signal from the second priority node satisfies the pass / fail criteria for the second priority node; evaluating the first subordinate node by automatically designating for verification a first subordinate node from among the subordinate nodes that is on the same subportion of the fabrication circuit as the first subordinate node if the measurement signal from the first subordinate node does not meet the pass / fail criteria for the first subordinate node; and determining whether the measurement signal from the first subordinate node meets the pass / fail criteria for the first subordinate node; A method comprising:

2. a process of evaluating the third priority node by automatically designating a third priority node to be verified from among the priority nodes if the measurement signal from the second priority node satisfies a pass / fail criterion for the second priority node, and a process of checking whether the measurement signal from the third priority node satisfies a pass / fail criterion for the third priority node; evaluating the second subordinate node by automatically designating for verification a second subordinate node from among the subordinate nodes that is on the same subportion of the fabrication circuit as the second subordinate node if the measurement signal from the second subordinate node does not meet the pass / fail criteria for the second subordinate node; and determining whether the measurement signal from the second subordinate node meets the pass / fail criteria for the second subordinate node; The method of claim 1 further comprising:

3. 2. The method of claim 1, further comprising the step of evaluating a subsequent priority node if the previous priority node meets the pass / fail criteria for said previous priority node, until evaluation of each of said priority nodes is complete.

4. 2. The method of claim 1, further comprising the step of evaluating subsequent subnodes of each of said priority nodes if the previous subnode satisfies the pass / fail criteria for said previous subnode, until evaluation of said subnodes of each of said priority nodes is complete.

5. 2. The method of claim 1, wherein the step of automatically designating the first priority node to be verified from among the priority nodes includes a step of designating a start node of a predetermined diagnosis tree as the first priority node.

6. A process of automatically designating the first priority node to be verified from among the priority nodes, receiving the circuit diagram data and the circuit simulation data in a computer-aided analysis tool; generating a diagnosis tree defining a sequence of nodes based on the circuit diagram data and the circuit simulation data; designating a starting node in the sequence of nodes of the diagnosis tree as the first priority node; 2. The method of claim 1, comprising:

7. determining whether the measurement signal from each of the first and second priority nodes satisfies the pass / fail criteria for each of the first and second priority nodes, acquiring measurement signals from each of the priority nodes; obtaining circuit simulation data including a simulation signal corresponding to each of the priority nodes based on a computer-aided analysis of the fabricated circuit; comparing the measured signals from each of the priority nodes with the simulated signals corresponding to each of the priority nodes; classifying the measurement signal from each of the priority nodes as passing if the measurement signal from each of the priority nodes is within pass / fail criteria for the respective priority node; classifying the measurement signals from each of the priority nodes as failing if the measurement signals from each of the priority nodes are outside the pass / fail criteria for each of the priority nodes; 2. The method of claim 1, wherein the pass / fail criteria for each of the priority nodes is based on a maximum desired variation from the simulation signal corresponding to each of the priority nodes.

8. The process of acquiring the measurement signals from each of the priority nodes includes: providing prompts to a human operator to position a probe coupled to a test and measurement device to obtain said measurement signals from each of said priority nodes; causing an automatic probing system to position the probe coupled to the test and measurement device and acquire the measurement signals from each of the priority nodes; 8. The method of claim 7, comprising at least one of:

9. A computer program comprising computer-executable instructions which, in response to execution by said computing device, cause said computing device to perform any of the methods of claims 1 to 8.

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