Digital Phase-Locked Loop

Abstract

A digital phase-locked loop circuit is provided that facilitates correction of group delay caused by an LPF and is capable of generating a phase-locked signal without being affected by distortion components even when targeting signals in a wide frequency range. [Solution] A digital phase-locked loop circuit includes a frequency range detection unit that includes an IIR-type LPF and measures the frequency of an input AC voltage or current, a square wave reference signal generation unit that includes multiple FIR-type LPFs and a zero-cross detector and generates a square wave reference signal from the input AC voltage or current, a switch that selects and switches one of the multiple FIR-type LPFs in accordance with the frequency of the input AC voltage or current measured by the frequency range detection unit, and a phase-locked loop signal generation unit that receives a square wave reference signal from the square wave reference signal generation unit formed by a signal from the FIR-type LPF selected by the switch and generates a phase-locked loop signal based on the square wave reference signal.

Description

[Technical Field]

[0001] The present invention relates to a digital phase-locked loop, and more particularly to a fully digital phase-locked loop used for phase synchronization of the input AC voltage or AC current of a bidirectional AC power converter. [Background technology]

[0002] In recent years, by using FPGAs (Field Program Gate Allays) and hardware description languages ​​(HDLs) to create electronic circuits that perform desired functions, it has become possible to implement them as small electronic chips without having to design custom LSIs such as ASICs.

[0003] Conventionally, ADPLL (All Digital Phase Locked Loop), which is a phase locked loop in which all components are digitalized, has been realized using HDL.

[0004] However, conventional ADPLLs are primarily used for phase synchronization of digital signals, such as clock signal synchronization, and have not been used as phase-locked loop circuits implemented in bidirectional AC power conversion devices.

[0005] The bidirectional AC power converter used as a simulated power supply or load is equipped with a phase-locked loop (PLL) to synchronize the output voltage or current with the input AC voltage or current from the device under test. The AC power input to the bidirectional AC power converter from the device under test contains distortion components (higher-order harmonics) and DC components due to disturbances. Therefore, it is necessary to remove these components from the input AC voltage or current using a high-pass filter (HPF) or low-pass filter (LPF).

[0006] FIG. 1 is a diagram showing a basic configuration for incorporating an ADPLL as a phase locked loop circuit implemented in a bidirectional AC power converter.

[0007] A phase locked loop 100 incorporating an ADPLL as a phase locked loop to be implemented in a bidirectional AC power conversion device must include an analog-to-digital converter (ADC) 102 that converts an input AC voltage or current 101, which is an analog signal, into a digital signal, an input unit 103, an ADPLL 104, and an output unit 108. In this configuration, the input unit 103 includes a high-pass filter (HPF) 106 and a low-pass filter (LPF) 107, and is intended to remove distortion components (high-order harmonics) and DC components due to disturbances contained in the input AC voltage or current 101.

[0008] The output section 105 includes a waveform bank RAM 108 and an AC gain 109, and is used to output the digital phase synchronization signal from the ADPLL as an AC voltage or current.

[0009] Furthermore, in order to realize the phase locked loop 100 using HDL, the input and output sections, excluding the ADC 102, must be digitized. Summary of the Invention [Problem to be solved by the invention]

[0010] 1, if the LPF 106 is implemented using a digital circuit, a phase delay occurs due to the LPF. Therefore, when the phase locked loop is digitized, it is necessary to perform delay correction of the output signal according to the phase delay of the LPF.

[0011] The frequency range of the AC voltage or current input to a bidirectional AC power converter is wide, from 40 Hz to 5 kHz. Therefore, when an infinite impulse response (IIR) LPF is used as the LPF, the phase delay changes depending on the frequency, making it difficult to correct the phase delay caused by the LPF when dealing with AC voltages or currents over a wide frequency range.

[0012] The phase characteristics of a finite impulse response (hereinafter referred to as "FIR") LPF are linear with respect to frequency, which makes it possible to easily correct phase delay. However, when targeting a wide frequency range from 40 Hz to 5 kHz, group delay correction has been difficult.

[0013] Furthermore, the frequencies of higher harmonics, which are distortion components caused by disturbances, change based on the frequency of the input AC voltage or current. Therefore, when a wide frequency range of input is targeted, as in the case of a bidirectional AC power converter, an FIR-type LPF, whose cutoff frequency characteristics are inferior to those of an IIR-type LPF, is unable to sufficiently remove harmonic components.

[0014] In view of these problems, the present disclosure aims to provide a digital phase-locked loop circuit that facilitates correction of group delay caused by an LPF and is capable of generating a phase-locked signal without being affected by distortion components even when targeting signals over a wide frequency range. [Means for solving the problem]

[0015] In order to solve such problems, one embodiment of the present disclosure is a digital phase synchronization circuit including: a frequency range detection unit including an infinite impulse response type low-pass filter and measuring the frequency of an input AC voltage or current; a square wave reference signal generation unit including a plurality of finite impulse response type low-pass filters and a zero-cross detector and generating a square wave reference signal from the input AC voltage or current; a switch that selects and switches one of the plurality of finite impulse response type low-pass filters in accordance with the frequency of the input AC voltage or current measured by the frequency range detection unit; and a phase synchronization signal generation unit that receives as input a square wave reference signal from the square wave reference signal generation unit formed by a signal from the finite impulse response type low-pass filter selected by the switch, and generates a phase synchronization signal based on the square wave reference signal.

[0016] The phase synchronization signal generating unit of the digital phase locked loop circuit of the present disclosure may include an LPF group delay compensator, which may include a plurality of ring buffers that are selected in response to the selection of the low-pass filter by the switch.

[0017] Yet another embodiment of the present disclosure may be configured to fix the signal output by the phase synchronization signal generation unit for a certain period of time from when the selection of the low-pass filter is switched by the switch.

[0018] The digital phase-locked loop of the present disclosure may be realized by hardware whose circuit configuration can be changed using a hardware description language. [Effects of the Invention]

[0019] In the digital phase-locked loop circuit of the present disclosure, the LPF filter of the square wave reference signal generation unit is realized by a finite impulse response type LPF with linear phase delay characteristics, and is switched according to the input frequency range. Furthermore, the frequency range detection unit uses an infinite impulse response type LPF with excellent frequency characteristics because it is not affected by phase delay.

[0020] This makes it possible to easily correct the group delay caused by the LPF contained in the rectangular wave signal input to the phase synchronization signal generation section at the subsequent stage, and provides a digital phase synchronization circuit that can generate a phase synchronization signal without being affected by distortion components even when targeting signals over a wide frequency range. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a diagram showing a basic configuration for incorporating an ADPLL as a phase locked loop circuit implemented in a bidirectional AC power conversion device. [Figure 2] 1 is a block diagram showing a schematic configuration of a phase locked loop according to a first embodiment of a digital phase locked loop of the present disclosure. [Figure 3]FIG. 10 is a diagram showing a frequency range in which the third low-pass filter and the fourth low-pass filter are switched by a switch. [Figure 4] FIG. 1 is a schematic diagram illustrating an example of a phase accumulator DDS. [Figure 5] FIG. 10 is a diagram for explaining the operation of the phase accumulator DDS. [Figure 6] FIG. 1 is a schematic diagram illustrating an example of an LPF group delay compensator. [Figure 7] FIG. 10 is a block diagram showing a schematic configuration of a phase locked loop according to a second embodiment of the digital phase locked loop of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the following description is an example, and some configurations may be changed without departing from the gist of the present disclosure. The same or similar reference numerals indicate the same or similar elements, and repeated explanations may be omitted. Numerical values ​​in the following description are examples, and other numerical values ​​may be used in the present disclosure without departing from the gist of the present disclosure.

[0023] (First embodiment) As shown in FIG. 2, one embodiment of the digital phase-locked loop circuit of the present disclosure is a digital phase-locked loop circuit including: a frequency range detection unit 207 including an infinite impulse response low-pass filter and measuring the frequency of an input AC voltage or current; a square wave reference signal generation unit 208 including a plurality of finite impulse response low-pass filters and a zero-cross detector and generating a square wave reference signal from the input AC voltage or current; a switch 211 that selects and switches one of the plurality of finite impulse response low-pass filters in accordance with the frequency measured by the frequency range detection unit; and a phase synchronization signal generation unit 204 that receives as input a square wave reference signal from the square wave reference signal generation unit formed by signals from finite impulse response low-pass filters 218 and 219 selected by switch 211 and generates a phase synchronization signal based on the square wave reference signal.

[0024] 2 shows a schematic configuration of a phase locked loop 200 according to a first embodiment of the digital phase locked loop of the present disclosure. In FIG. 2, the phase locked loop 200 is connected to an input AC voltage or current 201.

[0025] The phase locked loop 200 of this embodiment is intended for AC voltages or currents in a wide frequency range, and in this embodiment, an example will be described in which a wide frequency range of 40 Hz to 5 KHz is input, but the frequency range may be other ranges.

[0026] The phase locked loop 200 of this embodiment includes an input section 203 to which an input AC voltage or current converted into a digital signal by an A / D converter (ADC) 202 is input, a phase locked signal generating section 204, and an output section 205, and each section other than the ADC 202 is configured by a digital circuit.

[0027] The ADC 202 of the present disclosure is an analog-to-digital converter that digitizes an AC voltage or current signal input from the outside.

[0028] The input unit 203 is composed of a high-pass filter (HPF) 206, a frequency range detection unit 207, and a square wave reference signal generation unit 208. The HPF 206 is a high-pass filter that removes direct current (DC) components contained in the input AC voltage or current. In this embodiment, since the phase delay of the HPF in the target frequency range of the input AC voltage or current is negligibly small, an infinite impulse response (IIR) type digital filter can be used, but a finite impulse response (FIR) type digital filter may also be used. The input AC voltage or current from which the DC component has been removed by the HPF is output to the frequency range detection unit 207 and square wave reference signal generation unit 208, which are connected downstream.

[0029] The digital phase-locked loop of the present disclosure is composed of digital circuits except for the ADC, and may therefore be realized by hardware whose logical configuration can be changed using a hardware description language (HDL) such as FPGA (Field Program Gate Allay).

[0030] (Frequency range detection section) The frequency range detection unit 207 includes a first frequency detector 209 for the low frequency range, a second frequency detector 210 for the high frequency range, and a switch 211 .

[0031] The first frequency detector 209 includes a first low-pass filter (LPF) 212, a first zero-cross detector 213, and a first frequency counter 214. The second frequency detector 210 includes a second low-pass filter (LPF) 215, a second zero-cross detector 216, and a second frequency counter 217.

[0032] The first and second LPFs are used to remove distortion components (harmonic signal components) from the input AC voltage or current whose frequency range is to be detected. Here, the cutoff frequency of the first LPF is set to 300 Hz, and the cutoff frequency of the second LPF is set to 3 kHz.

[0033] The phase-locked loop has a wide frequency operating range, and the frequency of higher harmonics varies depending on the frequency. For example, the 50th harmonic of 50 Hz is 2.5 kHz, and the 50th harmonic of 1 kHz is 50 kHz. For this reason, multiple frequency detectors with LPFs corresponding to the frequency range to be measured are provided.

[0034] Furthermore, each LPF is configured as an IIR type. By using an IIR type LPF, the cutoff characteristics of frequencies above the cutoff frequency are improved, making it possible to increase the S / N ratio. The frequency range detector is advantageous in that it is not affected by phase delay.

[0035] In the first and second frequency detectors, the first and second zero-cross detectors respectively detect zero crosses of the output signals from the first and second LPFs, and the first and second frequency counters count the periods of the zero-cross signals and output them to the switch 211 in the subsequent stage.

[0036] In this embodiment, in order to appropriately cut harmonic components in the low frequency range and the high frequency range depending on the target frequency range, the frequency range detection unit 207 is provided with two frequency measuring devices, one for the low frequency range and one for the high frequency range, but three or more frequency measuring devices may be provided depending on the target frequency range.

[0037] The switch 211 is configured to output a selection signal sel to a selector 221 provided in the square wave reference signal generation unit 208, which selects and switches between the third and fourth low-pass filters 218, 219 of the square wave reference signal generation unit 208 according to the frequency range of the input AC voltage or current from the signals from the first and second frequency counters. This selection signal sel outputs a selector selection signal according to the frequency of the input AC voltage or current 201 measured in the frequency range detection unit 207, as will be described later.

[0038] The switch 211 generates a NOT_SEL_STS signal that is active high when the frequency of the input AC voltage or current is outside the target frequency range, and a NOT_SWITCH_STS signal that is active low for a certain period of time after switching of the low-pass filter, and outputs each signal to the phase synchronization signal generation unit 204. As will be described later, the phase synchronization signal generation unit 204 is configured to input this NOT_SWITCH_STS signal to the CE terminals of the first flip-flop circuit 229 and the second flip-flop circuit 230.

[0039] FIG. 3 is a diagram showing the frequency range in which the third low-pass filter 218 and the fourth low-pass filter 219 are switched by the switch 211. As shown in FIG.

[0040] 3 shows a low frequency range f1 in which the third low-pass filter 218 is selected and a high frequency range f2 in which the fourth low-pass filter 219 is selected. As shown in the figure, the low frequency range f1 is f min ≦f1≦f mid1 , the high frequency range f2 is f mid2 ≦f2≦f max In this way, f1 and f2 are set to f mid1 -f mid2 This prevents frequent switching at frequency boundaries due to jitter in the phase locked loop.

[0041] In addition, if the frequency range of the input AC voltage or current is f min If it is smaller than f max If the value is greater than f, the switcher zero It outputs a signal sel to select the generator.

[0042] If three or more frequency detectors are provided depending on the target frequency ranges, a square wave generator may be selected depending on the three or more frequency ranges. In this case, the hysteresis region may be set as shown in Figure 3 for two adjacent frequency ranges.

[0043] (Square wave reference signal generator) Returning to FIG. 2, the square wave reference signal generator 208 includes a third low-pass filter 218 for the low frequency range, a fourth low-pass filter 219 for the high frequency range, and f zero It includes a generator 220, a selector 221, and a third zero-cross detector 222.

[0044] The phase-locked loop of the present disclosure is intended for use in phase synchronization of the input AC voltage or current of a bidirectional AC power converter. The input AC voltage or current input to the bidirectional AC power converter contains distortion components (harmonic components). Therefore, for accurate phase detection, it is desirable to remove the harmonic components from the reference signal input to the phase-locked loop.

[0045] To remove harmonic components, an LPF that removes frequency components higher than the frequency range of the input AC voltage or current may be provided. However, because the frequency range of the input AC voltage or current targeted by the bidirectional AC power converter spans a wide frequency band from 40 Hz to 5 KHz, the cutoff frequency of the FIR LPF must be set to different values ​​for the low and high frequency ranges.

[0046] Therefore, in this embodiment, in order to remove distortion components (harmonic signal components) from the input AC voltage or current, a square wave reference signal generating unit 208 is used that is selectable between a third LPF 218 and a fourth LPF 219. Here, the cutoff frequency of the third LPF 218 is set to 300 Hz, and the cutoff frequency of the fourth LPF 219 is set to 3 kHz.

[0047] The plurality of LPFs 218, 219 included in the square wave generating unit of this embodiment are characterized by being configured as FIR type in order to easily compensate for the phase delay caused by the LPFs. By using FIR type LPFs, the phase delay becomes linear with respect to frequency. In other words, the time delay caused by the third and fourth LPFs becomes a constant group delay regardless of frequency. For example, when an FIR filter with a tap coefficient of 1 is used, the phase delay is half the number of taps. As a specific example, when the number of FIR taps is 256 and the control period Δts=4 μs, the group delay is 256 / (2×4×10 -6 ) = 0.512ms.

[0048] The outputs from the third and fourth LPFs are selected by a selector and input to the third zero cross detector 222 at the subsequent stage, where a square wave is generated and output from the square wave reference signal generator 208 .

[0049] The selector 221 selects the output from the third LPF 218, the output from the fourth LPF 219, and f zeroThe output of the generator 220 is selected in response to a selection signal sel from the switch 211 and output to the phase synchronization signal generating unit 204 at the subsequent stage.

[0050] Therefore, the signal from the third or fourth LPF selected according to the frequency of the input AC voltage or current is converted into a square wave by the square wave reference signal generating unit 208 and input to the subsequent phase synchronization signal generating unit 204 as the reference signal ref.

[0051] In the present embodiment, an example has been described in which the rectangular wave reference signal generating unit 208 includes two low-pass filters corresponding to the two frequency ranges set in the frequency range detecting unit 207. However, if three or more frequency detectors are provided according to the target frequency ranges, three or more low-pass filters may be provided that are selected according to the three or more frequency ranges.

[0052] (Phase synchronization signal generation section) Next, the phase synchronization signal generation unit 204 will be described with reference to Fig. 2. The phase synchronization signal generation unit 204 includes a third frequency counter 224, a phase detector 225, a phase lead / lag counter 226, a loop filter 227, a normalizing DDS 228, a first flip-flop circuit 229, a second flip-flop circuit 230, a phase accumulator DDS 231, a frequency limit circuit 232, a phase lock determinator 233, and an LPF group delay compensator 234, and is configured to output clock synchronization signal data dds[y-1:yz] to an output unit 205 that includes a waveform bank RAM 235 and an AC gain 236 that generate an analog output AC voltage or current.

[0053] The phase synchronization signal generating unit 204 is a PLL (phase locked loop) that receives the reference signal ref output from the rectangular wave reference signal generating unit 208, generates and outputs a phase synchronization signal based on the reference signal ref, and is realized entirely by digital circuits.

[0054] (Third frequency counter) The third frequency counter 224 is configured to count the periods of the reference signal ref input to the phase synchronization signal generator 204, and input the count value to the subsequent normalization DDS 228. A typical PLL uses only a phase difference signal, but the phase synchronization signal generator of this embodiment uses a combination of a phase change amount Δθ1 that becomes the center frequency of pclk, which is the synchronization signal output from the phase synchronization signal generator, and a phase change amount Δθ2 that controls the phase lead / lag from the center frequency of pclk, so that synchronization is always achieved as long as the input frequency is stable and within the target frequency range described above.

[0055] The third frequency counter 224 counts one period of the rectangular wave signal of the reference signal ref at the system control period Δts. The third frequency counter 224 is configured to be reset for each period of the reference signal ref. Therefore, the third frequency counter outputs a frequency count value ccnt for each period of the reference signal ref, and inputs it to the normalization DDS 228 at the downstream stage.

[0056] The third frequency counter is also configured to output a CCNT_STS signal indicating whether the third frequency counter is in an overflow state to a phase lock determiner 233, which will be described later. Here, when the third frequency counter is in an overflow state, the CCNT_STS signal becomes active high.

[0057] (phase detector) The phase detector 225 detects the phase lead or lag of the signal, which is the feedback of the phase synchronization signal output from the phase synchronization signal generator, using the reference signal ref as a reference. The phase detector 225 compares the phase of the reference signal ref with that of the signal, and outputs a LEAD signal if the phase of the signal leads the reference signal ref, a LAG signal if the phase lags, and a MATCH signal if the phase matches. These signals are generated in synchronization with the reference signal ref every cycle ti of the input frequency, and are internally processed at control cycle intervals Δts.

[0058] (Phase Advance / Delay Counter) Next, the phase advance / delay counter 226 will be described. The phase advance / delay counter 226 is configured to count the phase difference between the reference signal ref and the signal at the control period Δts and output it as the phase difference count value pcnt. The phase difference count value pcnt is output every period ti of the reference signal ref. The phase difference count value pcnt counted by the phase advance / delay counter 226 is negative in the case of phase advance, positive in the case of phase delay, and 0 when the phases match.

[0059] Also, the phase advance / delay counter 226 is configured to output a PCNT_STS signal, which is information indicating whether the counted phase advance / delay is within a predetermined range, to a phase lock discriminator 233 described later. In this embodiment, it is determined whether the counted phase advance / delay is within a predetermined range by -5 < pcnt < 5, and when the phase count value pcnt is within this range, the OCNT_STS signal is set to active high. However, the range of the phase count value pcnt may be other than this.

[0060] (Loop Filter) The phase difference count value pcnt is output to the loop filter 227. The loop filter 227 calculates a moving average of the phase difference count value pcnt for several periods of the reference signal ref and outputs the phase difference average count value pcnt ave configured to do so. By using the moving average of the phase difference count value pcnt to perform subsequent processing, the moving synchronization operation is stabilized even when the phase difference fluctuates greatly temporarily. Although not limited, here, it is configured to calculate a moving average for 16 periods and output it to the subsequent stage.

[0061] Also, the loop filter 227 is configured to output a pcnt avg _STS signal, which is information indicating whether the output phase difference average count value pcnt avg is within a predetermined range, to the phase lock discriminator 233 described later. In this embodiment, the output phase difference average count value pcntavg Determine whether it is within a predetermined range with -5 < pcnt < 5, and the phase difference average count value pcnt avg When pcnt is within this range avg _STS signal is set to active high, but the range of the phase difference average count value pcnt avg may be otherwise

[0062] (Normalized DDS) The normalized DDS 228 performs a process of converting from the frequency count value ccnt and the phase difference average count value pcnt ave to the phase change amount Δθ that can be used by the subsequent phase accumulator DDS 231

[0063] Specifically, from the frequency count value ccnt and pcnt ave to the phase change amount Δθ that is the frequency of the reference signal ref to be synchronized, that is, the center frequency of pclk output from the synchronization control unit, 1と the phase change amount Δθ2 for controlling the phase advance / delay from the center frequency of pclk is output

[0064] Assuming that the phase change amount Δθ1 is related to the frequency count value ccnt, the control period Δts, and the period of the reference signal ref as ti, and ccnt = ti / Δts, then Δθ1 = 2 y ·Δts / ti = 2 y / ccnt, where y is the number of bits of the normalized DDS 228

[0065] Also, the phase change amount Δθ2 is obtained as follows

[0066] pcnt ave is the average value of the phase difference, so the phase difference ratio between the reference signal ref and the output signal signal of the phase control unit is pcnt ave / ccnt. Let the value converted from this phase difference ratio to the input value of the phase accumulator DDS be Δθe, then Δθe = (pcnt ave / ccnt) · Δθ1

[0067] Since Δθe is the phase difference itself, if it is used as is, the control amount will be too large and oscillation will occur. Therefore, here, during the transition of the ADPLL, Δθ2 = (1 / 2 5 )·Δθe, while ADPLL is stable, Δθ2=(1 / 2 7 )·Δθe. In this way, the normalized DDS228 uses the phase difference ratio to normalize the amount of phase change in the ADPLL so that it has the same ratio regardless of frequency.

[0068] (flip-flop circuit) The Δθ1 and Δθ2 output from the normalized DDS 228 are latched in a first flip-flop circuit 229 and a second flip-flop circuit 230, which operate at a control period Δts, and output to a DDS phase accumulator 231. The two flip-flop circuits are connected so that the NOT_SWITCH_STS signal from the switch 211 is input to the CE terminal. The switch 211 is configured to output an active low signal as the NOT_SWITCH_STS signal for a fixed period of time from when the low-pass filter is switched.

[0069] Therefore, when the low-pass filter is switched by switch 211, first flip-flop circuit 229 and second flip-flop circuit 230 do not update Δθ1 and Δθ2 held therein for a certain period of time. As a result, the frequency and phase of the output from the phase synchronization signal generation unit are fixed for a certain period of time. In this way, the phase synchronization signal generated by phase synchronization signal generation unit 204 is not affected by the difference in group delay between third LPF 218 and fourth LPF 219 provided in square wave reference signal generation unit 208 when the LPFs are switched.

[0070] This certain time may be equal to or longer than the group delay time of the switched LPF, but in this embodiment, it is set to two periods of the reference signal ref so that updating is performed in accordance with the zero crossings of the third zero crossing detector. This also prevents the influence of past data remaining when switching the ring buffer of the LPF group delay compensator (described later).

[0071] (Phase accumulator DDS) The phase accumulator DDS 231 can change the output frequency at a fixed control period Δts. In this embodiment, the phase accumulator DDS is used as the oscillator of the phase synchronization signal generator 204. The phase accumulator DDS 231 operates to add the phase change amount (Δθ1+Δθ2), such as dds[y-1:0]=dds[y-1:0]+(Δθ1+Δθ2). In the following, a case where the number of bits y of the DDS is 32 will be described, but the number of bits of the DDS may be other than this.

[0072] The DDS shown as an example in Figure 4(a) operates as follows: dds[31:0] = dds[31:0] + (Δθ1 + Δθ2)[31:0]. As shown in Figure 4(a), the DDS uses a D-FF (register) to hold the output dds[31:0]. Here, dds[31:0] expresses values ​​from 0d to 4294967295d by concatenating 32 bits in descending order as shown in Figure 4(b). Note that the final d in the number indicates a decimal number. CE is input to the D-FF 410 in Figure 4(a) at control period Δts intervals. Each time CE is input, (Δθ1 + Δθ2) is added. For ease of explanation, the following describes the operation of the DDS when the phase change amount (Δθ1 + Δθ2) is a constant Δθ.

[0073] If the value of Δθ is small, it takes time for dds[31:0] to reach a full count. The value of Δθ determines the period t of the output frequency. o The phase change amount Δθ and the output period t o The relationship is Δθ=(2 y ·Δts) / t oIt is expressed as:

[0074] If Δθ is added to dds[31:0], which is a full count, dds[31:0] becomes 0d. The full count of dds is expressed in binary as follows: dds[31:0]=4294967295d=1111_1111_1111_1111_1111_1111_1111b. Note that the b at the end of the number indicates a binary number. Underscores are placed between the numbers to make the number of digits easier to read. In this case, for example, if 1b is added, the result is 1_0000_0000_0000_0000_0000_0000_0000_0000_0000b, but since the 33rd bit does not exist, the carry 1 disappears and dds[31:0] becomes 0d. Adding 5d to dds[31:0]=4294967295d results in dds[31:0]=4d. In this way, even if Δθ is added to this phase accumulator DDS, dds[31:0] does not become 0d, so addition is always performed at Δθ intervals, and continuity is maintained because the intervals are equal.

[0075] Figure 5(a) shows the period t when Δθ is changed. o In this example, t o When the value of Δθ at =10 ms is doubled, t o = 20 ms. Figure 5(b) is a diagram explaining how to create a periodic waveform (phase clock). As shown in the figure, dds[31:0] is added by Δθ, so the inversion of the most significant bit, dds

[31] , becomes the periodic waveform (phase clock), pclk.

[0076] dds[31:0] is 0000_0000_0000_0000_0000_0000_0000_0000b~ 0111_1111_1111_1111_1111_1111_1111_1111b and 1000_0000_0000_0000_0000_0000_0000_0000b~ 1111_1111_1111_1111_1111_1111_1111_1111b As shown here, in these two ranges, the only difference is that dds

[31] is 0 or 1, and dds[30:0] is the exact same value. o During this time, the interval where dds

[31] =0 and the interval where dds

[31] =1 are the same time. The inverse of this dds

[31] is called a phase clock or pclk (Phase Clock).

[0077] As explained above, the phase accumulator DDS 231 uses the data of dds

[31] to calculate the output period t according to the input phase change amount Δθ. o can be output as pclk.

[0078] The data of dds[31:0] from the phase accumulator DDS 231 is used as a read address of a WaveBankRAM 235 in which waveform data, which will be described later, is stored.

[0079] (Operation taking θ2 into consideration) As shown in Figure 4(a), the phase accumulator DDS 231 receives a phase change amount Δθ1, which is the center frequency of the pclk output from the synchronization control unit, and a phase change amount Δθ2, which controls the phase lead / lag from the center frequency of the pclk. As described above, Δθ1 is determined by the frequency count value ccnt of the third frequency counter 224, and is therefore instantaneously reflected for each period ti of the reference signal ref. Δθ2 controls the phase lead / lag from the center frequency, i.e., the phase change amount of the pclk output from the phase control unit. As described above, Δθ2 is determined by the moving average of the loop filter, and therefore the phase gradually synchronizes.

[0080] When Δθ2>0, the input Δθ becomes larger, so the frequency of pclk becomes higher, and as a result, the phase can be advanced. Also, when Δθ2<0, the input Δθ becomes smaller, so the frequency of pclk becomes lower, and as a result, the phase can be delayed.

[0081] (Frequency limit circuit) The frequency limit circuit 232 is configured to determine whether the frequency of the pclk output from the phase accumulator DDC 231 is within the specification range or not, and to output an OUT_OF_RANGE_STS signal indicating whether the frequency of the pclk is outside the specification range or not to the phase lock determinator. pclk But, f min1 <f pclk <f max1 where f min1 =f min -f min Margin,f max1 =f max +f max In this embodiment, the margin is set to 6.25%. min and f max is determined appropriately based on the specifications, but as described above, in this embodiment, f min is 40Hz, f max is 5KHz.

[0082] (Phase lock detector) The phase lock determinator 233 is for notifying an external system of the operating state of the phase synchronization signal generator 204. The phase lock determinator 233 receives the NOT_SEL_STS signal and NOT_SWITCH_STS signal from the switch 211, the CCNT_STS signal from the third frequency counter 224, the PCNT_STS signal from the phase lead / lag counter 226, the pcnt_STS signal from the loop filter 227, and the NOT_SEL_STS signal from the switch 211. avg The OUT_OF_RANGE_STS signal from the phase synchronization signal generator 232 and the OUT_OF_RANGE_STS signal from the frequency limit circuit 232 are input to the OUT_OF_RANGE_STS signal generator 232, and these signals are used to determine the operating state of the phase synchronization signal generator as follows.

[0083] The phase lock determiner 233 determines that the phase is in an unlocked state when the following three conditions are met: the input frequency is outside the specification range (the NOT_SEL_STS signal is active high), a certain time has passed since the square wave generator was switched (the NOT_SWITCH_STS signal is active high), and the third frequency counter has overflowed (the CCNT_STS signal is active high).

[0084] Also, pcnt avg is within the range of ±5 (pcnt avg The lock state is determined when the following three conditions are met: pcnt is within ±5 (PCNT_STS signal is active high), pcnt is within ±5 (PCNT_STS signal is active high), and the input frequency is within the specification range (NOT_SEL_STS signal is active low).

[0085] And pcnt avg is outside the range of ±5 (pcnt avg A state transition is determined to be occurring when the following three conditions are met: pcnt is within the range of ±5 (PCNT_STS signal is active low), pcnt is within the range of ±5 (PCNT_STS signal is active low), and the input frequency is within the specification range (NOT_SEL_STS signal is active low).

[0086] (LPF group delay compensator) The reference signal ref input to the phase synchronization signal generation unit 204 contains a group delay caused by the third LPF 218 or the fourth LPF 219 included in the square wave reference signal generation unit 208. For this reason, the phase synchronization signal generation unit 204 includes an LPF group delay compensator 234 in the feedback loop of pclk, which delays the pclk output from the phase control unit by the amount of the group delay.

[0087] In the digital phase-locked loop of the present disclosure, the LPF of the square wave reference signal generating unit 208 that forms the reference signal ref input to the phase synchronization signal generating unit 204 is configured as an FIR type, and therefore the delay caused by the LPF is a group delay having a linear characteristic with respect to frequency. Therefore, the LPF group delay compensator can easily perform correction by using a ring buffer or the like as exemplified in FIG.

[0088] Fig. 6 shows an example of an LPF group delay compensator using ring buffers. The LPF group delay compensator 600 in Fig. 6 includes a first ring buffer 610 and a second ring buffer 620 that operate with a control period Δts to compensate for the group delay of the third LPF and the fourth LPF.

[0089] An example will be described in which the group delay of 0.512 ms is corrected when the control period Δts is 4 μs, the tap coefficient is 1, and the order of the FIR filter is 256.

[0090] To correct this group delay, the value 128 addresses before in the ring buffer is used as the signal for phase difference detection. In this case, the amount of delay to be corrected is 128 x 4 μs = 0.512 ms. Specifically, if pclk data is written to address 1, the data at address 129 is read. After the next Δts has elapsed, pclk is written to address 2 and the data at address 130 is read. In this way, the address difference between writing and reading is fixed at 128, and the data from 128 addresses before is output.

[0091] 6, there are provided a first ring buffer 610 corresponding to the group delay amount of the third LPF, a second ring buffer 620 corresponding to the group delay amount of the fourth LPF, and a selector 630 that switches between the outputs from the two ring buffers and outputs the signal using a signal SEL from a switch 211. When realizing a delay circuit using HDL, there are advantages such as requiring fewer logic resources if a delay is performed using memory rather than using multiple stages of registers to perform a delay.

[0092] (output section) The output unit 205, the phase synchronization signal generation unit 204 of the movement synchronization circuit of this embodiment, uses dds[y-1:0] from the phase accumulator DD231S as a read address to read waveform data stored in the waveform bank RAM 235, and multiplies the value by ACGAIN236 to form an analog synchronization signal with adjusted amplitude.

[0093] In Figure 2, if the number of bits in the waveform bank RAM address is z (y>z), dds[y-1:yz] is used as the bit read address. For example, if the number of bits y in the DDS is 32 and the number of bits z in the waveform bank RAM is 12, the upper 12 bits, dds[31:20], are set to be used as the read address.

[0094] (Second embodiment) Next, a second embodiment of the digital phase-locked loop of the present disclosure will be described with reference to Fig. 7. A phase-locked loop 700 of this embodiment is different in that a square wave reference signal generating unit 702 includes multiple square wave generators 703 and 704, and a switch 211 is configured to select and switch one of the multiple square wave generators according to the frequency measured by the frequency range detecting unit.

[0095] That is, the phase locked loop circuit of this embodiment is a digital phase locked loop circuit that includes a frequency range detection unit 207 that includes an infinite impulse response type low-pass filter and measures the frequency of the input AC voltage or current, a square wave reference signal generation unit 702 that includes a finite impulse response type low-pass filter and a zero-cross detector and has a plurality of square wave generators that output square waves from the input AC voltage or current, a switch 211 that selects and switches one of the plurality of square wave generators according to the frequency measured by the frequency range detection unit, and a phase locked loop signal generation unit 204 that receives as input a square wave reference signal from a square wave generation circuit 703, 704 selected by the switch 211 and generates a phase locked loop signal based on the square wave reference signal.

[0096] Fig. 7 shows a schematic configuration of a phase-locked loop 700 according to this embodiment of the digital phase-locked loop of the present disclosure. Fig. 7 also illustrates a case where the phase-locked loop 700 is connected to an input AC voltage or current 201. Like the first embodiment of Fig. 2, the phase-locked loop 700 according to this embodiment is also intended for AC voltages or currents over a wide frequency range. In this embodiment, a case where a wide frequency range of 40 Hz to 5 KHz is input will be described as an example, but the frequency range may be other than this.

[0097] The phase locked loop 700 of this embodiment includes an input unit 701 to which an input AC voltage or current converted into a digital signal by an A / D converter (ADC) 202 is input, a phase locked signal generating unit 204, and an output unit 205, and each unit other than the ADC 202 is configured by a digital circuit. In Fig. 7, the same reference numerals as in Fig. 2 are assigned to the same components as in Fig. 2, and therefore will not be described in detail here.

[0098] The input unit 701 is made up of a high-pass filter (HPF) 206 , a frequency range detection unit 207 , and a square wave reference signal generation unit 702 .

[0099] The digital phase-locked loop of this embodiment is also composed of digital circuits except for the ADC, and therefore may be realized by hardware whose logical configuration can be changed using a hardware description language (HDL) such as FPGA (Field Program Gate Allay).

[0100] (Square wave reference signal generator) The square wave reference signal generating unit 702 of this embodiment includes a first square wave generator 703 for a low frequency range, a second square wave generator 704 for a high frequency range, and f zero The first square wave generator 703 includes a generator 705 and a selector 706. The first square wave generator 703 includes a third low-pass filter (LPF) 707 and a third zero-cross detector 708. The second square wave generator 704 includes a fourth low-pass filter (LPF) 709 and a fourth zero-cross detector 710.

[0101] In this embodiment as well, in order to remove distortion components (harmonic signal components) from the input AC voltage or current, two square wave generators are used, which include a third LPF 707 and a fourth LPF 709. Here, the cutoff frequency of the third LPF is set to 300 Hz, and the cutoff frequency of the fourth LPF is set to 3 kHz.

[0102] This embodiment is also characterized in that the LPFs provided in the rectangular wave generating circuits 703 and 704 are configured as FIR types in order to easily compensate for the phase delay caused by the LPFs.

[0103] In the square wave reference signal generating unit 702, the outputs from the third and fourth LPFs are input to the subsequent third and fourth zero cross detectors, respectively, to generate square waves, which are then output from the first square wave generator 703 and the second square wave generator 704.

[0104] The selector 706 selects the output from the first square wave generator 703, the output from the second square wave generator 704, and f zero The output of the generator 705 is selected in response to a selection signal sel from the switch 211 and output to the phase synchronization signal generating unit 204 at the subsequent stage.

[0105] Therefore, the rectangular wave from the rectangular wave reference signal generating unit 702, which is selected according to the frequency of the input AC voltage or current, is input as a reference signal ref to the subsequent phase synchronization signal generating unit 204.

[0106] In the present embodiment, an example has been described in which the square wave reference signal generating unit 702 includes two square wave generators corresponding to the two frequency ranges set in the frequency range detecting unit 207. However, if three or more frequency detectors are provided according to the target frequency ranges, three or more square wave generators may be provided that are selected according to the three or more frequency ranges.

[0107] The phase synchronization signal generating section 204 and the output section 205 are the same as those in the first embodiment, and therefore a description thereof will be omitted here. [Explanation of symbols]

[0108] 200, 700... Phase locked circuit 201 Input AC voltage or current 202 Analog-to-Digital Converter (ADC) 203, 701... Input section 204... Phase synchronization signal generation section 205 Output section 206 High-pass filter (HPF) 207 Frequency range detector 208, 702... Square wave reference signal generator 209 First frequency detector 210 Second frequency detector 211·············Switch 212: First low-pass filter (LPF) 213 First zero-cross detector 214 First frequency counter 215 Second low-pass filter (LPF) 216 Second zero-cross detector 217 Second frequency counter 218, 707...Third low-pass filter (LPF) 219, 709...Fourth low-pass filter (LPF) 220, 705...f zero generator 221, 706·········Selector 222 Third zero-cross detector 224...Third frequency counter 225 Phase Detector 226 Phase lead / lag counter 227 Loop filter 228...Normalized DDS 229 First flip-flop circuit 230 Second flip-flop circuit 231 Phase Accumulator DDS 232 Frequency limit circuit 233 Phase lock determiner 234 LPF group delay compensator 235 Waveform bank RAM 236 AC gain 600 LPF group delay compensator 610 First ring buffer 620 Second ring buffer 630·············Selector 703 First square wave generator 704 Second Square Wave Generator 708 Third zero-cross detector 710: Fourth zero-cross detector

Claims

1. A frequency range detection unit including an infinite impulse response type low pass filter, the frequency detector including a plurality of frequency detectors for detecting a predetermined frequency range from the output of the infinite impulse response type low pass filter to which an input AC voltage or current is input, the frequency detectors each having a different cutoff characteristic of the infinite impulse response type low pass filter and configured to distinguish and measure different frequency ranges of the input AC voltage or current; a square wave reference signal generating unit which receives the input AC voltage or current, and includes a plurality of finite impulse response low-pass filters and a zero-cross detector, each having a cutoff characteristic corresponding to the cutoff characteristic of the infinite impulse response low-pass filter of each of the plurality of frequency detectors, and which generates a square wave reference signal from the input AC voltage or current by inputting outputs from the finite impulse response low-pass filters to the zero-cross detector; a switch that selects and switches one of the plurality of finite impulse response low-pass filters in accordance with the frequency range of the input AC voltage or current measured by the frequency range detection unit; a phase synchronization signal generation unit that receives a rectangular wave reference signal from the rectangular wave reference signal generation unit, the rectangular wave reference signal being generated by inputting an output from the finite impulse response low-pass filter selected by the switch to the zero-crossing detector, and that generates a phase synchronization signal based on the rectangular wave reference signal; A digital phase locked loop circuit.

2. 2. The digital phase-locked loop circuit according to claim 1, wherein the phase-locked signal generating unit includes an LPF group delay compensator.

3. 3. The digital phase-locked loop circuit according to claim 2, wherein the LPF group delay compensator includes a plurality of ring buffers that are selected in response to selection of the finite impulse response type low-pass filter by the switch.

4. 2. The digital phase-locked loop circuit according to claim 1, wherein the signal output by the phase-locked signal generating unit is fixed for a certain period of time from when the selection of the finite impulse response type low-pass filter is switched by the switch.

5. 2. The digital phase-locked loop circuit according to claim 1, wherein each frequency range detected by each frequency detector is set so as to have an area that partially overlaps with each adjacent frequency range, and this overlapping area is set as a hysteresis area for selection of the plurality of finite impulse response type low-pass filters.

6. 6. The digital phase-locked loop circuit according to claim 1, which is realized by hardware whose circuit configuration can be changed using a hardware description language.

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