Semiconductor substrate, its manufacturing method and manufacturing apparatus, GaN-based crystal, semiconductor device, electronic device

Abstract

A semiconductor substrate according to the present invention is provided with a main substrate, a mask pattern that is positioned above the main substrate and includes a mask section, and adjacent first and second semiconductor sections that are positioned above the mask pattern. The first semiconductor section has a first lower edge positioned on the mask section and a first protruding part that projects further to the second semiconductor section side than the first lower edge.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor substrate and the like. [Background technology]

[0002] For example, Patent Document 1 discloses a technique for forming a plurality of semiconductor layers corresponding to the openings of a plurality of masks by using an ELO (Epitaxial Lateral Overgrowth) method. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2011-66390 Summary of the Invention

[0004] The semiconductor substrate according to the present disclosure comprises a main substrate, a mask pattern located above the main substrate and including a mask portion, and adjacent first and second semiconductor portions located above (in an upper layer of) the mask pattern, wherein the first semiconductor portion has a first lower edge located above the mask portion and a first protrusion portion that protrudes further toward the second semiconductor portion than the first lower edge. [Brief explanation of the drawings]

[0005] [Figure 1] 1A and 1B are a plan view and a cross-sectional view showing the configuration of a semiconductor substrate according to an embodiment of the present invention; [Figure 2] FIG. 10 is a cross-sectional view showing another configuration of the semiconductor substrate according to the embodiment. [Figure 3] 1 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to the present embodiment. [Figure 4] 1 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to an embodiment of the present invention; [Figure 5] 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] FIG. 10 is a plan view showing an example of separation of an element portion. [Figure 7] 10A and 10B are cross-sectional views showing an example of separation and isolation of element portions. [Figure 8] 1 is a schematic diagram illustrating a configuration of an electronic device according to an embodiment of the present invention. [Figure 9] FIG. 10 is a schematic diagram showing another configuration of the electronic device according to the embodiment. [Figure 10] 1A and 1B are a plan view and a cross-sectional view showing the configuration of a semiconductor substrate according to a first embodiment. [Figure 11] FIG. 1 is a cross-sectional view showing an example of lateral growth of an ELO semiconductor layer. [Figure 12] 4 is a cross-sectional view showing another configuration of the semiconductor substrate according to the first embodiment. FIG. [Figure 13] FIG. 10 is a cross-sectional view showing another configuration of the semiconductor substrate according to the embodiment. [Figure 14] 1A and 1B are plan views showing a process of separating an element portion in Example 1. FIG. [Figure 15] 4A to 4C are cross-sectional views showing a step of separating element parts in Example 1. [Figure 16] 4 is a cross-sectional view showing another configuration of the semiconductor substrate of the first embodiment. FIG. [Figure 17] 3 is a cross-sectional view showing another configuration of the semiconductor substrate 10 of the first embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing another example of separation of element portions. [Figure 19] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to a second embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing another configuration of the semiconductor substrate according to the second embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing another configuration of the semiconductor substrate of the second embodiment. [Figure 22] FIG. 10 is a cross-sectional view showing another configuration of the semiconductor substrate of the second embodiment. [Figure 23] FIG. 10 is a schematic cross-sectional view showing the configuration of Example 4. [Figure 24] FIG. 10 is a cross-sectional view showing an example of application of the fourth embodiment to an electronic device. [Figure 25]FIG. 10 is a schematic cross-sectional view showing the configuration of Example 5. [Figure 26] FIG. 10 is a cross-sectional view showing the configuration of Example 6. [Figure 27] FIG. 10 is a cross-sectional view showing the configuration of Example 7. DETAILED DESCRIPTION OF THE INVENTION

[0006] [Semiconductor substrate] FIG. 1 is a plan view and a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIG. 1, the semiconductor substrate 10 (semiconductor wafer) according to this embodiment includes a main substrate 1 (only the upper surface and its vicinity are shown), a mask pattern 6 located above the main substrate 1 and including a mask portion 5, and a first semiconductor portion 8F and a second semiconductor portion 8S located above the mask pattern 6 and adjacent to each other. The first semiconductor portion 8F has a first lower edge 8c located above the mask portion 5 and a first protruding portion H1 that protrudes toward the second semiconductor portion 8S beyond the first lower edge 8c in a plan view. The mask pattern 6 can include a first opening K1 and a second opening K2 adjacent to each other in a first direction (hereinafter, X direction), and a mask portion 5 located between the first opening K1 and the second opening K2.

[0007] The first overhanging portion H1 may have any structure as long as it overhangs the first lower edge 8c in the X direction. While the end face of the first overhanging portion H1 in FIG. 1 includes two faces, this is not limited thereto and may include only one face, or three or more faces. The face included in the end face of the first overhanging portion H1 may be flat or curved. The first overhanging portion H1 may include the first lower edge 8c and have a face EC that is not perpendicular to the X direction.

[0008] The semiconductor substrate 10 may have an underlayer 4 including a seed portion 3S above the main substrate 1, and the first semiconductor portion 8F may be configured to contact the seed portion 3S at the first opening K1. The first and second openings K1 and K2 may be tapered (having a shape that narrows toward the underlayer 4). The underlayer 4 may be formed so as to overlap at least the first and second openings K1 and K2.

[0009] In the semiconductor substrate 10, multiple layers are stacked on the main substrate 1, and the stacking direction can be referred to as the "upward direction." Also, viewing the semiconductor substrate 10 from a line of sight parallel to the normal direction of the semiconductor substrate 10 can be referred to as a "planar view." A semiconductor substrate refers to a substrate that includes a semiconductor portion, and the main substrate 1 may be a semiconductor or a non-semiconductor. In this specification, the main substrate 1 and the base layer 4 are collectively referred to as the base substrate UK, and the main substrate 1, the base layer 4, and the mask pattern 6 are collectively referred to as the template substrate (substrate for ELO) 7.

[0010] The first semiconductor portion 8F includes, for example, a nitride semiconductor. A nitride semiconductor can be expressed, for example, as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The first semiconductor portion 8F may be doped (for example, n-type containing donors) or non-doped.

[0011] The first semiconductor portion 8F including a GaN-based semiconductor can be formed by the ELO (Epitaxial Lateral Overgrowth) method, but other methods may be used as long as they can achieve low defects. In the ELO method, for example, a heterogeneous substrate having a lattice constant different from that of the GaN-based semiconductor is used as the main substrate 1, a GaN-based semiconductor is used for the seed portion 3S, an inorganic compound film is used for the mask pattern 6, and the GaN-based first semiconductor portion 8F can be grown laterally on the mask portion 5. In this case, the thickness direction (Z direction) of the first semiconductor portion 8F is set to the thickness direction (Z direction) of the GaN-based crystal. <0001> The width direction (first direction, X direction) of the longitudinal first and second openings K1 and K2 can be the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y direction) of the first and second openings K1 and K2 can be the <1-100> direction (m-axis direction) of the GaN-based crystal. A layer formed by the ELO method is sometimes referred to as an ELO semiconductor layer (including the first semiconductor portion 8F).

[0012] The first semiconductor portion 8F formed by the ELO method includes a dislocation inheritance portion NS that overlaps with the first opening K1 in a planar view, and a low-defect portion EK (dislocation non-inheritance portion) that overlaps with the mask portion 5 in a planar view and has fewer threading dislocations than the dislocation inheritance portion NS. If an active layer (for example, a layer in which electrons and holes recombine) is included above the first semiconductor portion 8F, the active layer can be provided so as to overlap with the low-defect portion EK in a planar view.

[0013] The portion of the first semiconductor portion 8F that overlaps with the mask portion 5 in plan view may be made of a GaN-based crystalline body that includes a GaN-based semiconductor and has an upper surface 8J and a lower surface 8U that are parallel to the (0001) plane (c-plane). <0001> The density of non-threading dislocations in a cross section parallel to the <1-100> direction is equal to or greater than the density of threading dislocations on the upper surface 8J, and the crystal grain has a lower edge 8c parallel to the <1-100> direction and a protruding portion (overhanging portion) H1 protruding in the <11-20> direction beyond the lower edge. <0001> The cross section parallel to the direction is, for example, the (1-100) plane (m-plane) or the (11-20) plane (a-plane).

[0014] Threading dislocations are dislocations (defects) that extend from the lower surface or interior of the first semiconductor portion 8F to its surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8F. Threading dislocations can be observed by performing CL (Cathode Luminescence) measurement on the surface (parallel to the c-plane) of the first semiconductor portion 8F. Non-threading dislocations are dislocations that are measured by CL in a cross section taken along a plane parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.

[0015] 2 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. As shown in FIG. 2, the semiconductor substrate 10 includes a main substrate 1, a base layer 4, a mask pattern 6, first and second semiconductor portions 8F-8S, a first functional layer 9F above the first semiconductor portion 8F, and a second functional layer 9S above the second semiconductor portion 8S. In plan view, the first semiconductor portion 8F and the first functional layer 9F overlap, and the second semiconductor portion 8S and the second functional layer 9S overlap. Each of the first and second functional layers 9F-9S may be a single layer or a laminate.

[0016] The first functional layer 9F may have at least one of a function as a component of a semiconductor device, an optical function, and a sensing function.

[0017] 2, because the first semiconductor portion 8F has the first protruding portion H1, during the formation of the first and second functional layers 9F and 9S, raw materials are less likely to reach the mask portion 5 located between the first and second semiconductor portions 8F and 8S, reducing the formation of deposits. In addition, the first functional layer 9F formed above the first semiconductor portion 8F is less likely to be formed below the top 8P of the first protruding portion H1, reducing the risk of the first functional layer 9F and the second functional layer 9S joining together.

[0018] [Manufacturing of semiconductor substrates] 3 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to this embodiment. In the method for manufacturing a semiconductor substrate shown in FIG. 3, after the step of preparing a template substrate (substrate for ELO growth) 7, a step of forming a first semiconductor portion 8F using the ELO method is performed. After the step of forming the first semiconductor portion 8F, a step of forming a first functional layer 9F can be performed as needed. In the step of preparing the template substrate 7, a mask pattern 6 may be formed on an underlying substrate UK.

[0019] FIG. 4 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 70 of FIG. 4 includes a semiconductor forming unit 72 that forms first and second semiconductor portions 8F and 8S adjacent to each other in the X direction (first direction) on a template substrate 7, and a control unit 74 that controls the semiconductor forming unit 72. The semiconductor forming unit 72 uses the ELO method to form a first semiconductor portion 8F (see FIG. 1) that has a first lower edge 8c located on the mask portion 5 and a first protruding portion H1 that protrudes in the X direction (a-axis direction) beyond the first lower edge 8c in a plan view. The semiconductor substrate manufacturing apparatus 70 may also be configured to form a first functional layer 9F.

[0020] The semiconductor forming unit 72 may include an MOCVD apparatus, and the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the semiconductor forming unit 72 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network, and this program and a recording medium on which this program is stored are also included in this embodiment.

[0021] [Semiconductor device manufacturing] FIG. 5 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to this embodiment. FIG. 6 is a plan view illustrating an example of separating the element portions. FIG. 7 is a cross-sectional view illustrating an example of separating and isolating the element portions. In the method for manufacturing a semiconductor device illustrated in FIG. 5, after the step of preparing a semiconductor substrate 10, a step of forming a first functional layer 9F on the first semiconductor portion 8F is performed as needed. Then, as illustrated in FIGS. 6 and 7, a step of forming a plurality of trenches TR (separation trenches) in the semiconductor substrate 10 to separate the element portions DS (including the low-defect portion EK of the first semiconductor portion 8F and the first functional layer 9F) is performed. The trenches TR penetrate the first functional layer 9F and the first semiconductor portion 8F. The base layer 4 and the mask portion 5 may be exposed in the trenches TR. The opening width of the trenches TR may be equal to or greater than the width of the first opening K1. At this stage, the element portions DS are van der Waals-bonded to the mask portion 5 and are part of the semiconductor substrate 10.

[0022] 7, the element portion DS is separated from the template substrate 7 to form a semiconductor device 20. The first functional layer 9F of the separated element portion DS includes an end face 9x perpendicular to the X direction, but the end face 9x is not eroded by etching, so a high-quality first functional layer 9F (particularly, the active layer) is realized. Note that the step of preparing the semiconductor substrate 10 in FIG. 5 may include each step of the semiconductor substrate manufacturing method shown in FIG.

[0023] [Semiconductor Devices] 7, a semiconductor device 20 (including, for example, a GaN-based crystal) can be formed by separating the element portion DS from the template substrate 7. As a method for separating, the semiconductor device 20 may be bonded to another carrier substrate using solder, or may be peeled off using an adhesive stamp made of a flexible material such as an adhesive material or polydimethylsiloxane (PDMS), which is a silicone elastomer.

[0024] Specific examples of the semiconductor device 20 include a light emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, and a transistor (including a power transistor and a high electron mobility transistor).

[0025] [Electronic equipment] Fig. 8 is a schematic diagram showing the configuration of an electronic device according to this embodiment. Electronic device 30 in Fig. 8 includes a semiconductor substrate 10 (a configuration that functions as a semiconductor device when including a template substrate 7, for example, when the template substrate 7 is light-transmitting), a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0026] 9 is a schematic diagram showing another configuration of an electronic device according to this embodiment. The electronic device 30 in FIG. 9 includes a semiconductor device 20 including at least a low-defect portion EK, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0027] Examples of the electronic device 30 include a display device, a laser emitting device (including a Fabry-Perot type and a surface emitting type), a lighting device, a communication device, an information processing device, a sensing device, and a power control device.

[0028] Example 1 (Overall composition) FIG. 10 is a plan view and a cross-sectional view illustrating the configuration of a semiconductor substrate according to the first embodiment. As shown in FIG. 10, the semiconductor substrate 10 according to the first embodiment includes a main substrate 1, an underlayer 4 located above the main substrate 1, a mask pattern 6 including first and second openings K1 and K2 adjacent to each other in the X direction and a mask portion 5 located between the first and second openings K1 and K2, and first and second semiconductor portions 8F and 8S located above the mask pattern 6. The first and second semiconductor portions 8F and 8S are formed by the ELO method and are separated from each other and adjacent to each other. The first and second semiconductor portions 8F and 8S may also be referred to as ELO semiconductor layers 8. The first and second semiconductor portions 8F and 8S may also be referred to as first and second semiconductor layers.

[0029] The first semiconductor portion 8F overlaps the first opening K1 in plan view and has a first protruding portion H1 that protrudes further in the X direction (toward the second semiconductor portion 8S) than the first lower edge 8c. The second semiconductor portion 8S overlaps the second opening K2 in plan view and has a second protruding portion H2 that protrudes further in the opposite direction in the X direction (toward the first semiconductor portion 8F) than the second lower edge 8d. The lower edge means, for example, the edge of the lower surface of the semiconductor layer portion, and the upper edge means, for example, the edge of the upper surface of the semiconductor layer portion.

[0030] (Main board) The main substrate 1 can be a heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor. Examples of heterogeneous substrates include single-crystal silicon (Si) substrates, sapphire (Al2O3) substrates, and silicon carbide (SiC) substrates. The surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any main substrate and surface orientation that allows the ELO semiconductor layer 8 to be grown by the ELO method may be used.

[0031] (base layer) As the underlayer 4, a buffer layer 2 (e.g., an AlN layer) and a seed layer 3 (e.g., a nitride semiconductor) can be provided in this order from the main substrate side. The buffer layer 2, for example, has the function of reducing the likelihood of the main substrate 1 and the seed layer 3 coming into direct contact with each other and melting. When a silicon substrate or the like is used for the main substrate 1, the silicon substrate will melt with the GaN-based semiconductor that is the seed layer 3. Therefore, providing a buffer layer 2 such as an AlN layer reduces melting. For example, when a main substrate 1 that does not melt with the GaN-based semiconductor seed layer 3 is used, it is possible to omit the buffer layer 2. An AlN layer, which is an example of the buffer layer 2, can be formed to a thickness of approximately 10 nm to 5 μm using, for example, an MOCVD apparatus. The buffer layer 2 may have at least one of the effects of increasing the crystallinity of the seed layer 3 and alleviating the internal stress of the ELO semiconductor layer 8.

[0032] The seed layer 3 may be made of, for example, a GaN-based semiconductor containing Al. The seed layer 3 includes a seed portion 3S (a growth starting point of the ELO semiconductor layer) that overlaps with the first opening K1 of the mask pattern 6. A graded layer in which the Al composition approaches GaN in a graded manner may be used as the seed layer 3. The graded layer may include, for example, a first layer, Al, 0.7 Ga 0.3 N layer and the second layer, Al 0.3 Ga 0.7 The second layer (Al:Ga:N=0.3:0.7:1) has a Ga composition ratio (0.7 / 2=0.35) greater than the first layer (Al:Ga:N=0.7:0.3:1) (0.3 / 2=0.15). The graded layer can be easily formed by MOCVD and may be composed of three or more layers. The use of a graded layer as the seed layer 3 can alleviate stress from the main substrate 1, which is a heterogeneous substrate. The seed layer 3 can include a GaN layer. In this case, the seed layer 3 may be a single GaN layer, or the top layer of the graded layer (seed layer 3) may be a GaN layer.

[0033] At least one of the buffer layer 2 (for example, aluminum nitride) and the seed layer 3 (for example, GaN-based semiconductor) can also be deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).

[0034] (Mask pattern) The mask pattern 6 (mask layer) includes a mask portion 5 and first and second openings K1 and K2. The first and second openings K1 and K2 function as growth initiation holes that expose the seed portions 3S and initiate the growth of the ELO semiconductor layer 8, and the mask portion 5 may function as a selective growth mask that causes the ELO semiconductor layer 8 to grow laterally. The first and second openings K1 and K2 are portions of the mask pattern 6 where the mask portion 5 is not present (non-forming portions), and may not be surrounded by the mask portion 5.

[0035] The mask pattern 6 may be, for example, a single layer film including one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000°C or higher), or a laminated film including at least two of these.

[0036] For example, a silicon oxide film having a thickness of approximately 100 nm to 4 μm (preferably approximately 150 nm to 2 μm) is formed on the entire surface of the underlayer 4 using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned using photolithography to form a resist with multiple stripe-shaped openings. Then, portions of the silicon oxide film are removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form multiple openings (including K1 and K2), and the resist is then removed using organic cleaning to form the mask pattern 6.

[0037] The first and second openings K1 and K2 have a longitudinal (slit-like) shape and are periodically arranged in the a-axis direction (X-direction) of the ELO semiconductor layer 8. The width of the first and second openings K1 and K2 is approximately 0.1 μm to 20 μm. The smaller the width of each opening, the fewer the number of threading dislocations propagating from each opening to the ELO semiconductor layer 8. This also facilitates peeling (separation) of the ELO semiconductor layer 8 from the template substrate 7 in a subsequent process. Furthermore, the area of ​​the low-defect portion EK (e.g., GaN-based crystal) with few surface defects can be increased.

[0038] Although a small amount of silicon oxide film may decompose and evaporate during the formation of the ELO semiconductor layer 8 and become incorporated into the ELO semiconductor layer 8, silicon nitride film and silicon oxynitride film have the advantage of being less susceptible to decomposition and evaporation at high temperatures.

[0039] Therefore, the mask pattern 6 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the underlayer 4, or may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order on the underlayer 4, or may be a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on the underlayer.

[0040] Pinholes and other abnormalities in the mask portion 5 can be eliminated by performing organic cleaning after film formation, then re-introducing the mask into the film formation equipment to form a film of the same type. A high-quality mask pattern 6 can also be formed using a general silicon oxide film (single layer) using such a re-film formation method.

[0041] (Example of template substrate) The main substrate 1 is a silicon substrate having a (111) surface, and the buffer layer 2 of the underlayer 4 is an AlN layer (for example, 30 nm). 0.6 Ga 0.4 A graded layer is formed in this order: an N layer (e.g., 300 nm) and a second GaN layer (e.g., 1 to 2 μm). That is, the Ga composition ratio (1 / 2=0.5) in the second layer (Ga:N=1:1) is greater than the Ga composition ratio (0.6 / 2=0.3) in the first layer (Al:Ga:N=0.6:0.4:1).

[0042] A laminated body in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) are formed in this order is used for the mask pattern 6. The silicon oxide film has a thickness of, for example, 0.3 μm, and the silicon nitride film has a thickness of, for example, 70 nm. The silicon oxide film and the silicon nitride film are each formed by plasma-enhanced chemical vapor deposition (CVD).

[0043] (Deposition of ELO semiconductor layer) In Example 1, ELO semiconductor layer 8 was a GaN layer, and ELO deposition of gallium nitride (GaN) was performed on template substrate 7 using an MOCVD apparatus included in semiconductor formation unit 72 in Fig. 4. Examples of ELO deposition conditions that can be used are: substrate temperature: 1120°C, growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, and V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied).

[0044] In this case, the first and second semiconductor portions 8F and 8S are selectively grown on the seed portion 3S (the GaN layer that is the uppermost layer of the seed layer 3) exposed in the first and second openings K1 and K2, and then grow laterally on the mask portion 5. Then, the first and second semiconductor portions 8F and 8S growing laterally on both sides of the mask portion 5 are stopped from meeting. Before the growth of the first and second semiconductor portions 8F and 8S is stopped, there may be a period during which the area of ​​the lower inclined surface EC expands in an overhanging state without substantially changing the lower spacing Pc in FIG. 10.

[0045] The width Wm of the mask portion 5 was 50 μm, the width of the first and second openings K1 and K2 was 5 μm, the lateral width of the ELO semiconductor layer 8 was 53 μm, the width (size in the X direction) of the low defect portion EK was 24 μm, and the thickness of the ELO semiconductor layer 8 was 5 μm. The aspect ratio of the ELO semiconductor layer 8 was 53 μm / 5 μm=10.6, which is a very high aspect ratio.

[0046] In forming the ELO semiconductor layer 8, it is preferable to reduce mutual reaction between the ELO semiconductor layer 8 and the mask portion 5 so that the ELO semiconductor layer 8 and the mask portion 5 are in contact with each other by van der Waals forces.

[0047] In the formation of the ELO semiconductor layer 8 in Example 1, the lateral film formation rate is increased. The method for increasing the lateral film formation rate is as follows. First, a vertically grown layer growing in the Z direction (c-axis direction) is formed on the seed portion 3S exposed from the first and second openings K1 and K2, and then a laterally grown layer growing in the X direction (a-axis direction) is formed. In this case, by setting the thickness of the vertically grown layer to 10 μm or less, 5 μm or less, 3 μm or less, or 1 μm or less, the thickness of the laterally grown layer can be kept low and the lateral film formation rate can be increased.

[0048] FIG. 11 is a cross-sectional view showing an example of lateral growth of an ELO semiconductor layer. As shown in FIG. 11, it is desirable to form an initial growth layer SL (part of the dislocation inheritance region NS) on a seed region 3S, and then laterally grow the first and second semiconductor regions 8F and 8S from the initial growth layer SL. The initial growth layer SL serves as the starting point for the lateral growth of the first and second semiconductor regions 8F and 8S. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the first and second semiconductor regions 8F and 8S in either the Z direction (c-axis direction) or the X direction (a-axis direction). The shapes of the first and second overhanging regions H1 and H2 in FIG. 10 can also be controlled by the ELO film formation conditions (X-direction growth conditions).

[0049] In the deposition of the first and second semiconductor portions 8F and 8S, a technique can be used in which deposition of the initial growth layer SL is stopped just before the edge of the initial growth layer SL rises above the upper surface of the mask portion 5 (when it is in contact with the upper end of the side surface of the mask portion 5) or just after it rises above the upper surface of the mask portion 5 (i.e., the ELO deposition conditions are switched from c-axis deposition conditions to a-axis deposition conditions at this timing). This technique allows lateral deposition to proceed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, thereby reducing the amount of material consumed in the thickness direction and enabling rapid lateral growth of the first and second semiconductor portions 8F and 8S. The initial growth layer SL can be formed to a thickness of 50 nm to 5.0 μm (e.g., 80 nm to 2 μm). The thickness of the mask portion 5 and the initial growth layer SL may be 500 nm or less.

[0050] 11, the first and second semiconductor portions 8F and 8S can increase the number of non-threading dislocations inside the low defect portion EK (reducing the threading dislocation density on the surface of the low defect portion EK) by forming an initial growth layer SL and then growing them laterally. Also, the distribution of impurity concentrations (e.g., silicon, oxygen) inside the low defect portion EK can be controlled.

[0051] 11, the aspect ratio of the first semiconductor portion 8F (ratio of size in the X direction to thickness = WL / d1) can be dramatically increased to 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more. Furthermore, by using the method of FIG. 11, the ratio of the width (WL) of the first semiconductor portion 8F to the width of the first opening K1 can be set to 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more, thereby increasing the proportion of low-defect portions EK. The first and second semiconductor portions 8F and 8S shown in FIG. 11 can be made of nitride semiconductor crystal (e.g., GaN crystal, AlGaN crystal, InGaN crystal, or InAlGaN crystal).

[0052] For example, by reducing the amount of ammonia supplied and depositing the film at a low V / III ratio (<1000), it becomes easier to form an inverted tapered shape as the lateral film deposition progresses. This is presumably because inverted tapered crystal planes are easily formed during facet deposition of the side surface of the ELO semiconductor layer 8. When depositing the film at a low V / III ratio (<1000) at a low temperature below 1000°C, it is preferable to use triethylgallium (TEG) as the gallium source gas. Compared to TMG, TEG decomposes organic materials more efficiently at low temperatures, allowing for a higher lateral film deposition rate.

[0053] As another example, if the thickness of the vertically grown layer (initial growth layer) is set to 2 μm or more and film formation is completed before the films growing laterally on the mask portion 5 meet, the thickness of the vertically grown layer makes it difficult for the Ga source material and the ammonia source material to be supplied to the gap portion, thereby suppressing growth below the end face of the ELO semiconductor layer 8. In this case, if film formation is performed at a high temperature (for example, a film formation temperature of 1050° C. or more) and under conditions of a high V / III ratio (>5000), an inversely tapered crystal plane is easily obtained.

[0054] The deposition temperature for the ELO semiconductor layer 8 is preferably 1150°C or lower, rather than higher temperatures exceeding 1200°C. It is also possible to form the ELO semiconductor layer 8 at temperatures below 1000°C, which is preferable from the viewpoint of reducing mutual reactions. It was found that in such low-temperature deposition, when trimethylgallium (TMG) is used as the gallium source, the source material is not sufficiently decomposed, and gallium atoms and carbon atoms are simultaneously incorporated into the ELO semiconductor layer 8 in greater amounts than usual. This is thought to be because, with the ELO method, deposition in the a-axis direction is fast and deposition in the c-axis direction is slow, resulting in greater incorporation during c-plane deposition.

[0055] It has been found that carbon incorporated into the ELO semiconductor layer 8 reduces reaction with the mask portion 5 and reduces adhesion between the mask portion 5 and the ELO semiconductor layer 8. Therefore, in low-temperature deposition of the ELO semiconductor layer 8, the amount of ammonia supplied is reduced and deposition is performed at a low V / III ratio (<1000), thereby allowing carbon elements in the raw materials or chamber atmosphere to be incorporated into the ELO semiconductor layer 8 and reducing reaction with the mask portion 5. In this case, the ELO semiconductor layer (first and second semiconductor portions 8F and 8S) contains carbon.

[0056] (Example of ELO semiconductor layer shape) In the semiconductor substrate 10 of Figure 10, the first semiconductor portion 8F has a first upper edge 8a located between the mask portion center 5c and the first opening K1 in a planar view, a first lower edge 8c located between the mask portion center 5c and the first opening K1 (located on the mask portion 5) in a planar view, and a first protrusion portion H1 that protrudes in the X direction (toward the second semiconductor portion 8S) beyond the first lower edge 8c in a planar view.

[0057] The second semiconductor portion 8S has a second upper edge 8b located between the mask portion center 5c and the second opening K2 in a planar view, a second lower edge 8d located between the mask portion center 5c and the second opening K2 (located on the mask portion 5) in a planar view, and a second protrusion portion H2 that protrudes in the X direction (toward the first semiconductor portion 8F) more than the second lower edge 8d in a planar view.

[0058] The portions of the first and second semiconductor portions 8F and 8S that overlap with the mask portion 5 in plan view are GaN-based crystalline bodies GK that contain a GaN-based semiconductor and have an upper surface 8J and a lower surface 8U that are parallel to the (0001) plane (c-plane). <0001> The non-threading dislocation density in a cross section parallel to the <1-100> direction is greater than the threading dislocation density on the upper surface 8J, and the crystal grain has a lower edge 8c parallel to the <1-100> direction and an overhanging portion H1 that overhangs in the <11-20> direction beyond the lower edge.

[0059] The non-threading dislocation density of the GaN-based crystal GK can be 10 times or more, for example, 20 times or more, the threading dislocation density. 6 [pcs / cm 2 ] or less. The width (size in the X direction) of the GaN-based crystal body GK can be, for example, 10 μm or more. In the GaN-based crystal body GK, threading dislocations that affect the characteristics of semiconductor devices are suppressed, while non-threading dislocations that have almost no effect are present, thereby also having the effect of mitigating film stress.

[0060] For the GaN-based crystal GK, the non-threading dislocation density in a cross section taken along a plane parallel to the (11-20) plane (a-plane) may be greater than the non-threading dislocation density in a cross section taken along a plane parallel to the (1-100) plane (m-plane). The GaN-based crystal GK is formed by lateral (X-direction) growth, and therefore can be configured such that the concentration of impurities (atoms contained in the mask pattern 6, such as silicon and oxygen) is lower at one end at the end of growth in the X-direction (first direction) than at the other end at the beginning of growth.

[0061] In Example 1, in the X direction, the maximum distance L1 between the first opening K1 and the first protrusion H1 is greater than the distance La between the first opening K1 and the first upper edge 8a, and in the X direction, the maximum distance L2 between the second opening K2 and the second protrusion H2 is greater than the distance Lb between the second opening K2 and the second upper edge 8b.

[0062] The side surface ES of the first semiconductor portion includes a lower inclined surface EC including the first lower edge 8c and an upper inclined surface EA including the first upper edge 8a, and a first acute angle θ1 formed between the lower inclined surface EC and a plane VF perpendicular to the X direction is smaller than a second acute angle θ2 formed between the upper inclined surface EA and the plane VF perpendicular to the X direction. The first acute angle θ1 may be 30° or less, 20° or less, or 15° or less. The distance Hp between the mask portion 5 and the top 8P of the first protrusion portion is greater than half the thickness d1 of the first semiconductor portion 8F. The second acute angle θ2 may be 75° or more, 80° or more, or 85° or more.

[0063] The minimum distance Px between the first semiconductor portion 8F and the second semiconductor portion 8S is smaller than the lower distance Pc indicating the distance between the first lower edge 8c and the second lower edge 8d and the upper distance Pa indicating the distance between the first upper edge 8a and the second upper edge 8b, and the upper distance Pa is larger than the lower distance Pc. The minimum distance Px is, for example, 5 μm or less, the lower distance Pc is, for example, 7 μm or less, and the upper distance Pa is, for example, 8 μm or less. The lower distance Pc may be smaller than the opening width of the first and second openings K1 and K2. The minimum distance Px may be smaller than the opening width of the first and second openings K1 and K2.

[0064] In this way, by providing the gap (gap space) Gp between the adjacent first and second semiconductor portions 8F and 8S, it is possible to reduce the internal stress of the ELO semiconductor layer 8 and reduce cracks and defects that occur in the ELO semiconductor layer 8. This effect is particularly significant when the main substrate 1 is a heterogeneous substrate.

[0065] (functional layer) FIG. 12 is a cross-sectional view showing another configuration of the semiconductor substrate according to Example 1. In FIG. 12, a first functional layer 9F is disposed on a first semiconductor portion 8F, and a second functional layer 9S is disposed on a second semiconductor portion 8S. The functional layer 9 (including the first and second functional layers 9F and 9S) can include, for example, at least one of an n-type semiconductor layer (e.g., GaN-based), an undoped semiconductor layer (e.g., GaN-based), a p-type semiconductor layer (e.g., GaN-based), a conductive layer, and an insulating layer. The undoped semiconductor layer can also be used as an active layer (a layer in which electrons and holes combine). The functional layer 9 can be formed by any method.

[0066] The first semiconductor portion 8F has a first protruding portion H1, and the second semiconductor portion 8S has a second protruding portion H2. This prevents raw materials (aluminum source, indium source) from reaching the mask portion 5 located between the first and second semiconductor portions 8F and 8S during the formation of the first and second functional layers 9F and 9S, reducing the formation of deposits. Furthermore, the functional layers 9F and 9S can be prevented from joining together.

[0067] As shown in FIG. 12, the first functional layer 9F formed above the first semiconductor portion 8F is unlikely to be formed below the apex 8P of the first protruding portion H1, and the second functional layer 9S formed above the second semiconductor portion 8S is unlikely to be formed below the apex 8Q of the second protruding portion H2. Therefore, the first and second functional layers 9F and 9S are naturally separated (self-separated) during formation. This improves the yield of the process of separating the element portions DS. In particular, it is desirable that the active layer included in the first functional layer 9F has a shape that does not reach the first lower edge 8c, and that the active layer included in the second functional layer 9S has a shape that does not reach the second lower edge 8d.

[0068] When forming, for example, a GaN-based p-type semiconductor layer in functional layer 9, silicon and oxygen separated from silicon-based mask pattern 6 (e.g., a silicon oxide film) may be incorporated and may compensate for the p-type dopant (e.g., Mg). When ELO semiconductor layer 8 is an n-type GaN-based semiconductor, silicon and the like may also be separated from ELO semiconductor layer 8. In Example 1, the rise of n-type dopants such as silicon is inhibited by first and second overhanging portions H1 and H2, making it difficult for n-type dopants to be incorporated into the p-type semiconductor layer, thereby improving the functionality of the p-type semiconductor layer.

[0069] The first functional layer 9F is a layer containing indium as a composition (for example, In x Ga (1-x) In the case where the first functional layer 9F includes a layer containing aluminum as a composition (e.g., an N layer, x being a positive number of 1 or less), since In atoms are larger than Ga atoms, lattice mismatch with the ELO semiconductor layer 8 may cause crystal defects and stress within the film. However, by separating the first functional layer 9F from the other functional layers, it is possible to suppress the propagation of crystal defects and alleviate stress within the film. In addition, when the first functional layer 9F includes a layer containing aluminum as a composition (e.g., Al x Ga (1-x) When the first functional layer 9F includes an N layer (x is a positive number less than 1), as the Al composition increases, lattice mismatch with the ELO semiconductor layer 8, differences in thermal expansion coefficients, etc. can cause crystalline defects such as cracks and crystal slippage on the crystal plane (for example, m-plane slippage in a GnN-based semiconductor layer), and intra-film stress. However, by separating the first functional layer 9F from the other functional layers, the propagation of crystalline defects can be suppressed and intra-film stress can be alleviated.

[0070] 13 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. When forming the functional layer 9, edge growth 9G (corners) may occur as shown in FIG. 13. For example, this occurs when the functional layer 9 includes an AlGaN layer. The edge growth may reach a width of 10 μm or more and a height of approximately 200 to 300 nm, which can hinder subsequent processes. However, by keeping the minimum width Px (minimum spacing) of the gap Gp to less than 10 μm, the edge growth 9G can be significantly reduced (for example, to a height of 100 nm or less).

[0071] (Separation and isolation of element parts) FIG. 14 is a plan view showing a process of separating the element portions in Example 1. FIG. 15 is a cross-sectional view showing a process of isolating the element portions in Example 1. In Example 1, as shown in FIG. 14, dry etching is used to form multiple trenches TR extending in the X direction to separate the element portions DS. In plan view, the element portion DS is surrounded by two trenches TR and two gaps Gp extending in the Y direction, making it possible to separate larger element portions DS than those in FIG. 6. Dry etching is achieved by a general photolithography method. After etching is completed, the photoresist used as a mask during etching must be removed. However, if organic cleaning using weak ultrasound is performed, for example, the element portions DS are less likely to peel off from the mask portion 5.

[0072] After separating the element portion DS, as shown in FIG. 15 , the semiconductor substrate 10 is immersed in an etchant ET to dissolve the mask pattern 6. Then, adhesive tape (e.g., adhesive dicing tape used for dicing semiconductor wafers) is attached to the surface of the ELO semiconductor layer 8. The semiconductor substrate 10 with the adhesive tape attached may then be cooled to a low temperature using a Peltier element (not shown). During this process, the adhesive tape, which generally has a larger thermal expansion coefficient than semiconductors, contracts significantly, applying stress to the ELO semiconductor layer 8. Because the ELO semiconductor layer 8 is bonded only to the underlayer 4 (seed portion) of the template substrate 7 and the mask portion 5 has been removed, the stress from the adhesive tape is effectively applied to the bonded portion with the underlayer 4 (of the template substrate 7), mechanically cleaving or destroying the bonded portion. This eliminates the need to etch away the bonded portion.

[0073] (Structure with dislocation inheritance removed) FIG. 16 is a cross-sectional view showing another configuration of the semiconductor substrate of Example 1. As shown in FIG. 16, the dislocation inheritance regions NS (portions overlapping with the first and second openings K1 and K2 in plan view) of the first and second semiconductor portions 8F and 8S can be removed from the semiconductor substrate 10 of FIG. 10. Furthermore, the portions of the underlayer 4 overlapping with the first and second openings K1 and K2 in plan view can also be removed. FIG. 17 is a cross-sectional view showing another configuration of the semiconductor substrate 10 of Example 1. As shown in FIG. 17, first and second functional layers 9F and 9S can be provided on the first and second semiconductor portions 8F and 8S of FIG. 16.

[0074] FIG. 18 is a cross-sectional view showing another step of separating the element portion in Example 1. Because the ELO semiconductor layer 8 and the mask portion 5 in FIG. 17 are bonded by van der Waals forces (weak forces), as shown in FIG. 18 , the element portion DS can be easily peeled off from the template substrate to form a semiconductor device 20 by pulling up the functional layer 9 using the attractive force (adhesive force, suction force, electrostatic force, etc.) of the stamp device ST, etc. The ability to directly peel off the element portion DS from the mask portion 5 using a viscoelastic elastomer stamp, an electrostatic adhesive stamp, etc., offers significant advantages in terms of cost, throughput, etc. After the viscoelastic elastomer stamp, the electrostatic adhesive stamp, etc., is brought into contact with the ELO semiconductor layer 8, ultrasonic vibrations, etc., may be applied. This vibration, etc., makes it even easier to peel off the ELO semiconductor layer 8 from the mask portion 5.

[0075] Example 2 Fig. 19 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 2. In the semiconductor substrate 10 of Fig. 19, the first semiconductor portion 8F has a first upper edge 8a located between the mask portion center 5c and the first opening K1 in plan view, a first lower edge 8c located between the mask portion center 5c and the first opening K1 (located on the mask portion 5) in plan view, and a first protruding portion H1 that protrudes in the X direction (toward the second semiconductor portion 8S) beyond the first lower edge 8c in plan view.

[0076] The second semiconductor portion 8S has a second upper edge 8b located between the mask portion center 5c and the second opening K2 in a planar view, a second lower edge 8d located between the mask portion center 5c and the second opening K2 (located on the mask portion 5) in a planar view, and a second protrusion portion H2 that protrudes in the X direction (toward the first semiconductor portion 8F) more than the second lower edge 8d in a planar view.

[0077] The portions of the first and second semiconductor portions 8F and 8S that overlap with the mask portion 5 in plan view are GaN-based crystalline bodies GK that contain a GaN-based semiconductor and have an upper surface 8J and a lower surface 8U that are parallel to the (0001) plane (c-plane). <0001> The non-threading dislocation density in a cross section parallel to the <1-100> direction is greater than the threading dislocation density on the upper surface 8J, and the crystal grain has a lower edge 8c parallel to the <1-100> direction and an overhanging portion H1 that overhangs in the <11-20> direction beyond the lower edge.

[0078] 18, the first upper edge 8a is the apex of the first overhanging portion H1, and the second upper edge 8b is the apex of the second overhanging portion H2. In the X direction, the distance La between the first opening K1 and the first upper edge 8a is greater than the distance Lc between the first opening K1 and the first lower edge 8c, and the distance Lb between the second opening K2 and the second upper edge 8b is greater than the distance Ld between the second opening K2 and the second lower edge 8d. The gap Gp between the first semiconductor portion 8F and the second semiconductor portion 8S has an inverse tapered shape that is wider on the mask portion 5 side.

[0079] 19, the upper spacing Pa, which indicates the spacing between the first upper edge 8a and the second upper edge 8b, is smaller than 5 μm. The ratio of the upper spacing Pa to the width Wm of the mask portion is less than 0.5, and the ratio of the lower spacing Pc, which indicates the spacing between the first lower edge 8c and the second lower edge 8d, to the width Wm of the mask portion is less than 0.7. The acute angle θ formed by the plane EF including the first upper edge 8a and the first lower edge 8c and the plane VF perpendicular to the X direction is 15° or less.

[0080] Fig. 20 is a cross-sectional view showing another configuration of a semiconductor substrate according to Example 2. In Fig. 20, a first functional layer 9F is disposed on a first semiconductor portion 8F, and a second functional layer 9S is disposed on a second semiconductor portion 8S.

[0081] 20, the first functional layer 9F formed above the first semiconductor portion 8F is unlikely to be formed below the apex 8P of the first protruding portion H1, and the second functional layer 9S formed above the second semiconductor portion 8S is unlikely to be formed below the apex 8Q of the second protruding portion H2, so the first and second functional layers 9F and 9S are separated from each other, thereby improving the yield of the process of separating the element portions DS.

[0082] Furthermore, when forming, for example, a GaN-based p-type semiconductor layer in the functional layer 9, the rise of n-type dopants such as silicon is significantly reduced by the first and second protrusions H1 and H2, making it difficult for n-type dopants to be incorporated into the p-type semiconductor layer, thereby improving the functionality of the p-type semiconductor layer.

[0083] Fig. 21 is a cross-sectional view showing another configuration of the semiconductor substrate of Example 2. In the semiconductor substrate 10 of Fig. 21, the first semiconductor portion 8F has a first upper edge 8a located between the mask portion center 5c and the first opening K1 in a plan view, a first lower edge 8c located between the mask portion center 5c and the first opening K1 (located on the mask portion 5) in a plan view, and a first protruding portion H1 that protrudes in the X direction (toward the second semiconductor portion 8S) beyond the first lower edge 8c in a plan view.

[0084] The second semiconductor portion 8S has a second upper edge 8b located between the mask portion center 5c and the second opening K2 in a planar view, a second lower edge 8d located between the mask portion center 5c and the second opening K2 (located on the mask portion 5) in a planar view, and a second protrusion portion H2 that protrudes in the X direction (toward the first semiconductor portion 8F) more than the second lower edge 8d in a planar view.

[0085] The portions of the first and second semiconductor portions 8F and 8S that overlap with the mask portion 5 in plan view are GaN-based crystalline bodies GK that contain a GaN-based semiconductor and have an upper surface 8J and a lower surface 8U that are parallel to the (0001) plane (c-plane). <0001> The non-threading dislocation density in a cross section parallel to the <1-100> direction is greater than the threading dislocation density on the upper surface 8J, and the crystal grain has a lower edge 8c parallel to the <1-100> direction and an overhanging portion H1 that overhangs in the <11-20> direction beyond the lower edge.

[0086] In the semiconductor substrate 10 of FIG. 21, the side surface ES (end surface) of the first semiconductor portion includes an upper inclined surface EA including the first upper edge 8a, a vertical surface EJ perpendicular to the X direction, and a lower inclined surface EC including the first lower edge 8c.

[0087] Fig. 22 is a cross-sectional view showing another configuration of the semiconductor substrate of Example 2. As shown in Fig. 22, first and second functional layers 9F and 9S can also be provided on the first and second semiconductor portions 8F and 8S of Fig. 21.

[0088] Example 3 In Examples 1 and 2, the ELO semiconductor layer 8 is a GaN layer, but this is not limiting. The ELO semiconductor layer 8 in Examples 1 and 2 can also be an InGaN layer, which is a GaN-based semiconductor layer. The lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. Lowering the deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. Furthermore, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. Incorporation of indium into the InGaN layer at an In composition level of 1% or more is desirable because it further reduces the reactivity with the mask portion 5. Triethylgallium (TEG) is preferably used as the gallium source gas.

[0089] Example 4 FIG. 23 is a schematic cross-sectional view showing the configuration of Example 4. In Example 4, a functional layer 9 constituting an LED is formed on an ELO semiconductor layer 8. The ELO semiconductor layer 8 is, for example, n-type doped with silicon or the like. The functional layer 9 includes, from bottom to top, an active layer 34, an electron-blocking layer 35, and a GaN-based p-type semiconductor layer 36. The active layer 34 is an MQW (multi-quantum well) and includes an InGaN layer and a GaN layer. The electron-blocking layer 35 is, for example, an AlGaN layer. The GaN-based p-type semiconductor layer 36 is, for example, a GaN layer. An anode 38 is disposed in contact with the GaN-based p-type semiconductor layer 36, and a cathode 39 is disposed in contact with the semiconductor layer 8. A semiconductor device 20 (including a GaN-based crystal) can be obtained by separating the ELO semiconductor layer 8 and the functional layer 9 from the template substrate 7. It is also possible to form the ELO semiconductor layer 8, remove the semiconductor substrate 10 from the film-forming apparatus, and then form the functional layer 9 using a separate apparatus. In this case, an n-type GaN layer may be inserted as an intermediate layer to serve as a buffer during regrowth between the ELO semiconductor layer 8 and the functional layer 9. The thickness of the intermediate layer may be about 0.1 μm to 3 μm.

[0090] 24 is a cross-sectional view showing an example of application of Example 4 to an electronic device. According to Example 4, a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B can be obtained, and by mounting these on a drive substrate (TFT substrate) 23, a micro LED display 30D (electronic device) can be configured. As an example, the red micro LED 20R, the green micro LED 20G, and the blue micro LED 20B are mounted on a plurality of pixel circuits 27 of the drive substrate 23 via a conductive resin 24 (e.g., anisotropic conductive resin) or the like, and then a control circuit 25, a driver circuit 29, etc. are mounted on the drive substrate 23. A part of the driver circuit 29 may be included in the drive substrate 23.

[0091] Example 5 FIG. 25 is a schematic cross-sectional view showing the configuration of Example 5. In Example 5, a functional layer 9 constituting a semiconductor laser is formed on an ELO semiconductor layer 8. The functional layer 9 includes, from bottom to top, an n-type cladding layer 41, an n-type guide layer 42, an active layer 43, an electron blocking layer 44, a p-type guide layer 45, a p-type cladding layer 46, and a GaN-based p-type semiconductor layer 47. Each of the guide layers 42 and 45 can be an InGaN layer. Each of the cladding layers 41 and 46 can be a GaN layer or an AlGaN layer. An anode 48 is disposed in contact with the GaN-based p-type semiconductor layer 47, and a cathode 49 is disposed in contact with the ELO semiconductor layer 8. By separating the ELO semiconductor layer 8 and the functional layer 9 from the template substrate 7, a semiconductor device 20 (including a GaN-based crystal) can be obtained.

[0092] Example 6 FIG. 26 is a cross-sectional view showing the configuration of Example 6. In Example 6, a sapphire substrate with a textured surface is used as the main substrate 1. The underlayer 4 includes a buffer layer 2 and a seed layer 3. In Example 6, a GaN layer with a (20-21) plane is deposited as the underlayer 4 on the main substrate 1. In this case, the ELO semiconductor layer 8 has the (20-21) plane, which is the primary crystal plane of the underlayer 4, and an ELO semiconductor layer 8 with a semipolar plane can be obtained. Providing a functional layer for a laser or LED on the semipolar plane has the advantage of increasing the recombination probability of electrons and holes in the active layer. Note that by using a sapphire substrate with a textured surface, a GaN layer with a (11-22) plane can also be deposited as the underlayer 4 on the main substrate 1.

[0093] Example 7 The underlayer 4 does not have to be formed over the entire substrate. If the underlayer 4 contains a material different from that of the main substrate 1, stress may be generated within the semiconductor substrate (ELO semiconductor layer, functional layer) due to differences in thermal expansion coefficient, lattice constant, etc. For this reason, the underlayer 4 (at least one of the buffer layer and the seed layer) may be provided locally so as to overlap each opening of the mask pattern 6. It is also possible to configure the semiconductor device without the underlayer 4.

[0094] FIG. 27 is a cross-sectional view showing the configuration of Example 7. The template substrate (substrate for ELO growth) 7 may be configured, for example, as shown in FIG. 27. For example, the template substrate 7 may be configured with a main substrate 1 and a mask pattern 6 (without an underlayer), and the portion of the surface of the main substrate 1 that overlaps with the first opening K1 may function as a seed portion. In this case, the main substrate 1 may be a GaN bulk substrate, a 6H—SiC bulk substrate, or a 4H—SiC bulk substrate. A bulk substrate is a wafer (freestanding substrate) cut out from a bulk crystal.

[0095] Furthermore, the template substrate 7 can be composed of the main substrate 1, a seed layer 3 (seed portion) locally arranged so as to overlap the first opening K1 in a plan view, and the mask pattern 6. In this case, the main substrate 1 may be a silicon substrate and the seed layer 3 may contain AlN, or the main substrate 1 may be a silicon carbide substrate and the seed layer 3 may contain a GaN-based semiconductor.

[0096] Furthermore, the template substrate 7 can be composed of a main substrate 1, a buffer layer 2 covering the main substrate 1, a seed layer 3 (seed portion) locally arranged so as to overlap with the first opening K1 in a plan view, and a mask pattern 6. For example, the main substrate 1 can be a silicon substrate, the buffer layer 2 can include at least one of AlN and SiC, and the seed layer 3 can include a GaN-based semiconductor.

[0097] Furthermore, the template substrate 7 can be composed of a main substrate 1, a buffer layer 2 (buffer portion) locally arranged so as to overlap with the first opening K1 in a planar view, a seed layer 3 (seed portion) locally arranged so as to overlap with the first opening K1 in a planar view, and a mask pattern 6. For example, the main substrate 1 can be a silicon substrate, the buffer layer 2 can include at least one of AlN and silicon carbide, and the seed layer 3 can include a GaN-based semiconductor. [Explanation of symbols]

[0098] 1 Main board 2. Buffer layer 3 Seed layer 3S Seed Department 4 Base layer 5 Mask section 6 Mask Pattern 8F 1st Semiconductor Department 8S 2nd Semiconductor Department 9F 1st functional layer 9S 2nd functional layer 10. Semiconductor substrate 20 Semiconductor Devices 30 Electronic equipment 70 Semiconductor substrate manufacturing equipment K1 1st opening K2 2nd opening EK Low defect area GK GaN crystal

Claims

1. a template substrate including a main substrate, a mask portion, and a first seed portion and a second seed portion; a first semiconductor portion in contact with the first seed portion and a second semiconductor portion in contact with the second seed portion; the first semiconductor portion and the second semiconductor portion include a nitride semiconductor and are adjacent to each other in an a-axis direction of the nitride semiconductor; the first semiconductor portion has a first lower edge along the m-axis direction of the nitride semiconductor and a first protruding portion that protrudes further toward the second semiconductor portion than the first lower edge, A semiconductor substrate, wherein the distance between the template substrate and the top of the first protruding portion is greater than half the thickness of the first semiconductor portion.

2. the template substrate includes a mask pattern including a first opening and a second opening adjacent to each other in a first direction, and the mask portion located between the first and second openings; the first lower edge is located between a center of the mask portion and the first opening in a plan view, 2. The semiconductor substrate of claim 1, wherein the second semiconductor portion has a second lower edge located between the center of the mask portion and the second opening in a planar view, and a second protrusion portion that protrudes toward the first semiconductor portion more than the second lower edge in a planar view.

3. the first semiconductor portion has a first upper edge located between a center of the mask portion and the first opening in a plan view; The semiconductor substrate according to claim 2 , wherein a maximum distance between the first opening and the first protruding portion in the first direction is greater than a distance between the first opening and the first upper edge.

4. the second semiconductor portion has a second upper edge located between a center of the mask portion and the second opening portion in a plan view; The semiconductor substrate according to claim 3 , wherein a maximum distance between the second opening and the second protruding portion in the first direction is greater than a distance between the second opening and the second upper edge.

5. the first semiconductor portion has a first upper edge which is an edge of an upper surface of the first semiconductor portion; The semiconductor substrate according to claim 1 , wherein the side surface of the first semiconductor portion includes a lower inclined surface including the first lower edge and an upper inclined surface including the first upper edge.

6. The semiconductor substrate according to claim 4 , wherein a minimum distance between the first semiconductor portion and the second semiconductor portion is smaller than a lower distance indicating a distance between the first lower edge and the second lower edge.

7. The semiconductor substrate according to claim 6 , wherein a minimum distance between the first semiconductor portion and the second semiconductor portion is smaller than an upper distance indicating a distance between the first upper edge and the second upper edge.

8. The semiconductor substrate of claim 7 , wherein the upper spacing is greater than the lower spacing.

9. the first semiconductor portion has a first upper edge located between a center of the mask portion and the first opening in a plan view; The semiconductor substrate of claim 2 , wherein the first upper edge is the top of the first overhang.

10. the second semiconductor portion has a second upper edge located between a center of the mask portion and the second opening portion in a plan view; The semiconductor substrate of claim 9 , wherein the second upper edge is the top of the second overhang.

11. The semiconductor substrate according to claim 10 , wherein a distance between the first opening and the first upper edge in the first direction is greater than a distance between the first opening and the first lower edge.

12. The semiconductor substrate according to claim 11 , wherein a distance between the second opening and the second upper edge in the first direction is greater than a distance between the second opening and the second lower edge.

13. The semiconductor substrate according to claim 12 , wherein a gap space sandwiched between said first semiconductor portion and said second semiconductor portion has an inversely tapered shape with a width wider on said mask portion side.

14. 14. The semiconductor substrate according to claim 10, wherein an upper distance indicating a distance between the first upper edge and the second upper edge is smaller than 5 μm.

15. 15. The semiconductor substrate according to claim 10, wherein a ratio of an upper spacing indicating a spacing between the first upper edge and the second upper edge to a width of the mask portion is less than 0.

5.

16. 16. The semiconductor substrate according to claim 1, wherein the first seed portion and the second seed portion are located above the main substrate.

17. the first semiconductor portion has a first upper edge located between a center of the mask portion and the first opening in a plan view; The semiconductor substrate according to claim 2 , wherein the side surface of the first semiconductor portion includes an upper inclined surface including the first upper edge, a vertical surface perpendicular to the first direction, and a lower inclined surface including the first lower edge.

18. 5. The semiconductor substrate according to claim 2, wherein a first functional layer is disposed above the first semiconductor portion.

19. the first functional layer includes an active layer; 20. The semiconductor substrate of claim 18, wherein the active layer does not extend to the first lower edge.

20. a second functional layer is disposed above the second semiconductor portion; The semiconductor substrate according to claim 18 or 19, wherein the first functional layer and the second functional layer are separated from each other.

21. the first functional layer includes a GaN-based p-type semiconductor layer, 21. The semiconductor substrate according to claim 18, wherein the mask pattern includes at least one of a silicon oxide film and a silicon nitride film.

22. The first and second openings have a second direction perpendicular to the first direction as a longitudinal direction, 5. The semiconductor substrate according to claim 2, wherein, in a plan view, the first semiconductor portion overlaps the first opening, and the second semiconductor portion overlaps the second opening.

23. a seed layer disposed above the primary substrate; 5. The semiconductor substrate according to claim 2, wherein the first semiconductor portion is in contact with the seed layer in the first opening.

24. the first semiconductor portion has a low-defect portion that overlaps with the mask portion in a plan view, The threading dislocation density of the low defect portion is 5×10 ６ [pcs / cm ２ ] or less, 5. The semiconductor substrate according to claim 2, wherein the size of the low defect portion in the first direction is 10 μm or more.

25. the first semiconductor portion has a low-defect portion that overlaps with the mask portion in a plan view, 5. The semiconductor substrate according to claim 2, wherein in the low defect portion, the non-threading dislocation density in a cross section parallel to the thickness direction is higher than the threading dislocation density on the top surface.

26. 5. The semiconductor substrate according to claim 2, wherein the first semiconductor portion includes a nitride semiconductor, and the main substrate is a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor.

27. the nitride semiconductor is GaN, the heterogeneous substrate is a silicon substrate, 27. The semiconductor substrate of claim 26, wherein the first direction is the <11-20> direction in GaN.

28. A GaN-based crystalline body including a GaN-based semiconductor and having an upper surface and a lower surface parallel to a (0001) plane, a non-threading dislocation density in a cross section parallel to the <0001> direction is greater than a threading dislocation density on the top surface, a lower edge parallel to the <1-100> direction and a protruding portion protruding in the <11-20> direction beyond the lower edge, A GaN-based crystal body in which the non-threading dislocation density in a cross section parallel to the (11-20) plane is greater than the non-threading dislocation density in a cross section parallel to the (1-100) plane.

29. A semiconductor device comprising the GaN-based crystalline material according to claim 28.

30. An electronic device comprising the semiconductor substrate according to any one of claims 1 to 27.

31. 30. An electronic device comprising the semiconductor device of claim 29.

32. The method for manufacturing a semiconductor substrate according to any one of claims 1 to 27, A method for manufacturing a semiconductor substrate, wherein the first and second semiconductor portions containing a Group III nitride semiconductor are grown by an ELO method with a V / III ratio of less than 1000.

33. 33. The method for manufacturing a semiconductor substrate according to claim 32, wherein the first and second semiconductor portions are grown at a temperature of 1150[deg.] C. or less.

34. The semiconductor substrate manufacturing apparatus according to any one of claims 1 to 27, A semiconductor substrate manufacturing apparatus comprising: a semiconductor forming section that forms the first and second semiconductor sections by an ELO method; and a control section that controls the semiconductor forming section.

35. A step of preparing a semiconductor substrate according to any one of claims 1 to 27; and forming a first functional layer above the first semiconductor portion.

36. 36. The method for manufacturing a semiconductor device according to claim 35, further comprising the step of peeling off at least a portion of the first semiconductor portion and the first functional layer from the template substrate.

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