Low noise infinite radio frequency delay locked loop

Abstract

Described herein is an apparatus and method for a low noise infinite radio frequency (RF) delay locked loop (DLL), comprising: a phase detector having a first input configured to receive a first RF signal, a second input, and an output, an infinite phase shifter having a first input configured to receive a second RF signal, an input bus, and an output connected to the second input of the phase detector, and a controller having a first input connected to the output of the phase detector and an output bus connected to the input bus of the infinite phase detector, wherein the output of the infinite phase shifter comprises a low noise signal that is phase-matched with the first RF signal.

Description

[Background technology]

[0001] In advanced radio frequency (RF) and microwave systems, it is often desirable to achieve precise phase alignment between two or more carrier signals, such as signals generated by oscillators. This allows for distributed clock synchronization or coherent combining of the carrier signals for effective phase noise reduction. Maintaining such RF phase alignment typically requires the use of one or more phase-locked loop (PLL) architectures.

[0002] A common PLL design practice is to consider the voltage-controlled oscillator (VCO) as part of the feedback loop, and to tailor the PLL characteristics, such as loop filter bandwidth and voltage swing, to the characteristics of that particular oscillator, such as tuning slope (Hz / V) and tuning voltage input range.

[0003] Delay-locked loops (DLLs) have the advantage of being applicable to signal sources other than voltage-controlled oscillators, allowing their design to be source-independent. Traditional DLLs have a limited delay range, which makes them difficult to set up and prone to loss of lock unless the source characteristics are tightly constrained. DLLs offering "infinite" delay (phase shift) overcome these difficulties, but do not operate at microwave frequencies, can induce additive phase noise, and require at least two loops and / or multiple pulse-to-sawtooth converters. Summary of the Invention

[0004] In accordance with the concepts described herein, an exemplary infinite RF DLL device and method provides phase alignment of RF signals for noise rejection or distributed clock synchronization.

[0005] In accordance with the concepts described herein, the present disclosure provides exemplary infinite RF DLL devices and methods, including source-independent RF DLLs.

[0006] In accordance with the concepts described herein, the present disclosure provides an exemplary infinite RF DLL device and method that includes one phase detector, one infinite phase shift actuator, and one actuator controller.

[0007] In accordance with the concepts described herein, the present disclosure provides an exemplary infinite RF DLL device and method that includes one feedback loop.

[0008] In accordance with the concepts described herein, the present disclosure provides an exemplary infinite RF DLL device and method in which the infinite phase shift actuator includes an in-phase / quadrature (I / Q) mixer.

[0009] In accordance with the concepts described herein, the present disclosure provides an exemplary infinite RF DLL device and method in which the infinite phase shift actuator includes an RF bridge.

[0010] In accordance with the concepts described herein, the present disclosure provides an exemplary infinite RF DLL device and method that operates in the microwave range.

[0011] In accordance with the concepts described herein, the present disclosure provides exemplary infinite RF DLL devices and methods that exhibit low noise.

[0012] In accordance with the concepts described herein, the present disclosure provides an exemplary infinite RF DLL device and method that operates continuously without abrupt switching.

[0013] In accordance with the concepts described herein, the present disclosure provides exemplary infinite RF DLL devices and methods that can be precisely controlled and / or calibrated.

[0014] The methods and processes for making and using the disclosed embodiments may be understood by reference to the figures in the accompanying drawings. It should be understood that the components and structures shown in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the concepts described herein. Like reference characters designate corresponding parts throughout the different views. Moreover, embodiments are illustrated in the drawings by way of example, and not by way of limitation. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram of a general embodiment of an infinite RF DLL. [Figure 2] FIG. 1 is a diagram of a general embodiment of an infinite RF DLL used to phase-lock two external VCOs. [Figure 3] FIG. 1 illustrates an exemplary embodiment of an infinite RF DLL with an I / Q mixer as an infinite phase shifter. [Figure 4] FIG. 1 illustrates an exemplary embodiment of an infinite RF DLL with an RF bridge as an infinite phase shifter. [Figure 5] FIG. 1 is a diagram of a typical multi-input / multi-output infinite RF DLL. [Figure 6] FIG. 1 is a diagram of an infinite RF DLL using frequency multiplier(s). [Figure 7] 1 is a flowchart of a general embodiment of an infinite RF DLL. DETAILED DESCRIPTION OF THE INVENTION

[0016] 1 illustrates an exemplary embodiment of an infinite RF DLL 100 configured to receive a first RF signal RF1 and a second RF signal RF2. In the exemplary embodiment, the RF DLL 100 includes an infinite phase shifter 101, a phase detector 103, and a controller 105.

[0017] The infinite RF DLL device 100 can be configured with external, stand-alone components, as compared to conventional devices that incorporate a DLL or PLL inside a signal source.

[0018] The infinite phase shifter 101 has a first input for receiving the second RF signal RF2, a bus input for receiving at least one control signal from the controller 105, and an output OUT. The phase detector 103 has a first RF connection for receiving at least a portion of the first RF signal RF1, a second RF connection for receiving a portion of the output of the infinite phase shifter 101, and an output.

[0019] The controller 105 has an input connected to the output of the phase detector 103 and at least one output connected to the bus input of the infinite phase shifter 101. The output OUT of the infinite phase shifter 101 provides a low noise signal that is phase-matched to the first RF signal RF1.

[0020] 2 illustrates an exemplary embodiment of a system having an infinite RF DLL 200 configured to receive first and second VCO inputs. In the exemplary embodiment, the system includes a reference device 201, a first VCO 203, and a second VCO 205. The DLL includes an infinite phase shifter 207, a phase detector 209, and a controller 211.

[0021] Reference device 201 outputs an oscillating voltage reference signal. First VCO 203 has an input connected to the output of reference device 201 and an output OUT1 for providing a first RF signal. Second VCO 205 has an input connected to the output of reference device 201 and an output for providing a second RF signal. The VCOs are independently phase locked to a common reference signal using an internal PLL.

[0022] Although VCOs 203 and 205 are phase-locked to a common reference 201, if a narrow-bandwidth internal PLL is used, the phase alignment may be insufficient for purposes such as adding coherent carriers. The Infinite RF DLL provides a completely external means for achieving precise phase alignment. In an exemplary embodiment, no feedback is provided from phase detector 209 to VCOs 203, 205, as in a conventional PLL. In an embodiment, at least one VCO output is post-processed and phase-aligned with the other VCO output. This arrangement allows an external DLL to be connected to various input signals and provide phase-aligned signals.

[0023] 3 illustrates an exemplary embodiment of an infinite RF DLL 300 having an I / Q mixer 301 as an infinite phase shifter. In the exemplary embodiment, the RF DLL 300 includes the I / Q mixer 301, a phase detector 303, and a controller 305.

[0024] The I / Q mixer 301 has a first input for receiving a second RF signal RF2 as a local oscillator signal (LO), a bus input for receiving both I and Q control signals from the controller 305, and an output OUT for providing an RF signal. The phase detector 303 has a first RF connection for receiving at least a portion of the first RF signal RF1, a second RF connection for receiving at least a portion of the RF output OUT of the I / Q mixer 301, and an output which is an intermediate frequency (IF) signal. The output enters the first input of the I / Q mixer 301. A phase-shifted output appears at the output OUT of the I / Q mixer 301. The phase of the output OUT is controlled using the bus inputs (I and Q signals) of the I / Q mixer 301.

[0025] The controller 305 has an input connected to the output of the phase detector 303 and respective outputs connected to the bus inputs of the I / Q mixer 301 for providing the I and Q control signals. The output OUT of the I / Q mixer 301 provides a low noise signal that is phase matched with the first RF signal RF1.

[0026] In the exemplary embodiment, controller 305 includes a low pass filter 309 and an I / Q driver 307. Low pass filter 309 has an input connected to the output of phase detector 303, and an output. I / Q driver 307 has an input connected to the output of low pass filter 309 and two outputs connected to two inputs of I / Q mixer 301 for providing I and Q control signals.

[0027] The controller can sample the output of the phase detector using an analog-to-digital converter and drive the I / Q ports of the infinite phase shifter using a digital-to-analog converter. The controller can operate the system using a closed-loop digital feedback algorithm.

[0028] The controller can consist of analog feedback components that generate I / Q control voltages depending on the output of the phase detector.

[0029] 4 illustrates an exemplary embodiment of an infinite RF DLL 400 having an RF bridge as the infinite phase shifter. In the exemplary embodiment, the infinite RF DLL 400 includes a first phase shifter 401, a second phase shifter 403, a first attenuator 405, a second attenuator 407, a phase detector 409, and a controller 411.

[0030] At least a portion of the first RF signal RF1 is provided to a phase detector 409. The first phase shifter 401 has a first input for receiving a portion of the second RF signal RF2, a second input signal for receiving a control signal from the controller 411, and an output. The second phase shifter 403 has a first input for receiving a portion of the second RF signal RF2, a second input signal for receiving a control signal from the controller 411, and an output. The incident power is split into two arms, where the first arm includes the first phase shifter 401 and an attenuator 405, and the second arm includes the second phase shifter 403 and a second attenuator 407. Each arm includes a >360 phase shifter and a voltage-variable attenuator. In an example of operation, only one arm is active, and the attenuator in the other arm is set to provide high attenuation. If the phase drift of the output signal OUT, described below, approaches the limit of the active phase shifter, the other phase shifter is set to an appropriately selected starting position, and the corresponding attenuation is reduced.

[0031] The first attenuator 405 has a first input connected to the output of the first phase shifter 401, a second input connected to the controller 411, and an output. The second attenuator 407 has a first input connected to the output of the second phase shifter 403, a second input connected to the controller 411, and an output. The outputs of the first attenuator 405 and the second attenuator 407 are combined to provide the RF signal OUT.

[0032] The phase detector 409 has a first RF connection for receiving at least a portion of the first RF signal RF1, a second RF connection for receiving at least a portion of the RF signal OUT of the first attenuator 405 and the second attenuator 407, and an output.

[0033] The controller 411 has an input connected to the output of the phase detector 409, a first output signal connected to the second input of the first phase shifter 401, a second output signal connected to the second input of the second phase shifter 403, a third output connected to the second input of the first attenuator 405, and a fourth output connected to the second input of the second attenuator 407. The output signal OUT is a combination of the outputs of the first attenuator 405 and the second attenuator 407 and provides a low noise signal that is phase matched with the first RF signal RF1.

[0034] In the exemplary embodiment, controller 411 includes a low pass filter 413 and an RF bridge controller 415. Low pass filter 413 has an input connected to the output of phase detector 409, and an output. RF bridge controller 415 has an input connected to the output of low pass filter 413, a first output connected to the second input of first phase shifter 401, a second output connected to the second input of second phase shifter 403, a third output connected to the second input of first attenuator 405, and a fourth output connected to the second input of second attenuator 407.

[0035] 5 is a diagram of an embodiment of a multi-input / multi-output Infinite RF DLL. A typical Infinite RF DLL 501 aligns signal RF2 to signal RF1. Any number of additional signals RF_N can also be aligned with additional Infinite RF DLLs 502. The external nature allows for scalable distributed clock synchronization.

[0036] 6 illustrates an exemplary embodiment of an infinite RF DLL using a frequency multiplier (or divider) to phase lock signals of different frequencies. The infinite RF DLL 600 is comprised of a phase detector 605, a controller 604, and an infinite phase actuator 603. The frequency multiplier may be placed in the phase detector reference arm 601, the phase detector feedback arm 602, or both.

[0037] 7 is a flowchart of an example method 700 of an infinite RF DLL in accordance with the concepts described herein. In an example embodiment, the method 700 includes receiving a first RF signal by a phase detector in step 701.

[0038] Step 703 of method 700 includes receiving a second RF signal by an infinite phase shifter. Step 705 of method 700 includes receiving an output of the infinite phase shifter by a phase detector. Step 707 of method 700 includes receiving an output of the phase detector by a controller. Step 709 of method 700 includes receiving an output of the controller by the infinite phase shifter. Step 711 of method 700 includes outputting a low noise signal by the infinite phase shifter that is phase-matched to the first RF signal.

[0039] While exemplary embodiments of the present disclosure have been described, it will be apparent to those skilled in the art that other embodiments incorporating these concepts may also be used. The embodiments contained herein should not be limited to the disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.

[0040] Elements of different embodiments described herein can be combined to form other embodiments not specifically described above. Various elements described in the context of a single embodiment may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.

[0041] Various embodiments of the concepts, systems, devices, structures, and techniques for which protection is sought are described herein with reference to the associated drawings. As noted above, in embodiments, the concepts and features described herein may be embodied in a digital multi-beam beamforming system. Alternative embodiments may be contemplated without departing from the scope of the concepts, systems, devices, structures, and techniques described herein.

[0042] It should be noted that in the above description and drawings, various connections and relationships (e.g., above, below, adjacent, etc.) are described between elements. These connections and / or relationships may be direct or indirect unless otherwise specified, and the described concepts, systems, devices, structures, and techniques are not intended to be limiting in this regard. Thus, coupling of entities can refer to direct or indirect coupling, and relationship between entities may be direct or indirect relationship.

[0043] As an example of an indirect positional relationship, reference in this description to forming layer "A" above layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," so long as the relevant properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layer(s). The following definitions and abbreviations shall be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and may include other elements not expressly listed or other elements inherent to such composition, mixture, process, method, article, or device.

[0044] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "one or more" and "one or more" are understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include indirect and direct "connections."

[0045] References in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but that all embodiments may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is believed to be within the knowledge of one of ordinary skill in the art to achieve such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0046] For purposes of this description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," and "bottom" (to name a few) and their derivatives refer to the structures and methods described as oriented in the drawings. The terms "overlying," "above," "on," "located on," or "located above" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that intervening elements, such as interface structures, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without intervening elements. Such terms may also be referred to as directional or positional terms.

[0047] The use of ordinal numbers such as "first," "second," "third," etc. in the claims to modify claim elements does not, in itself, imply a priority, precedence, or order of one claim element relative to other claim elements, or the chronological order in which method actions are performed, but is merely used as a label to distinguish one claim element with a particular name from another element with the same name (other than the use of the ordinal number) to distinguish between claim elements.

[0048] The terms "approximately" and "about" may be used in some embodiments to mean within ±20% of a target value, in some embodiments within ±10% of a target value, in some embodiments within ±5% of a target value, and even in some embodiments within ±2% of a target value. The terms "approximately" and "about" may include the target value. The term "substantially equal" may be used to refer to values ​​that are in some embodiments within ±20% of each other, in some embodiments within ±10% of each other, in some embodiments within ±5% of each other, and even in some embodiments within ±2% of each other.

[0049] The term "substantially" may be used in some embodiments to refer to a value within ±20%, in some embodiments within ±10%, in some embodiments within ±5%, and even in some embodiments within ±2% of a relative measurement. For example, a first direction that is "substantially" perpendicular to a second direction may refer to a first direction that is within ±20% of forming a 90° angle with the second direction in some embodiments, within ±10% of forming a 90° angle with the second direction in some embodiments, within ±5% of forming a 90° angle with the second direction, and even in some embodiments within ±2% of forming a 90° angle with the second direction.

[0050] It is to be understood that the disclosed subject matter is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings, as the disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways.

[0051] It is also to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. Thus, those skilled in the art will appreciate that the conception underlying the present disclosure may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out some of the purposes of the disclosed subject matter. Accordingly, the claims should be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.

[0052] While the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that the disclosure is made by way of example only, and that numerous changes can be made in the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter.

Claims

1. 1. A radio frequency (RF) delay locked loop (DLL) device comprising: a phase detector having a first input, a second input, and an output configured to receive the first RF signal; an infinite phase shifter having a first input configured to receive a second RF signal, an input bus, and an output connected to the second input of the phase detector; a controller having a first input connected to the output of the phase detector and an output bus connected to the input bus of the infinite phase shifter; the output of the infinite phase shifter comprises a low noise signal phase-matched to the first RF signal; The infinite phase shifter a first phase shifter having a first input configured to receive the second RF signal, an input bus, and an output; a first attenuator having a first input connected to the output of the first phase shifter, a second input, and an output; a second phase shifter having a first input configured to receive the second RF signal, an input bus, and an output; a second attenuator having a first input connected to the output of the second phase shifter, a second input, and an output; an output signal of the first attenuator and an output signal of the second attenuator are combined to generate the low-noise signal; device.

2. a reference signal device having an output; a first voltage controlled oscillator (VCO) having an input connected to the output of the reference signal device and an output connected to the first input of the phase detector, the VCO configured to provide the first RF signal; 10. The device of claim 1, further comprising: a second VCO having an input connected to the output of the reference signal device and an output connected to the first input of the infinite phase shifter, the second VCO configured to provide the second RF signal.

3. The controller: a low pass filter having an input connected to the output of the phase detector, and an output; an RF bridge controller; 2. The device of claim 1, wherein the RF bridge controller has an input connected to the output of the low pass filter, a first output bus connected to the input bus of the first phase shifter, a second output bus connected to the input bus of the second phase shifter, a first output connected to the second input of the first attenuator, and a second output connected to the second input of the second attenuator.

4. The device of claim 3 , wherein the first attenuator and the second attenuator each comprise a voltage variable attenuator.

5. a frequency multiplier or divider is used in the phase detector reference arm, the phase detector feedback arm, or both; the phase detector reference arm is an input path to the first input of the phase detector; 2. The device of claim 1, wherein the phase detector feedback arm is an input path to the second input of the phase detector.

6. 1. A method for an infinite radio frequency (RF) delay locked loop (DLL), comprising: receiving a first RF signal with a phase detector; receiving a second RF signal with an infinite phase shifter; receiving an output of the infinite phase shifter by the phase detector; receiving an output of the phase detector by a controller; receiving an output of the controller by the infinite phase shifter; outputting a low noise signal that is phase-matched to the first RF signal by the infinite phase shifter; The infinite phase shifter a first phase shifter having a first input configured to receive the second RF signal, an input bus, and an output; a first attenuator having a first input connected to the output of the first phase shifter, a second input, and an output; a second phase shifter having a first input configured to receive the second RF signal, an input bus, and an output; a second attenuator having a first input connected to the output of the second phase shifter, a second input, and an output; combining the output signal of the first attenuator and the output signal of the second attenuator to generate the low-noise signal; The method.

7. Generating a reference signal; providing the first RF signal to an input of the phase detector based on the reference signal using a first voltage controlled oscillator (VCO); 7. The method of claim 6, further comprising: using a second VCO to provide the second RF signal to an input of the infinite phase shifter based on the reference signal.

8. The controller: a low pass filter having an input connected to the output of the phase detector, and an output; an RF bridge controller; 7. The method of claim 6, wherein the RF bridge controller has an input connected to the output of the low pass filter, a first output bus connected to the input bus of the first phase shifter, a second output bus connected to the input bus of the second phase shifter, a first output connected to the second input of the first attenuator, and a second output connected to the second input of the second attenuator.

9. 7. The method of claim 6, wherein the first attenuator and the second attenuator each comprise a voltage variable attenuator.

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