Semiconductor Devices

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device includes one die pad DPH, the other die pad DPL, a semiconductor chip CPL mounted on the other die pad DPL, a semiconductor chip CPC mounted on the one die pad DPH, a semiconductor chip CPH mounted on the one die pad DPH, and a sealing body for sealing the above components. The semiconductor chip CPC includes two coils L1a and L1b that are magnetically coupled to each other. One coil L1a in the semiconductor chip CPC is electrically connected to a circuit formed in the semiconductor chip CPL, and the other coil L1b in the semiconductor chip CPC is electrically connected to a circuit formed in the semiconductor chip CPH. In cross-sectional view, the other coil L1b is located closer to the die pad DPH than the one coil L1a. Power consumption during operation of the semiconductor chip CPH is greater than power consumption during operation of the semiconductor chip CPL.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device incorporating a plurality of semiconductor chips. [Background technology]

[0002] A semiconductor device in the form of a semiconductor package can be manufactured by mounting a semiconductor chip on a die pad, electrically connecting the pad electrodes of the semiconductor chip to the leads via wires, and sealing them with resin.

[0003] International Publication No. 2015-114758 (Patent Document 1) describes a technique for transmitting an electrical signal by inductively coupling two coils within a semiconductor chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2015-114758 Summary of the Invention [Problem to be solved by the invention]

[0005] It is desirable to improve the reliability of a semiconductor device that incorporates three semiconductor chips and uses a magnetically coupled coil within one of the semiconductor chips to transmit signals between two of the semiconductor chips.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] According to one embodiment, a semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip and a third semiconductor chip mounted on the second chip mounting portion, and a sealing body that seals them. The third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. The first coil is electrically connected to a first circuit formed in the first semiconductor chip, and the second coil is electrically connected to a second circuit formed in the second semiconductor chip. In a cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. The power consumption of the second semiconductor chip during operation is greater than the power consumption of the first semiconductor chip during operation. The area of ​​the second chip mounting portion is greater than the area of ​​the first chip mounting portion. [Effects of the Invention]

[0008] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit diagram illustrating an inverter circuit using a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a top view of a semiconductor device according to an embodiment; [Figure 3] 1 is a plan perspective view of a semiconductor device according to an embodiment; [Figure 4] 1 is a plan perspective view of a semiconductor device according to an embodiment; [Figure 5] 1 is a plan perspective view of a semiconductor device according to an embodiment; [Figure 6] FIG. 2 is a bottom view of the semiconductor device according to the embodiment; [Figure 7] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 8] FIG. 2 is a plan view of the semiconductor device according to the embodiment during the manufacturing process; [Figure 9] 9 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 8. FIG. [Figure 10] 10 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 9. FIG. [Figure 11] 11 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 10. FIG. [Figure 12] 12 is a cross-sectional view of the same semiconductor device as in FIG. 11 during the manufacturing process. [Figure 13] 1 is a cross-sectional view schematically showing a semiconductor chip in a semiconductor device according to an embodiment of the present invention; [Figure 14] 1 is a cross-sectional view schematically showing a semiconductor chip in a semiconductor device according to an embodiment of the present invention; [Figure 15] FIG. 1 is a plan perspective view of a semiconductor device of a first studied example. [Figure 16] FIG. 2 is a cross-sectional view of a semiconductor device of a first studied example. [Figure 17] FIG. 10 is a cross-sectional view schematically showing a semiconductor chip in a semiconductor device of a second studied example. [Figure 18] FIG. 10 is a plan perspective view of a semiconductor device according to a modified example. [Figure 19] FIG. 10 is a plan perspective view of a semiconductor device according to a modified example. [Figure 20] FIG. 10 is a plan view of a lead frame used to manufacture a semiconductor device according to a modified example. [Figure 21] FIG. 10 is a plan view of a semiconductor device according to a modified example during a manufacturing process. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0012] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0013] (Embodiment) <Circuit configuration> Fig. 1 is a circuit diagram showing an inverter circuit using a semiconductor device PKG of this embodiment. In Fig. 1, the portion surrounded by a dotted line and labeled CPH is formed in the semiconductor chip CPH, the portion surrounded by a dotted line and labeled CPL is formed in the semiconductor chip CPL, the portion surrounded by a dotted line and labeled CPC is formed in the semiconductor chip CPC, and the portion surrounded by a dashed line and labeled PKG is formed in the semiconductor device PKG. In the inverter circuit shown in Fig. 1, two semiconductor devices PKG are used.

[0014] The semiconductor device PKG used in the inverter circuit shown in Fig. 1 includes semiconductor chips CPC, CPL, and CPH. A transmitter circuit TX1 and a receiver circuit RX2 are formed in the semiconductor chip CPL, and a receiver circuit RX1, a transmitter circuit TX2, and a drive circuit (control circuit) DR are formed in the semiconductor chip CPH. A transformer TR1 consisting of magnetically coupled coils L1a and L1b, and a transformer TR2 consisting of magnetically coupled coils L2a and L2b are formed in the semiconductor chip CPC. The inverter circuit shown in Fig. 1 also includes a control circuit CC, which is formed in another semiconductor chip provided outside the semiconductor package PKG.

[0015] The transmitter circuit TX1 and receiver circuit RX1 are circuits for transmitting signals from the control circuit CC to the driver circuit DR. The transmitter circuit TX1 converts the signal sent from the control circuit CC to the transmitter circuit TX1 and transmits it to the receiver circuit RX1 via the transformer TR1. The receiver circuit RX1 converts the signal received from the transmitter circuit TX1 via the transformer TR1 and transmits it to the driver circuit DR. The transmitter circuit TX2 and receiver circuit RX2 are circuits for transmitting signals from the driver circuit DR to the control circuit CC. The transmitter circuit TX2 converts the signal sent from the driver circuit DR to the transmitter circuit TX2 and transmits it to the receiver circuit RX2 via the transformer TR2. The receiver circuit RX2 converts the signal received from the transmitter circuit TX2 via the transformer TR2 and transmits it to the control circuit CC.

[0016] 1 has power transistors TS1 and TS2. The power transistor TS1 is a transistor for a high-side switch (high potential side switch), and the power transistor TS2 is a transistor for a low-side switch (low potential side switch). The power transistors TS1 and TS2 are each formed in separate semiconductor chips provided outside the semiconductor package PKG.

[0017] In the following, a case where the power transistors TS1 and TS2 are power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) will be described. IGBTs (Insulated Gate Bipolar Transistors) can also be used as the power transistors TS1 and TS2. In that case, in the following description of the power transistors TS1 and TS2, "source" should be read as "emitter" and "drain" should be read as "collector."

[0018] In addition, in this application, the term "MOSFET" includes not only MISFETs (Metal Insulator Semiconductor Field Effect Transistors) that use an oxide film (silicon oxide film) as a gate insulating film, but also MISFETs that use an insulating film other than an oxide film as a gate insulating film.

[0019] The power transistors TS1 and TS2 are connected in series, and the source (S1) of the power transistor TS1 is connected to the drain (D2) of the power transistor TS2. A power supply potential (power supply voltage) V1 is supplied to the drain (D1) of the power transistor TS1 from a power supply (battery) BT1. A power supply potential (power supply voltage) V2 is supplied to the control circuit CC from a power supply (battery) BT2. The power supply potential V1 supplied to the drain (D1) of the power transistor TS1 is significantly higher than the power supply potential V2 (e.g., several volts to several tens of volts) supplied to the control circuit CC, and is, for example, 100 volts or more (several hundred volts). A reference potential lower than the power supply potential V1, for example, a ground potential (GND), is supplied to the source (S2) of the power transistor TS2. The gate (G1) of the power transistor TS1 and the gate (G2) of the power transistor TS2 are each connected to a drive circuit DR.

[0020] In this embodiment, the same number of semiconductor devices PKGs as the number of power transistors TS1 and TS2 are used. In this case, a drive circuit DR provided in the semiconductor device PKG for the power transistor TS1 controls the voltage of the gate (G1) of the power transistor TS1, and a drive circuit DR provided in the semiconductor device PKG for the power transistor TS2 controls the voltage of the gate (G2) of the power transistor TS2. As another form, one semiconductor device PKG may be used for two power transistors TS1 and TS2, and in that case, a drive circuit DR provided in the common semiconductor device PKG controls the voltages of the gates (G1 and G2) of the two power transistors TS1 and TS2.

[0021] The operation of the power transistors TR1 and TR2 can be controlled by controlling the gate voltage supplied to the gates (G1, G2) of each power transistor TS1 and TS2 from the drive voltage DR in accordance with a signal (control signal) supplied from the control circuit CC to the drive circuit via the transmission circuit TX1, transformer TR1, and receiver circuit RX1.

[0022] A terminal T1 provided between the source (S1) of the power transistor TS1 and the drain (D2) of the power transistor TS2 is an output terminal of the inverter circuit. The terminal T1 is connected to a load LOD. The load LOD is, for example, a motor coil. The DC power supplied to the inverter circuit is converted into AC power by the inverter circuit and supplied to the load LOD.

[0023] A transformer TR1 is interposed between the transmitter circuit TX1 and the receiver circuit RX1, and a transformer TR2 is interposed between the transmitter circuit TX2 and the receiver circuit RX2. The control circuit CC can transmit a signal (control signal) to the driver circuit DR via the transmitter circuit TX1, transformer TR1, and receiver circuit RX1. The driver circuit DR can also transmit a signal to the control circuit CC via the transmitter circuit TX2, transformer TR2, and receiver circuit RX2. Coils L1a, L1b, L2a, and L2b can each be considered as inductors.

[0024] The transformer TR1 is formed by coils L1a and L1b formed within the semiconductor chip CPC. However, coils L1a and L1b are not connected by any conductor but are magnetically coupled to each other. Therefore, when current flows through coil L1a, an induced electromotive force is generated in coil L1b in response to changes in the current, resulting in an induced current. Coil L1a is the primary coil, and coil L1b is the secondary coil. By utilizing this, a signal is sent from the transmitter circuit TX1 to coil L1a (primary coil) of the transformer TR1, causing a current to flow. The receiver circuit RX1 then detects (receives) the induced current (or induced electromotive force) generated in coil L1b (secondary coil) of the transformer TR1. This allows the receiver circuit RX1 to receive a signal corresponding to the signal sent by the transmitter circuit TX1.

[0025] The transformer TR2 is formed by coils L2a and L2b formed within the semiconductor chip CPC. However, coils L2a and L2b are not connected by a conductor but are magnetically coupled. Therefore, when current flows through coil L2b, an induced electromotive force is generated in coil L2a in response to changes in the current, resulting in an induced current. Coil L2b is the primary coil, and coil L2a is the secondary coil. By utilizing this, the transmitter circuit TX2 sends a signal to coil L2b (primary coil) of the transformer TR2 to cause a current to flow. The receiver circuit RX2 then detects (receives) the induced current (or induced electromotive force) generated in coil L2a (secondary coil) of the transformer TR2. This allows the receiver circuit RX2 to receive a signal corresponding to the signal sent by the transmitter circuit TX2.

[0026] Signals can be transmitted between the semiconductor chip CPL and the semiconductor chip CPH via a path from the transmitting circuit TX1 via the transformer TR1 to the receiving circuit RX1, and a path from the transmitting circuit TX2 via the transformer TR2 to the receiving circuit RX2.

[0027] The semiconductor chip CPL and the semiconductor chip CPH have different voltage levels. For example, the semiconductor chip CPL is electrically connected to a low-voltage region having a circuit (e.g., a control circuit CC) that operates or is driven at a low voltage (e.g., several volts to several tens of volts) via a wire BW and a lead LD (specifically, a lead LD2) described later. The semiconductor chip CPH is electrically connected to a high-voltage region having a circuit (e.g., power transistors TS1 and TS2) that operates or is driven at a voltage higher than the low voltage (e.g., 100 V or higher) via a wire BW and a lead LD (specifically, a lead LD1) described later. However, since signals are transmitted between the semiconductor chips CPL and CPH via transformers TR1 and TR2, signals can be transmitted between circuits of different voltages.

[0028] Although FIG. 1 shows a case where the control circuit CC is built into a semiconductor chip other than the semiconductor chips CPC, CPH, and CPL, as another embodiment, the control circuit CC can also be built into the semiconductor chip CPL.

[0029] <About the structure of semiconductor devices> FIG. 2 is a top view of the semiconductor device PKG of this embodiment, FIGS. 3 to 5 are planar perspective views of the semiconductor device PKG, FIG. 6 is a bottom view (rear view) of the semiconductor device PKG, and FIG. 7 is a cross-sectional view of the semiconductor device PKG. FIG. 3 shows a planar perspective view of the upper surface of the semiconductor device PKG when the sealing portion MR is seen through. FIG. 4 shows a planar perspective view of the upper surface of the semiconductor device PKG when the wires BW are further seen through (omitted) in FIG. 3. FIG. 5 shows a planar perspective view of the upper surface of the semiconductor device PKG when the semiconductor chips CPC, CPH, and CPL are further seen through (omitted) in FIG. 4. In FIGS. 3 to 5, the position of the outer periphery of the sealing portion MR is indicated by a dotted line. Also, a cross-sectional view of the semiconductor device PKG taken along line A1-A1 in FIGS. 2 and 3 substantially corresponds to FIG. 7. Also, FIGS. 2 to 6 show the X and Y directions. Here, the X direction and the Y direction are directions that intersect with each other, and more specifically, are directions that are perpendicular to each other.

[0030] The semiconductor device (semiconductor package) PKG of this embodiment shown in Figures 2 to 7 is a semiconductor device in the form of a resin-sealed semiconductor package, and in this case is a semiconductor device in the form of an SOP (Small Outline Package). Hereinafter, the configuration of the semiconductor device PKG will be described with reference to Figures 2 to 7.

[0031] The semiconductor device PKG of this embodiment shown in Figures 2 to 7 has three semiconductor chips CPC, CPH, and CPL, a die pad DPH on which two semiconductor chips CPC and CPH are mounted, a die pad DPL on which one semiconductor chip CPL is mounted, a plurality of wires (bonding wires) BW, a plurality of leads LD, and a sealing part MR that seals these.

[0032] The sealing portion MR as a sealing body is made of a resin material such as a thermosetting resin material, and may contain a filler, etc. For example, the sealing portion MR may be formed using an epoxy resin containing a filler.

[0033] The sealing portion MR has an upper surface MRa which is one of the main surfaces, a lower surface (rear surface, bottom surface) MRb which is the main surface opposite the upper surface MRa, and side surfaces MRc1, MRc2, MRc3, and MRc4 which intersect with the upper surface MRa and the lower surface MRb. The side surfaces MRc1 and MRc3 are approximately parallel to the X direction, and the side surfaces MRc2 and MRc4 are approximately parallel to the Y direction. In the sealing portion MR, the side surfaces MRc1 and MRc3 are located opposite each other, and the side surfaces MRc2 and MRc4 are located opposite each other, with the side surface MRc1 intersecting with the side surfaces MRc2 and MRc4, and the side surface MRc3 intersecting with the side surfaces MRc2 and MRc4. The upper surface MRa and the lower surface MRb are each parallel to both the X direction and the Y direction. The planar shape of the sealing portion MR, i.e., the planar shapes of the upper surface MRa and the lower surface MRb of the sealing portion MR, are, for example, rectangular (oblong). The sealing portion MR has a corner KD1 where the side surface MRc1 and the side surface MRc2 of the sealing portion MR intersect, a corner KD2 where the side surface MRc2 and the side surface MRc3 of the sealing portion MR intersect, a corner KD3 where the side surface MRc3 and the side surface MRc4 of the sealing portion MR intersect, and a corner KD4 where the side surface MRc4 and the side surface MRc1 of the sealing portion MR intersect.

[0034] A portion of each of the leads LD of the semiconductor device PKG is sealed within the sealing portion MR, and another portion protrudes from the side surface of the sealing portion MR to the outside of the sealing portion MR. Hereinafter, the portion of the lead LD located within the sealing portion MR will be referred to as an inner lead portion, and the portion of the lead LD located outside the sealing portion MR will be referred to as an outer lead portion. A plating layer (not shown), such as a solder plating layer, may be formed on the outer lead portion of the lead LD.

[0035] The semiconductor device PKG of this embodiment has a structure in which a part of each lead LD (outer lead part) protrudes from the side surface of the sealing part MR, and the following description will be based on this structure, but is not limited to this structure. For example, it is also possible to adopt a structure in which each lead LD hardly protrudes from the side surface of the sealing part MR and a part of each lead LD is exposed at the lower surface MRb of the sealing part MR (SON (Small Outline Nonleaded Package) type structure).

[0036] The multiple leads LD of the semiconductor device PKG are composed of multiple leads LD arranged on the side surface MRc1 of the sealing portion MR and multiple leads LD arranged on the side surface MRc3 of the sealing portion MR. In the cases of FIGS. 2 to 7, no leads LD are arranged on the side surfaces MRc2 and MRc4 of the sealing portion MR. Hereinafter, the leads LD arranged on the side surface MRc1 of the sealing portion MR will be designated with the symbol LD1 and referred to as leads LD1. Furthermore, the leads LD arranged on the side surface MRc3 of the sealing portion MR will be designated with the symbol LD2 and referred to as leads LD2.

[0037] Each outer lead portion of the plurality of leads LD arranged on the side surface MRc1 of the sealing portion MR protrudes from the side surface MRc1 of the sealing portion MR to the outside of the sealing portion MR. Also, each outer lead portion of the plurality of leads LD arranged on the side surface MRc3 of the sealing portion MR protrudes from the side surface MRc3 of the sealing portion MR to the outside of the sealing portion MR. The outer lead portion of each lead LD is bent so that the lower surface near the end of the outer lead portion is positioned on approximately the same plane as the lower surface MRb of the sealing portion MR. The outer lead portion of the lead LD functions as an external connection terminal portion (external terminal) of the semiconductor device PKG.

[0038] The die pad DPL is a chip mounting portion on which a semiconductor chip CPL is mounted, and the die pad DPH is a chip mounting portion on which two semiconductor chips CPC and CPH are mounted. The die pads DPH and DPL are spaced apart in the X direction, and a part of the sealing portion MR is interposed between the die pads DPH and DPL. Of the die pads DPH and DPL, the die pad DPH is arranged on the side closer to the side surface MRc1 of the sealing portion MR, and the die pad DPL is arranged on the side closer to the side surface MRc3 of the sealing portion MR. That is, in the Y direction, the die pad DPH is arranged between the die pad DPL and the side surface MRc1 of the sealing portion MR, and the die pad DPL is arranged between the die pad DPH and the side surface MRc3 of the sealing portion MR. Each of the die pads DPH and DPL is sealed within the sealing portion MR and is not exposed from the sealing portion MR. That is, each of the die pads DPH and DPL is not exposed at the upper surface MRa and the lower surface MRb of the sealing portion MR.

[0039] The die pads DPH, DPL and the leads LD are made of a conductor, preferably a metal material such as copper (Cu) or a copper alloy. The die pads DPH, DPL and the leads LD are preferably made of the same material (the same metal material), which makes it easier to fabricate a lead frame LF (described later) in which the die pads DPH, DPL and the leads LD are connected, and also makes it easier to manufacture a semiconductor device PKG using the lead frame LF.

[0040] The die pad DPH has an upper surface DPHa which is the main surface on which the semiconductor chips CPC and CPH are mounted, a lower surface (back surface) DPHb which is the main surface opposite thereto, and side surfaces DPHc1, DPHc2, DPHc3, and DPHc4 which intersect with the upper surface DPHa and the lower surface DPHb. In the die pad DPH, the side surface DPHc1 is located on the side of the side surface MRc1 of the sealing portion MR, the side surface DPHc2 is located on the side of the side surface MRc2 of the sealing portion MR, the side surface DPHc3 is located on the side of the side surface MRc3 of the sealing portion MR, and the side surface DPHc4 is located on the side of the side surface MRc4 of the sealing portion MR. In the die pad DPH, the side surfaces DPHc1 and DPHc3 are located opposite to each other, the side surfaces DPHc2 and DPHc4 are located opposite to each other, the side surface DPHc1 intersects with the side surfaces DPHc2 and DPHc4, and the side surface DPHc3 intersects with the side surfaces DPHc2 and DPHc4.

[0041] The die pad DPL also has an upper surface DPLa which is the main surface on which the semiconductor chip CPL is mounted, a lower surface (back surface) DPLb which is the main surface opposite thereto, and side surfaces DPLc1, DPLc2, DPLc3, and DPLc4 which intersect with the upper surface DPLa and the lower surface DPLb. In the die pad DPL, the side surface DPLc1 is located on the side surface MRc1 of the sealing portion MR, the side surface DPLc2 is located on the side surface MRc2 of the sealing portion MR, the side surface DPLc3 is located on the side surface MRc3 of the sealing portion MR, and the side surface DPLc4 is located on the side surface MRc4 of the sealing portion MR. In the die pad DPL, the side surfaces DPLc1 and DPLc3 are located opposite each other, and the side surfaces DPLc2 and DPLc4 are located opposite each other, with the side surface DPLc1 intersecting with the side surfaces DPLc2 and DPLc4, and the side surface DPLc3 intersecting with the side surfaces DPLc2 and DPLc4. A side surface DPHc3 of the die pad DPH and a side surface DPLc1 of the die pad DPL face each other via a part of the sealing portion MR.

[0042] The side surfaces DPHc1 and DPHc3 of the die pad DPH and the side surfaces DPLc1 and DPLc3 of the die pad DPL are substantially parallel to the X direction, and the side surfaces DPHc2 and DPHc4 of the die pad DPH and the side surfaces DPLc2 and DPLc4 of the die pad DPL are substantially parallel to the Y direction. The upper surface DPHa and the lower surface DPHb of the die pad DPH and the upper surface DPLa and the lower surface DPLb of the die pad DPL are each substantially parallel to both the X direction and the Y direction. The planar shape of each of the die pads DPH and DPL is, for example, rectangular.

[0043] Of the multiple leads LD arranged on the side surface MRc1 of the encapsulating unit MR, the inner lead portion of lead LD1a is integrally connected to the side surface DPHc1 of the die pad DPH, the inner lead portion of lead LD1b is integrally connected to the side surface DPHc2 of the die pad DPH, and the inner lead portion of lead LD1c is integrally connected to the side surface DPHc4 of the die pad DPH. The leads LD1a, LD1b, and LD1c function as suspension leads that support the die pad DPH on the framework of the lead frame during manufacturing of the semiconductor device PKG. Furthermore, of the multiple leads LD arranged on the side surface MRc3 of the encapsulating unit MR, the inner lead portion of lead LD2a is integrally connected to the side surface DPLc2 of the die pad DPL, and the inner lead portion of lead LD2b is integrally connected to the side surface DPLc4 of the die pad DPL. The leads LD2a and LD2b function as suspension leads that support the die pad DPL on the framework of the lead frame during manufacturing of the semiconductor device PKG. On the side surface MRc1 of the sealing portion MR, a plurality of leads LD (LD1) are lined up in the X direction, with the leads LD1b and LD1c located at both ends of the arrangement. Also, on the side surface MRc3 of the sealing portion MR, a plurality of leads LD (LD2) are lined up in the X direction, with the leads LD2a and LD2b located at both ends of the arrangement.

[0044] Each of the semiconductor chips CPC, CPH, and CPL has a front surface that is one main surface and a back surface that is the opposite main surface. The semiconductor chip CPH is mounted on the upper surface DPHa of the die pad DPH via a bonding material BDH, with the back surface of the semiconductor chip CPH facing the die pad DPH. The semiconductor chip CPC is mounted on the upper surface DPHa of the die pad DPH via a bonding material BDC, with the back surface of the semiconductor chip CPC facing the die pad DPH. The semiconductor chip CPL is mounted on the upper surface DPLa of the die pad DPL via a bonding material BDL, with the back surface of the semiconductor chip CPL facing the die pad DPL. That is, of the semiconductor chips CPC, CPH, and CPL, the semiconductor chips CPC and CPH are mounted on the die pad DPH, and the semiconductor chip CPL is mounted on the die pad DPL. The planar dimensions (planar area) of the die pad DPH are larger than the planar dimensions (planar area) of the die pad DPL, so it is possible to mount two semiconductor chips CPC and CPH on the die pad DPH.

[0045] On the upper surface DPHa of the die pad DPH, the region where the semiconductor chip CPC is mounted and the region where the semiconductor chip CPH is mounted are spaced apart (specifically, spaced apart in the Y direction). That is, the semiconductor chips CPC and CPH are not stacked on top of each other, but are arranged side by side on the upper surface DPHa of the die pad DPH at a distance from each other. In a plan view, the semiconductor chips CPL, CPC, and CPH are arranged side by side in the Y direction, with the semiconductor chip CPC being arranged between the semiconductor chips CPL and CPH. The planar dimensions (planar area) of the die pad DPH are larger than the planar dimensions (planar area) of the semiconductor chips CPC and CPH, and the semiconductor chips CPC and CPH are included in the upper surface DPHa of the die pad DPH in a planar view. Furthermore, the planar dimensions (planar area) of the die pad DPL are larger than the planar dimensions (planar area) of the semiconductor chip CPL, and the semiconductor chip CPL is included in the upper surface DPLa of the die pad DPL in a planar view. The semiconductor chips CPC, CPH, and CPL each have a rectangular planar shape, for example. The rectangle forming the planar shape of the semiconductor chips CPC, CPH, and CPL has two sides substantially parallel to the X direction and two sides substantially parallel to the Y direction.

[0046] The bonding materials BDC, BDH, and BDL can be suitably made of a conductive bonding material such as silver paste. The back surface of the semiconductor chip CPH is bonded and fixed to the die pad DPH via the bonding material BDH, the back surface of the semiconductor chip CPC is bonded and fixed to the die pad DPH via the bonding material BDC, and the back surface of the semiconductor chip CPL is bonded and fixed to the die pad DPL via the bonding material BDL. The semiconductor chips CPC, CPH, and CPL are sealed within the sealing portion MR and are not exposed from the sealing portion MR.

[0047] An insulating bonding material can also be used as the bonding materials BDC, BDH, and BDL. However, when a conductive bonding material is used as the bonding materials BDC, BDH, and BDL, there is an advantage that the heat generated in the semiconductor chips CPC, CPH, and CPL can be easily conducted to the die pads DPH and DPL via the bonding materials BDC, BDH, and BDL.

[0048] A plurality of pads PH1, PH2, PH3, and PH4 are formed on the surface of the semiconductor chip CPH. A plurality of pads PL1, PL2, PL3, and PL4 are formed on the surface of the semiconductor chip CPL. A plurality of pads PC1, PC2, PC3, and PC4 are formed on the surface of the semiconductor chip CPC. Note that "bonding pads," "bonding pad electrodes," "pad electrodes," or "electrodes" will be simply referred to as "pads."

[0049] The pads PH1, PH2, PH3, and PH4 of the semiconductor chip CPH are electrically connected to circuits (such as the above-mentioned receiving circuit RX1, transmitting circuit TX2, and driving circuit DR) formed in the semiconductor chip CPH through internal wiring of the semiconductor chip CPH. Here, the pad PH1 of the semiconductor chip CPH is a pad electrically connected to the pad PC3 of the semiconductor chip CPC through a wire BW. The pad PH2 of the semiconductor chip CPH is a pad electrically connected to the pad PC4 of the semiconductor chip CPC through a wire BW. The pad PH3 of the semiconductor chip CPH is a pad electrically connected to the lead LD1 through a wire BW. The pad PH4 of the semiconductor chip CPH is a pad electrically connected to the die pad DPH through a wire BW. The pad PH1 of the semiconductor chip CPH is electrically connected to the receiving circuit RX1 in the semiconductor chip CPH through internal wiring of the semiconductor chip CPH, and the pad PH2 of the semiconductor chip CPH is electrically connected to the transmitting circuit TX2 in the semiconductor chip CPH through internal wiring of the semiconductor chip CPH.

[0050] Each of the pads PL1, PL2, PL3, and PL4 of the semiconductor chip CPL is electrically connected to a circuit (such as the above-mentioned transmitting circuit TX1 and receiving circuit RX2) formed in the semiconductor chip CPL through the internal wiring of the semiconductor chip CPL. Here, the pad PL1 of the semiconductor chip CPL is a pad electrically connected to the pad PC1 of the semiconductor chip CPC via a wire BW. The pad PL2 of the semiconductor chip CPL is a pad electrically connected to the pad PC2 of the semiconductor chip CPC via a wire BW. The pad PL3 of the semiconductor chip CPL is a pad electrically connected to the lead LD2 via a wire BW. L The pad PL4 is electrically connected to the die pad DPL via the wire BW. The pad PL1 of the semiconductor chip CPL is electrically connected to the transmitting circuit TX1 in the semiconductor chip CPH via the internal wiring of the semiconductor chip CPL, and the pad PL2 of the semiconductor chip CPL is electrically connected to the receiving circuit RX2 in the semiconductor chip CPL via the internal wiring of the semiconductor chip CPL.

[0051] The pad PC1 of the semiconductor chip CPC is a pad electrically connected to the coil L1a formed in the semiconductor chip CPC. The pad PC2 of the semiconductor chip CPC is a pad electrically connected to the coil L2a formed in the semiconductor chip CPC. The pad PC3 of the semiconductor chip CPC is a pad electrically connected to the coil L1b formed in the semiconductor chip CPC. The pad PC4 of the semiconductor chip CPC is a pad electrically connected to the coil L2b formed in the semiconductor chip CPC.

[0052] A plurality of pads PH1 of the semiconductor chip CPH and a plurality of pads PC3 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PH1 of the semiconductor chip CPH, and the other end of the wire BW is connected to the pad PC3 of the semiconductor chip CPC. Also, a plurality of pads PH2 of the semiconductor chip CPH and a plurality of pads PC4 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PH2 of the semiconductor chip CPH, and the other end of the wire BW is connected to the pad PC4 of the semiconductor chip CPC.

[0053] A plurality of pads PL1 of the semiconductor chip CPL and a plurality of pads PC1 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PL1 of the semiconductor chip CPL, and the other end of the wire BW is connected to the pad PC1 of the semiconductor chip CPC. Also, a plurality of pads PL2 of the semiconductor chip CPL and a plurality of pads PC2 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PL2 of the semiconductor chip CPL, and the other end of the wire BW is connected to the pad PC2 of the semiconductor chip CPC.

[0054] Furthermore, the pads PH3 of the semiconductor chip CPH and the leads LD1 are electrically connected to each other via wires BW, i.e., one end of the wire BW is connected to each of the pads PH3 of the semiconductor chip CPH, and the other end of the wire BW is connected to the inner lead portion of the lead LD1.

[0055] Furthermore, the pads PL3 of the semiconductor chip CPL and the leads LD2 are electrically connected to each other via wires BW, i.e., one end of the wire BW is connected to each of the pads PL3 of the semiconductor chip CPL, and the other end of the wire BW is connected to the inner lead portion of the lead LD2.

[0056] Furthermore, the pads PH4 of the semiconductor chip CPH and the die pad DPH are electrically connected via wires BW. That is, one end of the wires BW is connected to each of the pads PH4 of the semiconductor chip CPH, and the other end of the wires BW is connected to the die pad DPH.

[0057] Furthermore, the pads PL4 of the semiconductor chip CPL and the die pad DPL are electrically connected via wires BW. That is, one end of the wires BW is connected to each of the pads PHL of the semiconductor chip CPL, and the other end of the wires BW is connected to leads LD2a and LD2b formed integrally with the die pad DPH.

[0058] The wire (bonding wire) BW is a conductive wire. Specifically, the wire BW is made of metal, and gold (Au) wire, copper (Cu) wire, or aluminum (Al) wire can be suitably used. The wire BW is sealed within the sealing portion MR and is not exposed from the sealing portion MR. In each lead LD, the connection point of the wire BW is an inner lead portion located within the sealing portion MR.

[0059] When the semiconductor device PKG is in use, the semiconductor chip CPL in the semiconductor device PKG is electrically connected to a circuit external to the semiconductor device PKG (specifically, the control circuit CC) via a wire BW (specifically, the wire BW electrically connecting the pad PL3 and the lead LD2), the lead LD2, etc. Also, when the semiconductor device PKG is in use, the semiconductor chip CPH in the semiconductor device PKG is electrically connected to a circuit external to the semiconductor device PKG (specifically, an inverter circuit constituted by power transistors TS1 and TS2) via a wire BW (specifically, the wire BW electrically connecting the pad PH3 and the lead LD1), the lead LD1, etc. The drive circuit DR formed in the semiconductor chip CPH is electrically connected to the transmitter circuit TX2 and receiver circuit RX1 formed in the semiconductor chip CPH via internal wiring of the semiconductor chip CPH, etc. Moreover, when the semiconductor device PKG is used, the drive circuit DR formed in the semiconductor chip CPH is electrically connected to a circuit (specifically, an inverter circuit constituted by power transistors TS1 and TS2) outside the semiconductor device PKG via a wire BW (specifically, a wire BW electrically connecting the pad PH3 and the lead LD1) and the lead LD1, etc. A power supply potential V1 supplied to the inverter circuit constituted by the power transistors TS1 and TS2 is higher than a power supply potential V2 supplied to the control circuit CC.

[0060] <About the manufacturing process of semiconductor devices> Next, a manufacturing process (assembly process) of the semiconductor device PKG of this embodiment will be described. Figures 8 to 12 are plan views or cross-sectional views of the semiconductor device PKG of this embodiment during the manufacturing process. Of these, Figures 8 to 11 are plan views, and Figure 12 is a cross-sectional view corresponding to Figure 7 above.

[0061] To manufacture the semiconductor device PKG, first, the lead frame LF is prepared (prepared), and then the semiconductor chips CPC, CPH, and CPL are prepared (prepared). Either the lead frame LF or the semiconductor chips CPC, CPH, and CPL may be prepared first, or they may be prepared simultaneously.

[0062] As shown in Fig. 8, the lead frame LF integrally includes a frame frame, die pads DPH and DPL, a plurality of leads LD, and support portions SG1 and SG2. The lead frame LF is made of, for example, a metal material containing copper (Cu) as a main component, and more specifically, copper (Cu) or a copper (Cu) alloy. Fig. 8 shows an area of ​​the lead frame LF from which one semiconductor device PKG is manufactured.

[0063] The frame of the lead frame LF is composed of frame portions LF1, LF2, LF3, and LF4 that surround the region where the semiconductor device PKG is to be formed in plan view. Frame portions LF1 and LF3 are located opposite each other, and frame portions LF2 and LF4 are located opposite each other, with frame portion LF1 intersecting with frame portions LF2 and LF4, and frame portion LF3 intersecting with frame portions LF2 and LF4. In plan view, frame portions LF1, LF2, LF3, and LF4 surround the die pads DPH and DPL. Frame portions LF1 and LF3 are approximately parallel to the X direction, and frame portions LF2 and LF4 are approximately parallel to the Y direction.

[0064] Of the leads LD constituting the lead frame LF, lead LD1 has one end connected to frame portion LF1, and lead LD2 has one end connected to frame portion LF3. Furthermore, support portion SG1 is connected to frame portion LF2, and support portion SG2 is connected to frame portion LF4. Die pad DPH is connected to frame portion LF1 via leads LD1a, LD1b, and LD1c, and die pad DPL is connected to frame portion LF3 via leads LD2a and LD2b.

[0065] Next, as shown in Fig. 9, the semiconductor chip CPH is mounted on the upper surface DPHa of the die pad DPH of the lead frame LF via the bonding material BDH (see Fig. 7), the semiconductor chip CPC is mounted on the upper surface DPHa of the die pad DPH via the bonding material BDC (see Fig. 7), and the semiconductor chip CPL is mounted on the upper surface DPLa of the die pad DPL via the bonding material BDL (see Fig. 7). At this time, the semiconductor chips CPC, CPH, and CPL are mounted with their back surfaces facing the die pad. Thereafter, the bonding materials BDC, BDH, and BDL are hardened by heat treatment or the like.

[0066] 10, a wire bonding process is performed. In the wire bonding process, the pad PH1 of the semiconductor chip CPH and the pad PC3 of the semiconductor chip CPC, the pad PH2 of the semiconductor chip CPH and the pad PC4 of the semiconductor chip CPC, the pad PL1 of the semiconductor chip CPL and the pad PC1 of the semiconductor chip CPC, and the pad PL2 of the semiconductor chip CPL and the pad PC2 of the semiconductor chip CPC are electrically connected via wires BW, respectively. In addition, the pad PH3 of the semiconductor chip CPH and the lead LD1, the pad PL3 of the semiconductor chip CPL and the lead LD2, the pad PH4 of the semiconductor chip CPH and the die pad DPH, and the pad PL4 of the semiconductor chip CPL and the leads LD2a and LD2b are electrically connected via wires BW, respectively.

[0067] Next, a resin sealing process (resin molding process) is performed to form a sealing portion MR that seals the die pads DPH, DPL, the semiconductor chips CPC, CPH, CPL, the wires BW, and the inner lead portions of the leads LD, as shown in FIGS. 11 and 12. Of the side surfaces MRc1, MRc2, MRc3, and MRc4 of the formed sealing portion MR, the side surface MRc1 faces the frame portion LF1, the side surface MRc2 faces the frame portion LF2, the side surface MRc3 faces the frame portion LF3, and the side surface MRc4 faces the frame portion LF4. When the sealing portion MR is formed, portions of the support portions SG1 and SG2 are also sealed within the sealing portion MR. Specifically, the support portion SG1 integrally includes a portion that is sealed within the sealing portion MR on the side surface MRc2 of the sealing portion MR and a portion that protrudes from the side surface MRc2 of the sealing portion MR to the outside of the sealing portion MR and is connected to the frame portion LF2. The support portion SG2 integrally has a portion sealed within the sealing portion MR on the side surface MRc4 side of the sealing portion MR, and a portion protruding from the side surface MRc4 of the sealing portion MR to the outside of the sealing portion MR and connected to the frame portion LF4.

[0068] The sealing portion MR is supported by the frame portion LF1 by a plurality of leads LD (LD1, LD1a, LD1b, LD1c) on the side of the side MRc1, by the frame portion LF3 by a plurality of leads LD (LD2, LD2a, LD2b) on the side of the side MRc3, by the frame portion LF2 by the support portion SG1 on the side of the side MRc2, and by the frame portion LF4 by the support portion SG2 on the side of the side MRc4. That is, the sealing portion MR is stably supported by the frame portions LF1, LF2, LF3, LF4 by the plurality of leads LD and the support portions SG1, SG2.

[0069] Next, a plating layer (not shown) is formed as needed on the outer lead portion of the lead LD exposed from the sealing portion MR. Thereafter, outside the sealing portion MR, the lead LD is cut at a predetermined position to separate it from the frame (frame portions LF1 and LF3) of the lead frame LF. At this time, the cutting process of the multiple leads LD (LD1, LD1a, LD1b, and LD1c) on the side surface MRc1 of the sealing portion MR and the cutting process of the multiple leads LD (LD2, LD2a, and LD2b) on the side surface MRc3 of the sealing portion MR are performed in any order, and then the supporting portions SG1 and SG2 of the portions protruding from the sealing portion MR are cut. This allows the cutting process of the leads LD to be performed in a state where the sealing portion MR is supported by the supporting portions SG1 and SG2 to the frame portions LF2 and LF4, thereby enabling the leads LD to be cut accurately.

[0070] Next, the outer lead portion of the lead LD protruding from the sealing portion MR is bent (lead processing, lead forming).

[0071] In this manner, the semiconductor device PKG shown in FIGS. 2 to 7 is manufactured.

[0072] <About semiconductor chips> Figures 13 and 14 are cross-sectional views schematically showing the semiconductor chips CPC, CPH, and CPL in the semiconductor device PKG. Figures 13 and 14 are cross sections approximately parallel to the Y direction, but Figure 13 corresponds to a cross section passing through pads PL1, PC1, PC3, and PH1 in Figure 4, and Figure 14 corresponds to a cross section passing through pads PL2, PC2, PC4, and PH2 in Figure 4. Figures 13 and 14 show the die pads DPH and DPL, the semiconductor chips CPC, CPH, and CPL, and the wires BW, but do not show the sealing portion MR.

[0073] 13 and 14, the semiconductor chip CPC has a semiconductor substrate SB1, a multilayer wiring structure MW1 formed thereon, and a protective film PA1 formed thereon. The multilayer wiring structure MW1 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA1 is a protective film located in the uppermost layer of the semiconductor chip CPC.

[0074] The semiconductor chip CPC also includes coils L1a, L1b, L2a, and L2b, which are formed by wiring layers that make up the multilayer wiring structure MW1. The coils L1a and L1b are shown in Fig. 13, and the coils L2a and L2b are shown in Fig. 14. Of the magnetically coupled coils L1a and L1b, the coil L1a is electrically connected to the pad PL1 of the semiconductor chip CPL via the pad PC1 of the semiconductor chip CPC and the wire BW, and the coil L1b is electrically connected to the pad PH1 of the semiconductor chip CPH via the pad PC3 of the semiconductor chip CPC and the wire BW (see Fig. 13). Furthermore, of the coils L2a and L2b that constitute the transformer TR2, the coil L2a is electrically connected to the pad PL2 of the semiconductor chip CPL via the pad PC2 of the semiconductor chip CPC and the wire BW, and the coil L2b is electrically connected to the pad PH2 of the semiconductor chip CPH via the pad PC4 of the semiconductor chip CPC and the wire BW (see Figure 14).

[0075] In the semiconductor chip CPC, of ​​the coils L1a and L1b, the coil L1b is located closer to the die pad DPH (see FIG. 13). In other words, in a cross-sectional view, the coil L1b is located closer to the die pad DPH than the coil L1a. Also, in the semiconductor chip CPC, of ​​the coils L2a and L2b, the coil L2b is located closer to the die pad DPH (see FIG. 14). In other words, in a cross-sectional view, the coil L2b is located closer to the die pad DPH than the coil L2a.

[0076] That is, in the semiconductor chip CPC, the coil L1a and the coil L1b are formed in positions that overlap in a plan view, and the coil L1b is formed below the coil L1a. Also, in the semiconductor chip CPC, the coil L2a and the coil L2b are formed in positions that overlap in a plan view, and the coil L2b is formed below the coil L2a.

[0077] In the following description, of the primary and secondary coils formed in the semiconductor chip CPC, the lower coil (closer to the semiconductor substrate SB1) will be referred to as the lower coil, and the upper coil (farther from the semiconductor substrate SB1) will be referred to as the upper coil. That is, in the semiconductor chip CPC, coil L1b is formed in a lower layer than coil L1a, and coil L2b is formed in a lower layer than coil L2a. In addition, in the semiconductor chip CPC, coils L1a and L2a are preferably formed in the same layer, and coils L1b and L2b are preferably formed in the same layer. Each of coils L1a, L1b, L2a, and L2b is formed by a spiral conductor pattern (wiring pattern).

[0078] The coils L1a and L2a are preferably formed in the uppermost wiring layer among the multiple wiring layers constituting the multilayer wiring structure MW1. In this case, the coils L1a and L2a are formed on the uppermost interlayer insulating film among the multiple interlayer insulating films constituting the multilayer wiring structure MW1. The coils L1a and L2a are covered with a protective film PA1, and pads PC1 are connected to both ends of the coil L1a, and pads PC2 are connected to both ends of the coil L2a.

[0079] The coils L1b and L2b are formed in a wiring layer below the wiring layer in which the coils L1a and L2a are formed, among the multiple wiring layers constituting the multilayer wiring structure MW1. Both ends of the coil L1b are connected to the pad PC3 via wiring (e.g., the wiring WR1 in FIG. 13) included in the multilayer wiring structure MW1, and both ends of the coil L2b are connected to the pad PC4 via wiring (e.g., the wiring WR2 in FIG. 14) included in the multilayer wiring structure MW1.

[0080] The pads PC1, PC2, PC3, and PC4 of the semiconductor chip CPC are formed in the uppermost wiring layer among the multiple wiring layers constituting the multilayer wiring structure MW1, and are each exposed from an opening in the protective film PA1. Wires BW are connected to the pads PC1, PC2, PC3, and PC4 exposed from the opening in the protective film PA1, respectively.

[0081] In another embodiment, coils L1a and L2a can be formed in a wiring layer other than the topmost wiring layer among the multiple wiring layers that make up the multilayer wiring structure MW1, but in that case, coils L1b and L2b must still be formed in a layer lower than coils L1a and L2a.

[0082] No semiconductor element (i.e., transistor such as the above-mentioned MOSFET) is formed in the semiconductor chip CPC. In other words, no semiconductor element (i.e., transistor such as the above-mentioned MOSFET) is formed on the semiconductor substrate SB1 constituting the semiconductor chip CPC.

[0083] The semiconductor chip CPH has a semiconductor substrate SB2, a multilayer wiring structure MW2 formed thereon, and a protective film PA2 formed thereon. The multilayer wiring structure MW2 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA2 is a protective film located in the uppermost layer of the semiconductor chip CPH.

[0084] A plurality of semiconductor elements (not shown), such as transistors, are formed on a semiconductor substrate SB2 constituting the semiconductor chip CPH. Pads PH1, PH2, PH3, and PH4 of the semiconductor chip CPH are formed on the uppermost wiring layer among a plurality of wiring layers constituting the multilayer wiring structure MW2, and are each exposed from an opening in the protective film PA2. Wires BW are connected to the pads PH1, PH2, PH3, and PH4 exposed from the opening in the protective film PA2, respectively.

[0085] The semiconductor chip CPL has a semiconductor substrate SB3, a multilayer wiring structure MW3 formed thereon, and a protective film PA3 formed thereon. The multilayer wiring structure MW3 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA3 is a protective film located in the uppermost layer of the semiconductor chip CPL.

[0086] A plurality of semiconductor elements (not shown), such as transistors, are formed on a semiconductor substrate SB3 constituting the semiconductor chip CPL. Pads PL1, PL2, PL3, and PL4 of the semiconductor chip CPL are formed on the uppermost wiring layer among a plurality of wiring layers constituting the multilayer wiring structure MW3, and are each exposed from an opening in the protective film PA3. Wires BW are connected to the pads PL1, PL2, PL3, and PL4 exposed from the opening in the protective film PA3, respectively.

[0087] In addition, when it is not necessary to transmit a signal from the semiconductor chip CPH to the semiconductor chip CPL in the semiconductor device PKG, the semiconductor chip CPH does not include the transmitting circuit TX2, the semiconductor chip CPL does not have the receiving circuit RX2, and the semiconductor chip CPC does not include the transformer TR2 (coils L2a and L2b). In this case, the semiconductor chip CPH does not have the pad PH2, the semiconductor chip CPL does not have the pad PL2, and the semiconductor chip CPC does not have the pads PC2 and PC4. At least one transformer is formed in the semiconductor chip CPC, but the number of transformers can be changed.

[0088] <About the study example> Fig. 15 is a plan perspective view of the semiconductor device PKG101 of the first study example studied by the present inventors, and corresponds to Fig. 3. Fig. 16 is a cross-sectional view of the semiconductor device PKG101 of the first study example, and corresponds to Fig. 7. The cross-sectional view of the semiconductor device PKG101 taken along line B1-B1 in Fig. 15 roughly corresponds to Fig. 16.

[0089] 15 and 16 has die pads DPH101 and DPL101 instead of the die pads DPH and DPL. A semiconductor chip CPH is mounted on the die pad DPH101 via a bonding material BDH, and a semiconductor chip CPL is mounted on the die pad DPL101 via a bonding material BDL. A semiconductor chip CPC101 corresponding to the semiconductor chip CPC is mounted not on the die pad DPH101 but on the die pad DPL101 via a bonding material BDC. Because the planar dimensions (planar area) of the die pad DPL101 are larger than the planar dimensions (planar area) of the die pad DPH101, it is possible to mount two semiconductor chips CPC101 and CPL on the die pad DPL101.

[0090] If the three semiconductor chips CPC101, CPH, and CPL were mounted on separate die pads, the planar dimensions (area) of the semiconductor device would increase. However, in the case of the semiconductor device PKG101 of the first study example, by mounting two semiconductor chips CPC101 and CPL on the die pad DPL101, the planar dimensions (area) of the semiconductor device can be reduced.

[0091] However, according to the study by the present inventors, it has been found that the following problem may occur in the semiconductor device PKG101 of the first studied example.

[0092] Of the semiconductor chips CPH and CPL included in the semiconductor device PKG101 of the first studied example, the semiconductor chip CPH generates a large amount of heat (power consumption) during operation because the semiconductor chip CPH has a drive circuit DR that operates at a power supply voltage higher than that of the transmission circuit TX1 and the reception circuit RX2.

[0093] In the case of the semiconductor device PKG101 of the first studied example, heat generated in the semiconductor chip CPH is conducted to the die pad DPH101 via the bonding material BDH, and heat generated in the semiconductor chips CPC101, CPL is conducted to the die pad DPL101 via the bonding materials BDC, BDL. The die pads DPH101, DPL101 are sealed in a sealing portion MR101 corresponding to the sealing portion MR, and are not exposed from the sealing portion MR101. This is because, if the die pads DPH101, DPL101 were exposed on the underside of the sealing portion MR101, there would be a concern about creeping discharge (discharge occurring along the surface of the sealing portion MR101) between the exposed portion of the die pad DPH101 and the exposed portion of the die pad DPL101.

[0094] For this reason, for the semiconductor chip CPH, which generates more heat than the semiconductor chip CPL, it is desirable to increase the volume of the die pad DPH101 on which the semiconductor chip CPH is mounted in order to suppress the temperature rise associated with the heat generation. However, increasing the thickness of the die pad DPH101 to increase the volume of the die pad DPH101 is undesirable because it leads to an increase in the thickness of the sealing portion MR101, thereby increasing the thickness of the semiconductor device PKG101. Furthermore, increasing the planar dimensions (planar area) of the die pad DPH101 to increase the volume of the die pad DPH101 is undesirable because it leads to an increase in the planar dimensions (planar area) of the sealing portion MR101, thereby increasing the planar dimensions (planar area) of the semiconductor device PKG101. However, if the die pad DPH101 on which the semiconductor chip CPH, which generates more heat than the semiconductor chip CPL, is mounted is small, the temperature rise of the semiconductor chip CPH associated with heat generation during operation of the semiconductor chip CPH will be large, which may reduce the reliability of the semiconductor device PKG101. It is desirable to suppress the temperature rise of the semiconductor chip CPH due to heat generation, thereby improving the reliability of the semiconductor device, and at the same time, to achieve miniaturization of the semiconductor device.

[0095] <Main features and effects> The semiconductor device PKG of this embodiment is a semiconductor device incorporating three semiconductor chips CPC, CPH, and CPL. The semiconductor chip CPC includes magnetically coupled coils L1a and L1b, and the coil L1a in the semiconductor chip CPC is electrically connected to a circuit (here, a transmitting circuit TX1) formed in the semiconductor chip CPL, and the coil L1b in the semiconductor chip CPC is electrically connected to a circuit (here, a receiving circuit RX1) formed in the semiconductor chip CPH. As a result, in the semiconductor device PKG, signals can be transmitted between the semiconductor chips CPL and CPH via the magnetically coupled coils L1a and L1b.

[0096] One of the main features of this embodiment is that the semiconductor device PKG has two die pads DPH, DPL and three semiconductor chips CPC, CPH, CPL, and the two semiconductor chips CPC, CPH are mounted on the die pad DPH, and one semiconductor chip CPL is mounted on the die pad DPL.

[0097] Unlike this embodiment, if three semiconductor chips CPC, CPH, and CPL are mounted on three die pads, respectively, the planar dimensions (planar area) of the semiconductor device will increase. In contrast, in the case of the semiconductor device PKG of this embodiment, by mounting two semiconductor chips CPC and CPH on the die pad DPH, the planar dimensions (planar area) of the semiconductor device can be reduced.

[0098] Also, unlike the present embodiment, assume that the transformers TR1 and TR2 are formed in one of the semiconductor chips CPH and CPL, for example, in the semiconductor chip CPH, without using the semiconductor chip CPC. In this case, semiconductor elements such as transistors are not formed in the planar region of the semiconductor chip CPH where the coils constituting the transformers TR1 and TR2 are formed, so the planar dimensions of the semiconductor chip CPH become quite large, increasing the manufacturing cost of the semiconductor chip CPH and, as a result, increasing the manufacturing cost of the semiconductor device. In contrast, in the present embodiment, the coils constituting the transformers TR1 and TR2 are formed in the semiconductor chip CPC, which is separate from the semiconductor chips CPH and CPL, so that the planar dimensions of each of the semiconductor chips CPC, CPH, and CPL can be reduced, and the manufacturing cost of the semiconductor device PKG can be reduced.

[0099] Moreover, the semiconductor device PKG of this embodiment can suppress the temperature rise of the semiconductor chip CPH due to heat generation and also achieve miniaturization of the semiconductor device PKG. This will be described below.

[0100] The planar dimensions (planar area) of the die pad DPL of the semiconductor device PKG of this embodiment can be made smaller than the planar dimensions (planar area) of the die pad DPL101 of the semiconductor device PKG101 of the first studied example. This is because the die pad DPL101 of the semiconductor device PKG101 of the first studied example mounts two semiconductor chips CPC, CPL and therefore needs to have planar dimensions large enough to accommodate the two semiconductor chips CPC, CPL. In contrast, the die pad DPL of the semiconductor device PKG of this embodiment only needs to have planar dimensions large enough to accommodate one semiconductor chip CPL, and the planar dimensions of the die pad DPL can be made smaller than the planar dimensions of the die pad DPL101.

[0101] Furthermore, the planar dimensions (planar area) of the die pad DPH of the semiconductor device PKG of this embodiment can be made larger than the planar dimensions (planar area) of the die pad DPH101 of the semiconductor device PKG101 of the first studied example. This is because the die pad DPH101 of the semiconductor device PKG101 of the first studied example only needs to have planar dimensions sufficient to accommodate one semiconductor chip CPH, whereas the die pad DPH of the semiconductor device PKG of this embodiment needs to have an area sufficient to accommodate two semiconductor chips CPC, CPH.

[0102] Here, it is assumed that the planar dimensions of the die pad DPH101 in the first studied example and the planar dimensions of the die pad DPH in this embodiment are the same. In this case, the planar dimensions of the die pad DPL in this embodiment can be made smaller than the planar dimensions of the die pad DPL101 in the first studied example, and accordingly, the planar dimensions (planar area) of the semiconductor device PKG in this embodiment can be made smaller than the planar dimensions (planar area) of the semiconductor device PKG101 in the first studied example.

[0103] That is, in the case of this embodiment, by mounting the semiconductor chip CPC on the die pad DPH on which the semiconductor chip CPH is mounted, rather than on the die pad DPL on which the semiconductor chip CPL is mounted, it is possible to increase the planar dimensions of the die pad DPH on which the semiconductor chip CPH is mounted while suppressing the planar dimensions of the semiconductor device PKG.

[0104] The power consumption of the semiconductor chip CPH during operation is greater than the power consumption of the semiconductor chip CPL during operation. Therefore, the amount of heat generated by the semiconductor chip CPH during operation is greater than the amount of heat generated by the semiconductor chip CPL during operation. Heat generated in each of the semiconductor chips CPH and CPC is conducted to the die pad DPH via the bonding materials BDH and BDC, and heat generated in the semiconductor chip CPL is conducted to the die pad DPL via the bonding material BDL. In this embodiment, as described above, the planar dimensions of the die pad DPH can be made larger than the planar dimensions of the die pad DPL. Therefore, heat generated in the semiconductor chip CPH during operation can be dissipated more easily through the die pad DPH than in the semiconductor device PKG101 of the first study example. This improves the reliability of the semiconductor device PKG. Meanwhile, the amount of heat generated by the semiconductor chip CPL during operation is smaller than that of the semiconductor chip CPH. Therefore, even if the planar dimensions (area) of the die pad DPL on which the semiconductor chip CPL is mounted are reduced, the impact on the reliability of the semiconductor device PKG is minimal.

[0105] That is, in this embodiment, in order to increase the planar dimensions of the die pad DPH on which the semiconductor chip CPH, which generates a large amount of heat during operation, is mounted while preventing an increase in the planar dimensions of the semiconductor device PKG, the semiconductor chip CPC is mounted on the die pad DPH on which the semiconductor chip CPH is mounted, rather than on the die pad DPL on which the semiconductor chip CPL is mounted. This makes it possible to increase the planar dimensions of the die pad DPH on which the semiconductor chip CPH, which generates a large amount of heat during operation, while keeping the total area of ​​the die pad DPH and the die pad DPL approximately the same as the total area of ​​the die pad DPH101 and the die pad DPL101 in the first studied example. As a result, it is possible to suppress the temperature rise of the semiconductor chip CPH due to heat generation and to reduce the size of the semiconductor device PKG.

[0106] Another main feature of this embodiment is that, within the semiconductor chip CPC, of ​​the coils L1a and L1b, the coil L1b is located closer to the die pad DPH, and of the coils L2a and L2b, the coil L2b is located closer to the die pad DPH. In other words, in a cross-sectional view, the coil L1b is located closer to the die pad DPH than the coil L1a, and the coil L2b is located closer to the die pad DPH than the coil L2a. This can further improve the reliability of the semiconductor device. This will be explained below.

[0107] In the transformers TR1 and TR2, a large potential difference may occur between the primary and secondary coils. Conversely, because of this potential difference, the primary and secondary coils are magnetically coupled, not connected by a conductor, for signal transmission. For this reason, when forming the transformers TR1 and TR2 within the semiconductor chip CPC, it is important to maximize the dielectric strength between the primary and secondary coils in order to improve the reliability of the semiconductor package PKG incorporating the semiconductor chips CPC, CPH, and CPL, or of electronic devices using such a device. Increasing the total thickness of the interlayer insulating film between the primary and secondary coils within the semiconductor chip CPC is an effective way to increase the dielectric strength between the primary and secondary coils.

[0108] However, if a large potential difference occurs between the primary coil and secondary coil formed within the semiconductor chip CPC, there is a concern that a large potential difference will also occur between the semiconductor substrate SB1 that constitutes the semiconductor chip CPC and the coil.

[0109] Fig. 17 is a cross-sectional view schematically showing semiconductor chips CPC201, CPH, and CPL in a semiconductor device PKG201 of a second study example studied by the present inventor, and corresponds to Fig. 13 above. The semiconductor chip CPC201 shown in Fig. 17 corresponds to the semiconductor chip CPC. As in the present embodiment, in the case of Fig. 17 (second study example), the semiconductor chip CPC201 corresponding to the semiconductor chip CPC is mounted on the die pad DPH, not on the die pad DPL.

[0110] However, the up-down relationship of the magnetically coupled coils is reversed between the semiconductor chip CPC201 shown in FIG. 17 and the semiconductor chip CPC of this embodiment. That is, in the case of the semiconductor chip CPC201 shown in FIG. 17, of the magnetically coupled coils L1a and L1b, coil L1a is located closer to the die pad DPH than coil L1b, and of the magnetically coupled coils L2a and L2b, coil L2a is located closer to the die pad DPH than coil L2b. That is, in the case of the semiconductor chip CPC201 shown in FIG. 17, coil L1a is formed below coil L1b, and coil L2a is formed below coil L2b. Note that coils L2a and L2b are not shown in FIG.

[0111] In the semiconductor chip CPC, CPC201, the dielectric strength voltage between the primary coil and the secondary coil can be ensured by thickening the interlayer insulating film between the primary coil and the secondary coil. On the other hand, if the interlayer insulating film between the lower one of the primary coil and the secondary coil and the semiconductor substrate SB1 in the semiconductor chip CPC, CPC201 is also thickened, the thickness of the entire multilayer wiring structure MW1 increases, leading to an increase in the thickness of the semiconductor chip CPC, CPC201. This is undesirable because it leads to an increase in the thickness of the sealing portion MR, MR101, and therefore to an increase in the thickness of the semiconductor device.

[0112] Furthermore, in order to accurately connect the pads PC3 and PC4 of the semiconductor chip CPC to the pads PH1 and PH2 of the semiconductor chip CPH and the pads PC1 and PC2 of the semiconductor chip CPC to the pads PL1 and PL2 of the semiconductor chip CPL via wires BW during the wire bonding process, it is desirable that the thicknesses of the semiconductor chips CPC, CPH, and CPL are approximately the same. Therefore, if the thickness of the semiconductor chip CPC is increased, it is desirable to increase the thickness of the semiconductor chip CPH accordingly. However, increasing the thickness of the semiconductor chip CPH makes it difficult to connect the pad PH3 of the semiconductor chip CPH to the lead LD with the wire BW. This is because increasing the thickness of the semiconductor chip CPH increases the risk that the wire BW connecting the pad PH3 of the semiconductor chip CPH to the lead LD will come into contact with the end of the top surface of the semiconductor chip CPH. From this perspective, it is also preferable not to increase the thickness of the semiconductor chips CPH and CPC too much.

[0113] On the other hand, thinning the semiconductor substrate SB1 that constitutes the semiconductor chip CPC in order to reduce the thickness of the semiconductor chip CPC leads to a reduction in the thickness of the semiconductor wafer used to manufacture the semiconductor chip CPC. Thinning the thickness of the semiconductor wafer increases the risk of chipping or cracking of the semiconductor wafer during transportation, and also makes transportation of the semiconductor wafer itself more difficult. Considering this point, it is not advisable to thin the thickness of the semiconductor substrate SB1 that constitutes the semiconductor chip CPC too much.

[0114] Therefore, in order to sufficiently ensure the dielectric strength voltage between the primary coil and secondary coil formed within the semiconductor chip CPC while suppressing the thickness of the semiconductor chip CPC to a certain extent (i.e., to ensure the thickness of the interlayer insulating film between the primary coil and secondary coil), it is effective to suppress the thickness of the interlayer insulating film between the lower coil and the semiconductor substrate SB1 of the primary coil and secondary coil formed within the semiconductor chip CPC.

[0115] In the following description, of the primary and secondary coils formed in the semiconductor chip CPC, the lower coil (closer to the semiconductor substrate SB1) will be referred to as the lower coil, and the upper coil (farther from the semiconductor substrate SB1) will be referred to as the upper coil. In the case of the semiconductor chip CPC of this embodiment, of the magnetically coupled coils L1a and L1b, coil L1b is the lower coil and coil L1a is the upper coil. Also, of the magnetically coupled coils L2a and L2b, coil L2b is the lower coil and coil L2a is the upper coil. On the other hand, in the case of the semiconductor chip CPC201 of the second study example shown in FIG. 17, of the coils L1a and L1b, coil L1a is the lower coil and coil L1b is the upper coil. Also, of the coils L2a and L2b, coil L2a is the lower coil and coil L2b is the upper coil.

[0116] In order to suppress the thickness of the interlayer insulating film between the lower coil of the semiconductor chip CPC and the semiconductor substrate SB1, it is desirable to prevent a large potential difference from occurring between the lower coil of the semiconductor chip CPC and the semiconductor substrate SB1. If a large potential difference does not occur between the lower coil of the semiconductor chip CPC and the semiconductor substrate SB1, even if the thickness of the interlayer insulating film between the lower coil of the semiconductor chip CPC and the semiconductor substrate SB1 is reduced to some extent, the reliability of the semiconductor chip CPC and the semiconductor device PKG including it will not be reduced.

[0117] Comparing the semiconductor chip CPC201 of the second study example (FIG. 17) with the semiconductor chip CPC of the present embodiment (FIGS. 13 and 14), the semiconductor chip CPC201 of the second study example (FIG. 17) has a higher risk of a large potential difference occurring between the lower coil and the semiconductor substrate SB1. This is because there is a concern that a high potential (high voltage) may be supplied to the coil L1b electrically connected to the semiconductor chip CPH via the wire BW and to the semiconductor substrate SB1 constituting the semiconductor chip CPC mounted on the die pad DPH via the bonding material BDC. The power supply potential (high voltage) V1 supplied from the power supply BT1 to a circuit external to the semiconductor device PKG (e.g., the inverter circuit shown in FIG. 1) can be supplied to the coil L1b via, for example, a route via the lead LD (specifically, the lead LD1), the wire BW electrically connecting the lead LD and the semiconductor chip CPH to each other, the semiconductor chip CPH, and the wire BW electrically connecting the semiconductor chip CPH and the semiconductor chip CPC to each other. Another route passes through the leads LD (specifically, leads LD1a, LD1b, and LD1c), the die pad DPH connected to the leads LD, the wires BW that electrically connect the die pad DPH and the semiconductor chip CPH to each other, the semiconductor chip CPH, and the wires BW that electrically connect the semiconductor chip CPH and the semiconductor chip CPC to each other. Meanwhile, the power supply potential (high voltage) V1 supplied from the power supply BT1 to the semiconductor substrate SB1 that constitutes the semiconductor chip CPC may pass through, for example, the leads LD (specifically, leads LD1a, LD1b, and LD1c), the die pad DPH connected to the leads LD, and the bonding material BDC interposed between the semiconductor chip CPC and the die pad DPH. The above-mentioned concern not only generates a large potential difference between the coil L1b (upper coil) and the coil L1a (lower coil) in the semiconductor chip CP201, but also generates a large potential difference between the coil L1a (lower coil) and the semiconductor substrate SB1.For this reason, in the semiconductor chip CP201 ​​where there is a concern that a large potential difference may occur between the lower coil and the semiconductor substrate SB1, it is necessary to thicken the interlayer insulating film between the lower coil and the semiconductor substrate SB1.

[0118] In contrast, in the semiconductor chip CPC of this embodiment, the coils L1b and L2b, which are electrically connected to the circuits in the semiconductor chip CPH via wires BW and the like, are formed as lower coils rather than upper coils within the semiconductor chip CPC. Even in this embodiment, mounting the semiconductor chip CPC and the semiconductor chip CPH on the die pad DPH raises concerns that a high potential may be supplied to the coil L1b (lower coil) of the semiconductor chip CPC and the semiconductor substrate SB1 constituting the semiconductor chip CPC. This generates a large potential difference between the coil L1b (lower coil) and the coil L1a (upper coil) in the semiconductor chip CPC, but no large potential difference occurs between the coil L1a (lower coil) and the semiconductor substrate SB1. Therefore, comparing the semiconductor chip CPC201 of FIG. 17 with the semiconductor chip CPC201 of FIG. 13, the semiconductor chip CPC201 of FIG. 17 has a higher risk of a large potential difference occurring between the lower coil and the semiconductor substrate SB1.

[0119] Therefore, in the semiconductor chip CPC of this embodiment, which has a low risk of a large potential difference occurring between the lower coil and the semiconductor substrate SB1, the thickness of the interlayer insulating film between the lower coil (here, coils L1b and L2b) and the semiconductor substrate SB1 can be reduced. Therefore, it is possible to sufficiently ensure the withstand voltage between the primary coil and the secondary coil formed in the semiconductor chip CPC while reducing the thickness of the semiconductor chip CPC.

[0120] As described above, in this embodiment, the transformer used to transmit signals between the semiconductor chip CPL and the semiconductor chip CPH is formed in the semiconductor chip CPC, and the semiconductor chip CPC is mounted on the die pad DPH on which the semiconductor chip CPH is mounted, rather than on the die pad DPL on which the semiconductor chip CPL is mounted. This suppresses the temperature rise of the semiconductor chip CPH due to heat generation and reduces the planar dimensions (planar area) of the semiconductor device PKG. Therefore, it is possible to achieve both improved reliability and miniaturization of the semiconductor device PKG. Furthermore, since the semiconductor chip CPC is mounted on the die pad DPH together with the semiconductor chip CPH, the coils L1b and L2b electrically connected to the circuits (here, the receiver circuit RX1 and the transmitter circuit TX2) in the semiconductor chip CPH are formed as lower coils in the semiconductor chip CPC. The coils L1a and L2a electrically connected to the circuits (here, the transmitter circuit TX1 and the receiver circuit RX2) in the semiconductor chip CPL are formed as upper coils in the semiconductor chip CPC. This makes it possible to suppress or prevent a large potential difference from occurring between the lower coil (here, coils L1b, L2b) of the semiconductor chip CPC and the semiconductor substrate SB1, thereby improving the reliability of the semiconductor chip CPC and the semiconductor device PKG including it. Furthermore, in the semiconductor chip CPC, the thickness of the interlayer insulating film between the lower coil (here, coils L1b, L2b) and the semiconductor substrate SB1 can be suppressed, thereby suppressing the thickness of the semiconductor chip CPC. As a result, the thickness of the semiconductor device PKG can be suppressed. Furthermore, since the thickness of the semiconductor substrate SB1 constituting the semiconductor chip CPC can be increased while suppressing the thickness of the semiconductor chip CPC, the semiconductor chip CPC can be manufactured more easily.

[0121] 15 and 16, the semiconductor chip CP101 is mounted on a die pad DPL101 on which the semiconductor chip CPL is mounted. Therefore, in the case of the semiconductor device PKG101 of the first studied example, it is preferable to use the semiconductor chip CP201 ​​of the second studied example (FIG. 17) as the semiconductor chip CP101, rather than the semiconductor chip CPC of the present embodiment (FIGS. 13 and 14). This is because, in the case of the semiconductor device PKG101 of the first studied example (FIGS. 15 and 16), the potential supplied from the die pad DPL101 to the semiconductor substrate constituting the semiconductor chip CPC101 is not the power supply potential (high voltage) V1 supplied from the power supply BT1 to a circuit external to the semiconductor device PKG (e.g., the inverter circuit shown in FIG. 1), but is the power supply potential (low voltage) V2 supplied from the power supply BT2 to a circuit external to the semiconductor device PKG (e.g., the control circuit CC shown in FIG. 1). This power supply potential (low voltage) V2 can be supplied to the semiconductor substrate constituting the semiconductor chip CPC101 via the lead LD (specifically, the lead LD connected to the die pad DPL101), the die pad DPL101 connected to this lead LD, and the bonding material BDC interposed between the semiconductor chip CPC and the die pad DPL101. For this reason, in the case of the semiconductor device PKG101 of the first studied example (FIGS. 15 and 16), in order to prevent a large potential difference from occurring between the lower coil and the semiconductor substrate in the semiconductor chip CP101, it is advantageous to configure the lower coil in the semiconductor chip CP101 as coils L1a and L2a electrically connected to the circuit in the semiconductor chip CPL, similar to the semiconductor chip CPC201 in FIG. 17. Therefore, the difference between the semiconductor device PKG101 of the first studied example (FIGS. 15 and 16) and the semiconductor device PKG of this embodiment is not only that the semiconductor chip CPC is mounted on a die pad DPH instead of a die pad DPL, but also that, in accordance with the change in the die pad, the magnetically coupled coils in the semiconductor chip CPC are reversed upside down. This was made possible by realizing that, when two semiconductor chips CPC and CPH are mounted on the die pad DPH, a high potential may be supplied to each of the coils L1b and L2b of the semiconductor chip CPC and to the semiconductor substrate SB1 constituting the semiconductor chip CPC.

[0122] When a high potential is supplied to the semiconductor chip CPH, the high potential is derived from the power supply potential V1 shown in FIG. 1. That is, since the lead LD1 of the semiconductor device PKG is electrically connected to a circuit (a circuit configured with power transistors TS1 and TS2) to which the power supply potential V1 is supplied, there is a possibility that the high potential derived from the power supply potential V1 may be supplied to the semiconductor chip CPH from the lead LD1 via the wire BW (the wire BW electrically connecting the lead LD1 to the pad PH3 of the semiconductor chip CPH). For this reason, transformers TR1 and TR2 are interposed in the transmission of signals between the semiconductor chip CPH and the semiconductor chip CPL. This makes it possible to prevent the high potential derived from the power supply potential V1 from being supplied to the semiconductor chip CPH, even if the high potential is supplied to the semiconductor chip CPH. When a high potential derived from the power supply potential V1 is supplied to the semiconductor chip CPH, the high potential can be supplied to the semiconductor chip CPH via the leads LD (specifically, leads LD1a, LD1b, and LD1c), the die pad DPH connected to the leads LD, and the wire BW electrically connecting the die pad DPH to the pad PH4 of the semiconductor chip CPH. When a high potential is supplied from the die pad DPH to the semiconductor substrate SB1 of the semiconductor chip CPC, the path includes the bonding material BDC interposed between the semiconductor chip CPC and the die pad DPH. Therefore, this embodiment is extremely effective when a conductive bonding material is used as the bonding material BDC. This embodiment is also extremely effective when the pad PH4 of the semiconductor chip CPH is electrically connected to the die pad DPH via the wire BW.

[0123] In this embodiment, bent portions are provided in the inner lead portions of the leads LD1a, LD1b, LD1c, LD2a, and LD2b so that the height position of (the upper surfaces DPHa, DPLa of) the die pads DPH and DPL is lower than the height position of (the upper surfaces of) the inner lead portions of the leads LD. In FIG. 5 and FIG. 19 described later, the bent portions of the inner lead portions of the leads LD1a, LD1b, LD1c, LD2a, and LD2b are indicated by hatching. The bent portions of the inner lead portions of the leads LD1a, LD1b, LD1c, LD2a, and LD2b are already provided before the die bonding process of the semiconductor chips CPC, CPH, and CPL is performed.

[0124] In a cross-sectional view, the height position of the die pad DPH is lower than the height position of the inner lead portion of the lead LD, thereby reducing the risk that the wire BW connecting the pad PH3 of the semiconductor chip CPH to the lead LD1 will contact the upper surface edge of the semiconductor chip CPH. Also, in a cross-sectional view, the height position of the die pad DPL is lower than the height position of the inner lead portion of the lead LD, thereby reducing the risk that the wire BW connecting the pad PL3 of the semiconductor chip CPL to the lead LD2 will contact the upper surface edge of the semiconductor chip CPL. Furthermore, by providing bent portions in the inner lead portions of the leads LD1a, LD1b, LD1c, LD2a, and LD2b to reduce the height of the die pads DPH and DPL, the thickness of the semiconductor chips CPC, CPH, and CPL can be increased accordingly. This allows the thickness of the semiconductor substrates SB1, SB2, and SB3 constituting the semiconductor chips CPC, CPH, and CPL to be increased, facilitating the manufacture of the semiconductor chips CPC, CPH, and CPL.

[0125] <Modification> 18 and 19 are planar perspective views showing a modified example of the semiconductor device PKG of this embodiment, and correspond to the above-mentioned FIGS. 3 and 5, respectively. Here, the modified semiconductor device PKG shown in FIGS. 18 and 19 will be denoted by the symbol PKG1 and referred to as the semiconductor device PKG1. Differences between the modified semiconductor device PKG1 and the above-mentioned semiconductor device PKG (FIGS. 2 to 7) will be described below.

[0126] The semiconductor device PKG1 of the modified example shown in FIGS. 18 and 19 does not have the support portions SG1 and SG2, but instead has support portions SG3, SG4, SG5, and SG6.

[0127] The support portion SG3 is connected to the side surface of the lead LD1b (the side surface of the portion extending in the Y direction), and extends in the X direction to reach the side surface MRc2 of the sealing portion MR. The support portion SG3 hardly protrudes from the side surface MRc2 of the sealing portion MR, and the tip surface of the support portion SG3 (the end surface opposite to the side connected to the lead LD1b) is exposed from the side surface MRc2 of the sealing portion MR.

[0128] The support portion SG4 is connected to the side surface of the lead LD2a (the side surface of the portion extending in the Y direction), and extends in the X direction to reach the side surface MRc2 of the sealing portion MR. The support portion SG4 hardly protrudes from the side surface MRc2 of the sealing portion MR, and the tip surface of the support portion SG4 (the end surface opposite to the side connected to the lead LD2a) is exposed from the side surface MRc2 of the sealing portion MR.

[0129] The support portion SG5 is connected to the side surface of the lead LD2b (the side surface of the portion extending in the Y direction), and extends in the X direction to reach the side surface MRc4 of the sealing portion MR. The support portion SG5 hardly protrudes from the side surface MRc4 of the sealing portion MR, and the tip surface of the support portion SG5 (the end surface opposite to the side connected to the lead LD2b) is exposed from the side surface MRc4 of the sealing portion MR.

[0130] The support portion SG6 is connected to the side surface of the lead LD1c (the side surface of the portion extending in the Y direction), and extends in the X direction to reach the side surface MRc4 of the sealing portion MR. The support portion SG6 hardly protrudes from the side surface MRc4 of the sealing portion MR, and the tip surface of the support portion SG6 (the end surface opposite to the side connected to the lead LD1c) is exposed from the side surface MRc4 of the sealing portion MR.

[0131] The die pad DPH, the leads LD1a, LD1b, LD1c, the supporting portions SG3 and SG6 are integrally formed, and the die pad DPL, the leads LD2a, LD2b, the supporting portions SG4 and SG5 are integrally formed.

[0132] The exposed portion of the support portion SG3 on the side surface MRc2 of the sealing portion MR is located near the corner KD1 of the sealing portion MR. The distance K1 (distance in the Y direction) from the exposed portion of the support portion SG3 on the side surface MRc2 of the sealing portion MR to the corner KD1 of the sealing portion MR is preferably 1 mm or less.

[0133] The exposed portion of the support portion SG4 on the side surface MRc2 of the sealing portion MR is located near the corner portion KD2 of the sealing portion MR. The distance K2 (distance in the Y direction) from the exposed portion of the support portion SG4 on the side surface MRc2 of the sealing portion MR to the corner portion KD2 of the sealing portion MR is preferably 1 mm or less.

[0134] The exposed portion of the support portion SG5 on the side surface MRc4 of the sealing portion MR is located near the corner KD3 of the sealing portion MR. The distance K3 (distance in the Y direction) from the exposed portion of the support portion SG5 on the side surface MRc4 of the sealing portion MR to the corner KD3 of the sealing portion MR is preferably 1 mm or less.

[0135] The exposed portion of the support portion SG6 on the side surface MRc4 of the sealing portion MR is located near the corner KD4 of the sealing portion MR. The distance K4 (distance in the Y direction) from the exposed portion of the support portion SG6 on the side surface MRc4 of the sealing portion MR to the corner KD4 of the sealing portion MR is preferably 1 mm or less. The corners KD1, KD2, KD3, and KD4 of the sealing portion MR are shown in FIG. 2 above and FIG. 21 described below.

[0136] Other than this, the semiconductor device PKG of the modified example is almost the same as the semiconductor device PKG of FIGS. 1 to 7, so a repeated description thereof will be omitted here.

[0137] Next, a manufacturing process of the semiconductor device PKG1 of the modified example will be described. Fig. 20 is a plan view of a lead frame LF used to manufacture the semiconductor device PKG1 of the modified example, and corresponds to Fig. 8 above.

[0138] First, the differences between the lead frame LF in Fig. 20 and the lead frame LF in Fig. 8 will be described below. The lead frame LF shown in Fig. 20 will be referred to as a modified lead frame LF.

[0139] The lead frame LF of the modified example shown in FIG. 20 does not have the above-mentioned supporting portions SG1 and SG2, but instead has supporting portions SG3, SG4, SG5, and SG6.

[0140] The support portion SG3 extends in the X direction, with one end integrally connected to a side surface of the lead LD1b (the side surface of the portion extending in the Y direction), and the other end integrally connected to the frame portion LF2. The support portion SG4 extends in the X direction, with one end integrally connected to a side surface of the lead LD2a (the side surface of the portion extending in the Y direction), and the other end integrally connected to the frame portion LF2. The support portion SG5 extends in the X direction, with one end integrally connected to a side surface of the lead LD2b (the side surface of the portion extending in the Y direction), and the other end integrally connected to the frame portion LF4. The support portion SG6 extends in the X direction, with one end integrally connected to a side surface of the lead LD1c (the side surface of the portion extending in the Y direction), and the other end integrally connected to the frame portion LF4.

[0141] Therefore, in the lead frame LF of the modified example, the die pad DPH is connected to the frame portion LF1 via the leads LD1a, LD1b, and LD1c, connected to the frame portion LF2 via the lead LD1b and the support portion SG3, and connected to the frame portion LF4 via the lead LD1c and the support portion SG6. Therefore, the die pad DPH is supported on the frame portions LF1, LF2, and LF4 by the leads LD1a, LD1b, and LD1c and the support portions SG3 and SG6. Furthermore, in the lead frame LF of the modified example, the die pad DPL is connected to the frame portion LF3 via the leads LD2a and LD2b, connected to the frame portion LF2 via the lead LD2a and the support portion SG4, and connected to the frame portion LF4 via the lead LD2b and the support portion SG5. Therefore, the die pad DPL is supported on the frame portions LF2, LF3, and LF4 by the leads LD2a, LD2, and the support portions SG4 and SG5.

[0142] Other than this, the lead frame LF of the modified example of FIG. 20 is almost the same as the lead frame 8 described above, so a repeated explanation will be omitted here.

[0143] The die bonding process and wire bonding process for manufacturing the semiconductor device PKG1 of the modified example are almost the same as those for manufacturing the semiconductor device PKG, so a repeated explanation thereof will be omitted here.

[0144] FIG. 21 is a plan view of the semiconductor device PKG1 of the modified example during the manufacturing process, showing the stage where the molding process has been carried out to form the sealing portion MR.

[0145] The molding process forms a sealing portion MR that seals the die pads DPH, DPL, the semiconductor chips CPC, CPH, CPL, the wires BW, and the inner lead portions of the leads LD.

[0146] When the sealing portion MR is formed, a portion of each of the support portions SG3, SG4, SG5, and SG6 is also sealed within the sealing portion MR. Specifically, the support portion SG3 integrally includes a portion sealed within the sealing portion MR near the corner KD1 of the sealing portion MR and a portion protruding from the side surface MRc2 of the sealing portion MR to the outside of the sealing portion MR and connected to the frame portion LF2. The support portion SG4 integrally includes a portion sealed within the sealing portion MR near the corner KD2 of the sealing portion MR and a portion protruding from the side surface MRc2 of the sealing portion MR to the outside of the sealing portion MR and connected to the frame portion LF2. The support portion SG5 integrally includes a portion sealed within the sealing portion MR near the corner KD3 of the sealing portion MR and a portion protruding from the side surface MRc4 of the sealing portion MR to the outside of the sealing portion MR and connected to the frame portion LF4. The support portion SG6 integrally has a portion sealed within the sealing portion MR near the corner portion KD4 of the sealing portion MR, and a portion protruding from a side surface MRc4 of the sealing portion MR to the outside of the sealing portion MR and connected to the frame portion LF4.

[0147] The sealing portion MR is supported by the frame portion LF1 by a plurality of leads LD (LD1, LD1a, LD1b, LD1c) on the side surface MRc1, by the frame portion LF3 by a plurality of leads LD (LD2, LD2a, LD2b) on the side surface MRc3, by the frame portion LF2 by the support portions SG3 and SG4 on the side surface MRc2, and by the frame portion LF4 by the support portions SG5 and SG6 on the side surface MRc4. That is, the sealing portion MR is stably supported by the frame portions LF1, LF2, LF3, and LF4 by the plurality of leads LD and the support portions SG3, SG4, SG5, and SG6.

[0148] After forming the sealing portion MR in the molding process, a plating layer (not shown) is formed as needed on the outer lead portion of the lead LD exposed from the sealing portion MR. Then, outside the sealing portion MR, the lead LD is cut at a predetermined position to separate it from the frame (frame portions LF1 and LF3) of the lead frame LF. At this time, the cutting process of the multiple leads LD (LD1, LD1a, LD1b, and LD1c) on the side surface MRc1 of the sealing portion MR and the cutting process of the multiple leads LD (LD2, LD2a, and LD2b) on the side surface MRc3 of the sealing portion MR are performed in any order, and then the supporting portions SG3, SG4, SG5, and SG6 protruding from the sealing portion MR are cut. This allows the cutting process of the leads LD to be performed while the sealing portion MR is supported by the supporting portions SG3, SG4, SG5, and SG6 on the frame portions LF2 and LF4, thereby enabling the leads LD to be cut accurately.

[0149] Thereafter, in the same manner as in the manufacturing process of the semiconductor device PKG, the outer lead portions of the leads LD protruding from the sealing portion MR are bent (lead processing, lead forming) to manufacture the semiconductor device PKG1 of the modified example.

[0150] When manufacturing the semiconductor device PKG1 of the modified example, in the lead frame LF, the die pad DPH is supported not only to the frame portion LF1 by the leads LD1a, LD1b, and LD1c but also to the frame portions LF2 and LF4 by the leads LD1b and LD1c and the support portions SG3 and SG6. Furthermore, in the lead frame LF, the die pad DPL is supported not only to the frame portion LF3 by the leads LD2a and LD2b but also to the frame portions LF2 and LF4 by the leads LD2a, LD2b, and the support portions SG4 and SG5. This allows the die pads DPH and DPL to be stably supported on the frame of the lead frame LF, facilitating the die bonding process, wire bonding process, and molding process. Furthermore, the lead LD cutting process can be performed in a state in which the sealing portion MR is supported on the frame portions LF2 and LF4 by the support portions SG3, SG4, SG5, and SG6, allowing the leads LD to be accurately cut.

[0151] Furthermore, in the semiconductor device PKG1 of the modified example, the supporting portions SG3 and SG4 are exposed on the side surface MRc2 of the sealing portion MR, but on the side surface MRc2 of the sealing portion MR, the exposed portion of the supporting portion SG3 is located near the corner KD1 of the sealing portion MR, and the exposed portion of the supporting portion SG4 is located near the corner KD2 of the sealing portion MR (see FIGS. 18, 19, and 21). Furthermore, the supporting portions SG5 and SG6 are exposed on the side surface MRc4 of the sealing portion MR, but on the side surface MRc4 of the sealing portion MR, the exposed portion of the supporting portion SG5 is located near the corner KD3 of the sealing portion MR, and the exposed portion of the supporting portion SG6 is located near the corner KD4 of the sealing portion MR (see FIGS. 18, 19, and 21). This makes it possible to increase the creepage distance (the distance along the surface of the sealing portion MR) between the exposed portion of the support portion SG3 and the exposed portion of the support portion SG4 from the sealing portion MR, and also to increase the creepage distance between the exposed portion of the support portion SG5 and the exposed portion of the support portion SG6 from the sealing portion MR, thereby further improving the reliability of the semiconductor device PKG1.

[0152] However, it is more preferable that the support portions SG3 and SG6 are not exposed on the side surface MRc1 of the sealing portion MR, and it is also more preferable that the support portions SG4 and SG5 are not exposed on the side surface MRc3 of the sealing portion MR. That is, it is preferable that the side surfaces of the support portions SG3, SG4, SG5, and SG6 are covered by the sealing portion MR. This makes it possible to more accurately suppress or prevent cracks from occurring in the sealing portion MR due to the support portions SG3, SG4, SG5, and SG6.

[0153] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0154] BDC,BDH,BDL Bonding material BT1,BT2 power supply BW Wire CC control circuit CPC, CPC101, CP201, CPH, CPL semiconductor chips DPH, DPH101, DPL, DPL101 die pad DPHa,DPLa top surface DPHb, DPLb bottom surface DPHc1,DPHc2,DPHc3,DPHc4,DPLc1,DPLc2,DPLc3,DPLc4 Side DR drive circuit KD1, KD2, KD3, KD4 Corner LD, LD1, LD1a, LD1b, LD1c, LD2, LD2a, LD2b leads LOD load MR sealing part MRa top surface MRb bottom side MRc1,MRc2,MRc3,MRc4 Side MW1,MW2,MW3 Multilayer wiring structure PA,PA2,PA3 Protective film PC1, PC2, PC3, PC4, PH1, PH2, PH3, PH4, PL1, PL2, PL3, PL4 Pads PKG,PKG101 Semiconductor device RX1,RX2 receiving circuit SB1, SB2, SB3 semiconductor substrate SG1,SG2,SG3,SG4,SG5,SG6 Support part TS1, TS2 power transistors TX1,TX2 transmitter circuit WR1, WR2 wiring

Claims

1. a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; a second semiconductor chip mounted on the second chip mounting portion; a third semiconductor chip mounted on the second chip mounting portion and including a first coil and a second coil; a sealing body that seals the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion, and the second chip mounting portion; Equipped with the first coil and the second coil are magnetically coupled to each other, the first coil is electrically connected to a first circuit formed in the first semiconductor chip; the second coil is electrically connected to a second circuit formed in the second semiconductor chip; In a cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil, The power consumption of the second semiconductor chip during operation is greater than the power consumption of the first semiconductor chip during operation, A semiconductor device, wherein the area of ​​the second chip mounting portion is larger than the area of ​​the first chip mounting portion.

2. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the first circuit is one of a transmitting circuit and a receiving circuit, and the second circuit is the other of the transmitting circuit and the receiving circuit.

3. 2. The semiconductor device according to claim 1, A semiconductor device in which no semiconductor element is formed in the third semiconductor chip.

4. 2. The semiconductor device according to claim 1, the first semiconductor chip is mounted on the first chip mounting portion via a first bonding material; the second semiconductor chip is mounted on the second chip mounting portion via a second bonding material, The semiconductor device, wherein the third semiconductor chip is mounted on the second chip mounting portion via a third bonding material.

5. 5. The semiconductor device according to claim 4, The semiconductor device, wherein the first bonding material, the second bonding material, and the third bonding material each have electrical conductivity.

6. 2. The semiconductor device according to claim 1, Multiple leads and A plurality of wires; Further provided with The semiconductor device, wherein the encapsulant encapsulates a portion of each of the plurality of leads and the plurality of wires.

7. 7. The semiconductor device according to claim 6, the first semiconductor chip has a plurality of first pads and a plurality of second pads; the second semiconductor chip has a plurality of third pads and a plurality of fourth pads; the third semiconductor chip has a plurality of fifth pads electrically connected to the first coil and a plurality of sixth pads electrically connected to the second coil, the plurality of wires include a plurality of first wires electrically connecting the plurality of first pads of the first semiconductor chip and the plurality of fifth pads of the third semiconductor chip, a plurality of second wires electrically connecting the plurality of third pads of the second semiconductor chip and the plurality of sixth pads of the third semiconductor chip, a plurality of third wires electrically connecting the plurality of second pads of the first semiconductor chip and a plurality of first leads among the plurality of leads, and a plurality of fourth wires electrically connecting the plurality of fourth pads of the second semiconductor chip and a plurality of second leads among the plurality of leads.

8. 8. The semiconductor device according to claim 7, the second semiconductor chip further includes a seventh pad; the plurality of wires further includes a fifth wire that electrically connects the seventh pad of the second semiconductor chip and the second chip mounting portion.

9. 8. The semiconductor device according to claim 7, the plurality of first leads are electrically connected to a third circuit external to the semiconductor device; the second leads are electrically connected to a fourth circuit external to the semiconductor device; A semiconductor device, wherein a power supply voltage supplied to the fourth circuit is higher than a power supply voltage supplied to the third circuit.

10. 7. The semiconductor device according to claim 6, In a cross-sectional view, the height positions of the first chip mounting portion and the second chip mounting portion are lower than the height positions of inner lead portions of the plurality of leads.

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