Storage device, liquid ejection head, and liquid ejection device

Abstract

To achieve more appropriate writing of information in a storage.SOLUTION: A storage comprises: a memory unit that includes an anti-fuse element; an information writing section that writes information in the anti-fuse element by periodically adding a signal to the memory unit; and a control section that performs drive control of the information writing section. The control section changes the period of the signal that should be output by the information writing section based on a result of determination as to whether the signal periodically output by the information writing section satisfies a reference.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates generally to storage devices. [Background technology]

[0002] Some electrical appliances are equipped with a storage device for storing product-specific information (see Patent Document 1). The storage device may use a memory element that can store information only once, a so-called OTP (One Time Programmable) memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-58130 Summary of the Invention [Problem to be solved by the invention]

[0004] As an example of an OTP memory, an anti-fuse element having a MOS structure is used, and in this case, information can be written by causing dielectric breakdown of the MOS structure. In general, there is a demand for a technology that more appropriately realizes information writing.

[0005] An exemplary object of the present invention is to enable more appropriate writing of information in a storage device. [Means for solving the problem]

[0006] One aspect of the present invention relates to a storage device, the storage device comprising: a memory unit including an antifuse element; an information writing unit that writes information into the antifuse element by periodically applying a signal to the memory unit; a control unit that controls the driving of the information writing unit, The control unit changes the period of the signal output by the information writing unit based on a determination result as to whether or not the signal periodically output by the information writing unit satisfies a criterion. It is characterized by: [Effects of the Invention]

[0007] According to the present invention, it is possible to realize more appropriate writing of information in a storage device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram showing an example of the overall configuration of a liquid ejection device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a liquid ejection head. [Figure 3] FIG. 3 is a diagram showing an example of a circuit configuration of a part of a control unit. [Figure 4] FIG. 3 is a diagram showing an example of a circuit configuration of a part of a control unit. [Figure 5] 10 is a timing chart showing signal levels of several nodes in the control unit. [Figure 6] FIG. 2 is a block diagram showing an example of the configuration of a calculation unit. [Figure 7] 10 is a flowchart showing an example of a method for changing frequency settings. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] 1 is a schematic diagram showing an example of the overall configuration of a liquid ejection device 1 according to an embodiment. The liquid ejection device 1 includes a liquid ejection head 11, a carriage 12, and a head controller 13 for controlling the driving of these components.

[0011] The liquid ejection head 11 is provided with a plurality of nozzles (ejection ports) for ejecting liquid, and includes a head substrate on which a plurality of liquid ejection elements corresponding to the plurality of nozzles are provided. Ink is typically used as the liquid. The liquid ejection head 11 drives each liquid ejection element based on a drive signal or control signal from a head controller 13. This causes ink to be ejected from the corresponding nozzle, and desired printing is performed on a printing medium P, such as a sheet of paper. This type of printing mode may be referred to as an inkjet method.

[0012] The liquid ejection head 11 is mounted on a carriage 12, which can move back and forth in direction d1 along a guide 14 based on a drive signal or control signal from a head controller 13. The recording medium P is transported in direction d2 by a transport mechanism of the liquid ejection device 1, and during this transport, the liquid ejection head 11 can move back and forth in direction d1 by the carriage 12.

[0013] The head controller 13 controls the driving of the liquid ejection head 11 while reciprocating the carriage 12. This allows desired recording to be achieved on the recording medium P, forming, for example, characters, symbols, figures, photographs, etc.

[0014] The head controller 13 may be expressed as a head driver or the like. The liquid ejection head 11 may be expressed simply as an ejection head, or may be expressed as a recording head. In this embodiment, the liquid ejection head 11 may also be expressed as an inkjet head, a serial head, or the like. The liquid ejection device 1 may also be expressed simply as an ejection device, or may be expressed as a recording device. In this embodiment, the liquid ejection device 1 may also be expressed as an inkjet printer or the like.

[0015] 2 is a block diagram showing an example of the configuration of the liquid ejection head 11. The liquid ejection head 11 includes a head substrate 21 and a head drive substrate 22. The head substrate 21 includes a functional unit 211 and a storage device 212. The head drive substrate 22 includes a calculation unit 221 and a power supply unit 222.

[0016] In the head substrate 21, the functional unit 211 is configured to be able to realize the main function of the liquid ejection head 11 (here, the recording function), and in this embodiment includes a plurality of liquid ejection elements 2111 and an element driving unit 2112 that can drive the liquid ejection elements 2111 individually. The liquid ejection elements 2111 may be simply referred to as ejection elements, or may be referred to as recording elements, etc. Although heater elements or electrothermal conversion elements are typically used as the liquid ejection elements 2111, other elements such as piezoelectric elements may also be used. Although a detailed description is omitted here, the functional unit 211 may be configured to be able to be driven by a known method; for example, the plurality of liquid ejection elements 2111 may be divided into several blocks and driven in block units (using a so-called time-division driving method).

[0017] The storage device 212, the details of which will be described later, is capable of storing information specific to the liquid ejection head 11. Examples of the specific information include an identifier, a serial number, and specific parameters.

[0018] In the head drive substrate 22, the calculation unit 221 performs calculation processing based on signals from an external device, drives the head substrate 21 based on the calculation results, and drives or controls, for example, the function unit 211 and the storage device 212. The calculation unit 221 uses an ASIC (application-specific integrated circuit), but may additionally or alternatively use a CPU (central processing unit) and memory.

[0019] The power supply unit 222 receives a power supply voltage from an external power supply, generates a plurality of power supply voltages, and is capable of supplying corresponding voltages to each element. In this embodiment, the power supply unit 222 generates and outputs voltages VH, VHT, and VDD as power supply voltages, and is also capable of outputting voltages GNDH and VSS as ground voltages. For example, the voltage VH is 24V (volts), the voltage VHT is 24V, the voltage VDD is 3.3V, the voltage GNDH is 0V, and the voltage VSS is 0V.

[0020] Incidentally, among the above-mentioned voltages VH and the like, those with the same potential can be prevented from electrical interference between power supply systems due to potential fluctuations by providing them individually, but they may also be provided in common.

[0021] The head substrate 21 and the head drive substrate 22 are connected to each other, and the functional unit 211 is capable of performing recording based on the calculation results of the calculation unit 221 using a voltage supplied from the power supply unit 222. Furthermore, although details will be described later, the storage device 212 is capable of storing information based on the calculation results of the calculation unit 221 using the voltage supplied from the power supply unit 222.

[0022] The storage device 212 includes a plurality of memory units 31, a plurality of information writing units 32, and a control unit 33. The memory unit 31 includes an anti-fuse element 311, a switch element 312, and protection elements 313a and 313b.

[0023] The antifuse element 311 is a memory element that can store information only once, i.e., it is a memory element that cannot be rewritten, and functions as a so-called OTP (One Time Programmable) memory. In this embodiment, a MOS (Metal Oxide Semiconductor) structure is used for the antifuse element 311. This MOS structure shows a state in which no information is written before dielectric breakdown, and a state in which information is written after dielectric breakdown.

[0024] A known high-voltage transistor such as a DMOS (Double-Diffused MOS) transistor may be used for the switch element 312. The switch element 312 is turned on or off based on a signal from the information writing unit 32. When the switch element 312 is turned on, a voltage VHT is supplied to the anti-fuse element 311, and when the switch element 312 is turned off, the supply is suppressed.

[0025] As will be described in detail later, the switch element 312 is periodically driven, and thereby the voltage VHT is periodically supplied to the anti-fuse element 311. This causes dielectric breakdown of the MOS structure of the anti-fuse element 311, and information is written to the anti-fuse element 311. Note that writing of information may be expressed as writing of information to the memory unit 31 or as writing of information to the storage device 212.

[0026] The protection element 313a is connected in parallel to the anti-fuse element 311, and a resistive element may be used for the protection element 313a. The protection element 313b is connected in series to the anti-fuse element 311, and a resistive element may be used for the protection element 313b. With this configuration, if an unexpected overvoltage such as ESD (electrostatic discharge) is applied to the power supply line of the power supply voltage VHT, the overvoltage can be guided to the other protection element 313c connected to that power supply line. This makes it possible to prevent unexpected writing of information to the anti-fuse element 311 due to the overvoltage.

[0027] The information writing unit 32 is a logic circuit provided corresponding to each memory unit 31, and in this embodiment is an AND circuit. A voltage VHTM generated from the voltage VHT via a step-down circuit 329 can be supplied to the information writing unit 32.

[0028] Here, the information writing unit 32 periodically applies a signal to the memory unit 31 based on a signal from the control unit 33, thereby writing information to the anti-fuse element 311. By periodically applying a signal to the memory unit 31, a large current from the parasitic capacitance is periodically supplied to the anti-fuse element 311, thereby making it possible to relatively quickly write information to the anti-fuse element 311. More specifically, the state of the MOS structure after dielectric breakdown includes a state in which dielectric breakdown has occurred sufficiently (a so-called hard breakdown state) and a state in which dielectric breakdown has occurred partially (a so-called soft breakdown state). Then, by periodically applying a signal to the memory unit 31, the electrical energy required to change the MOS structure from a state before dielectric breakdown to a hard breakdown state via a soft breakdown state can be appropriately supplied to the MOS structure.

[0029] The information writing unit 32 may be expressed as an information writing control unit, or simply as a writing control unit, or may be expressed as an information writing execution unit, or simply as a writing execution unit.

[0030] The control unit 33 is configured to be able to execute drive control of the information writing unit 32. The control unit 33 includes a selection unit 331 and a determination unit 332. The selection unit 331 selects one of the multiple memory units 31 into which information should be written (the memory unit 31 to which information should be written) based on a signal from the calculation unit 221. The determination unit 332 is configured to be able to determine whether the signal periodically output by the information writing unit 32 satisfies a criterion, and for example, a comparison circuit for comparing the signal to be input to the information writing unit 32 with the signal output by the information writing unit 32 can be used as the determination unit 332.

[0031] Details will be described later, but with this configuration, the control unit 33 changes the period of the signal to be output by the information writing unit 32 based on the determination result of whether the signal periodically output by the information writing unit 32 satisfies the criteria.

[0032] The calculation unit 221 includes a measurement unit 41, a processing unit 42, and a signal period setting unit 43. The measurement unit 41 measures the judgment results of the judgment unit 332, and in this case, measures the number of times the signal output by the information writing unit 32 does not satisfy the criteria. The processing unit 42, details of which will be described later, outputs a predetermined signal to the signal period setting unit 43 based on the measurement results of the measurement unit 41. The signal period setting unit 43 can set the period of the signal to be output by the information writing unit 32 based on the signal from the processing unit 42, i.e., the measurement results of the measurement unit 41.

[0033] FIG. 3 mainly illustrates an example of the circuit configuration of the selection unit 331. The selection unit 331 receives one or more control signals (an enable signal HE, a clock signal CLK, and a latch signal LT) in addition to the signal SigI from the calculation unit 221. Here, the signal SigI corresponds to a signal to be input to the information writing unit 32. The selection unit 331 includes a logic circuit unit 3311 and a selector 3312. The logic circuit unit 3311 includes, for example, a shift register, a latch circuit, etc., and outputs an enable signal EN and a selection signal SEL based on the signals HE, CLK, and LT. The selector 3312 outputs the signal SigI to the multiple information writing units 32 via a buffer circuit 3313 based on the enable signal EN. Furthermore, one of the multiple information writing units 32 is driven based on the selection signal SEL, thereby supplying the signal SigO to the corresponding memory unit 31.

[0034] With this configuration, the selection section 331 can select, from the plurality of memory units 31, the memory unit 31 into which information is to be written.

[0035] 4 mainly shows an example of the circuit configuration of the determination unit 332. The determination unit 332 includes logical sum circuits (OR circuits) 511 and 512, exclusive logical sum circuits (XOR circuits) 521 and 522, and flip-flop circuits 5311, 5312, 5321, and 5322.

[0036] The OR circuit 511 receives output signals SigO from each of the multiple information write units 32 and outputs a signal corresponding to the results to the flip-flop circuits 5311 and 5321 via a buffer circuit 541. The signal SigI is input to the flip-flop circuits 5311 and 5312 via a buffer circuit 542 and also input to the flip-flop circuits 5321 and 5322 via an inverter circuit 551. The output terminal of the flip-flop circuit 5311 is connected to the input terminal of the flip-flop circuit 5312. The output terminal of the flip-flop circuit 5321 is connected to the input terminal of the flip-flop circuit 5322. The XOR circuit 521 outputs a signal corresponding to the output signals of the flip-flop circuits 5311 and 5312 to the OR circuit 512. The XOR circuit 522 outputs a signal corresponding to the output signals of the flip-flop circuits 5311 and 5322 to the OR circuit 512. The OR circuit 512 receives signals from the XOR circuits 521 and 522 and outputs a signal D_OUT corresponding to the signals to the measurement unit 41.

[0037] With this configuration, the determination unit 332 determines whether the signal SigI, which is the signal to be input to the information writing unit 32, and the signal SigO, which is the signal output by the information writing unit 32, match, and outputs the determination result as a signal D_OUT to the measurement unit 41. From this perspective, it can be said that this determination result (signal D_OUT) corresponds to the result of comparison between the signal SigI, which is to be input to the information writing unit 32, and the signal SigO, which is output by the information writing unit 32.

[0038] If the signals SigI and SigO do not match based on the signal D_OUT, the measuring unit 41 counts up the measurement value.

[0039] 5(a1) to 5(b2) show examples of timing charts illustrating the signal levels (potentials) of the nodes nd1 to nd9 in the determination unit 332. FIGS. 5(a1) and 5(b1) show examples when the signal SigO follows the signal SigI. FIGS. 5(a2) and 5(b2) show examples when the signal SigO does not follow the signal SigI. In this embodiment, when the signal SigO follows the signal SigI (as in FIGS. 5(a1) and 5(b1)), the XOR circuits 521 and 522 both output an L level (low level). On the other hand, when the signal SigO does not follow the signal SigI (as in FIGS. 5(a2) and 5(b2)), the XOR circuits 521 and / or 522 output an H level (high level), and therefore the signal D_OUT becomes an H level.

[0040] Based on such signal D_OUT, if signal SigO does not follow signal SigI (as in Figures 5(a2) and 5(b2)), the measurement unit 41 counts up the measurement value, assuming that signals SigI and SigO do not match.

[0041] 6 mainly shows an example of the configuration of the calculation unit 221. In the calculation unit 221, the processing unit 42 outputs a setting signal ST to the signal period setting unit 43 based on the measurement results of the measurement unit 41. The setting signal ST is used to set the period of the signal to be output by the information writing unit 32. For example, if the degree of match between the signals SigI and SigO satisfies a criterion, the processing unit 42 maintains or does not change the setting signal ST to be output to the signal period setting unit 43. On the other hand, if the degree of match between the signals SigI and SigO does not satisfy the criterion, the processing unit 42 changes the setting signal ST to be output to the signal period setting unit 43. This allows the signal period setting unit 43 to set, update, or maintain the period of the signal to be output by the information writing unit 32.

[0042] In the following description, M is an integer equal to or greater than 2, and m is an arbitrary integer between 1 and M. The frequency fm of the signal to be output by the information writing unit 32 can be selectively set from frequencies f1 to fM. For example, when M=6, frequency fm can be set to any of frequencies f1 to f6. Frequencies f1 to f6 may be set in advance, for example, f1=3 MHz (megahertz), f2=4 MHz, f3=5 MHz, f4=6 MHz, f5=7 MHz, f6=8 MHz, etc. Furthermore, the initial value of frequency fm may be fixed, for example, as frequency fm=f3, or may be arbitrarily determined by the manufacturer of the liquid ejection head 11 or the user of the liquid ejection device 1.

[0043] Although detailed description will be omitted here, when recording is performed, the processing unit 42 outputs recording data received from an external device to the function unit 211 via the control unit 33.

[0044] 7 is a flowchart showing an example of a method for changing the setting of the frequency fm. This flowchart is executed by the calculation unit 221 (mainly the processing unit 42), and the outline thereof is to set an initial value of the frequency fm, and then update or maintain the frequency fm based on the measurement result of the measurement unit 41.

[0045] In step S7000 (hereinafter simply referred to as "S7000"; the same applies to other steps described below), it is determined whether or not to execute writing of information to the storage device 212. This determination can be made, for example, based on whether or not there is a command from an external device instructing writing of information to the storage device 212. If writing of information is to be executed, the process proceeds to S7010; if not, the process returns to S7000 (or ends this flowchart).

[0046] In S7010, a memory unit 31 to be written to is selected from among the plurality of memory units 31. The memory unit 31 to be selected can be determined based on the command instructing the external device to write information to the storage device 212.

[0047] In S7020, the initial value of the frequency fm is set. Here, it is assumed that the frequency fm is set to f3.

[0048] In S7030, writing information to the selected memory unit 31 is started. This step is performed by the information writing unit 32 outputting a signal of the frequency fm to the memory unit 31. Here, the number of times the information writing unit 32 outputs a signal to the memory unit 31 is continuously measured by the arithmetic unit 221 as the signal output count Nw.

[0049] In S7040, it is determined whether the signal output count Nw has reached a reference value. For this reference value, a sufficient number of times to put the MOS structure of the anti-fuse element 311 into a hard breakdown state may be set, and for example, values such as several thousand or several tens of thousand can be set. If the signal output count Nw reaches the reference value, proceed to S7200; otherwise, proceed to S7050. <00001​​​​​​​​​​​​​​In S7100, it is determined whether the degree of coincidence is higher than the standard. If the degree of coincidence is higher than the standard (that is, when DvalH < Dval), it proceeds to S7110. Otherwise (that is, when Dval < DvalL), it proceeds to S7120.

[0054] In S7110, the frequency fm is changed to a higher one. For example, when the frequency fm = f3, it is changed to the frequency fm = f4. Then, the writing of information is resumed and it returns to S7040.

[0055] In S7120, the frequency fm is changed to a lower one. For example, when the frequency fm = f3, it is changed to the frequency fm = f2. Then, the writing of information is resumed and it returns to S7040.

[0056] In S7200, it is determined whether it is necessary to write information to another memory unit 31. If it is necessary to write information to another memory unit 31, it returns to S7010 and starts writing information to the other memory unit 31 in the same procedure. If it is not necessary to write information to another memory unit 31, it is regarded that the writing of information to the storage device 212 is completed, and this flowchart is terminated.

[0057] In this way, when the degree of coincidence between the signal SigI and the signal SigO is within the standard range, the signal period setting unit 43 does not change the period of the signal that the information writing unit 32 should output. On the other hand, when the degree of coincidence is higher than the standard, the signal period setting unit 43 changes the period of the signal that the information writing unit 32 should output to a higher one, and when the degree of coincidence is lower than the standard, the signal period setting unit 43 changes the period of the signal that the information writing unit 32 should output to a lower one.

[0058] According to this embodiment, the period of the signal to be output by the information writing unit 32 can be changed based on the measurement results of the measuring unit 41. This makes it possible to efficiently supply electrical energy to the MOS structure when writing information to the antifuse element 311, and relatively quickly change the MOS structure from a state before breakdown to a soft breakdown state and then to a hard breakdown state. Therefore, according to this embodiment, more appropriate information writing in the memory device 212 can be relatively easily achieved.

[0059] In the above example, steps such as obtaining the measurement results of the measurement unit 41 (see S7050) and evaluating the degree of coincidence Dval (see S7060) are performed for each pulse of the signal of frequency fm, but as another example, they may be performed for each set of pulses. In this case, parameters required to achieve the same content as each step, such as Dval and Km, are initialized for each period of multiple pulses, and other parameters may be used incidentally.

[0060] In the above description, for ease of understanding, each element is denoted by a name related to its function. However, each element is not limited to having the content described in the embodiment as its main function, and may have that function auxiliary to the content. Therefore, each element is not strictly limited to the expression, and the expression can be replaced with a similar expression. In the same spirit, the expression "apparatus" may be replaced with "unit," "component," "piece," "member," "structure," "assembly," etc., or may be omitted.

[0061] For ease of understanding, the elements corresponding to the above-described functions are illustrated separately here, but they may be configured at least partially as an integrated unit, or some of them may be configured separately. For example, the individual elements of the head substrate 21 and the head drive substrate 22 may be configured at least partially as an integrated unit. For example, some of the functions of the control unit 33 may be included in the calculation unit 221, or some of the functions of the calculation unit 221 may be included in the control unit 33.

[0062] (program) The present invention may be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in a computer of the system or device read and execute the program. For example, the present invention may be realized by a circuit (e.g., an ASIC) that realizes one or more functions.

[0063] (others) In the above description, an inkjet recording device has been exemplified as the liquid ejection device 1, but the present invention is not limited to this. That is, the device 1 may be a single-function printer having only a recording function, or a multi-function printer having multiple functions such as a recording function, a fax function, and a scanner function. Furthermore, the device 1 may be, for example, a manufacturing device for manufacturing color filters, electronic devices, optical devices, microstructures, etc. using a predetermined recording method.

[0064] Furthermore, the term "recording" as used in this specification should be interpreted broadly. Therefore, the form of "recording" does not matter whether the object formed on the recording medium is significant information such as characters or figures, or whether it is visible to humans or not.

[0065] Furthermore, the term "recording medium" should be interpreted broadly, just like the above-mentioned "recording." Therefore, the concept of "recording medium" can include not only commonly used paper, but also any material that can accept ink, such as cloth, plastic film, metal plate, glass, ceramics, resin, wood, leather, etc.

[0066] Furthermore, "ink" should be interpreted broadly, just like the above-mentioned "recording." Therefore, the concept of "ink" includes not only a liquid that forms an image, design, pattern, etc. by being applied to a recording medium, but also ancillary liquids that can be used for processing the recording medium, treating the ink (for example, solidifying or insolubilizing the coloring material in the ink applied to the recording medium), etc.

[0067] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0068] 212: memory device, 31: memory unit, 311: anti-fuse element, 32: information writing section, 33: control section.

Claims

1. a memory unit including an antifuse element; an information writing unit that writes information into the antifuse element by periodically applying a signal to the memory unit; a control unit that controls the driving of the information writing unit, The control unit changes the period of the signal to be output by the information writing unit based on a determination result as to whether or not the signal periodically output by the information writing unit satisfies a criterion.

1. A storage device comprising:

2. further comprising a plurality of memory units; the memory unit is one of the plurality of memory units; The control unit includes a selection unit that selects one of the plurality of memory units that includes the anti-fuse element into which information is to be written.

2. The storage device according to claim 1.

3. The determination result corresponds to a comparison result between a signal to be input to the information writing unit and a signal output by the information writing unit.

3. The storage device according to claim 1 or 2.

4. The control unit is connected to or includes a signal period setting unit that sets the period of the signal to be output by the information writing unit based on the determination result.

4. The storage device according to claim 1, wherein the first and second storage units are connected to each other.

5. The signal period setting unit If the degree of coincidence between the signal to be input to the information writing unit and the signal output by the information writing unit is higher than a reference value, the period of the signal output by the information writing unit is changed to a higher period; If the degree of coincidence between the signal to be input to the information writing unit and the signal output by the information writing unit is lower than a reference value, the period of the signal output by the information writing unit is changed to a lower period; When the degree of coincidence between the signal to be input to the information writing unit and the signal output by the information writing unit is within a reference range, the period of the signal output by the information writing unit is not changed.

5. The storage device according to claim 4.

6. the memory unit further includes a switch element connected in series with the anti-fuse element; The switch element is turned on based on the signal output from the information writing unit.

6. The storage device according to claim 1, wherein the storage device is a storage device having a plurality of storage areas.

7. The anti-fuse element has a MOS structure.

7. The storage device according to claim 1, wherein the storage device is a storage device having a plurality of storage areas.

8. A storage device according to any one of claims 1 to 7; a discharge element for discharging the liquid; A liquid ejection head characterized by:

9. The liquid ejection head according to claim 8, a head controller for controlling the driving of the liquid ejection head; A liquid ejection device characterized by:

Images