Semiconductor epitaxial wafer manufacturing method

Abstract

To provide a manufacturing method for a semiconductor epitaxial wafer, capable of manufacturing the semiconductor epitaxial wafer with fewer epitaxial defects by setting a thermal process condition in accordance with an ion injection condition even when the ion injection is performed under a condition of forming an amorphous region in a surface part of a semiconductor wafer, which is a substrate.SOLUTION: In a method of obtaining a semiconductor epitaxial wafer, an amorphous region is formed in a surface part of a semiconductor wafer by injecting ions to a surface of the semiconductor wafer; the semiconductor wafer is subjected to a recrystallization thermal process for recovering the crystallinity of the amorphous region; and then an epitaxial layer is formed on the surface of the semiconductor wafer. A recrystallization thermal process condition of the recrystallization thermal process is calculated using a dynamic Monte Carlo method simulation on the basis of the ion injection condition. The recrystallization thermal process is performed under the calculated recrystallization thermal process condition.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a method for producing a semiconductor epitaxial wafer. [Background technology]

[0002] Metal contamination is one of the factors that degrade the characteristics of semiconductor devices. For example, in back-illuminated solid-state imaging devices, metal contamination in the semiconductor epitaxial wafer that serves as the substrate for these devices increases the dark current of the solid-state imaging device, resulting in defects called white defects. Back-illuminated solid-state imaging devices have been widely used in digital video cameras and mobile phones such as smartphones in recent years because they allow external light to be directly absorbed by the sensor by locating the wiring layer and other components below the sensor section, enabling clearer images and videos to be captured even in dark places. Therefore, there is a need to minimize white defects.

[0003] Metal contamination of wafers occurs primarily during the semiconductor epitaxial wafer manufacturing process and the solid-state imaging device manufacturing process (device manufacturing process). Metal contamination in the former semiconductor epitaxial wafer manufacturing process is thought to be caused by heavy metal particles from the components of the epitaxial growth furnace, or by heavy metal particles generated by metal corrosion of the piping materials used in the furnace, which uses chlorine-based gases as the gas used during epitaxial growth. While these metal contamination issues have been somewhat alleviated in recent years by replacing the components of epitaxial growth furnaces with more corrosion-resistant materials, they are still not sufficient. Meanwhile, in the latter solid-state imaging device manufacturing process, heavy metal contamination of semiconductor substrates is a concern during processes such as ion implantation, diffusion, and oxidation heat treatment.

[0004] To suppress such heavy metal contamination, there is a technology to form gettering sites in semiconductor wafers to capture heavy metals. One known method is to implant ions into the semiconductor wafer and then form an epitaxial layer. In this method, the ion-implanted region functions as the gettering site.

[0005] Patent Document 1 describes a method for producing a semiconductor epitaxial wafer, which includes a first step of irradiating the surface of a semiconductor wafer with cluster ions to form an ion-implanted region (modified layer) in the surface layer portion of the semiconductor wafer, in which constituent elements of the cluster ions form a solid solution, and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer.

[0006] In order to improve the gettering ability of the modified layer formed by ion implantation, for example, it is effective to increase the dose of implanted ions. However, increasing the dose of implanted ions results in the formation of an amorphous region made of amorphous semiconductor in the surface portion of the semiconductor wafer, which causes many epitaxial defects in the subsequently formed semiconductor epitaxial layer.

[0007] Therefore, when an amorphous region is formed on the surface of a semiconductor wafer by ion implantation, a recrystallization heat treatment is performed to restore the crystallinity of the amorphous region before forming an epitaxial layer (see Patent Document 1).

[0008] Regarding the recrystallization heat treatment, Patent Document 2 describes a technique for recrystallizing an amorphous region by subjecting a silicon wafer to a heat treatment in a non-oxidizing atmosphere at a temperature of 450°C or higher and 800°C or lower for a relatively long period of time of 300 seconds or higher and 120 minutes or lower.

[0009] On the other hand, Patent Document 3 describes a technique in which a silicon wafer is heated in a non-oxidizing atmosphere at a rate of 10°C / s or more, and heat-treated at a maximum temperature of 350°C to 700°C for a relatively short time of 1 second to 100 seconds. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] International Publication No. 2012 / 157162 [Patent Document 2] Patent Publication No. 2015-156455 [Patent Document 1] Japanese Patent Application Publication No. 2020-170794 Summary of the Invention [Problem to be solved by the invention]

[0011] As is clear from the differences in the heat treatment conditions in the techniques of Patent Document 2 and Patent Document 3, the conditions for the recrystallization heat treatment are not self-evident. Furthermore, the degree of damage to the surface of the semiconductor wafer caused by ion implantation depends on the ion implantation conditions. Therefore, it is important to determine appropriate conditions for the recrystallization heat treatment according to the ion implantation conditions and to perform the recrystallization heat treatment of the amorphous region under the determined conditions.

[0012] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to propose a method for producing a semiconductor epitaxial wafer with few epitaxial defects by performing a recrystallization heat treatment according to the ion implantation conditions when ion implantation is performed under conditions that form an amorphous region in the surface portion of a semiconductor wafer that is a substrate. [Means for solving the problem]

[0013] The present invention, which solves the above problems, is as follows.

[0014] [1] A method for manufacturing a semiconductor epitaxial wafer, comprising: an ion implantation step of implanting ions that contribute to gettering into a surface of a semiconductor wafer to form an amorphous region in a surface portion of the semiconductor wafer; a recrystallization heat treatment step of performing a recrystallization heat treatment on the semiconductor wafer after the ion implantation step to restore crystallinity of the amorphous region; and an epitaxial layer formation step of forming a semiconductor epitaxial layer on the surface of the semiconductor wafer after the recrystallization heat treatment step to obtain a semiconductor epitaxial wafer, Prior to the recrystallization heat treatment step, an amorphous region identifying step of calculating a three-dimensional concentration distribution of vacancies and interstitial elements formed in the semiconductor wafer after the ion implantation using a dynamic Monte Carlo simulation based on the ion implantation conditions in the ion implantation step, and identifying the amorphous region in the semiconductor wafer based on the three-dimensional concentration distribution; a recrystallization heat treatment condition calculation step of calculating, using a dynamic Monte Carlo simulation, recrystallization heat treatment conditions under which the amorphous region does not remain on the surface of the semiconductor wafer after the recrystallization heat treatment step; and a recrystallization heat treatment step performed under the recrystallization heat treatment conditions calculated in the recrystallization heat treatment condition calculation step;

[0015] [2] The method for producing a semiconductor epitaxial wafer according to [1], wherein the ions are cluster ions containing at least carbon and hydrogen.

[0016] [3] determining in advance a relationship between the recrystallization heat treatment conditions calculated in the recrystallization heat treatment condition calculation step and the hydrogen concentration distribution in the obtained semiconductor epitaxial wafer; The method for producing a semiconductor epitaxial wafer according to [2] above, wherein the heat treatment step is carried out under recrystallization heat treatment conditions that result in a semiconductor epitaxial wafer having a peak value of hydrogen concentration distribution that satisfies specifications.

[0017] [4] The method for producing a semiconductor epitaxial wafer according to [2] or [3], wherein the heat treatment condition calculation step calculates recrystallization heat treatment conditions such that no amorphous region remains on the surface of the semiconductor wafer and a portion of the amorphous region remains inside the semiconductor wafer.

[0018] [5] The method for producing a semiconductor epitaxial wafer according to any one of [2] to [4], wherein in the heat treatment condition calculation step, a plurality of recrystallization heat treatment conditions are calculated, and a condition with the lowest heat treatment temperature or the shortest heat treatment time is selected from the calculated plurality of recrystallization heat treatment conditions.

[0019] [6] The method for producing a semiconductor epitaxial wafer according to any one of [1] to [5] above, wherein the ion implantation conditions in the ion implantation step are calculated using a dynamic Monte Carlo simulation.

[0020] [7] The method for producing a semiconductor epitaxial wafer according to any one of [1] to [6], wherein the semiconductor wafer is a silicon wafer, and the semiconductor epitaxial layer is a silicon epitaxial layer. [Effects of the Invention]

[0021] According to the present invention, even when ion implantation is performed under conditions that result in the formation of an amorphous region in the surface portion of the semiconductor wafer substrate, a recrystallization heat treatment can be performed according to the ion implantation conditions, thereby producing a semiconductor epitaxial wafer with few epitaxial defects. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are diagrams showing a cross-sectional TEM image and a hydrogen concentration distribution, respectively, of a silicon wafer having an amorphous region formed on its surface. [Figure 2] FIG. 1 is a diagram illustrating an amorphous particle to be recrystallized. [Figure 3] FIG. 1 is a diagram showing the relationship between the ratio of adjacent amorphous particles and the activation energy of solid phase epitaxial growth for amorphous particles to be recrystallized. [Figure 4] 1A and 1B are diagrams showing amorphous and crystalline regions in a silicon wafer immediately after ion implantation and after recrystallization heat treatment, respectively. [Figure 5] 1A is a graph showing the relationship between the heat treatment temperature and the proportion of amorphous regions on the wafer surface, and FIG. 1B is a graph showing the relationship between the heat treatment temperature and the thickness of the amorphous regions. [Figure 6] (A) Cross-sectional TEM images of silicon wafers after recrystallization heat treatment at a heat treatment temperature of 750°C and (B) heat treatment at a heat treatment temperature of 600°C. [Figure 7] 1A and 1B are diagrams showing hydrogen concentration distributions in silicon wafers after recrystallization heat treatment at a heat treatment temperature of 750°C and 600°C, respectively. [Figure 8] FIG. 10 is a diagram showing the number of stacking faults per unit area in silicon epitaxial layers for Comparative Example 1, Comparative Example 2, and an example of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. A method for manufacturing a semiconductor epitaxial wafer according to the present invention includes an ion implantation step of implanting ions that contribute to gettering into a surface of a semiconductor wafer to form an amorphous region in a surface portion of the semiconductor wafer, a recrystallization heat treatment step of performing a recrystallization heat treatment on the semiconductor wafer after the ion implantation step to restore crystallinity of the amorphous region, and an epitaxial layer formation step of forming an epitaxial layer on the surface of the semiconductor wafer after the recrystallization heat treatment step to obtain a semiconductor epitaxial wafer. Here, prior to the recrystallization heat treatment step, a dynamic Monte Carlo simulation is used based on the ion implantation conditions in the ion implantation step to calculate a three-dimensional concentration distribution of vacancies and interstitial elements formed in the semiconductor wafer after the ion implantation, and an amorphous region identification step is performed to identify amorphous regions in the semiconductor wafer based on the three-dimensional concentration distribution; and a recrystallization heat treatment condition calculation step is performed using the dynamic Monte Carlo simulation to calculate recrystallization heat treatment conditions that prevent amorphous regions from remaining on the surface of the semiconductor wafer after the recrystallization heat treatment step, and the recrystallization heat treatment step is performed under the recrystallization heat treatment conditions calculated in the recrystallization heat treatment condition calculation step.

[0024] The present inventors have conducted extensive research into a method for calculating the conditions for a recrystallization heat treatment for recrystallizing an amorphous region according to ion implantation conditions, in order to manufacture a semiconductor epitaxial wafer with few epitaxial defects even when ion implantation is performed under conditions that form an amorphous region in the surface portion of the semiconductor wafer. As a result, the present inventors have concluded that experimentally determining the recrystallization heat treatment conditions for various ion implantation conditions is difficult, requires a lot of effort, and requires a lot of time.

[0025] Therefore, the inventors have investigated a method for calculating the recrystallization heat treatment conditions using a calculation method, and as a result, have found that by using the Kinetic Monte Carlo method (KMC), the recrystallization heat treatment conditions can be calculated more easily and accurately depending on the ion implantation conditions than by experiment, and have completed the present invention. Each step will be described below.

[0026] <Ion implantation process> First, ions that contribute to gettering are implanted into the surface of a semiconductor wafer to form an amorphous region in the surface portion of the semiconductor wafer (ion implantation step).

[0027] By implanting ions that contribute to gettering into the surface of the semiconductor, the ion-implanted regions function as gettering sites for heavy metals that have become mixed into the manufactured semiconductor epitaxial wafer. The ion implantation step is performed under conditions in which an amorphous region is formed in the surface portion of the semiconductor wafer, for example, by increasing the dose of implanted ions so that the manufactured epitaxial wafer has a high gettering ability.

[0028] The semiconductor wafer that serves as the substrate for the semiconductor epitaxial wafer can be, for example, a bulk single crystal wafer made of silicon or a compound semiconductor (GaAs, GaN, SiC) without an epitaxial layer on its surface. Such a semiconductor wafer can be obtained by slicing a single crystal ingot of silicon or the like grown by the Czochralski (CZ) method or the floating zone (FZ) method using a wire saw or the like. Carbon and / or nitrogen may be added to the semiconductor wafer to obtain a higher gettering capability. Furthermore, a predetermined concentration of any dopant may be added to the semiconductor wafer to produce a so-called n + Type or p + type, or n - Type or p - It may also be a mold substrate.

[0029] Alternatively, the semiconductor wafer may be a semiconductor epitaxial wafer in which a semiconductor epitaxial layer is formed on the surface of a bulk semiconductor wafer. For example, an epitaxial silicon wafer in which a silicon epitaxial layer is formed on the surface of a bulk single-crystal silicon wafer can be used as the semiconductor epitaxial wafer. The silicon epitaxial layer can be formed by a CVD method under typical conditions. The thickness of the epitaxial layer is preferably within the range of 0.1 to 10 μm, and more preferably within the range of 0.2 to 5 μm.

[0030] The ions to be implanted can be monomer ions, which are ions of a single atom. Alternatively, the implanted ions can be cluster ions, which are ionized by giving a positive or negative charge to a cluster formed by the aggregation of multiple atoms or molecules (usually about 2 to 2000). From the viewpoint of obtaining a higher gettering ability, it is preferable that the implanted ions be cluster ions. Conventional devices can be used as the device for generating monomer ions or cluster ions.

[0031] The element (ion species) of the ions to be implanted is not particularly limited as long as it is an element that contributes to gettering of heavy metals, and examples of such elements include carbon, boron, phosphorus, arsenic, etc. However, from the viewpoint of obtaining higher gettering ability, it is preferable that the implanted ions contain carbon as a constituent element.

[0032] The implanted ions preferably contain two or more elements including carbon as a constituent element, and more preferably contain one or more dopant elements selected from the group consisting of boron, phosphorus, arsenic, and antimony in addition to carbon. Because the types of metals that can be efficiently gettered vary depending on the type of element in solid solution, dissolving two or more elements can address a wider range of metal contamination. For example, carbon can efficiently getter nickel, and boron can efficiently getter copper and iron.

[0033] Furthermore, the implanted ions may contain hydrogen, oxygen, fluorine, etc. as constituent elements in addition to carbon, and are preferably cluster ions containing at least carbon and hydrogen. When the implanted ions contain hydrogen as a constituent element, hydrogen remains on the surface of the semiconductor wafer that will become the substrate of the semiconductor epitaxial wafer, and during the device formation process, hydrogen can passivate interface state defects in the semiconductor epitaxial layer, thereby improving device characteristics such as reducing leakage current. In this specification, the effect of hydrogen is referred to as the "hydrogen passivation effect."

[0034] When the implanted ions are cluster ions, the compound to be ionized is not particularly limited. As the carbon source compound that can be ionized, ethane, methane, carbon dioxide (CO2), etc. can be used. As the boron source compound that can be ionized, diborane, decaborane (B 10 H 14 For example, when a mixture of dibenzyl and decaborane is used as the source gas, hydrogen compound clusters consisting of carbon, boron, and hydrogen can be generated. 12 ) as a source gas, cluster ions consisting of carbon and hydrogen can be generated. 16 H 10 ), dibenzyl (C 14 H 14 ) Cluster C generated from n H m It is preferable to use a carbon source compound (3≦n≦16, 3≦m≦10) because it is easy to control a small-sized cluster ion beam. C3H5, C5H5, etc. can be suitably used as a carbon source compound for generating such small-sized cluster ions.

[0035] The compound to be ionized is preferably a compound containing both carbon and the above-mentioned dopant element. By implanting such a compound as cluster ions, both carbon and the dopant element can be solid-dissolved in a single implantation.

[0036] When implanting cluster ions, the cluster size can be appropriately set to 2 to 100, preferably 60 or less, and more preferably 50 or less.

[0037] In addition to the above-mentioned ion species, the ion implantation conditions include implantation energy, dose, dose rate (a parameter equivalent to the beam current value), irradiation angle, semiconductor wafer temperature during ion implantation, and protective oxide film thickness. In the present invention, the above seven parameters are appropriately set so that the ion-implanted region has high gettering ability, and ion implantation is performed under conditions that form an amorphous region in the surface portion of the semiconductor wafer.

[0038] The implantation energy is generally set within the range of 5 to 200 keV in both cases of implanting monomer ions and implanting cluster ions.

[0039] The ion dose can be adjusted by controlling the ion implantation time. In the present invention, to form an amorphous region by ion implantation, the dose is set to, for example, 1.0×10 15 ~1.0×10 16 atoms / cm 2 When only carbon and hydrogen ions are implanted, the dose used to calculate the three-dimensional vacancy concentration distribution is the carbon dose. In this way, the doses of elements other than hydrogen are used in the calculation to obtain the vacancy concentration distribution. The reason why the hydrogen dose is not taken into consideration is that in the formation of vacancies, the concentration of vacancies formed by elements other than carbon and hydrogen is two or more orders of magnitude higher than the concentration of vacancies formed by hydrogen, and the doses of elements other than carbon and hydrogen are more dominant in the formation of vacancies than the hydrogen dose.

[0040] The beam current value can be set within a range of, for example, 100 μA to 3000 μA. The dose rate corresponding to this range is 1.0×10 12 ~5.0×10 14The irradiation angle of the ions with respect to the wafer surface can be set within the range of, for example, −7.0 degrees to +7.0 degrees.

[0041] The temperature of the semiconductor wafer during ion implantation can be room temperature. Furthermore, by lowering the temperature of the semiconductor wafer during ion implantation to less than 25°C, more preferably to 0°C or less, a higher gettering ability can be obtained. The temperature of the semiconductor wafer during ion implantation is preferably -200°C or higher, more preferably -120°C or higher.

[0042] A protective oxide film may be formed on the surface of the semiconductor wafer before ion implantation, and its thickness is not particularly limited, but can be 0 to 0.025 μm. If a protective oxide film is not intentionally formed, a value of 0.001 μm can be input as the thickness of the protective oxide film, assuming a natural oxide film, and calculations can be performed using the KMC method.

[0043] When the ion implantation conditions under which an amorphous region is formed are known in advance through experiments or the like, the ion implantation conditions can be performed under those conditions. Alternatively, the ion implantation conditions under which an amorphous region is formed can be calculated using KMC simulation. Specifically, the above seven ion implantation parameters are used as one set, and the three-dimensional concentration distribution of vacancies and interstitial elements is calculated by KMC simulation. Then, based on the calculated three-dimensional concentration distribution, it is determined whether an amorphous region has been formed in the surface portion of the semiconductor wafer, and the conditions under which an amorphous region has been formed can be used as the ion implantation conditions.

[0044] Figure 1(A) shows a cross-sectional TEM image of a silicon wafer immediately after ion implantation. Figure 1(B) shows the hydrogen concentration distribution in a silicon wafer with an amorphous region formed on the surface. Note that the ion implantation was performed using C3H5 cluster ions at a dose of 3.0 × 10 15 Carbon Atoms / cm 2The implantation was performed with an acceleration energy of 80 keV and a wafer temperature of 25°C (room temperature). Figure 1(A) shows that an amorphous region is formed at a depth of approximately 20 to 80 nm inside the silicon wafer. Furthermore, the contrast of the TEM image suggests that amorphous and crystalline regions are mixed on the wafer surface. Furthermore, Figure 1(B) shows that immediately after ion implantation, hydrogen is distributed at a high concentration from the surface to a depth of approximately 100 nm.

[0045] <Recrystallization heat treatment process> Next, after the ion implantation step, the semiconductor wafer is subjected to a recrystallization heat treatment to restore the crystallinity of the amorphous region (recrystallization heat treatment step). As described above, if a semiconductor epitaxial layer is formed directly on the surface of a semiconductor wafer in which an amorphous region has been formed on the surface by ion implantation, a large number of epitaxial defects will be formed in the formed semiconductor epitaxial layer. Therefore, in the present invention, prior to the recrystallization heat treatment step, a KMC method simulation is used to calculate recrystallization heat treatment conditions that will result in a semiconductor epitaxial wafer with a small number of epitaxial defects.

[0046] Specifically, the method performs an amorphous region identification step in which a KMC simulation is used to calculate the three-dimensional concentration distribution of vacancies and interstitial elements formed in the semiconductor wafer after ion implantation based on the ion implantation conditions in the ion implantation step, and identifies amorphous regions in the semiconductor wafer based on the three-dimensional concentration distribution, and a recrystallization heat treatment condition calculation step in which a KMC simulation is used to calculate recrystallization heat treatment conditions that will not leave amorphous regions on the surface of the semiconductor wafer after the recrystallization heat treatment step.These two steps will be described below.

[0047] <<Amorphous region identification process>> First, using a KMC simulation, the three-dimensional concentration distribution of vacancies and interstitial elements formed in a semiconductor wafer after ion implantation is calculated, and amorphous regions in the semiconductor wafer are identified based on the three-dimensional concentration distribution (amorphous region identifying step).

[0048] The KMC method is a method for calculating the time evolution of many-body systems based on statistical mechanics and probability theory. It sets the frequency (transition probability) of events that occur in the many-body system, and uses random numbers to calculate the time evolution according to that frequency. The KMC method is used to analyze the growth process of semiconductor epitaxial layers, the thermal diffusion of atoms on the surface of semiconductor wafers, and the adsorption process of molecules on the surface of semiconductor wafers.

[0049] In the present invention, the three-dimensional concentration distribution of vacancies and interstitial elements in a semiconductor wafer after ion implantation is calculated using KMC simulation, and amorphous regions in the semiconductor wafer are identified based on the obtained three-dimensional concentration distribution. The calculation of the three-dimensional concentration distribution of vacancies and interstitial elements can be performed using, for example, KMC simulation of ion implantation using a model described in M. Jaraiz, "Atomic Scale Simulations of Arsenic Ion Implantation and Annealing in Silicon," Mater. Res. Soc. Symp. Proc. 54, 532 (1998).

[0050] Specifically, first, a calculation model is set up. The size of the calculation model can be set appropriately based on the reproducibility of experimental results, calculation resources, etc. For example, a calculation model with a width of 80 nm, a depth of 80 nm, and a height of 800 nm can be set up.

[0051] Ion implantation using virtual particles is performed on the surface of the calculation model set up as described above under predetermined ion implantation conditions, and the three-dimensional concentration distribution of vacancies and interstitial elements is calculated. In this specification, the total concentration of vacancies and interstitial elements generated by ion implantation is calculated as 1.5 × 1022 atoms / cm 3 The above region is called the "amorphous region", and the total concentration of vacancies and interstitial elements is 1.5 × 10 22 atoms / cm 3 Regions below this are defined as "crystalline regions." In amorphous regions, the concepts of vacancies and interstitial elements disappear, and the amorphous region is treated as an aggregate of amorphous defects (particles).

[0052] As mentioned above, in the three-dimensional concentration distribution of vacancies and interstitial elements obtained by the KMC method, the total concentration of vacancies and interstitial elements was 1.5 × 10 22 atoms / cm 3 The above region is called the "amorphous region", 1.5 × 10 22 atoms / cm 3 Regions less than this are identified as "crystalline regions."

[0053] <<Recrystallization heat treatment condition calculation process>> Next, using a KMC simulation, recrystallization heat treatment conditions that prevent amorphous regions from remaining on the surface of the semiconductor wafer after the recrystallization heat treatment process are calculated (recrystallization heat treatment condition calculation process). Specifically, using the KMC method, a simulation is performed in which a recrystallization heat treatment is performed under predetermined recrystallization heat treatment conditions for an ion-implanted calculation model, and the amorphous region is recrystallized. In this simulation, solid-phase epitaxial growth from the interface between the amorphous region and the crystalline region is calculated. The heat treatment conditions can include the heat treatment temperature and the heat treatment time.

[0054] The rate V of solid phase epitaxial growth can be expressed as the following formula (1).

number

[0055] k B , T, E a are the Boltzmann constant, the heat treatment temperature, and the activation energy of solid phase epitaxial growth, respectively. Previous research has shown that amorphous particles recrystallize more easily when there are fewer amorphous particles adjacent to them. Therefore, the activation energy E a is set to a different value depending on the ratio of adjacent amorphous particles, as shown in Figure 3. The activation energy value for the ratio of adjacent amorphous particles can be determined by analyzing cross-sectional TEM images, planar TEM images, and crystallinity evaluation results by X-ray photoelectron spectroscopy after recrystallization heat treatment in previous experiments.

[0056] Figure 4 shows the amorphous and crystalline regions in a silicon wafer, determined using KMC simulations. (A) shows the region immediately after ion implantation, and (B) shows the region after recrystallization heat treatment. In Figures 4(A) and 4(B), the boundary between the amorphous and crystalline regions is indicated by a solid line. Figure 4(A) shows the region after ion implantation using 3 × 10 C3H5 cluster ions. 15 Carbon atoms / cm 2 The figure (B) shows the results obtained when implanting with a dose of 600°C and a recrystallization heat treatment time of 4 seconds.

[0057] As shown in Figure 4(A), immediately after ion implantation, amorphous regions are present discretely on the surface of the silicon wafer, and amorphous and crystalline regions are mixed. It can also be seen that amorphous regions are formed inside (surface) the silicon wafer. In contrast, as shown in Figure 4(B), after recrystallization heat treatment, the amorphous regions that existed before the heat treatment have completely recrystallized, and the entire surface of the silicon wafer has become crystalline. It can also be seen that the amorphous regions have recrystallized from both the surface and interior of the silicon wafer, reducing their thickness.

[0058] As will be described later in the Examples, an epitaxial wafer with few epitaxial defects can be obtained by forming a semiconductor epitaxial layer on the surface of a semiconductor wafer in which the amorphous region on the surface has been completely recrystallized, as shown in Figure 4(B). Therefore, according to the present invention, the recrystallization heat treatment conditions under which the amorphous region on the semiconductor surface is completely recrystallized after the recrystallization heat treatment are calculated by the KMC method.

[0059] Figure 5(A) shows the relationship between the heat treatment temperature in the recrystallization heat treatment and the proportion of amorphous regions on the surface of the silicon wafer, and Figure 5(B) shows the relationship between the heat treatment temperature and the thickness of the amorphous regions. Note that Figures 5(A) and (B) were obtained by fixing the heat treatment time at 4 seconds and varying the heat treatment temperature.

[0060] Figure 5(A) shows that the amorphous region on the surface of the silicon wafer is completely recrystallized when the heat treatment temperature is 600°C or higher. Figure 5(B) also shows that the thickness of the amorphous region inside the silicon wafer decreases when the heat treatment temperature is 580°C or higher, and becomes zero when the heat treatment temperature is 650°C or higher.

[0061] Thus, when the heat treatment time is 4 seconds, the amorphous region on the surface of the silicon wafer can be completely recrystallized into a crystalline region by setting the heat treatment temperature to 600°C or higher. Furthermore, by setting the heat treatment temperature to 650°C or higher, the amorphous region inside the semiconductor wafer formed by ion implantation can also be completely recrystallized into a crystalline region. Therefore, a heat treatment temperature of 600°C or higher and a heat treatment time of 4 seconds can be set as the recrystallization heat treatment conditions.

[0062] Figure 6 shows cross-sectional TEM images of silicon wafers after recrystallization heat treatment, with (A) being for a heat treatment temperature of 750°C and (B) being for a heat treatment temperature of 600°C. Figure 6(A) shows that when the heat treatment temperature is 750°C, the amorphous regions on the surface of the silicon wafer are completely recrystallized to become crystalline regions, and the amorphous regions inside the silicon wafer are also completely recrystallized.

[0063] In contrast, Figure 6(B) shows that when the heat treatment temperature is 600°C, the amorphous region on the surface of the silicon wafer is completely recrystallized to become a crystalline region, but amorphous regions remain inside the silicon wafer. However, it can be seen that the thickness of the amorphous region is smaller than that immediately after ion implantation shown in Figure 1.

[0064] In this way, the cross-sectional TEM images shown in FIGS. 6(A) and (B) reflect the results of the KMC method simulation shown in FIGS. 5(A) and (B).

[0065] Figure 7 shows the relationship between depth from the wafer surface and hydrogen concentration, with (A) for a heat treatment temperature of 750°C and (B) for a heat treatment temperature of 600°C. Figure 7(A) shows that when the heat treatment temperature is 750°C, the hydrogen concentration in the ion-implanted region is low, and the hydrogen has diffused. On the other hand, Figure 7(B) shows that when the heat treatment temperature is 600°C, the hydrogen concentration in the hydrogen-implanted region is high, and much hydrogen remains in the amorphous region.

[0066] As is clear from Fig. 7, the lower the heat treatment temperature of the recrystallization heat treatment, the more hydrogen remains in the surface portion of the semiconductor wafer. Therefore, in order to obtain a semiconductor epitaxial wafer having the desired hydrogen passivation effect, it is preferable to determine in advance the relationship between the recrystallization heat treatment conditions calculated in the recrystallization heat treatment condition calculation step and the hydrogen concentration distribution in the obtained semiconductor epitaxial wafer, and to perform the recrystallization heat treatment step under recrystallization heat treatment conditions that will obtain a semiconductor epitaxial wafer whose peak value of the hydrogen concentration distribution satisfies the specifications.

[0067] Furthermore, in the recrystallization heat treatment condition calculation step, it is preferable to calculate recrystallization heat treatment conditions such that no amorphous region remains on the surface of the semiconductor wafer and a portion of the amorphous region remains inside the semiconductor wafer. By leaving a portion of the amorphous region formed by ion implantation inside the semiconductor wafer, hydrogen can be captured and left in the amorphous region, thereby improving the hydrogen passivation effect.

[0068] Furthermore, in the recrystallization heat treatment condition calculation step, it is preferable to calculate a plurality of recrystallization heat treatment conditions and select the condition with the lowest heat treatment temperature or the shortest heat treatment time from the calculated plurality of recrystallization heat treatment conditions, thereby suppressing the thermal diffusion of hydrogen remaining in the amorphous region and improving the hydrogen passivation effect.

[0069] The recrystallization heat treatment step can be carried out using a rapid temperature increase / decrease heat treatment device such as RTA (Rapid Thermal Annealing) or RTO (Rapid Thermal Oxidation).

[0070] <Epitaxial layer formation process> Subsequently, after the recrystallization heat treatment step, a semiconductor epitaxial layer is formed on the surface of the semiconductor wafer to obtain a semiconductor epitaxial wafer (epitaxial layer forming step).

[0071] Examples of semiconductor epitaxial layers formed on semiconductor wafers include silicon epitaxial layers, which can be formed under typical conditions. For example, hydrogen is used as a carrier gas, and source gases such as dichlorosilane and trichlorosilane are introduced into a chamber. While the growth temperature varies depending on the source gas used, epitaxial growth can be performed on the semiconductor wafer by CVD at temperatures generally ranging from 1000 to 1200°C. The thickness of the semiconductor epitaxial layer is preferably within the range of 1 to 15 μm. By making the thickness of the semiconductor epitaxial layer 1 μm or greater, changes in the resistivity of the semiconductor epitaxial layer due to out-diffusion of dopants from the semiconductor wafer can be suppressed. Furthermore, by making the thickness of the semiconductor epitaxial layer 15 μm or less, effects on the spectral sensitivity characteristics of the solid-state imaging device can be suppressed.

[0072] The epitaxial layer formation step can be carried out using a commercially available single-wafer epitaxial growth apparatus.

[0073] In this manner, the semiconductor epitaxial wafer according to the present invention can be manufactured. [Example]

[0074] Examples of the present invention will be described below, but the present invention is not limited to these examples.

[0075] (Example of invention) An epitaxial silicon wafer was manufactured according to the semiconductor epitaxial wafer manufacturing method of the present invention. First, a silicon wafer (diameter: 300 mm, thickness: 775 μm, dopant: boron) was prepared as a substrate. Next, a cluster ion generator (manufactured by Nissin Ion Equipment Co., Ltd., model number: CLARIS) was used to generate C3H5 clusters from cyclohexane, and a carbon dose of 3 × 10 15 Carbon atoms / cm 2The ions were implanted into the surface of the silicon wafer to form an amorphous region on the surface of the silicon wafer (ion implantation process). The ion implantation energy was 80 keV, the beam current was 850 μA, the irradiation angle was 0 degrees, the wafer temperature during irradiation was 25°C, and the thickness of the protective oxide film (native oxide film) was 1.0 nm. The above ion implantation conditions are known to form an amorphous region on the surface of the wafer.

[0076] Next, prior to the recrystallization heat treatment process, the three-dimensional concentration distribution of vacancies and interstitial silicon was determined based on the ion implantation conditions in the ion implantation process using the TCAD simulator Sentaurus Process (manufactured by Nihon Synopsys, LLC), which is capable of calculating KMC method simulations, and the amorphous regions were identified (amorphous region identification process).

[0077] Next, using KMC simulation, we calculated recrystallization heat treatment conditions that would not leave an amorphous region on the surface of the semiconductor wafer after the recrystallization heat treatment process (recrystallization heat treatment condition calculation process). Based on the results, we set the recrystallization heat treatment temperature to 600°C and the heat treatment time to 4 seconds. Then, we performed recrystallization heat treatment at 600°C for 4 seconds on the silicon wafer after ion implantation (recrystallization heat treatment process).

[0078] Next, the silicon wafer after ion implantation was transferred into a rapid thermal annealing (RTA) device and subjected to a recrystallization heat treatment at 600° C. for 4 seconds (recrystallization heat treatment step).

[0079] The silicon wafer was then transferred into a single-wafer epitaxial growth apparatus (manufactured by Applied Materials, Inc.) and subjected to a hydrogen bake treatment at 1120°C for 30 seconds. After that, a silicon epitaxial layer (thickness: 5 μm) was epitaxially grown on the surface of the silicon wafer by CVD at 1150°C using hydrogen as the carrier gas and trichlorosilane as the source gas, yielding one epitaxial silicon wafer.

[0080] (Comparative Example 1) An epitaxial silicon wafer was produced in the same manner as in the invention example, except that the recrystallization heat treatment step was not performed. All other conditions were the same as in the invention example.

[0081] (Comparative Example 2) An epitaxial silicon wafer was manufactured in the same manner as in the invention example, except that the heat treatment temperature in the recrystallization heat treatment step was set to 750° C. All other conditions were the same as in the invention example.

[0082] FIG. 8 shows the number of stacking faults in the silicon epitaxial layer for Comparative Example 1, Comparative Example 2, and the invention example. The number of stacking faults is calculated per unit area (1 cm) in one obtained epitaxial silicon wafer. 2 ) (i.e., stacking fault density), and is normalized with the number in Comparative Example 1 being 1. From FIG. 8, it can be seen that a large number of stacking faults were formed in Comparative Example 1, which did not undergo recrystallization heat treatment. In contrast, in Comparative Example 2, in which the recrystallization heat treatment temperature was 750°C, the number of epitaxial defects was almost zero, and also in the inventive example, in which the recrystallization heat treatment temperature was 600°C, the number of epitaxial defects was almost zero.

[0083] The hydrogen concentration distributions shown in Figures 7(A) and 7(B) correspond to Comparative Example 1 and the Example of the Invention, respectively, and it can be seen that a large amount of hydrogen remains on the surface of the silicon wafer in the Example of the Invention. Therefore, the epitaxial silicon wafer of the Example of the Invention has a higher hydrogen passivation effect than that of Comparative Example 1. [Industrial Applicability]

[0084] According to the present invention, even when ion implantation is performed under conditions that result in the formation of an amorphous region in the surface portion of a semiconductor wafer serving as a substrate, a recrystallization heat treatment can be performed in accordance with the ion implantation conditions to produce a semiconductor epitaxial wafer with few epitaxial defects, which is useful in the semiconductor wafer manufacturing industry.

Claims

1. A method for manufacturing a semiconductor epitaxial wafer, comprising: an ion implantation step of implanting ions that contribute to gettering into a surface of a semiconductor wafer to form an amorphous region in a surface portion of the semiconductor wafer; a recrystallization heat treatment step of performing a recrystallization heat treatment on the semiconductor wafer after the ion implantation step to recover crystallinity of the amorphous region; and an epitaxial layer formation step of forming a semiconductor epitaxial layer on the surface of the semiconductor wafer after the recrystallization heat treatment step to obtain a semiconductor epitaxial wafer, Prior to the recrystallization heat treatment step, an amorphous region identifying step of calculating a three-dimensional concentration distribution of vacancies and interstitial elements formed in the semiconductor wafer after the ion implantation using a dynamic Monte Carlo simulation based on the ion implantation conditions in the ion implantation step, and identifying the amorphous region in the semiconductor wafer based on the three-dimensional concentration distribution; a recrystallization heat treatment condition calculation step of calculating, using the dynamic Monte Carlo simulation, recrystallization heat treatment conditions under which the amorphous region does not remain on the surface of the semiconductor wafer after the recrystallization heat treatment step; and a recrystallization heat treatment step for performing the recrystallization heat treatment under the recrystallization heat treatment conditions calculated in the recrystallization heat treatment condition calculation step;

2. 2. The method for producing a semiconductor epitaxial wafer according to claim 1, wherein the ions are cluster ions containing at least carbon and hydrogen.

3. a relationship between the recrystallization heat treatment conditions calculated in the recrystallization heat treatment condition calculation step and a hydrogen concentration distribution in the obtained semiconductor epitaxial wafer is obtained; 3. The method for producing a semiconductor epitaxial wafer according to claim 2, wherein the heat treatment step is carried out under recrystallization heat treatment conditions that give the semiconductor epitaxial wafer a hydrogen passivation effect with a desired peak value of the hydrogen concentration distribution.

4. 4. The method for producing a semiconductor epitaxial wafer according to claim 2, wherein the heat treatment condition calculation step calculates recrystallization heat treatment conditions such that no amorphous region remains on the surface of the semiconductor wafer and a portion of the amorphous region remains inside the semiconductor wafer.

5. 4. The method for producing a semiconductor epitaxial wafer according to claim 2 or 3, wherein, in the heat treatment condition calculation step, a plurality of the recrystallization heat treatment conditions are calculated, and a condition with the lowest heat treatment temperature or the shortest heat treatment time is selected from the calculated plurality of the recrystallization heat treatment conditions.

6. 3. The method for producing a semiconductor epitaxial wafer according to claim 1, wherein the ion implantation conditions in the ion implantation step are calculated using a dynamic Monte Carlo simulation.

7. 3. The method for producing a semiconductor epitaxial wafer according to claim 1, wherein the semiconductor wafer is a silicon wafer, and the semiconductor epitaxial layer is a silicon epitaxial layer.

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