High-resolution FET VDS zero-volt crossing timing detection method

Abstract

To provide a control module for detecting a zero-volt cross in a field-effect transistor, and a method for controlling the transistor.SOLUTION: A comparator (200) to use in a zero-volt switching detection circuit compares the drain source voltage (Vds) of a transistor with a threshold voltage (VTH-ds). A gate voltage signal (Vgs) of the transistor is supplied to a clock input of the comparator (200) and the gate voltage signal (Vgs) is used to latch the result of the comparison with the output of the comparator (200). On the basis of the value of the output of the comparator (200), a control function is executed on the transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] In a zero-volt switching (ZVS) scheme, a field-effect transistor (FET) carrying power to a load is switched on or off when the drain-source voltage is at or near zero volts. ZVS uses pulse-width modulation (PWM), but with an additional, separate phase to the PWM timing to enable ZVS operation. Zero-volt switching allows the voltage regulator to engage in "soft switching," thus avoiding the switching losses typically incurred during conventional PWM operation and timing. [Background technology]

[0002] ZVS is useful for a variety of power conversion systems that require high switching frequencies at higher input voltages and voltage drops. Wireless power transfer and charging systems are examples of technologies that can greatly benefit from zero-voltage switching. The Alliance for Wireless Power (A4WP) is an industry standards group that uses the principles of magnetic resonance to develop wireless energy transfer systems over long distances. A4WP wireless power transfer uses a directed, controlled magnetic field to replace traditional power cords. To do this, a transmitter has one or more primary windings to induce a uniform magnetic field on its surface. A receiver within the magnetic field has a secondary winding that captures the magnetic energy and converts it into electrical energy. In A4WP wireless power transfer, the switching frequency is a multiple of 6.78 MHz. Accurate zero-voltage crossing (ZVC) detection is the starting point for high-efficiency ZVS control. With such high-frequency switching, zero-voltage switching timing accuracy must be on the order of nanoseconds. Conventional zero-voltage crossing detection methods use very fast comparators and gate drivers with very little delay. However, typical comparator delays already exceed the nanosecond range. Summary of the Invention

[0003] In a described example of a control module for controlling a field effect transistor, the control module includes a comparator and control circuitry. The comparator receives the drain-source voltage of the transistor and compares it to a threshold voltage. The comparator has a clock input that receives the gate voltage of the transistor so that the received gate voltage is used to latch the result of the comparison with the output of the comparator. The control circuitry receives the comparator output and performs a control function for the transistor based on the value of the comparator output.

[0004] In another described example of a control module for controlling a field effect transistor, the control module includes a drain-source voltage comparator, a gate-source voltage comparator, and at least one latch element. The drain-source voltage comparator is configured to calculate the drain-source voltage (V ds ) and transfer it to V ds Compare with the threshold. V ds The comparator is V ds V crossing the threshold ds V indicates ds The gate-source voltage comparator has at least one output configured to provide an edge transition signal. The gate-source voltage comparator is configured to compare the gate-source voltage (V gs ) and transfer it to V gs Compare with the threshold. V gs The comparator is V gs V crossing the threshold gs V indicates gs and at least one output configured to provide an edge transition signal. The at least one latch element has a data input, a clock input, and an output. The data input is connected to a V ds Comparator to V ds operatively coupled to receive an edge transition signal, the clock input being V gs Edge transition signal is V ds V serves to latch edge transition signals to the latch output. gs Comparator to V gsThe edge transition signal is operably coupled to receive the edge transition signal.

[0005] In a method for controlling a field effect transistor, a comparator compares the drain-source voltage of the transistor with a threshold voltage, a gate voltage signal of the transistor is supplied to a clock input of the comparator such that the gate voltage signal is used to latch the result of the comparison with the output of the comparator, and a control function for the transistor is performed based on the value of the comparator output. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic block diagram of an exemplary wireless power transfer system.

[0007] [Figure 2] FIG. 2 is a functional block diagram of a comparator for use in a zero volt switching detection circuit in accordance with an example embodiment.

[0008] [Figure 3] FIG. 10 is a timing diagram illustrating the timing relationship between the Vds signal, the Vgs signal, the ON_LATE flag, and the OFF_LATE flag in accordance with an example embodiment.

[0009] [Figure 4] 3 is a functional block diagram of a comparator system that may implement a comparator, such as the comparator described in connection with FIG. 2, in accordance with an example embodiment.

[0010] [Figure 5] 5 is a timing diagram illustrating timing relationships for various signals in a comparator system such as that shown in FIG. 4 according to an exemplary timing and control scheme.

[0011] [Figure 6] 1 is a flowchart of a method for controlling a field effect transistor according to an example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Exemplary aspects are directed to techniques for achieving accurate and efficient zero-volt crossing detection in high-frequency zero-volt switching systems. For illustrative purposes, the zero-volt crossing detection method is described herein in the context of an A4WP wireless power transfer and charging system. However, aspects of the exemplary embodiments are applicable to virtually any system that uses zero-volt switching.

[0013] FIG. 1 is a schematic block diagram of an exemplary wireless power transfer system 100. A primary side 105 of the wireless power transfer system 100 includes a primary side control module 110, illustratively including an integrated circuit controller. The primary side control module 110 generates and provides control signals to external switches Q1, Q2, Q3, and Q4. In the exemplary embodiment shown in FIG. 1, switches Q1, Q2, Q3, and Q4 are metal-oxide semiconductor field-effect transistors (MOSFETs), and the control signals provided by the primary side control module 110 are gate driver signals. The junction of switches Q1 and Q3 defines a tank node N1, and the junction of switches Q2 and Q4 defines a tank node N2. Specifically, in the exemplary embodiment of FIG. 1, tank node N1 is defined by the junction of the source of transistor Q1 and the drain of transistor Q3. Tank node N2 is defined by the junction of the source of transistor Q2 and the drain of transistor Q4. The drains of transistors Q1 and Q2 are connected to an input voltage V in The sources of transistors Q3 and Q4 are coupled to ground. Tank nodes N1 and N2 are connected to the primary side capacitor C primary and the primary inductor L primary The tank node N1 is coupled to a primary-side LC tank circuit including a primary-side capacitor C primary is coupled to the first terminal of the primary inductor L primary is the capacitor C primary and the tank node N2.

[0014] Primary inductor L primary is the current across the air gap M to the secondary inductor L secondary On the secondary side 115 of the wireless power transmission system 100, a secondary-side inductor L secondary and secondary side capacitor C secondary An LC tank circuit including a secondary inductor L is coupled to tank nodes N3 and N4. Tank node N3 is coupled to secondary inductor L secondary Connected to the first terminal of the secondary capacitor C secondary is the inductor L secondary and a tank node N4. A secondary side control module 120, which in the exemplary embodiment comprises an integrated circuit controller, generates and provides control signals to external switches Q5, Q6, Q7, and Q8 arranged in an H-bridge configuration. In the exemplary embodiment, the primary side control module 110 and the secondary side control module 120 are part of a single integrated circuit. In the exemplary embodiment shown in FIG. 1, switches Q5, Q6, Q7, and Q8 are MOSFETs, and the control signals provided by the secondary side control module 120 are gate driver signals. The junction of switches Q5 and Q7 defines a tank node N3, and the junction of switches Q6 and Q8 defines a tank node N4. Specifically, in the exemplary embodiment of FIG. 1, tank node N3 is defined by the junction of the source of transistor Q5 and the drain of transistor Q7. Tank node N4 is defined by the junction of the source of transistor Q6 and the drain of transistor Q8. The sources of transistors Q7 and Q8 are coupled to ground. The drains of transistors Q5 and Q6 are connected to the output voltage V BRIDGE_OUT Define an output node NO that provides:

[0015] In an exemplary embodiment, an integrated phase-locked loop (PLL) (not shown) locks to an external high-frequency crystal oscillator (also not shown). The phase-locked loop is illustratively integrated on the same integrated circuit as the primary side control module 110 and the secondary side control module 120. The primary side control module 110 includes a digital pulse-width modulation (PWM) generation state machine that works in conjunction with the phase-locked loop to generate drive waveforms that drive four gate driver circuits in the primary side control module 110. These four gate driver circuits drive the gates of primary side transistors Q1, Q2, Q3, and Q4 and a series LC resonator tank to transfer power across the air gap M. On the secondary side 115, a resonant capacitor C secondary The recovered signal captured across the secondary side is sliced. The secondary side control module 120 contains a PWM generation state machine that attempts to drive the gates of transistors Q5, Q6, Q7, and Q8 of the secondary side H-bridge for synchronous rectification. To maximize the efficiency of the primary side 105 and secondary side 115, it is important to optimize the switching times for transistors Q1 through Q8. Zero volt switching (ZVS) is an effective means of optimizing these switching times. Accurate zero volt crossing (ZVC) detection is important to maximize the efficiency of the ZVS scheme.

[0016] The zero-volt switching event determines the turn-on event for each of the primary-side transistors Q1-Q4. The turn-off edges are conveniently synchronized to a reference clock that sets the timing reference for the entire system. On the secondary side 115, the timing reference is the primary-side inductor L primary Current waveform I through P The secondary side control module 120 performs synchronous rectification that emulates a full-bridge diode rectifier. Zero volt switching conditions are detected for both the turn-on and turn-off edges of the secondary side transistors Q5-Q8.

[0017] To illustrate aspects of switching control according to example embodiments, the operation and control of transistor Q1 will now be described. This description of transistor Q1 also pertains to the other primary-side transistors Q2-Q4, and in many respects, secondary-side transistors Q5-Q8. The drain-source voltage signal V of transistor Q1 ds is complex due to ringing generated by the transistor bond wires. primary (dI P / dt) is the additional voltage I ds R ds The ZVS detection circuit in the primary side control module 110 detects the V ds is a predetermined threshold V TH-ds In an exemplary embodiment, the ZVS detection circuit detects whether the voltage is above or below V ds a predetermined threshold V TH-ds FIG. 2 is a functional block diagram of a comparator 200 for use in such a ZVS detection circuit according to an example embodiment. In an example embodiment, a comparator such as comparator 200 of FIG. 2 corresponds to each of the external transistors Q1-Q8. Ideally, a comparator such as comparator 200 of FIG. 2 corresponds to each of the external transistors Q1-Q8. TH-ds is set to 0V. However, in an exemplary embodiment, V TH-ds is set to a value that is still reasonably close to ZVS conditions but is relatively immune to parasitic effects, such as 1 V. The gate-source voltage V gs is used as a clock to latch the comparator output. Comparator 200 has two inputs, referred to herein as ON_LATE and OFF_LATE. The latched outputs, ON_LATE and OFF_LATE, indicate whether the switching edge is early or late relative to the ZVS condition. The primary side control module 105 uses the ON_LATE and OFF_LATE flags to adjust the timing control of the gate driver signals provided to transistor Q1 to determine the transistor switching times and V dsThe ON_LATE and OFF_LATE signals are averaged over multiple (e.g., eight) PWM cycles to obtain average values ​​over a longer period of time, thereby reducing noise sensitivity. Again, while this switching control scheme has been described with respect to transistor Q1, it should be noted that the same or similar principles apply to the other primary-side transistors Q2-Q4 and secondary-side transistors Q5-Q8.

[0018] V gs is the gate-source threshold voltage V TH-gs As shown by the intersection with gs When the signal transitions from low to high, the drain-source threshold voltage V TH-ds V with ds The result of the signal comparison is latched at the ON_LATE output of the comparator 200. The drain-source voltage V ds But V gs If the signal is less than the threshold voltage when going high (thereby latching the comparator output), the ON_LATE output signal becomes (or remains) 1 (logic high) and V ds This indicates that the gate driver signal went high (turning on transistor Q1) after the signal had fallen to 0. Therefore, the gate driver signal turned on transistor Q1 with a delay. Meanwhile, V gs When the signal goes high, the drain-source voltage V ds is still greater than the threshold voltage, the ON_LATE output signal becomes (or remains) at 0 (logic low), and V ds Indicates that the gate driver signal went high before the signal dropped to 0. V ds Note that the signal may change faster or slower than the gate driver signal switches the transistor on or off due to the effect of the current being driven through the LC tank circuit by the associated load. ds is V gsgoes low before going high. For maximum switching efficiency, the gate driver signal (and therefore V gs signal) goes high, and V ds It is desirable for the signals to go low as simultaneously as possible.

[0019] V gs When the signal transitions from high to low, the threshold voltage V TH-ds V against ds The result of the signal comparison is latched at the OFF_LATE output of the comparator 200. The drain-source voltage V ds But it starts to rise, and V gs Immediately after the signal goes low (thereby latching the signal), the circuit V TH-ds When V crosses V, the OFF_LATE output goes to (or remains at) 1 (logic high), and the gate driver signal keeps transistor Q1 on and V ds otherwise, the LC tank circuit will ds would have driven V high (to its off-state voltage level). Thus, the gate driver signal delayed turning off transistor Q1. Meanwhile, V gs When the signal goes low, the drain-source voltage V ds If V does not rise immediately, the OFF_LATE output signal goes to 0 (logic low) and V ds This indicates that the gate driver signal went low before the signal dropped to 0. For maximum switching efficiency, the gate driver signal (and therefore V gs signal) goes low, and V ds It is desirable for the signals to go high as simultaneously as possible.

[0020] Figure 3 shows the V ds signal, V gs 1 is a timing diagram illustrating an example timing relationship between signals, an ON_LATE flag, and an OFF_LATE flag. ds V for latching the comparator gsFor purposes of illustrating signal utilization, the timing diagram of FIG. 3 represents an ideal system without considering various system delays present in real-world systems. Such delays are explained and taken into account hereinafter. As noted above, the gate-source voltage V gs is used to latch the output of comparator 200. gs When the signal goes high, the drain-source voltage V ds The threshold voltage V TH-ds The result of the comparison against V is latched in ON_LATE. At time t1 in Figure 3, gs The signal goes high due to the gate driver signal provided by the primary side control module 110 (or by the secondary side control module for secondary side transistors Q5-Q8). As shown in FIG. 3, at time t1, the drain-source voltage V ds is the comparator threshold voltage V TH-ds 3, which is shown to be about 1 V. ds is V TH-ds is smaller, the ON_LATE flag goes high and the gate driver signal is delayed, i.e., V ds This indicates that the transistor was turned on after the signal had already gone low.

[0021] As mentioned above, V gs When the signal goes low, the drain-source voltage V ds The threshold voltage V TH-ds At time t2 in FIG. 3, based on the gate driver signals provided by the primary side control module 110 (or by the secondary side control module for secondary side transistors Q5-Q8), V gs The signal goes low. As shown in Figure 3, the drain-source voltage V ds begins to rise at time t2, and V gs Immediately after the signal goes low, the threshold voltage V TH-ds Therefore, the OFF_LATE flag goes high, indicating that the gate driver signal has turned off the transistor late.

[0022] At time t3 in FIG. gs The signal goes high again. As shown in FIG. 3, at time t3, the drain-source voltage V ds is still the threshold voltage V TH Since it is larger, the ON_LATE flag goes low and the gate driver signal is turned on early, i.e., V ds At time t4 in Figure 3, V gs The signal goes low again. At time t4, the drain-source voltage V ds is still the threshold voltage V TH is smaller, so the OFF_LATE flag goes low and the gate driver signal is turned on early, i.e., V ds Before the signal goes high, it indicates that the transistor has been turned off.

[0023] In an exemplary embodiment, a PWM state machine in the primary side control module 110 controls the V corresponding to each of the primary side transistors Q1-Q4 to regulate the control bits to the phase locked loop. ds Similarly, the PWM state machine in the secondary side control module 120 uses the latched outputs from the comparators to generate the V corresponding to each of the secondary side transistors Q5-Q8. ds The latched outputs from the comparators are used to regulate the control bits to the phase-locked loop. The PWM state machine uses control algorithms that attempt to obtain locked positions for the rising and falling edges of the gate driver waveforms. These algorithms illustratively use initial pulse width values ​​for the gate driver waveforms. For example, in an exemplary embodiment, hard-coded values ​​for the initial pulse widths at the start of the search algorithm are set to 40% DC on the primary side and 10% DC on the secondary side. During operation, V ds Signal and V gsTo maximize signal alignment, the pulse width is dynamically adjusted based on the values ​​of the ON_LATE and OFF_LATE flags (illustratively averaged over multiple PWM cycles).

[0024] In an exemplary embodiment, the primary-side PWM state machine and the secondary-side PWM state machine each first attempt to lock the rising edge of the gate driver waveform to the ON_LATE flag. This is done by continuously shifting the position of the rising edge of the gate driver signal until the ON_LATE flag changes state. In an exemplary embodiment, the time period between position changes is programmable via non-volatile memory (NVM) and can be adjusted based on the system's bandwidth requirements. The PWM state machine then repeats the process for the falling edge. The PWM state machine performs this process for all four external transistors (transistors Q1-Q4 for the primary-side PWM state machine and transistors Q5-Q8 for the secondary-side PWM state machine). When both the rising and falling edges for all four external transistors reach their optimal positions for zero-volt switching, the state machine toggles the edges around those positions.

[0025] 4 is a functional block diagram of a comparator system 400 that implements a comparator such as comparator 200 described in connection with FIGS. 2 and 3 according to an example embodiment. Comparator system 400 implements the timing control scheme described in connection with FIGS. 2 and 3, thereby controlling V gs The signal is used as a clock signal to control the latching of the output of comparator 200 (or the output of comparator system 400). Also, comparator system 400 constitutes part of the timing delays mentioned above in a practical system. As shown in FIG. 4, comparator system 400 actually consists of two comparators, V ds Comparator 410 and V gs A comparator 420 is used. ds Comparator 410 detects the drain-source voltage V dsand set it to a predetermined threshold V TH-ds As explained in relation to Figure 2, ideally, the threshold V TH-ds is set to 0V. However, in an exemplary embodiment, V TH-ds is set to a value such as 1 V that is still fairly close to ZVS conditions but is relatively immune to parasitic effects. V ds Comparator 410 has two inputs, referred to herein as RISE_P and FALL_P. The RISE_P output is V ds The signal exceeds the voltage threshold V TH-ds V ds Responds to the rising edge of the signal. The FALL_P output is V ds The signal exceeds the voltage threshold V TH-ds V ds Responds to the falling edge of the signal.

[0026] V gs Comparator 420 detects the gate-source voltage V ds and compares it to a predetermined value corresponding to the turn-on threshold voltage of the associated transistor. gs Comparator 420 V gs The inputs are directly coupled to the gate up and gate down pins of the gate driver circuit. gs Comparator 420 has two outputs, referred to herein as ON_CLK and OFF_CLK. The ON_CLK output is V gs The signal exceeds the voltage threshold V TH-gs V ds The OFF_CLK output responds to the rising edge of the V gs The signal exceeds the voltage threshold V TH-gs V ds Responds to the falling edge of the signal.

[0027] V ds Comparator 410 and V gsEach comparator 420 experiences an inherent amount of delay. ds A signal changes state (i.e., a voltage threshold V TH-ds (rise above or fall below) and the corresponding V ds There is an inherent amount of delay between the time the output (RISE_P or FALL_P) changes state (i.e., goes high or goes low). gs The time at which the signal changes state (i.e., rises above or falls below the voltage threshold VTH-gs) and the corresponding V ds There is a specific delay between the time when V changes state and the time when V ds Comparator 410 and V gs The amount of delay introduced by comparator 420 can vary from part to part and in response to process variations. Delay matching / trimming module 430 includes circuitry to account for and adjust for these inherent delays. ds Comparator 410 and V gs Each output of both comparators 420 is provided to a delay element in delay matching / trimming module 430. Specifically, the RISE_P signal is provided to delay element 435, the FALL_P signal is provided to delay element 440, the OFF_CLK signal is provided to delay element 445, and the ON_CLK signal is provided to delay element 450. Each of delay elements 435-450 also includes a trim input (not shown) for receiving a trim value indicating the amount of delay to be introduced by the corresponding delay element. These trim values ​​may be determined during or after manufacturing by a variety of methods, which may include testing. In an exemplary embodiment, the trim values ​​are stored in non-volatile memory. In this manner, delay matching / trimming module 430 adjusts the delays of V ds Comparator 410 and V gs It is possible to compensate for delays inherent in the comparator 420. In an exemplary embodiment, the delay matching / trimming module 430 also compensates for the delay that exists between the time when the PWM signal controlling the gate driver circuit changes state and the time when the gate voltage changes in response.

[0028] In this way, the delay matching / trimming module 430 adjusts the delay ds Comparator 410 and V gs They generate delayed adjusted versions of the signals received from comparator 420. Specifically, delay element 435 outputs a signal referred to herein as RISE_P_DLY, delay element 440 outputs a signal referred to herein as FALL_P_DLY, delay element 445 outputs a signal referred to herein as OFF_CLK_DLY, and delay element 450 outputs a signal referred to herein as ON_CLK_DLY.

[0029] The output latch and averaging logic module 460 receives the V ds Comparator 410 and V gs The output latch and averaging logic module 460 receives the delay adjusted output of the comparator 420. gs As represented by the output of comparator 420, V gs At times dictated by the rising and falling edges of the signal, V ds 4, the ON_LATE flag and the ON_LATE flag latch are implemented using two D flip-flops 465 and 470. D flip-flop 470 receives the FALL_P_DLY signal from delay matching / trimming module 430 at its D input and the ON_CLK_DLY signal at its clock input. Therefore, when the ON_CLK_DLY signal goes high, the gate-source voltage V gs When V indicates that V is going high, the value present at the D input, i.e., the value of the FALL_P_DLY signal, is latched to the output Q as the ON_LATE flag. gs The signal is V gs Threshold V TH-gs before rising above V ds The voltage is V ds Threshold V TH-dsIn other words, ON_LATE=1 means that the transistor is "late", i.e., the drain-source voltage drops below its threshold V TH-ds This indicates that the voltage drops below 100V and then turns on.

[0030] The D flip-flop 465 receives the RISE_P_DLY signal from the delay matching / trimming module 430 at its D input and the OFF_CLK_DLY signal at its clock input. As a result, when the OFF_CLK_DLY signal goes high, the gate-source voltage V gs When V indicates that V is going low, the value present at the D input, i.e., the value of the RISE_P_DLY signal, is latched at the output Q as the OFF_LATE flag. gs The signal is V gs Threshold V TH-gs before dropping below V ds The voltage is V ds Threshold V TH-ds , it is a digital 1 (logic high). In other words, OFF_LATE=1 means that the transistor is "late", i.e., the drain-source voltage rises above its threshold V TH-ds indicates that the signal rose above 0 and then turned off.

[0031] 2 and 3, the PWM state machines of primary side control module 110 and secondary side control module 120 use the ON_LATE and OFF_LATE flags to generate desired switching waveforms, such as by iteratively adjusting the positions of the rising and falling edges of PWM signals used to generate the gate driver signals supplied to transistors Q1-Q8 based on the ON_LATE and OFF_LATE flags. In an exemplary embodiment, output latch and averaging logic module 460 includes averaging logic that serves to average the ON_LATE and OFF_LATE signals over multiple (e.g., eight) PWM cycles to obtain average values ​​over a longer period of time, thereby reducing noise sensitivity.

[0032] 5 is a timing diagram illustrating timing relationships for various signals in a comparator system, such as comparator system 400 of FIG. 4, according to an exemplary timing and control scheme. The timing diagram of FIG. 5 illustrates the PWM control signal, the gate-source voltage V gs , drain-source voltage V ds , ON_CLK signal, ON_CLK_DLY signal, FALL_P signal, FALL_P_DLY signal, and ON_LATE flag. These signals are described above in connection with FIG. 4. PWM / V gs The graph shows the pulse width modulation signal PWM and the gate-source voltage V gs Both are shown. The PWM signal is illustratively generated by a pulse width modulation state machine and provided to a gate driver circuit that generates gate driver signals based on the PWM signal. The gate-source voltage V gs represents the gate driver signal provided to the gate of the transistor by the gate driver circuit. At time t1 in FIG. 5, the PWM signal goes high. After a driver delay 500, the gate-source voltage V gs is the transistor turn-on threshold V TH-gs , which in the example embodiment of FIG. 5 is 2.5 V at time t2. gs After a comparator delay of 510, V gs The ON_CLK output of comparator 420 drops to V at time t. TH-gs V crossing the threshold gs At time t3, the drain-source voltage V ds is the drain-source voltage threshold V TH-ds , which is set to 1V in the exemplary embodiment of FIG. ds After the comparator delay 520, at time t3, V TH-ds V crossing the threshold ds In response to the signal, V ds The FALL_P output of comparator 410 goes high at time t5.

[0033] As shown in Figure 5, V gs Comparator delay 510 and V dsThere is a delay mismatch between the comparator delay 520 and V gs Comparator 420 is V ds The ON_CLK_DLY signal receives a longer delay than the ON_CLK signal. Delay matching / trimming module 430 compensates for this delay mismatch by performing delay matching on the ON_CLK and FALL_P signals. Specifically, delay elements 440 and 450 apply delays to the FALL_P and ON_CLK signals, respectively. The amount of delay applied is defined by trim values ​​provided to delay elements 440 and 450. The trim values ​​are illustratively based on the amount of delay inherent in each of comparators 410 and 420, as determined during and after manufacturing through testing and other means. The output of delay element 440, called FALL_P_DLY, constitutes a delay-adjusted version of the FALL_P signal, and the output of delay element 450, called ON_CLK_DLY, constitutes a delay-adjusted version of the ON_CLK signal. In accordance with the implemented delay adjustments, the FALL_P_DLY signal goes high at t6 and the ON_CLK_DLY signal goes high at t7. The FALL_P_DLY signal is provided to D flip-flop 470 of output latch and averaging logic module 460, and the ON_CLK_DLY signal is provided to the clock input of D flip-flop 470. Therefore, when the ON_CLK_DLY signal goes high at time t7, the value of the D input is latched into the Q output of the flip-flop, which provides the ON_LATE flag. Because the FALL_P_DLY signal is high at time t7, the ON_LATE flag advances accordingly. Due to the small delay inherent in D flip-flop 460, ON_LATE goes high at time t8, causing V gs This reflects the signal going high, thereby delaying the transistor (i.e., drain-source voltage V ds V TH-ds after it drops below 100mV, then turn it on.

[0034] 6 is a flowchart of a method for controlling a field effect transistor according to an example embodiment. In block 600, a comparator compares the drain-source voltage of the transistor to a threshold voltage. In block 610, a gate voltage signal of the transistor is provided to a clock input of the comparator so that the gate voltage signal is used to latch the result of the comparison to the output of the comparator. In block 620, a control function for the transistor is performed based on the value of the comparator output.

[0035] Modifications may be made to the exemplary embodiment described, and other embodiments are possible, within the scope of the claims of the present invention. For example, the embodiment described uses a V ds Although other variations are possible, including a zero-volt crossing detection scheme implemented by a comparator, and for example, although the described embodiments include a wireless power transfer system that uses zero-volt switching, other systems may use zero-volt switching as well.

Claims

1. a control module for controlling a gate drive signal of a transistor, a comparator circuit element comprising: The drain-source voltage (V ｄｓ a first comparator having a first input to receive a drain-source voltage (V ds ), a second input to receive a drain-source threshold voltage, a first output, and a second output, the first comparator being configured to determine a comparison result between the drain-source voltage (V ds ) and the drain-source threshold voltage; The gate-source voltage of the transistor (V ｇｓ a second comparator having a third input receiving the gate-source threshold voltage, a fourth input receiving the gate-source threshold voltage, a third output, and a fourth output; outputting the comparison result at the fourth output in response to the rising edge of the gate-source voltage (V gs ) being above the gate-source threshold voltage; outputting the comparison result to the third output in response to the falling edge of the gate-source voltage (V gs ) being below the gate-source threshold voltage; the second comparator configured as a latch element having a first latch input coupled to the first output, a second latch input coupled to the third output, a third latch input coupled to the second output, a fourth latch input coupled to the fourth output, a first latch output, and a second latch output, wherein the second latch input operates to latch the first latch input to the first latch output and the fourth latch input operates to latch the third latch input to the second latch output; the comparator circuitry including: control circuitry coupled to the first latch output and the second latch output, adjusting the timing of the edge of the gate drive signal by continuously shifting the position of the rising edge of the gate drive signal in response to the second latch output; adjusting an edge of the gate drive signal by continuously shifting a position of a falling edge of the gate drive signal in response to the first latch output; the control circuitry configured as follows: a control module.

2. 10. The control module of claim 1, the comparison result at the fourth output includes an ON_LATE flag indicating whether the gate-source voltage turned on the transistor before or after the drain-source voltage transitioned from a fifth voltage to a sixth voltage lower than the fifth voltage; a control module including an OFF_LATE flag where the comparison result at the third output indicates whether the gate-source voltage turned off the transistor before or after the drain-source voltage went from a seventh voltage to an eighth voltage higher than the seventh voltage.

3. 10. The control module of claim 1, the comparator circuitry: a delay matching module operatively coupled between the first and second comparators and the latch element, applying a harmonic delay to at least one of the first, second, third and fourth outputs to compensate for mismatches in delays inherent in the first and second comparators; Delay Adjustment V ｄｓ providing edge transition signals to the first and second latch inputs to adjust delay V ｇｓ providing edge transition signals to the second and fourth latch inputs; a control module configured to:

4. 10. The control module of claim 1, The control module, wherein the control circuitry is further configured to adjust timing of edges of the gate drive signal based on the first and second latch outputs.

5. 10. The control module of claim 1, The control module, wherein the latch element includes at least one D flip-flop.

6. 10. The control module of claim 1, The first comparator is V ｄｓ The rise is the V ｄｓ V indicates that it is above the threshold ｄｓ A rising edge signal and V ｄｓ The falling edge is V ｄｓ V indicates that the threshold is below ｄｓ a falling edge signal; The second comparator is V ｇｓ The rise is the V ｇｓ V indicates that it is above the threshold ｇｓ A rising edge signal and V ｇｓ The falling edge is V ｇｓ V indicates that the threshold is below ｇｓ and a falling edge signal.

7. 1. A method of controlling a gate drive signal for a transistor, comprising: The first comparator detects the drain-source voltage (V ｄｓ ) and receiving, by the first comparator, a drain-source threshold voltage; A second comparator detects the gate-source voltage (V ｇｓ ) and receiving, by the second comparator, a gate-source threshold voltage; determining, by the first comparator, a comparison result between the drain-source voltage and the drain-source threshold voltage; outputting, by a latch element, the comparison result at a second output of the latch element in response to the rising edge of the gate-source voltage (V gs ) being above the gate-source threshold voltage; outputting, by the latch element, the comparison result at a first output of the latch element in response to the falling edge of the gate-source voltage (V gs ) being below the gate-source threshold voltage; shifting, by control circuitry, a position of a rising edge of the gate drive signal in response to the comparison result at a second output of the latching element; shifting, by the control circuitry, a position of a falling edge of the gate drive signal in response to the comparison result at the first output of the latching element; Including, The method, wherein the gate-source voltage (V gs ) is used as a clock signal for latching the first and second outputs of the latch element.

8. 8. The method of claim 7, the comparison result at the second output of the latch element includes an ON_LATE flag indicating whether the gate-source voltage turned on the transistor before or after the drain-source voltage transitioned from a fifth voltage to a sixth voltage lower than the fifth voltage; the comparison result at the first output of the latch element includes an OFF_LATE flag indicating whether the gate-source voltage turned off the transistor before or after the drain-source voltage went from a seventh voltage to an eighth voltage higher than the seventh voltage.

9. 9. The method of claim 8, The method of claim 1, wherein the timing of the edges of the gate drive signal is based on the value of the ON_LATE flag and the value of the OFF_LATE flag.

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