Deck-select transistors for three-dimensional cross-point memories.

Abstract

To provide a memory device structure, a method of fabricating a deck select transistor, and a system, which increase the memory density while minimizing the decoder transistor footprint.SOLUTION: A memory device structure 100 includes first line structures 102, where each of the first line structures, includes a first transistor channel 110. The memory device structure further includes a second plurality of line structures 112 substantially orthogonal to the first line structures, where each of the second line structures includes a second transistor channel 120. A memory cell 122 is at each cross-point between the first plurality of line structures 102 and the second plurality of line structures 112.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] A three-dimensional (3D) cross-point memory array may have tiers or decks of memory cells. However, in this manner, an increase in the total number of memory cells may be proportional to an increase in the number of decoder transistors required, thereby increasing the overall footprint of the decoder transistors. Therefore, a solution is needed to increase memory density while minimizing the decoder transistor footprint. [Brief explanation of the drawings]

[0002] The materials described herein are illustrated for purposes of illustration and not limitation in the accompanying figures. For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be depicted in their simplified, "idealized" shapes and arrangements for clarity of discussion, although it will be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and orthogonal intersections may be depicted while ignoring the finite roughness, chamfers, and imperfect angle intersections characteristic of structures formed by nanofabrication techniques. Furthermore, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or similar elements. [Figure 1] 1 is an isometric view of a memory device structure, according to an embodiment of the present disclosure, the memory device structure including a plurality of transistors. [Figure 2A] FIG. 2 is an isometric view of a portion of the memory device structure in FIG. 1 according to an embodiment of the present disclosure. [Figure 2B] 2B is a cross-sectional view through the line structure in FIG. 2A. [Figure 2C] 2B is a cross-sectional view taken along a line perpendicular to the line structure in FIG. 2A. [Figure 2D] FIG. 2B is a cross-sectional view of the gate portion of the line structure in FIG. 2A. [Figure 3A] FIG. 2 is an isometric view of a portion of the memory device structure in FIG. 1 according to an embodiment of the present disclosure. [Figure 3B] FIG. 3B is a cross-sectional view of the line structure in FIG. 3A. [Figure 3C] FIG. 3B is a cross-sectional view of the gate portion of the line structure in FIG. 3A. [Figure 4A] FIG. 2 is an isometric view of a portion of the memory device structure in FIG. 1 according to an embodiment of the present disclosure. [Figure 4B] FIG. 4B is a cross-sectional view of the line structure in FIG. 4A. [Figure 4C] FIG. 4B is a cross-sectional view of the gate portion of the line structure in FIG. 4A. [Figure 4D] FIG. 4B is a cross-sectional view taken along a line perpendicular to the line structure in FIG. 4A. [Figure 5A] 2 is a cross-sectional view of the structure of the memory device taken along line AA' in FIG. [Figure 5B] 1 is a cross-sectional view of a memory cell according to an embodiment of the present disclosure. [Figure 5C] FIG. 1 is a cross-sectional view of a non-volatile memory element according to an embodiment of the present disclosure. [Figure 5D] FIG. 1 is a cross-sectional view of a non-volatile memory element according to an embodiment of the present disclosure. [Figure 5E] FIG. 1 is a cross-sectional view of a selector element according to an embodiment of the present disclosure. [Figure 6] A method of manufacturing a device structure such as that described in connection with Figure 2A, Figure 3A or Figure 4A. [Figure 7A] 1 is a cross-sectional view of multiple interconnects patterned in a dielectric on a substrate according to an embodiment of the present disclosure. [Figure 7B] FIG. 7B is an isometric view of the structure in FIG. 7A. [Figure 8A] 7B shows the structure of FIG. 7A following the formation of a plurality of line segments on the substrate. [Figure 8B] FIG. 8B is an isometric view of the structure in FIG. 8A. [Figure 9]8B following the formation of a dielectric between each of the plurality of line segments forming the block. [Figure 10A] 9 following processing of the etching portion of the block. [Figure 10B] FIG. 10B is a cross-sectional view of the line structure in FIG. 10A. [Figure 11A] 10B shows the structure of FIG. 10A following the formation of a thin film channel (TF channel) material above the multiple line structures. [Figure 11B] FIG. 1 is a cross-sectional view through multiple line structures. [Figure 12A] 11C is a cross-sectional view of the structure in FIG. 11B following a process of removing portions of the channel material between portions of adjacent line structures. [Figure 12B] FIG. 11C is a cross-sectional view of the structure in FIG. 11B following a process of removing portions of channel material from above the line structures. [Figure 13A] The structure of FIG. 11B is shown following the formation of a gate dielectric layer 1300. [Figure 13B] FIG. 13B is a cross-sectional view through a number of line structures in FIG. 13A. [Figure 14A] The structure of Figure 13A is shown following the formation of a gate electrode. [Figure 14B] 14B is a cross-sectional view of a gate electrode on a plurality of line structures in FIG. 14A. [Figure 15A] The structure of FIG. 9 is shown in which an ALD deposition process is utilized to selectively deposit TFT channel material around a portion of the line structure. [Figure 15B] 15B is a cross-sectional view of the gate electrode around the line structure in FIG. 15A. [Figure 16A] 10 shows the structure of FIG. 9 following the formation of a plurality of openings. [Figure 16B] The structure of FIG. 16A is shown after a sacrificial dielectric has been formed in each of the plurality of openings on dielectric 702, followed by the formation of a channel layer 1606 on dielectric 1604. [Figure 16C] The structure of Figure 16D is shown following the process of reducing the channel height. [Figure 16D]The structure of Figure 16C is shown following the formation of a gate dielectric layer. [Figure 16E] The structure of Figure 16D is shown following the formation of a gate electrode on the gate dielectric layer. [Figure 16F] The structure of Figure 16E is shown following a process that removes a portion of the gate dielectric layer. [Figure 16G] The structure of Figure 16F is shown following the formation of source structures adjacent to each channel. [Figure 17] 1 is an isometric view of a system in which a memory device structure is coupled by multiple logic transistors and peripheral components. [Figure 18] FIG. 1 is a block diagram of an example computing system including a deck select transistor array coupled with a memory device array that enables print scaling of decoder transistors. [Figure 19] FIG. 1 is a block diagram of an example mobile device including a deck select transistor array coupled with a memory device array that enables print scaling of decoder transistors. DETAILED DESCRIPTION OF THE INVENTION

[0003] Deck select transistors for three-dimensional (3D) crosspoints and methods of fabrication are described. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as operations associated with memory devices and transistors, have not been described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0004] In some instances, in the following description, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring the present disclosure. Throughout this specification, reference to an "embodiment" or "one embodiment" or "some embodiments" means that a specific feature, structure, function, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, specific features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment wherever specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0005] As used in this description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that as used herein, the term "and / or" refers to and includes any and all possible combinations of one or more of the associated listed items.

[0006] The terms "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between two or more components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in physical, electrical, or magnetic contact with each other, either directly or indirectly (with other elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship).

[0007] As used herein, the terms "over," "under," "between," and "on" refer to the relative location of one component or material to another component or material, where such physical relationship is noteworthy. For example, in the context of materials, a material disposed above or below another may be in direct contact or may have one or more intervening materials. Furthermore, a material disposed between two materials may be in direct contact with the two or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material / ingredient. In the context of component assemblies, a similar distinction is made. As used throughout this description and claims, a list of items combined by the terms "at least one of" or "one or more of" may mean any combination of the listed terms.

[0008] As used herein, the term "adjacent" generally refers to the location of something next to (e.g., immediately next to, or nearby with one or more intervening elements between) or next to (e.g., abutting) another.

[0009] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0010] The term "device" may generally refer to an apparatus depending on the context of the use of the term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures with active and / or passive elements, etc. Generally, a device is a three-dimensional structure having a plane along the x-y directions and a height along the z direction in an x-y-z Cartesian coordinate system. The plane of a device may also be the plane of an apparatus that contains the device.

[0011] As used throughout this description and in the claims, a list of items combined with the terms "at least one of" or "one or more of" may mean any combination of the listed terms.

[0012] The terms "substantially equal," "approximately equal," and "nearly equal," unless otherwise specified in the express context of their use, mean that the difference between the two items so described is only a random variation. In the art, such variation is typically less than ±10% of a predetermined target value.

[0013] Terms such as "left," "right," "front," "back," "top," "bottom," "over," and "under" in this description and claims, if any, are used for descriptive purposes and do not necessarily describe permanent positional relationships. For example, as used herein, terms such as "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" refer to the relative location of one component, structure, or material within a device relative to another referenced component, structure, or material. Here, such physical relationships are noteworthy. These terms are used herein for descriptive purposes only, primarily within the context of the device's z-axis, and thus may be relative to the device's orientation. Thus, in the context of the figures provided herein, a first material "above" a second material may also be "below" the second material if the device is oriented upside down relative to the context of the figures provided. In the context of materials, a material disposed above or below another material may be in direct contact or may have one or more intervening materials. Furthermore, a material disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. In the context of component assembly, a similar distinction is made.

[0014] The term "between" may be used in the context of the z-axis, x-axis, or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or may be separated from both of the other two materials by one or more intervening materials. Thus, a material that is "between" two other materials may be in contact with either of the other two materials, or may be connected to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or may be separated from both of the other two devices by one or more intervening devices.

[0015] The memory cells are used in conjunction with large arrays of decoder transistors for various 3D cross-point memory applications. A 3D cross-point memory array includes a series of word lines on a first plane and a series of bit lines on a second plane above the first plane, where the word lines cross over with the bit lines (or vice versa). A memory cell is located at each point of crossover between the word lines and bit lines (cross-point), and the memory cell couples the word line with the corresponding bit line to form a single memory array deck, or decks as we call them.

[0016] Decoder transistors may be individually coupled to each word line and bit line to address a particular memory cell in the deck. The number of decoder transistors required to address each memory cell (bit cell) is proportional to the number of memory cells in the 3-D cross-point array. The number may increase proportionally with the increase in the number of bit lines and word lines. To accommodate a greater number of decoder transistors near the cross-point array, e.g., below the 3-D cross-point memory array, the physical length of the word lines and bit lines may be increased. Alternatively, the decoder transistors may occupy an area laterally adjacent to the memory array. In either example, a larger chip area may be utilized.

[0017] Increasing the number of layers (decks) of memory cells to form a three-dimensional array can increase memory density per unit area. However, increasing the number of memory cells also proportionally increases the number of decoder transistors required. In some examples, a single deck may include 8K bit lines and 8K word lines. Thus, a single 8K x 8K deck may require 16K decoder transistors. Because the number of decoder transistors increases proportionally with the number of decks, enabling a high-density memory array for a given die size can be very challenging.

[0018] However, the inventors have devised a configuration that can reduce the number of decoder transistors below a 3D cross-point memory array by integrating deck select transistors within each word line and each bit line of a deck. Furthermore, vertically spaced word lines (and bit lines) across multiple decks are connected together. In one example, a memory array may include two decks, with each word line of a first deck connected to a corresponding word line of a second deck directly below by an interconnect via. Each pair of word lines is connected by a single decoder transistor below the memory array. For example, a first interconnect via can be used to connect a pair of word lines, and a second interconnect via can connect the lowest word line to the decoder transistor. As the number of decks increases, each word line from each successive deck may be connected together by an intervening interconnect via. The lowest word line corresponding to the lowest-level deck may further be connected to a single decoder transistor below the highest deck.

[0019] Similarly, each bit line in the first deck may be coupled to a corresponding bit line in the second deck directly below by an interconnect via. Each pair of bit lines is coupled to a single decoder transistor by an interconnect via. When the number of decks is increased, each bit line from each successive deck is coupled to a single decoder transistor. For example, a first bit line from the first deck may be coupled to a first bit line from the second deck directly above the first bit line. Thus, the total number of decoder transistors in the memory array is equal to the total number of word lines and bit lines on any given deck and is independent of the number of decks. During operation, all word lines (bit lines) coupled across multiple decks may be biased simultaneously. However, because deck select transistors are present between the memory cells on each deck and the interconnect vias, a single memory cell can be selected for programming by biasing the appropriate deck select transistor.

[0020] When each deck includes a large number of word lines and bit lines (e.g., 8K), a large number of routing lines are required to accommodate each deck select transistor. To alleviate the challenge of individually routing each transistor, the gates of each deck select transistor on each word line (bit line) of a single deck can be electrically coupled together. A single routing conductor can be coupled to a single deck select transistor. During operation, all deck select transistors on the word lines (bit lines) of a single deck are at the same gate bias. However, a single deck select transistor and a single word line-bit line combination can be biased to program a single memory cell.

[0021] In embodiments of the first deck select transistor, each word line (bit line) includes a line portion (herein, oxidized line portion) that is sufficiently oxidized to form an electrical break, and channel material is adjacent to at least one sidewall of the oxidized line portion. In some such embodiments, a gate structure is adjacent to the channel material, and immediately conductive portions of the word line (or bit line) on either side of the oxidized line portion can function as source or drain regions of the deck select transistor. In some embodiments, the channel material completely covers the oxidized line portion, and the gate structure covers the channel material. In exemplary embodiments, the transistor is a thin-film transistor including an amorphous or polycrystalline channel.

[0022] In second deck select transistor embodiments, each word line (bit line) is divided into two collinear conductive line segments with a channel material (also collinear) between the two conductive line segments and two collinear conductive line segments. The two conductive line segments on either side of the channel material can function as source or drain regions for second deck select transistor embodiments. In some such embodiments, gate structures are adjacent to two or more surfaces of the channel material. In an exemplary embodiment, gate structures are on three surfaces of the channel material (e.g., on the top surface and two sidewall surfaces), and the deck select transistors are FIN-FET devices.

[0023] 1 is an isometric view of a memory device structure 100 including deck select transistors, such as deck select transistors 101A and 101B. The memory device structure 100 includes a first line structure 102 (herein, line structure 102) along a first direction (e.g., the x-axis). The line structure 102 includes a line 104 (herein, line 104) adjacent to a line structure 106 (herein, line 106), the line 104 including a channel 108, and the line 106 including a transistor channel 110. The memory device structure 100 further includes a second plurality of line structures 112 (herein, line structure 112) along a second direction (e.g., the y-axis). As shown, the line structure 112 is directly along the y-axis. The line structure 112 includes a line 114 adjacent to a line 116, the line 114 including a transistor channel 118, and the line 116 including a transistor channel 120.

[0024] The memory device structure 100 further includes a memory cell at each cross point between the line structure 102 and the line structure 112. The total number of memory cells per deck is equal to the product of the number of lines in the line structure 112 and the number of lines in the line structure 112. As shown, the memory device structure 100 includes 64 memory cells on a single deck. The example memory device structure 100 includes, for example, a memory cell 122 at the cross point between the line 104 and the line structure 114, a memory cell 124 at the cross point between the line 104 and the line structure 116, and a memory cell 126 at the intersection between the line 106 and the line structure 114.

[0025] In an embodiment, memory device structure 100 includes multiple layers of line structures, such as line structures 102 and 112. Each pair of line structures, e.g., line structures 102 and 112, separated by an array of memory cells, such as memory cell array 127, constitutes a memory deck. The lines in line structures 102 and 112 operate as multiple word line and bit line pairs, respectively (or vice versa). In an exemplary embodiment, memory structure 100 includes three decks. A first deck 128 includes line structures 102 and 112 and memory cell array 127.

[0026] In the exemplary embodiment, memory device structure 100 further includes a second deck 130 below deck 128. Deck 130 includes a plurality of line structures 132 (herein referred to as line structures 132) parallel to line structures 112. Line structures 132 include lines 134 and 136, which include transistor channels 138 and 140. The lines in line structures 132 and 134 operate as a plurality of word line and bit line pairs, respectively (or vice versa).

[0027] The memory device structure 100 further includes a plurality of line structures 142 (herein referred to as line structures 142) parallel to the line structures 112. In the illustration, the line structures 142 have their longitudinal axes along the y-axis. The line structures 142 include a line structure 144 adjacent to a line structure 146, where the line 144 includes a transistor channel 148 and the line 146 includes a transistor channel 150. The deck 130 further includes a memory cell at each cross point between the line structures 132 and 142. As shown, a memory cell 152 is located at the cross point between the line structures 134 and 144, and a memory cell 153 is located at the cross point between the line structures 134 and 144.

[0028] In an exemplary embodiment, memory device structure 100 includes an 8x8 array of orthogonal lines per deck. Depending on the embodiment, deck 128 or 130 can include between 2000 and 8000 lines.

[0029] Each deck select transistor, e.g., transistor 101A, includes a gate electrode adjacent to the channel and a gate dielectric layer interposed between the gate electrode and the channel. In an exemplary embodiment, the individual gate electrodes of each deck select transistor, e.g., transistors 101A and 101B, are coupled together. As shown, gate structure 166 includes the gate electrodes of adjacent transistor channels in each line of line structure 102. The gate dielectric layer insulates the respective channel layers of each deck select transistor (e.g., 101A, 101B) in line structure 102. In an embodiment, coupling between the gate electrodes of different deck select transistors 101A, 101B, etc., advantageously allows the gate electrodes to be biased simultaneously, saving considerable space for other required circuitry. In an embodiment, line structure 102 includes 8,000 lines, and all 8,000 gate electrodes may be coupled by a single routing conductor.

[0030] The memory device structure 100 further includes gate structures 168, 172, and 174 adjacent to the plurality of transistor channels. The gate structures 168, 172, and 174 include one or more features of the gate structure 166, such as a gate electrode and a gate dielectric layer. It should be understood that each gate structure 166, 168, 172, and 174 may be independently biased through one or more bias electrodes (not shown).

[0031] The memory device structure 100 may include different deck select transistor architectures, including different gate and channel structures with different FET characteristics (eg, N-FET and P-FET).

[0032] FIG. 2A is an isometric view of a deck select transistor 200 according to an embodiment of the present disclosure. A portion of the channel 108 has been removed for clarity. As shown, each line structure in the line structure 102 has various portions with varying material composition along its longitudinal length (e.g., the x-axis). In the exemplary embodiment, each line in the line structure 102 also has a cross-sectional area in the yz plane that varies along the x-direction in a region within the channel 108. Portions of the gate structure 202 and the channel 108 have been omitted to reveal the shape of a representative line, e.g., line 104, and channel, e.g., channel 108. In the exemplary embodiment, the gate structure 202 includes a gate dielectric layer and a gate electrode. In the exemplary embodiment, the gate dielectric layer is not explicitly shown. As shown, the gate structure 202 is adjacent to each transistor channel in each line of the line structure 102.

[0033] 2B is a cross-sectional view of deck select transistor 200 through line A-A' in the structure of FIG. 2A. In an exemplary embodiment, line 104 has line portion 104A and line portion 104B including a metal or a metal-containing alloy, and line portion 104C between line portion 104A and line portion 104B. In an embodiment, line portion 104C includes a metal and oxygen. Deck select transistor 200 includes a channel 108 and a gate structure 202 on channel 108. As shown, gate structure 202 includes a gate dielectric layer 202A on channel 108 and a gate electrode 202B on gate dielectric layer 202A. In an exemplary embodiment, line portion 104A is a source or drain region, and line portion 104B is a drain or source region of deck select transistor 200. In the exemplary embodiment, terminal interconnect is coupled to line portion 104B, and memory cell 122 is on and coupled to line portion 104B. Although only one memory cell is shown, the entire line portion 104B is long enough to include multiple memory cells as shown in Figure 1. Referring again to Figure 2B, because line portions 104A and 104B are conductive, the entire line portion 104B may be considered a source or a drain.

[0034] Line segment 104C is for insulation and has a length L along the x-axis. O In some embodiments, L O The length of line portion 104C is between 10 nm and 500 nm. The length of line portion 104C is the maximum effective gate length of deck select transistor 200, L G Decide.

[0035] In the exemplary embodiment, line 104 also includes line portion 104D between line portions 104B and 104C. Line portion 104D can have the same or substantially the same material composition as line portion 104B. As shown, line 104 also includes portion 104E between line portions 104A and 104C. Line portion 104E has the same or substantially the same material composition as line portions 104A or 104B. Line portions 104D and 104E can be considered lateral sources or drains below channel 108. In some embodiments, line structure portions 104A, 104D, and 104E include a metal such as tungsten, tantalum, or titanium. In other embodiments, line structure portions 104A, 104D, and 104E include nitrogen and at least one of tungsten, tantalum, or titanium.

[0036] As shown, line segments 104D and 104E have lengths L1 and L2, respectively. In some embodiments, L1 and L2 are in the ranges between 10 nm and 100 nm, and between 10 nm and 100 nm, respectively. L1 may be equal to or different from L2.

[0037] As shown, line 104 has a height relative to lowest surface 104F that varies along the x-direction. In an exemplary embodiment, the height of line 104 decreases near channel 108 compared to away from channel 108. As shown, line portions 104A and 104B have a height H1. In an embodiment, H1 is between 15 nm and 100 nm. As shown, portions 104C, 104D, and 104E have a height H2 that is less than H1. In an embodiment, H2 is between 10 nm and 95 nm. In an exemplary embodiment, H2 is substantially uniform along the x-axis.

[0038] In the exemplary embodiment, the channel 108 extends laterally beyond the line segment 104C along the x-axis and above the line segments 104D and 104E. C In the exemplary embodiment, the channel 108 has a thickness T substantially equal to the difference between the heights of the line portion 104A and the line portion 104C, 104D, or 104E, respectively. C In another embodiment, T C is greater than or less than the difference between the heights of line portion 104A and line portion 104C, 104D or 104E, respectively.

[0039] The gate structure 202 has a gate length that is less than the lateral width of the channel 108 (the L effective In an embodiment, L G is between 50 nm and 600 nm. In an exemplary embodiment, gate structure 202 does not extend above line portions 104A and 104B.

[0040] In an embodiment, the gate electrode 202 comprises at least one P-type work function metal or an N-type work function metal, depending on whether the transistor is to be a P-FET transistor or an N-FET transistor. Examples of N-type materials include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide. Examples of P-type materials include ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides, such as ruthenium oxide.

[0041] In an embodiment, the gate dielectric layer 202A comprises a material with a high dielectric constant, or a high-K material. Examples of gate dielectric layer 202A include oxygen and one or more of the following elements: hafnium, silicon, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, or zinc. Examples of high-K materials that may be used for the gate dielectric layer 202A include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum oxide, aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0042] In some embodiments, the gate structure 202 includes one or more work function layers (gate electrodes 202B) and a fill metal (not shown) on the one or more work function layers, the fill metal filling the space between the gate electrodes of each adjacent line. In some such embodiments, the gate structure 202 includes an additional layer of conductive material extending above the gate electrodes 202B.

[0043] 2C is a cross-sectional view of line segment 104A or 104B. In an exemplary embodiment, the outline (dashed line) of line segment 104C indicates the relative widths of line segments 104C and 104A, 104B. As shown, line segment 104A or 104B is laterally wider (along the y-direction) than line segment 104C. In one embodiment, line segments 104A and 104B have a width W A and the line portion 104C has a width W C W A is W C In an embodiment, W A is at least 5 nm, W C is greater than.

[0044] FIG. 2D is a cross-sectional view of the structure in FIG. 2A through line CC'. In an exemplary embodiment, line segment 104C has a rectangular cross-section in the yz plane, and channel 108 is on at least three surfaces of line segment 104C. As shown, channel 108 is adjacent to surface 104G and sidewalls 104H and 104J of line segment 104C. Such a channel 108 may be referred to as a saddle-shaped channel 108. As shown, gate dielectric layer 202A and gate electrode 202B are conformal to sidewalls 104H and 104J and surface 104G. In some such embodiments, deck select transistor 200 is known as a saddle-shaped FET.

[0045] FIG. 3A is an isometric view of a deck select transistor 300 according to an embodiment of the present disclosure. As shown, each line in the line structure 102 varies in material composition along its longitudinal length (x-axis). In the exemplary embodiment, each line in the line structure 102 also has a cross-sectional area in the y-z plane that varies along the x-axis in regions within the transistor channel 302 and in regions away from the transistor channel 302. Portions of the transistor channel 302 and gate structure 304 are omitted to clarify the shape of the representative line structure, e.g., line 104 and transistor channel 302. The gate dielectric layer is not shown in the figure to provide clarity. In the exemplary embodiment, the transistor channel 302 surrounds line portions 104C, 104D (not visible), and 104E. In the exemplary embodiment, the channel 302 asymmetrically surrounds the line 104. In an embodiment, the gate structure 304 has one or more features of the gate structure 202. As shown, a gate structure 302 couples each transistor channel to each line of line structure 102 .

[0046] Figure 3B is a cross-sectional view of deck select transistor 300 through line A-A' in the structure of Figure 3A. In an exemplary embodiment, line 104 has one or more of the characteristics described above in connection with Figure 2B.

[0047] In the exemplary embodiment, transistor channel 302 extends laterally along the x-axis beyond line portion 104C and above line portions 104D and 104E. C In an exemplary embodiment, the transistor channel 302 has a thickness T that is substantially equal to the difference between the heights of the line portion 104A and the line portion 104C, 104D, or 104E, respectively. C In another embodiment, T Cis greater than or less than the difference between the heights of line portion 104A and each of line portions 104C, 104D, or 104E. However, as shown, channel 302 has a bottom surface 302A below bottom surface 104F of line portion 104A. As shown, gate dielectric layer 304A and gate electrode 304B of gate structure 304 are also below bottom surface 104F.

[0048] In an embodiment, the gate dielectric layer 304A and the gate electrode 304B comprise a material that is the same or substantially the same as the material of the gate dielectric layer 204A and the gate electrode 204B, respectively, as described in connection with Figure 2B. In an embodiment, the transistor channel 302 comprises a material that is the same or substantially the same as the material of the channel 108.

[0049] In some embodiments, the gate structure 304 includes one or more work function layers (gate electrode 304B) and a fill metal on the one or more work function layers, with the fill metal (not shown) filling the space between the gate electrodes of each adjacent line. In some such embodiments, the gate structure 304 includes an additional layer of conductive material extending above the gate electrode 304B. The additional layer of conductive material may also extend below a portion of the gate electrode 304B that is below the surface 104F.

[0050] 3C is a cross-sectional view of the structure in FIG. 3A through line B-B'. In an exemplary embodiment, line segment 104C has a rectangular cross-section in the yz plane, and transistor channel 302 overlies line segment 104C. As shown, gate dielectric layer 304A overlies line segment 104C and channel 302, and gate electrode 304B overlies gate dielectric layer 304A. In some such embodiments, deck select transistor 300 is known as a gate-all-around FET. Depending on the application, deck select transistor 300 may be a P-FET or an N-FET.

[0051] In a third embodiment, the deck select transistor includes a FinFET architecture (an example of a non-planar transistor). FIG. 4A is an isometric view of a deck select transistor 400 according to an embodiment of the present disclosure. Portions of gate structures 402 are omitted to reveal the shape of respective transistor channels, e.g., transistor channel 404. The gate dielectric layer is not shown in the figure to provide clarity. Gate structures 402 are adjacent to each line of line structure 102.

[0052] 4B is a cross-sectional view of the deck select transistor 400 through line A-A' in the structure of FIG. 4A. In the exemplary embodiment, the line 104 has a first portion 104A and a second portion 104B. As shown, the line 104 also includes a deck select transistor channel 404 between line portions 104A and 104B. In the exemplary embodiment, line portion 104A is one of the source or drain regions, and line portion 104B is the other of the source or drain region of the deck select transistor 400. As shown, the transistor channel 404 has a length L O In an embodiment, L O is between 50 nm and 600 nm.

[0053] As shown, line segments 104A and 104B have a height H1. In an embodiment, H1 is between 15 nm and 100 nm. Transistor channel 404 has a height H2. As shown, H2 is greater than H1. In an embodiment, H2 is between 10 nm and 95 nm. In an exemplary embodiment, H2 is substantially uniform along the x-axis. Depending on the desired fin height, H2 may be less than H1.

[0054] As shown, the gate structure 402 is located, in cross section, above the channel 404. Depending on the manufacturing process, the gate structure 402 may extend over the length L of the transistor channel 404. O Gate length L less than or equal to G LG L O If shorter, the gate dielectric layer 402A may be adjacent to the sidewall of the gate electrode 402B. It should be understood that the memory cell 122 is coupled to the line portion 104B of the deck select transistor 400, and the terminal interconnect 155 is coupled to the line portion 104A of the deck select transistor 400.

[0055] In an embodiment, the gate dielectric layer 402A and the gate electrode 402B comprise a material that is the same or substantially the same as the material of the gate dielectric layer 204A and the gate electrode 204B, respectively. In an embodiment, the transistor channel 404 comprises a material that is the same or substantially the same as the material of the channel 108.

[0056] In some embodiments, the gate structure 402 includes one or more work function layers (gate electrodes 402B) and a fill metal (not shown) on the one or more work function layers, the fill metal filling the space between the gate electrodes of each adjacent line. In some such embodiments, the gate structure 402 includes an additional layer of conductive material extending above the gate electrodes 402B.

[0057] FIG. 4C is a cross-sectional view of the structure of FIG. 4A through line B-B'. In an exemplary embodiment, the transistor channel 404 has a rectangular cross-section in the yz plane. As shown, the transistor channel 404 has a rectangular cross-section in the yz plane. In an exemplary embodiment, a gate dielectric layer 402A is on the top surface 404A and on sidewall surfaces 404B and 404C of the transistor channel 404. A gate electrode 402B is on the gate dielectric layer 402A adjacent to surfaces 404A, 404B, and 404C. In some such embodiments, the deck select transistor 300 is known as a finFET (an example of a non-planar transistor). Depending on the application, the deck select transistor 400 may be a P-FET or an N-FET.

[0058] 4D is a cross-sectional view of the structure in FIG. 4A through line B-B'. In an exemplary embodiment, the outline (dashed line) of transistor channel 404 indicates the relative widths of line 104 and channel 404. As shown, line portions 104A and 104B are laterally wider (along the y-direction) than transistor channel 404. As shown, line portions 104A and 104B have a width W A and the line portion 104C has a width W C In an exemplary embodiment, W A is W C In an embodiment, W A is at least 5 nm, W C is greater than.

[0059] 1 , memory device structure 100 further includes groups of terminal interconnects that connect lines aligned along the same direction across two or more decks. In an exemplary embodiment, each of terminal interconnect groups 154 and 158 includes multiple terminal interconnects. In an exemplary embodiment, each terminal interconnect in terminal interconnect group 154 ​​connects between a single line in line structure 102 and a corresponding vertically aligned line in line structure 132. For example, lines 104 and 134 are connected by terminal interconnect 155, and lines 106 and 136 are connected by terminal interconnect 156. In operation, any single terminal interconnect, for example, terminal interconnect 155, can simultaneously bias two lines 104 and 134 on two different decks to the same potential. However, a single memory cell, for example memory cell 122, can preferably be programmed above memory cell 152 (below memory cell 122) by biasing deck select transistor 101A.

[0060] In the exemplary embodiment, each transistor channel is between a terminal interconnect and a memory cell. For example, channel 108 is laterally between memory cell 122 and terminal interconnect 155, and transistor channel 138 is laterally between memory cell 152 and terminal interconnect 155. Similarly, transistor channel 110 is laterally between memory cell 124 and terminal interconnect 155, and transistor channel 140 is laterally between memory cell 153 and terminal interconnect 156.

[0061] Also as shown, each terminal interconnect in group 158 of terminal interconnects is coupled between a single line in line structure 112 on deck 128 and a corresponding vertically aligned line in line structure 142 on deck 130. In the exemplary embodiment, lines 114 and 144 are coupled by terminal interconnect 160, and lines 116 and 146 are coupled by terminal interconnect 162. In operation, terminal interconnect 160 can simultaneously bias two lines 114 and 144 on two different decks to the same potential.

[0062] In the exemplary embodiment, transistor channel 118 lies laterally between memory cell 122 and terminal interconnect 160, and transistor channel 120 lies laterally between memory cell 152 and terminal interconnect 155. Similarly, transistor channel 148 lies laterally between memory cell 152 and terminal interconnect 160, and transistor channel 150 lies laterally between memory cell 164 and terminal interconnect 162.

[0063] In an embodiment, the wires in each of the wire structures 102, 112, 132 and 142 comprise a metal such as tungsten, tantalum or titanium, or an alloy comprising nitrogen and at least one of tungsten, tantalum or titanium.

[0064] In embodiments, transistor channels 110, 118, 120, 138, 140, 148, and 150 each comprise a polycrystalline or amorphous material suitable for thin film transistors.

[0065] In some embodiments, channels 110, 118, 120, 138, 140, 148, and 150, etc., comprise an n-type semiconductor material. Examples of n-type semiconductor materials include two or more of In, Ga, Zn, Mg, Al, Sn, Hf, O, W, such as In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, InWO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, or InMgZnO.

[0066] In embodiments, the n-type channel may be doped with Ti, W, Cu, Mn, Mg, Fe, Hf, Al, Ni, CO, or Ru. In embodiments, the dopant concentration is 10 16 atoms / cm 3 and 10 20 atoms / cm 3 and the channel has a thickness between 1 nm and 80 nm.

[0067] In other embodiments, channels 110, 118, 120, 138, 140, 148, and 150, etc., comprise p-type semiconductor materials such as NbO, NiO, CoO, SnO, CuO, AgAlO, CuAlO, AlScOC, SrBPO, LaSiOSe, LaCuSe, RbSnO, LaOS, KSnO, NaFeOSe, ZnRhO, or CuO. x and x is 1 or 2.

[0068] In embodiments, each of interconnects 155, 156, 160, 162 comprises copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, ruthenium, molybdenum, cobalt, and alloys thereof, or alloys comprising nitrogen and one or more of copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, titanium, tin, or lead. In some embodiments, each of interconnects 155, 156, 160, 162 comprises a metal carbide, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide.

[0069] In the exemplary embodiment, memory device structure 100 further includes additional memory cells corresponding to additional decks between deck 128 and deck 130 .

[0070] 5A is a cross-sectional view through line A-A' of the structure in FIG. 1, illustrating the configuration of additional memory cells within deck 500. Deck 500 includes line structures 102 and 142 and memory cell array 502. In the cross-sectional view, two memory cells are shown, e.g., memory cell 504 between line 104 and line 144, and memory cell 506 between line 106 and line 144. Other memory cells at the intersections between the respective lines in each of line structures 102 and 142 are not visible in the cross-sectional view.

[0071] In embodiments, the associated transistors corresponding to each deck can all be P-FETs or N-FETs. In some embodiments, both P-FETs and N-FETs are implemented in memory device structure 100, with N-FET and P-FET transistors on alternating line structures. For example, the deck select transistors corresponding to channels 104 and 106 can be P-FETs or N-FETs, the deck select transistors corresponding to channels 118 and 120 can be N-FETs or P-FETs, the deck select transistors corresponding to channels 148 and 150 can be P-FETs or N-FETs, and the deck select transistors corresponding to channels 138 and 140 can be N-FETs or P-FETs.

[0072] It should be understood that in some embodiments, all memory cells within a given deck have the same structure, i.e., either the non-volatile memory elements are on the selector devices or vice versa.

[0073] 5B, the selector element 508 is above the non-volatile memory element 510. In other embodiments, the selector element 508 is below the non-volatile memory element 510. The non-volatile memory element 510 may include phase change memory, resistive random access memory (R-RAM), ovonic threshold switch (OTS) memory, or conductive bridge RAM.

[0074] Also, as shown, each of the memory cells 122, 124, 504, 106, 152, and 153 has a height H MC In the embodiment, the height H MC depends on the thickness and structure of each selector element 508 and non-volatile memory element 510 .

[0075] 5C shows a cross-sectional view of an exemplary non-volatile memory element 502 including a resistive random access memory (RRAM) device including an oxygen vacancy switch. In the embodiment shown, the RRAM material stack includes a bottom electrode 512, a switching layer 514 above the bottom electrode 512, an oxygen exchange layer 516 above the switching layer 514, and a top electrode 518 on the oxygen exchange layer 516.

[0076] In an embodiment, the bottom electrode 512 comprises an amorphous layer. In an embodiment, the bottom electrode 512 is a topologically smooth electrode. In an embodiment, the bottom electrode 512 comprises a material such as W, Ta, TaN, or Sn. In an embodiment, the bottom electrode 512 is composed of Ru layers interleaved with Ta layers. In an embodiment, the bottom electrode 512 has a thickness between 20 nm and 50 nm. In an embodiment, the top electrode 518 comprises a material such as W, Ta, TaN, or Sn. In an embodiment, the top electrode 518 has a thickness between 120 nm and 70 nm. In an embodiment, the bottom electrode 512 and the top electrode 518 are the same metal, such as Ta or Sn.

[0077] The switching layer 514 may be, for example, a metal oxide containing atoms of oxygen and one or more metals such as, but not limited to, Hf, Zr, Ti, Ta, or W. In the case of titanium or hafnium, or tantalum, which has an oxidation state of +4, the switching layer 514 has the chemical composition MO X where O is oxygen and X is 2 or substantially close to 2. For tantalum, which has an oxidation state of +5, the switching layer 514 has the chemical composition MO X where O is oxygen and X is 5 or substantially close to 5. In an embodiment, the switching layer 514 has a thickness between 1 nm and 5 nm.

[0078] The oxygen exchange layer 516 acts as a source of oxygen vacancies or 2‐In an embodiment, the oxygen exchange layer 516 is composed of a metal such as, but not limited to, hafnium, tantalum, or titanium. In an embodiment, the oxygen exchange layer 516 has a thickness between 5 nm and 20 nm. In an embodiment, the thickness of the oxygen exchange layer 516 is at least twice that of the switching layer 514. In another embodiment, the thickness of the oxygen exchange layer 516 is at least twice that of the switching layer 514. In an embodiment, the RRAM device has a combined total thickness of the individual layers that is between 60 nm and 100 nm, and a width that is between 10 nm and 50 nm.

[0079] While an oxygen vacancy switch device is shown in FIG. 5C, the RRAM device may include other examples such as a phase change device.

[0080] 5D is a cross-sectional view of a memory element structure in which the RRAM device includes a phase-change layer. In an exemplary embodiment, non-volatile memory element 510 includes electrode layers 512 and 518 and an insulator layer 517 between electrode layers 512 and 518.

[0081] In some such embodiments, insulator layer 517 exhibits charge carrier tunneling behavior. In some such embodiments, insulator layer 517 comprises oxygen and a metal, such as, but not limited to, aluminum, hafnium, tantalum, and titanium. In further embodiments, insulator layer 517 is also doped with one or more metal atoms, such as, but not limited to, copper, silver, or gold atoms. In some such embodiments, insulator layer 517 is doped with one or more metal atoms, such as, but not limited to, copper, silver, or gold atoms, to a concentration between 2% and 10% (atomic). In embodiments, insulator layer 517 has a thickness between 2 nm and 5 nm.

[0082] In another embodiment, insulator layer 517 includes a threshold switch material, e.g., a phase change material. In some examples, insulator layer 517 may include a phase change material that exhibits at least two different electrical states characterized by two different resistances, such as a conductive state and a resistive state. In some examples, the phase change material exhibits at least two different material states, such as amorphous and crystalline, that correspond to two different resistance states. In embodiments, a phase change material that is entirely in the crystalline phase is conductive or resistive when the phase change material is in the amorphous state. However, by adjusting the relative extent of the crystalline and amorphous phases for a given amount of phase change material, the resistance of the phase change material can be adjusted. In embodiments, the resistance state of the phase change material may be set by heating and cooling the phase change material in a specific manner, for example, by applying a voltage bias between electrodes 512 and 518 to induce Joule heating.

[0083] In an embodiment, the phase change material includes Ge and Te. In an embodiment, the phase change material further includes Sb. In an embodiment, the phase change material includes a ternary alloy of Ge, Te, and Sb, such as Ge2Sb2Te5. In an embodiment, the phase change material includes a binary, ternary, or quaternary alloy including at least one element from the Group V periodic table, such as Te, Se, or S. In an embodiment, the phase change material includes a binary, ternary, or quaternary alloy having at least one of Te, Se, or S, the alloy further including an element from the Group V periodic table, such as Sb. In an embodiment, the phase change material includes a dopant, such as silver, indium, gallium, nitrogen, silicon, or germanium. In an embodiment, the dopant concentration is between 5% and 20% of the total composition of the phase change material. In an embodiment, the insulator layer 517 has a thickness (e.g., measured along the x-axis) of between 2 nm and 15 nm.

[0084] 5E is a cross-sectional view of a structure of a selector element 508 according to an embodiment of the present disclosure. As shown, the selector device includes a metal-insulator-metal (MIM) stack. The MIM stack of the selector element 510 includes a selector electrode 520 and an insulator layer 522 between the selector electrode 520 and the selector electrode 524.

[0085] In embodiments, insulator layer 522 comprises an Ovonic threshold switch material. In embodiments, the insulator comprises an alloy of Ge, As, and Se, such as GeAsSe, GeSe, or AsSe. In embodiments, the alloy Ge, As, and Se may include a dopant, such as As-doped GeSe, Ge-doped AsSe, or GeAsSe doped with In, Te, or Sb. In embodiments, insulator layer 522 has a thickness that depends on the material, and is between 5 nm and 20 nm. Electrodes 520 and 524 may comprise a material that is the same or substantially the same as the material of electrodes 512 and 518.

[0086] In another embodiment, the insulator layer 522 comprises a material capable of undergoing a reversible insulator-metal transition. In an embodiment, the transition is triggered by a thermal process or by an electrical process. In some such embodiments, the insulator layer 522 comprises oxygen and atoms of one or more metals, such as, but not limited to, niobium, vanadium, and tantalum. In some specific examples, the insulator layer 522 comprises vanadium dioxide (IV) VO2, vanadium oxide (V) VO5, or niobium oxide (V) Nb2O5. In one specific example, the insulator layer 522 comprises niobium oxide (V) Nb2O5 and may exhibit filamentary conduction. In an embodiment, the insulator layer 522 is amorphous. In an embodiment, the insulator layer 522 capable of undergoing an insulator-metal transition has a thickness between 5 nm and 20 nm.

[0087] In some embodiments where an insulator-metal transition occurs, insulator layer 522 further comprises a dopant, such as silver, copper, or gold. In embodiments, the dopant concentration is between 0.1 and 10% of the total composition of insulator layer 522. A dopant concentration between 0.1 and 10% may promote filamentary conduction.

[0088] In embodiments, selector electrodes 520 and 524 include a conductive material such as tin and TaN, or a metal such as Ta, W, or Pt. In embodiments, selector electrodes 520 and 524 have a thickness between 5 nm and 20 nm. Electrodes 520 and 524 may or may not have the same thickness.

[0089] FIG. 6 illustrates a method 600 for fabricating the deck select transistor 200 or 304 in FIGS. 2A-2D and 3A-3C according to an embodiment of the present disclosure. Method 600 begins at step 610 with forming a plurality of vias in a dielectric above a substrate. Method 600 continues at step 620 with forming a plurality of lines above each of the plurality of vias. Method 600 continues at step 630 with a process of oxidizing a portion of each of the lines in the plurality of lines to form an oxidized region within each of the plurality of lines, spaced apart from the via. Method 600 continues at step 640 with forming a transistor channel material on the oxidized region of each of the lines. Method 600 concludes at step 650 with forming a gate structure on the channel material of each of the plurality of lines.

[0090] 7A is a cross-sectional view of a terminal interconnect array 700 formed in a dielectric 702 above a substrate 704 in accordance with an embodiment of the present disclosure. In an embodiment, a plurality of vias are patterned in the dielectric 702 by a masking and etching process. After the formation of the plurality of vias, a liner layer followed by a fill metal is deposited in the plurality of vias, and a planarization process is performed to form terminal interconnects 155, 156, 706, and 708. In an embodiment, the dielectric 702 comprises silicon and one or more of oxygen, nitrogen, or carbon, and the patterning process comprises plasma etching. In an embodiment, the terminal interconnects 706 and 708 comprise the same material as the material of the terminal interconnects 155 and 156.

[0091] 7B is an isometric view of a terminal interconnect array 700 formed in a dielectric 702 above a substrate 704. In an embodiment, each terminal interconnect in the terminal interconnect array 700 has a substantially rectangular outline in plan view. In other embodiments, the outline in plan view may be circular or oval.

[0092] Figure 8A shows the structure of Figure 7A following the formation of a plurality of line segments 800 above substrate 704. In an embodiment, each line segment 801 of the plurality of line segments 800 includes a conductive line 802, a hard mask 804, a dielectric 806, and a hard mask 808 on the dielectric 806.

[0093] In an embodiment, a material layer stack of multiple line segments 801 is deposited on the dielectric 702 and on the terminal interconnect 700. In an embodiment, forming the material layer stack includes depositing a first layer of hard mask material on the conductive layer, depositing a dielectric layer on the layer of hard mask material, and depositing a second layer of hard mask material on the dielectric layer. A resist mask may be formed on the second layer of hard mask material, and the material layer stack is patterned. In an embodiment, the patterning process includes a plasma etching process. Individual layers in the material layer stack are patterned to form multiple line segments 800. The second layer of hard mask material is patterned to form hard mask 808, the dielectric layer is patterned to form dielectric 806, the first layer of hard mask material is patterned to form hard mask 804, and the conductive layer is patterned to form conductive line 802. As shown, portions of the dielectric 702 are also recessed during the patterning process. It should be understood that terminal interconnects 700 are not exposed during the patterning process. In the exemplary embodiment, four line segments 801 are shown. The formation of the four line segments 801 creates openings 809 between each line segment 801. The number of lines in line segments 800 equals the number of word lines or bit lines in the memory array.

[0094] In an embodiment, hard masks 804 and 808 include silicon and one or more of oxygen, nitrogen, or carbon. In an embodiment, dielectric 806 includes silicon and one or more of oxygen, nitrogen, or carbon. In an exemplary embodiment, dielectric 806 includes silicon and one or more of oxygen or carbon. In an embodiment, conductive line 802 includes the material of line 104. Figure 8B is an isometric view of the structure in Figure 8A.

[0095] FIG. 9 illustrates the structure of FIG. 8B following the formation of dielectric 810 in each opening 809 to form block 900. In an embodiment, dielectric 810 is deposited within opening 809. The deposition process may include plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or chemical vapor deposition (CVD) processes. In an embodiment, the dielectric includes silicon and nitrogen and / or carbon. In an embodiment, dielectric 810 is planarized. In an embodiment, a chemical mechanical polishing (CMP) process is utilized to planarize dielectric 810, forming a top surface 810A that is substantially coplanar with top surface 808A of hard mask 808.

[0096] 10A shows the structure of FIG. 9 following a process to etch a portion of block 900. In an embodiment, a plasma etching process is utilized to etch dielectric 810 and a portion of each line segment 801 to form portions 1000A and 1000B of block 900. Region 1002 between the two portions 1000A and 1000B exposes line structure 802.

[0097] In an embodiment, a plasma etching process etches hard mask 808, dielectric 806, and hard mask 804, exposing the top surface of dielectric 702 adjacent conductive line 802. A subsequent etching process is utilized to recess the upper and lateral portions of conductive line 802. In an embodiment, a combination of wet chemical and plasma etching processes is utilized to form the lateral and vertical recesses.

[0098] After the etching process, exposed region 1002 is partially masked, and an oxidation process is performed. In an embodiment, the sacrificial mask comprises a material that is not corroded by plasma oxidation or a wet chemical process. The mask outline is defined by dashed line 1004. The mask forms an opening over a portion of region 1002. In an embodiment, plasma oxidation or a wet chemical process is utilized to oxidize a portion of conductive line 802 within region 1002. The oxidation process forms oxidized line portion 802A between line portions 802B and 802C, which are conductive. After the oxidation process, the sacrificial mask is removed. The length (along the x-axis) of line portion 802A depends on the desired gate length of the transistor being formed. In an embodiment, if conductive line 802 comprises a pure metal such as W, Ta, Ti, or Ru, or an alloy of a metal such as WN, Sn, or Sn, line portion 802A is oxidized sufficiently to become non-conductive.

[0099] 10B is a cross-sectional view taken along line A-A' of the structure in FIG. 10A. A cross-section of line segment 802A is shown. A cross-section of an unetched portion of conductive line 802 (shown by a dashed line) is superimposed to show the relative size between conductive line 802 and line segment 802A. As shown, line segment 802A has a width W A From smaller width W C The width W decreases laterally. C corresponds to the width of the unetched portion of the conductive line 802. The height of the line portion 802A decreases from H1 to H2. The decrease in height may be between 5 nm and 20 nm.

[0100] FIG. 11A illustrates the structure of FIG. 10A following the formation of a thin film channel material (here, channel material) 1100 over line portions 802A, 802B, and 802C of each conductive line 802 in region 1002. In an embodiment, a mask (not shown) is formed on the structure of FIG. 10A. A PVD, PEVCD, or CVD deposition process may be utilized to deposit channel material 1100. In an embodiment, channel material 1100 comprises a material that is the same or substantially the same as the material of channel 108. In an embodiment, channel material 1100 is deposited on all surfaces of line portions 802A, 802B, and 802C exposed by the mask. Channel material 1100 is also deposited on exposed surfaces of dielectric 702. In an embodiment, channel material 1100 is deposited to a thickness of between 5 nm and 20 nm.

[0101] Figure 11B is a cross-sectional view taken along line A-A' (through line segment 802A) of the structure in Figure 11A. In an exemplary embodiment, channel material 1100 is conformally deposited on the sidewalls and top surface of line segment 802A.

[0102] 12A is a cross-sectional view of the structure in FIG. 11B following a process for removing a portion of channel material 1100 above dielectric 702 and adjacent line portion 802A. In an embodiment, a mask 1200 (inner dashed line 1200) is patterned over the portion of channel material 1100 above line portion 802A. In an embodiment, a plasma etching process is utilized to etch away the exposed portion of channel material 1100 not covered by mask 1200. The plasma etching process adjacent each line portion 802A (and on portions 802B and 802C that are in and out of the plane of the figure) forms channel 1202. It should be understood that the process of isolating each channel associated with each conductive line 802 enables each conductive line 802 to selectively program a memory cell within a memory device structure.

[0103] In some embodiments, the channel material 1100 is also removed from the top surface of each line segment 802A, as shown in Figure 12B. The masking and etching processes used above in connection with Figure 12A may be used to form openings above the top surface of each line segment 802A. As shown, the plasma etching process forms channels 1202 adjacent the sidewalls of the line segments 802A.

[0104] FIG. 13A illustrates the structure of FIG. 11B following the formation of gate dielectric layer 1300. In an embodiment, gate dielectric layer 1300 comprises a material that is the same or substantially the same as that of gate dielectric layer 202A. In an embodiment, gate dielectric layer 1300 is blanket deposited on the structure of FIG. 11B by an atomic layer deposition (ALD) or PVD process. In an embodiment, the gate dielectric layer is conformally deposited on channel 1202 (hidden in the figure), dielectric 702, line portions 802B and 802C (hidden in the figure), and the sidewalls of each line segment 801 exposed in portion 1002; as shown, gate dielectric layer 1300 is also deposited on portions 1000A and 1000B.

[0105] Figure 13B is a cross-sectional view taken along line A-A' of the structure in Figure 13 A. As shown, a gate dielectric layer 1300 is conformally deposited around the channel 1202.

[0106] 14A shows the structure of FIG. 13A following the formation of a gate electrode 1400. In an embodiment, the material of the gate electrode 1400 is blanket deposited on the gate dielectric layer 1300.

[0107] In an embodiment, the material of the gate electrode 1400 is planarized. The planarization process may include, for example, a chemical mechanical polishing (CMP) process. In an exemplary embodiment, the CMP process removes material of the gate electrode 1400 and the gate dielectric layer 1300 in regions 1000A and 1000B and forms the gate electrode 1400 in region 1002. In an embodiment, the process of forming the gate electrode 1400 is complete with a process of forming a thin film transistor 1402 having one or more of the characteristics described in connection with FIGS. 2A-2D . The planarization process is fully selective to the hard mask 808. As shown, the CMP process does not remove the hard mask 808 from above each line segment 801. The hard mask 808 also serves as a polish stop during the fabrication process.

[0108] Figure 14B is a cross-sectional view taken along line A-A' of the structure in Figure 14A. In an exemplary embodiment, gate electrode 1400 extends continuously across each channel 1202 covering each line portion 802A. It should be understood that in operation, gate electrode 1400 can activate each channel 1202 above each line portion 802A as needed.

[0109] 14A , in embodiments, in subsequent steps, materials for fabricating memory cells above each line structure can be deposited after removing hard mask 808, dielectric 806, and hard mask 804 from above each conductive line 802. In some embodiments, a dielectric can be blanket deposited over the structure of FIG. 14A , and via openings can be formed to fabricate RRAM devices.

[0110] In other examples, transistor 306 may be fabricated with modifications to the process flows described in connection with Figures 7A-14B. In one embodiment, Figure 15A shows the structure of Figure 9, where an ALD deposition process is utilized to selectively deposit thin film transistor channel material (channel material) 1500 around line portion 802A (hidden in the figure) and portions of line structure portions 802B and 802C not covered by a mask. In some such embodiments, the deposition process utilizes precursors that can advantageously nucleate on oxidized metal material.

[0111] Figure 15B is a cross-sectional view of the structure in Figure 15A taken along line A-A'. As shown, a deposited TFT channel material 1500 is deposited to entirely cover line portion 802A to form individual channels 1500. The method of forming the gate electrode is substantially identical to one or more process steps described in connection with Figures 10A-14B.

[0112] In another example, a transistor, such as transistor 400 described in connection with FIG. 4A, can be fabricated with modifications to the process flow described in connection with FIG. 7A-FIG. 14B. FIG. 16A shows the structure of FIG. 9 following the formation of multiple openings 1600 in region 1002. In an exemplary embodiment, multiple openings 1600 are formed by fully etching line segment 801 across the entire surface.

[0113] 16B shows the structure of FIG. 16A after forming a sacrificial dielectric 1604 in each opening 1600 on the dielectric 702, followed by forming a channel layer 1606 on the dielectric 1604 in each of the plurality of openings 1600. Portion 1602 of region 1002 is clearly shown. In embodiments, the dielectric is deposited by an ALD process. In embodiments, channel layer 1606 is deposited or grown on channel layer 1606. In embodiments, channel layer 1606 comprises a material that is the same or substantially the same as the material of channel layer 404. In embodiments, dielectric 1604 comprises a material that is the same or substantially the same as the material of dielectric 702. In embodiments, the lateral thickness of opening 1600 (along the y-axis) and the deposited thickness of dielectric 1604 can be controlled to obtain a desired lateral thickness (y-axis) of channel layer 1606.

[0114] 16C shows the structure of FIG. 16D following a process to reduce the height of the channel layer 1606. In an embodiment, the dielectric 1604 and the channel layer 1606 are recessed by a plasma etching process, a wet chemical etching process, or a combination thereof. As shown, the dielectric 1604 and the channel layer 1606 are recessed by a thickness T1 relative to a top surface 1606A of the channel layer 1606. The channel layer 1606 may be recessed vertically prior to recessing the dielectric to prevent a lateral reduction in the thickness of the channel layer 1606. The channel layer 1606 is recessed to a desired height H of the fin structure to be formed. F As shown, the top surface 1606B of the channel layer 1606 is substantially planar. In some embodiments, the top edge portion of the channel layer 1606 is rounded.

[0115] The process of selectively recessing dielectric 1604 and channel layer 1606 may be performed after masking region 1000A and portion 1602A of region 1602. In an exemplary embodiment, the exposed portions of dielectric 810 in region 1602 are removed after recessing dielectric 1604 and channel layer 1606.

[0116] In an embodiment, the exposed sidewalls of dielectric 1604A are removed prior to the formation of the gate structure in the next step.

[0117] FIG. 16D shows the structure of FIG. 16C following the formation of gate dielectric layer 1610 after removing exposed sidewalls of dielectric 1604B (shown in FIG. 16C). Gate dielectric layer 1610 comprises a material that is the same or substantially the same as that of gate dielectric layer 202A. In an exemplary embodiment, the gate dielectric layer is conformally deposited on dielectric 702 and around channel layer 1606 adjacent to the portion of dielectric 1604 below channel 1606. Gate dielectric layer 1610 is also deposited on top of hard mask 808 (hidden in the figure) and dielectric 810 on the top surface of channel layer 1606A and on the adjacent dielectric 1604. In an embodiment, gate dielectric layer 1610 is deposited to a thickness of between 1 nm and 10 nm by an ALD process.

[0118] Figure 16E shows the structure of Figure 16D following the formation of gate electrode 1612 on gate dielectric layer 1610. In an embodiment, the process for forming gate electrode 1612 is the same or substantially the same as the process utilized to form gate electrode 1400. In an embodiment, the material of gate electrode 1612 is blanket deposited on gate dielectric layer 1610 and planarization is performed. In an exemplary embodiment, the planarization process insulates gate electrode 1612 but does not remove gate dielectric layer 1610.

[0119] Figure 16F shows the structure of Figure 16E following a process to remove a portion of gate dielectric layer 1610. In an embodiment, the gate dielectric layer is removed from over hard mask 808, from over dielectric 810, and from over a portion of dielectric 1604 and channel layer 1606 in region 1602A. In an exemplary embodiment, dielectric 1604 and channel layer 1606 in region 1602A are etched and removed after removing gate dielectric layer 1610 in region 1602A. An opening 1614 is formed in region 1602 adjacent to region 1602B.

[0120] FIG. 16G shows the structure of FIG. 16F following the formation of source structures 1616 adjacent each channel 1606 in region 1602B. In an embodiment, source structures 1616 include a material, such as the material of line 802, to prevent the formation of a barrier junction between line 802 and source structure 1616. The source structure may have a height above or below conductive line 802. Dielectric 810 is not shown for clarity. While only the formation of source structure 1616 has been shown, a drain structure is simultaneously formed on the opposite side of the source structure during the fabrication process. Transistor 1620 is an example of a FinFET transistor and has one or more features of transistor 400 described in connection with FIG. 4B.

[0121] 17 is an isometric view of a system 1700 in which a memory device structure including a plurality of deck select transistors, e.g., memory device structure 100, is coupled by a plurality of logic decoder transistors and programming transistors. In an exemplary embodiment, lines 134 and 144 are coupled by decoder transistors 1702 and 1704, respectively. Although not shown, each line structure in line structures 132 and 142 and deck 130 are coupled with a decoder transistor. In an exemplary embodiment, line structures 102 and 112 are coupled to decoder transistors via line structures 132 and 142, respectively. In some such embodiments, the total number of decoder transistors, e.g., decoder transistors 1702 or 1704, is equal to the total number of line structures in each of the plurality of line structures 132 and 142.

[0122] In an exemplary embodiment, each of gate structures 166, 168, 172, and 174 is independently coupled to a logic programming transistor 1706, 1708, 1710, and 1712, respectively. In some such embodiments, the total number of programming transistors is equal to the total number of independent gate structures in memory device structure 100.

[0123] 18 is a block diagram of an example system 1800 including deck select transistors in a memory device structure that enables print scaling of decoder transistors. System 1800 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device, or other mobile or embedded computing device. It will be understood that some components are shown generically and that not all components of such a device are shown in system 1800.

[0124] The memory 1862 includes a memory device structure 100, such as for the example memory device structure of FIG. 1. In one example, the deck select transistor 1890 represents a deck select transistor according to any example provided herein. The deck select transistor 1890 allows the memory 1862 to provide selection of a target cell within the memory array. The use of the described deck select transistor allows for selection with lower energy utilization compared to conventional decoder transistors.

[0125] System 1800 includes a processor 1810, which performs the primary processing operations of system 1800. Processor 1810 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations performed by processor 1810 include running an operating platform or operating system on which applications and device functions run. The processing operations may include operations related to I / O (input / output) with a human user or other device, operations related to power management, operations related to connecting system 1800 to another device, or a combination thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interfacing methods, or a combination thereof. Processor 1810 may execute data stored in memory. Processor 1810 may write or edit data stored in memory.

[0126] In one example, system 1800 includes one or more sensors 1812. Sensors 1812 may represent embedded sensors or interfaces, external sensors, or a combination. Sensors 1812 enable system 1800 to monitor or detect one or more conditions of the environment or device in which system 1800 is implemented. Sensors 1812 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors or combinations. Sensors 1812 may also include sensors for biometric systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user characteristics. Sensors 1812 should be understood broadly and are not limited to the many different types of sensors that may be implemented with system 1800. In one example, the one or more sensors 1812 couple to the processor 1810 via front-end circuitry integrated into the processor 1810. In one example, the one or more sensors 1812 couple to the processor 1810 via another component of the system 1800.

[0127] In one example, system 1800 includes audio subsystem 1820, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. Audio functionality can include speaker or headphone output and microphone input. Devices for such functionality can be integrated into or connected to system 1800. In one example, a user interacts with system 1800 by providing audio commands that are received or processed by processor 1810.

[0128] Display subsystem 1830 represents hardware (e.g., display devices) and software components (e.g., drivers) that provide visual displays for presentation to a user. In one example, the display includes a tactile component or touchscreen element through which a user interacts with the computing device. Display subsystem 1830 includes display interface 1832, which includes the specific screen or hardware device used to provide the display to the user. In one example, display interface 1832 includes logic (e.g., a graphics processor) separate from processor 1810 that executes at least some processes related to the display. In one example, display subsystem 1830 includes a touchscreen device that provides both output and input to the user. In one example, display subsystem 1830 includes a high-definition (HD) display or an ultra-high-definition (UHD) display that provides output to the user. In one example, the display subsystem includes or drives a touchscreen display. In one example, display subsystem 1830 generates display information based on data stored in memory, based on processes performed by processor 1810, or both.

[0129] I / O controller 1840 represents hardware devices and software components involved in interaction with a user. I / O controller 1840 can operate to manage hardware that is part of audio subsystem 1820 or display subsystem 1830, or both. Additionally, I / O controller 1840 represents connection points for additional devices that connect to system 1800 through which a user may interact with the system. For example, devices that can be attached to system 1800 can include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use with specific applications, such as a card reader or other device.

[0130] As described above, I / O controller 1840 can interact with audio subsystem 1820, display subsystem 1830, or both. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of system 1800. Furthermore, audio output can be provided instead of or in addition to display output. In another example, if the display subsystem includes a touchscreen, the display device can also function as an input device and be managed at least in part by I / O controller 1840. Additionally, additional buttons or switches can be present on system 1800 to provide I / O functions managed by I / O controller 1840.

[0131] In one example, I / O controller 1840 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware that may be included in system 1800 or sensors 1812. The inputs may be part of direct user interaction, as well as provide environmental input to the system to affect system operation (such as filtering for noise, adjusting a display for brightness detection, applying a camera flash, or other functions).

[0132] In one example, system 1800 includes power management 1850, which manages battery power usage and features related to battery charging and power-saving operation. Power management 1850 manages power from a power source 1852, which provides power to components of system 1800. In one example, power source 1852 includes an AC-DC (alternating current-to-direct current) adapter for plugging into a wall outlet. Such AC power can be renewable energy (e.g., solar power, motion-based power). In one example, power source 1852 includes only DC power, which can be provided by a DC power source such as an external AC-DC converter. In one example, power source 1852 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, power source 1852 can include an internal battery or a fuel cell power source.

[0133] Memory subsystem 1860 includes memory device(s) 1862 for storing information in system 1800. Memory subsystem 1860 may include non-volatile (state remains unchanged when power to the memory device is interrupted) or volatile (state is indeterminate when power to the memory device is interrupted) memory devices, or a combination thereof. Memory 1860 may store application data, user data, music, photos, documents, or other data and system data (whether long-term or temporary) related to the execution of applications and functions of system 1800. In one example, memory subsystem 1860 includes memory controller 1864 (which may also be considered part of the control of system 1800 and potentially part of processor 1810). Memory controller 1864 includes a scheduler that generates and issues commands to control access to memory device 1862.

[0134] Connections 1870 include hardware devices (e.g., wireless or wired connectors and communications hardware or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) that allow system 1800 to communicate with external devices. External devices can be other computing devices, separate devices such as wireless access points or base stations, and peripherals such as headsets, printers, or other devices. In one example, system 1800 exchanges data with external devices for storage in memory or display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory, for reading, writing, or editing data.

[0135] Connection 1870 can include multiple different types of connections. For generalization, system 1800 is illustrated with cellular connection 1872 and wireless connection 1874. Cellular connection 1872 generally refers to a cellular network connection provided by a wireless carrier via, for example, GSM (Global System for Mobile Communications) or variations or derivatives, CDMA (Code Division Multiple Access) or variations or derivatives, TDM (Time Division Multiplexing) or variations or derivatives, LTE (Long Term Evolution—also referred to as “4G”), or other cellular service standards. Wireless connection 1874 refers to a non-cellular wireless connection and may include a personal area network (e.g., Bluetooth), a local area network (e.g., WiFi), or a wide area network (e.g., WiMAX), or other wireless communications, or a combination. Wireless communication refers to the transfer of data through the use of modulated electromagnetic radiation over a non-solid medium. Wired communication occurs over a solid communication medium.

[0136] Peripheral connections 1880 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) that make the peripheral connections. It is understood that system 1800 can be a peripheral device to other computing devices (“to”) 1882, as well as have peripheral devices connected to it (“from”) 1884. System 1800 typically has a “docking” connector for connecting to other computing devices, such as for purposes of managing (e.g., downloading, uploading, modifying, synchronizing) content on system 1800. Additionally, the docking connector may enable system 1800 to connect to certain peripherals that, for example, allow system 1800 to control the output of content to audiovisual or other systems.

[0137] In addition to proprietary docking connectors or other proprietary connection hardware, system 1800 can make peripheral connections 1880 via generic or standards-based connectors. Generic types include Universal Serial Bus (USB) connectors (which can include any of several different hardware interfaces), DisplayPorts, including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), or other types.

[0138] 19 is a block diagram of an example computing system including deck select transistors in a memory device structure that enables print scaling of decoder transistors. System 1900 represents a computing device according to any example herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or other electronic device.

[0139] The system 1900 includes a memory device structure in a memory 1930, such as for the example memory device structure 100 of FIG. 1. In one example, the deck select transistors 1990 represent deck select transistors according to any of the examples provided herein. The deck select transistors 1990 enable the memory 1930 to provide selection of target cells within the memory device structure. The use of the described deck select transistors enables selection with lower energy utilization compared to conventional decoder transistors.

[0140] System 1900 includes processor 1910, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware or combination for providing processing or execution of instructions for system 1900. Processor 1910 controls the overall operation of system 1900 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0141] In one example, system 1900 includes an interface 1912 coupled to processor 1910 and may represent a high-speed or high-throughput interface for system components requiring a high-bandwidth connection, such as memory subsystem 1920 or graphics interface component 1940. Interface 1912 represents interface circuitry and may be a standalone component or may be integrated on the processor die. Interface 1912 may be integrated as circuitry on the processor die or may be integrated as a component of a system-on-chip. If present, graphics interface 1940 interfaces to a graphics component for providing a visual display to a user of system 1900. Graphics interface 1940 may be a standalone component or may be integrated on the processor die or on a system-on-chip. In one example, graphics interface 1940 can drive a high-definition (HD) display that provides output to a user. In one example, the display may include a touchscreen display. In one example, graphics interface 1940 generates a display based on data stored in memory 1930, or based on operations performed by processor 1910, or both.

[0142] Memory subsystem 1920 represents the main memory of system 1900 and provides storage for code executed by processor 1910 or data values ​​used in executing routines. Memory subsystem 1920 can include one or more memory devices 1930, such as one or more of various random access memories (RAMs), such as read-only memory (ROM), flash memory, DRAM, or other memory devices, or combinations of such devices. In some embodiments, memory subsystem 1920 includes persistent memory (PMem), which can provide higher RAM capacity than traditional DRAM. PMem may operate in a persistent mode, i.e., utilizes non-volatile devices (e.g., RRAM, PCM, CBRAM, etc.) integrated with selectors in a tiered architecture to store data without using power applied to memory subsystem 920 for non-volatile data storage. In other embodiments, memory subsystem 1920 includes a solid-state drive (SSD) residing in a NAND package for high-speed storage.

[0143] Memory 1930 stores and hosts, among other things, an operating system (OS) 1932 for providing a software platform for the execution of instructions within system 1900. Furthermore, applications 1934 can execute on the software platform of OS 1932 from memory 1930. Applications 1934 represent programs. Such programs have their own operating logic for performing one or more functions. Processes 1936 represent agents or routines that provide auxiliary functionality to OS 1932 or one or more applications 1934, or a combination. OS 1932, applications 1934, and processes 1936 provide the software logic for providing functionality to system 1900. In one example, memory subsystem 1920 includes memory controller 1922, which generates and issues commands to memory 1930. It is understood that memory controller 1922 can be a physical part of processor 1910 or a physical part of interface 1912. For example, memory controller 1922 may be an integrated memory controller that is integrated on a circuit with processor 1910, such as on a processor die or system-on-chip.

[0144] Although not specifically shown, it is understood that system 1900 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or the like. A bus or other signal line can communicatively or electrically couple components together, or both communicatively and electrically couple components. A bus can include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuit, or a combination. A bus can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other bus, or a combination.

[0145] In one example, system 1900 includes interface 1914, which can be coupled to interface 1912. Interface 1914 can be a lower speed interface than interface 1912. In one example, interface 1914 represents an interface circuit, which can include standalone components and integrated circuits. In one example, multiple user interface components, peripheral components, or both, couple to interface 1914. Network interface 1950 provides system 1900 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 1950 can include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a USB (Universal Serial Bus), or other wired or wireless standards-based or proprietary interface. Network interface 1950 can exchange data with remote devices, including sending data stored in memory or receiving data stored in memory.

[0146] In one example, system 1900 includes one or more input / output (I / O) interfaces 1960. I / O interface 1960 may include one or more interface components through which a user interacts with system 1900 (e.g., audio, alphanumeric, haptic / touch, or other interface modalities). Peripheral interface 1970 may include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that depend on and connect to system 1900. A dependent connection is one in which system 1900 provides a software or hardware platform, or both, on which operations execute and with which a user interacts.

[0147] In one example, system 1900 includes a storage subsystem 1980 that stores data in a nonvolatile manner. In one example, in some system implementations, at least some components of storage 1980 may overlap with components of memory subsystem 1920. Storage subsystem 1980 includes storage device 1984, which can be or can include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid-state, or optical-based disks, or a combination. Storage 1984 holds code or instructions and data 1986 in a persistent state (i.e., values ​​are retained even when power is interrupted to system 1900). Memory 1930 is typically execution or operating memory that provides instructions to processor 1910, although storage 1984 can collectively be considered "memory." While storage 1984 is nonvolatile, memory 1930 may include volatile memory (i.e., the value or state of the data is indeterminate when power is interrupted to system 1900). In one example, storage subsystem 1980 includes a controller 1982 that interfaces with storage 1984. In one example, controller 1982 can be a physical part of interface 1914 or processor 1910, or can include circuitry or logic in both processor 1910 and interface 1914.

[0148] The power source 1902 provides power to the components of the system 1900. More specifically, the power source 1902 typically interfaces with one or more power sources 1904 within the system 1902 to provide power to the components of the system 1900. In one example, the power source 1904 includes an AC-DC (alternating current-to-direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy (e.g., solar-powered) power source 1902. In one example, the power source 1902 includes a DC power source, such as an external AC-DC converter. In one example, the power source 1902 or the power source 1904 includes wireless charging hardware that charges via proximity to a charging magnetic field. In one example, the power source 1902 can include an internal battery or fuel cell power source.

[0149] Thus, one or more embodiments of the present disclosure generally relate to deck select transistors for 3D cross point memories and methods of fabrication.

[0150] In a first example, a memory device structure includes a first plurality of line structures, each individual line structure of the first plurality of line structures including a first transistor channel, and a second plurality of line structures substantially orthogonal to the first plurality of line structures, each individual line structure of the second plurality of line structures including a second transistor channel and a memory cell at each cross point between the first and second plurality of line structures.

[0151] In a second example, as described in any of the first examples, the first deck includes a first plurality of line structures and a second plurality of line structures. The memory device structure further includes a second deck above or below the first deck, the second deck including a third plurality of line structures substantially parallel to the first plurality of line structures, each individual line structure of the third plurality of line structures including a third transistor channel. The memory device structure further includes a fourth plurality of line structures substantially parallel to the second plurality of line structures, each individual line structure of the fourth plurality of line structures including a fourth transistor channel. A memory cell is located at each cross point between the third plurality of line structures and the fourth plurality of line structures. The device structure further includes a plurality of terminal interconnects between the first deck and the second deck, each of the plurality of terminal interconnects being coupled between an individual one of the line structures on the first deck and a corresponding individual one of the line structures on the second deck, and a transistor channel being between the individual one of the plurality of terminal interconnects and the memory cell.

[0152] In a third example, with respect to any of the first to second examples, the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures each include tungsten, tantalum, or titanium, or an alloy thereof further containing nitrogen.

[0153] In a fourth example, any of the first transistor channel, the second transistor channel, the third transistor channel, and the fourth transistor channel each include a polycrystalline or amorphous material.

[0154] In a fifth example, with respect to any of the first to fourth examples, the polycrystalline or amorphous material is In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, ZnRh2O4, or CuO x and x is 1 or 2.

[0155] In a sixth example, with respect to any of the first to fifth examples, each of the first, second, third, and fourth plurality of line structures includes a first portion and a second portion, each of the first and second portions including a metal, and a third portion located between the first and second portions and including a metal and oxygen.

[0156] In a seventh example, as with any of the sixth examples, the transistor channel covers the third portion.

[0157] In an eighth example, with respect to any of the first to seventh examples, the transistor channel extends above the top surface and below the bottom surface of the first or second portion.

[0158] In a ninth example, with respect to any of the first to eighth examples, each of the first, second, third, and fourth plurality of line structures includes a first portion and a second portion each including a metal, and a third portion located between the first and second portions, and the third portion includes a material for a transistor channel.

[0159] In a tenth example, related to any of the first to ninth examples, the third portion has a height greater than the height of the first portion or the height of the second portion.

[0160] In an eleventh example, with respect to any of the first to tenth examples, the individual transistor channels in the first plurality of line structures, the second plurality of line structures, the third plurality of line structures and the fourth plurality of line structures are electrically connected in parallel through gate structures.

[0161] In a twelfth example, with respect to any of the first to eleventh examples, the memory device structure further includes a memory cell at each cross point between the first plurality of line structures and the third plurality of line structures.

[0162] In a thirteenth example, related to any of the first to twelfth examples, the memory cell includes a non-volatile memory element coupled to the selector element.

[0163] In a fourteenth example, a method for fabricating a deck select transistor includes forming a conductive via above a substrate and forming an interconnect line structure above and coupled to the via, the via being coupled to a first portion of the line structure. The method further includes oxidizing a second portion of the line structure and depositing a channel material on a sidewall adjacent to the second portion of the line structure. The method further includes depositing a gate oxide layer on the channel material and forming a gate electrode on the gate oxide layer.

[0164] In a fifteenth example, with respect to any of the fourteenth examples, before the step of oxidizing the second portion of the line structure, the method includes the step of performing an etching process to reduce the lateral and vertical thicknesses of the line structure.

[0165] In a sixteenth example, with respect to any of the fourteenth and fifteenth examples, oxidizing the second portion of the line structure includes blocking electrical conductivity of the line structure.

[0166] In a 17th example, related to any of the 14th to 16th examples, the step of forming the channel includes a step of surrounding a second portion of each of the line structures in the plurality of interconnect line structures, and the step of forming the gate electrode includes a step of surrounding the channel.

[0167] In an 18th example, related to any of the 14th to 17th examples, the step of forming a channel further includes the steps of depositing a channel material on the top surface and sidewalls of the second portion of the line structure, and removing a portion of the channel material from the top surface.

[0168] In a nineteenth example, a system includes a processor, and the memory device structure includes a first plurality of line structures along a first direction, the first plurality of line structures including a first line structure adjacent to a second line structure, the first line structure including a first transistor channel, the second line structure including a second transistor channel, the memory device structure further includes a second plurality of line structures, the second plurality of line structures being substantially orthogonal to the first plurality of line structures along a second direction orthogonal to the first direction, the second plurality of line structures including a third line structure adjacent to a fourth line structure, the third line structure including a third transistor channel, and the fourth line structure including a fourth transistor channel. The memory device structure further includes a memory cell at each cross point between the first plurality of line structures and the second plurality of line structures, and a plurality of terminal interconnects, each of the plurality of terminal interconnects being coupled between each of the line structures and each of the plurality of logic transistors, and each of the transistor channels being between each of the plurality of terminal interconnects and the memory cell.

[0169] In a twentieth example, related to any of the nineteenth examples, the system further includes a memory controller coupled with the memory device structure. Other possible claims [Item 1] a first plurality of line structures, each individual line structure of the first plurality of line structures having a first transistor channel; a second plurality of line structures substantially orthogonal to the first plurality of line structures, each individual line structure of the second plurality of line structures having a second transistor channel; a memory cell at each cross point between the first plurality of line structures and the second plurality of line structures; A memory device structure comprising: [Item 2] a first deck having the first plurality of line structures and the second plurality of line structures, and the memory device structure further comprising a second deck above or below the first deck, the second deck comprising: a third plurality of line structures substantially parallel to the first plurality of line structures, each individual line structure of the third plurality of line structures including a third transistor channel; a fourth plurality of line structures substantially parallel to the second plurality of line structures, each individual line structure of the fourth plurality of line structures including a fourth transistor channel; a memory cell at each cross point between the third plurality of line structures and the fourth plurality of line structures; and The memory device structure further comprises a plurality of terminal interconnects between the first deck and the second deck, each of the plurality of terminal interconnects being coupled between each of the line structures on the first deck and a corresponding one of the line structures on the second deck; Item 2. The memory device structure of item 1, wherein each of the transistor channels is between each of the plurality of terminal interconnects and the memory cell. [Item 3] 3. The memory device structure of item 2, wherein the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures each comprise tungsten, tantalum, or titanium, or an alloy thereof further containing nitrogen. [Item 4] 3. The memory device structure of claim 2, wherein the first transistor channel, the second transistor channel, the third transistor channel, and the fourth transistor channel each comprise a polycrystalline or amorphous material. [Item 5] The polycrystalline or amorphous materials include In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, InWO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, and CuO x Item 5. The device structure according to item 4, comprising NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, ZnRh2O4. [Item 6] Each of the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures comprises: a first portion and a second portion, each of the first portion and the second portion comprising a metal; a third portion between the first portion and the second portion, the third portion including the metal and oxygen; and Item 3. The memory device structure of item 2, wherein each of the corresponding transistor channels is adjacent to a sidewall of the third portion. [Item 7] Item 7. The memory device structure of item 6, wherein the transistor channel covers the third portion. [Item 8] Item 8. The memory device structure of item 7, wherein the transistor channel extends above a top surface and below a bottom surface of the first portion or the second portion. [Item 9] Each of the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures comprises: a first portion and a second portion, each of which comprises a metal; a third portion between the first portion and the second portion, the third portion including material of the transistor channel; and Item 3. The memory device structure of item 2, having: [Item 10] Item 9. The memory device structure of item 8, wherein the third portion has a height greater than a height of the first portion or a height of the second portion. [Item 11] 3. The memory device structure of item 2, wherein the individual transistor channels in the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures are electrically connected in parallel through gate structures. [Item 12] Item 3. The memory device structure of item 2, further comprising a memory cell at each cross point between the first and third plurality of line structures. [Item 13] Item 3. The memory device structure of item 2, wherein the memory cell has a non-volatile memory element coupled to a selector element. [Item 14] 1. A method of fabricating a deck select transistor, comprising: The above method is forming a conductive via above a substrate; forming an interconnect line structure above and connected to the via, the via being connected to a first portion of the line structure; oxidizing a second portion of the line structure; depositing a channel material on a sidewall adjacent the second portion of the line structure; depositing a gate oxide layer over the channel material; forming a gate electrode on the gate oxide layer; A method for providing the above. [Item 15] Item 15. The method according to item 14, wherein before the step of oxidizing the second portion of the line structure, the method further comprises the step of performing an etching process to reduce lateral and vertical thicknesses of the line structure. [Item 16] Item 15. The method according to item 14, wherein oxidizing the second portion of the line structure comprises blocking electrical conductivity of the line structure. [Item 17] Item 15. The method of item 14, wherein forming the channel comprises surrounding the second portion of each of the line structures in the plurality of interconnect line structures, and forming the gate electrode comprises surrounding the channel. [Item 18] Item 15. The method of item 14, wherein forming the channel further comprises depositing the channel material on a top surface and a sidewall of the second portion of the line structure; and removing a portion of the channel material from the top surface. [Item 19] a processor; Memory device structure and Equipped with The memory device structure is a first plurality of line structures, each individual line structure of the first plurality of line structures having a first transistor channel; a second plurality of line structures substantially orthogonal to the first plurality of line structures, each individual line structure of the second plurality of line structures having a second transistor channel; a memory cell at each cross point between the first plurality of line structures and the second plurality of line structures; a plurality of terminal interconnects, each of which is coupled between a respective one of the line structures and a respective one of the logic transistors, and each of which is between the respective one of the plurality of terminal interconnects and the memory cell; A system comprising: [Item 20] 20. The system of claim 19, further comprising a memory controller coupled to the memory device structure.

Claims

1. A memory device structure, comprising: a first plurality of line structures, each individual line structure of the first plurality of line structures having a first transistor channel; a second plurality of line structures substantially orthogonal to the first plurality of line structures, each individual line structure of the second plurality of line structures having a second transistor channel; a memory cell at each cross point between the first plurality of line structures and the second plurality of line structures; Equipped with a first deck having the first plurality of line structures and the second plurality of line structures, and the memory device structure further comprising a second deck above or below the first deck, the second deck comprising: a third plurality of line structures substantially parallel to the first plurality of line structures, each individual line structure of the third plurality of line structures including a third transistor channel; a fourth plurality of line structures substantially parallel to the second plurality of line structures, each individual line structure of the fourth plurality of line structures including a fourth transistor channel; a memory cell at each cross point between the third plurality of line structures and the fourth plurality of line structures; and The memory device structure further comprises a plurality of terminal interconnects between the first deck and the second deck, each of the plurality of terminal interconnects being coupled between each of the line structures on the first deck and a corresponding one of the line structures on the second deck; a respective one of the first transistor channel, the second transistor channel, the third transistor channel, and the fourth transistor channel is between a respective one of the plurality of terminal interconnects and the memory cell;

2. The first plurality of line structures extend in a first direction, and the second plurality of line structures extend in a second direction perpendicular to the first direction; the first transistor channel and the third transistor channel at least partially overlap each other when viewed in a third direction perpendicular to the first direction and the second direction; the second transistor channel and the fourth transistor channel at least partially overlap each other when viewed from the third direction; The memory device structure of claim 1 .

3. 3. The memory device structure of claim 1, wherein the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures each comprise tungsten, tantalum, or titanium, or an alloy thereof further containing nitrogen.

4. 4. The memory device structure of claim 1, wherein the first transistor channel, the second transistor channel, the third transistor channel, and the fourth transistor channel each comprise a polycrystalline or amorphous material.

5. The polycrystalline or amorphous material may be In ２ O ３ , Ga ２ O ３ , ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, InWO, GaZnMg O, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, CuO ｘ , NbO, NiO, CoO, SnO, Cu ２ O, AgAlO, CuAlO ３ , AlScOC, Sr ３ BPO ３ , La ２ SiO ４ Se, LaCuSe, Rb ２ Sn ２ O ３ , La ２ O ２ S ２ , K. ２ Sn ２ O ３ , Na ２ FeOSe ２ , ZnRh ２ O ４ 5. The memory device structure of claim 4, comprising:

6. Each of the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures comprises: a first portion and a second portion, each of the first portion and the second portion comprising a metal; a third portion between the first portion and the second portion, the third portion including the metal and oxygen; and 6. The memory device structure of claim 1, wherein each of the first transistor channel, the second transistor channel, the third transistor channel, and the fourth transistor channel is adjacent to a sidewall of a corresponding third portion.

7. The memory device structure of claim 6 , wherein the transistor channel overlies the third portion.

8. The memory device structure of claim 7 , wherein the transistor channel extends above a top surface and below a bottom surface of the first portion or the second portion.

9. The memory device structure of claim 8 , wherein the third portion has a height greater than a height of the first portion or a height of the second portion.

10. Each of the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures comprises: a first portion and a second portion, each of which comprises a metal; a third portion between the first portion and the second portion, the third portion including material of the transistor channel; and 10. The memory device structure of claim 1, wherein:

11. 10. The memory device structure of claim 1, wherein individual transistor channels in the first plurality of line structures, the second plurality of line structures, the third plurality of line structures, and the fourth plurality of line structures are electrically coupled in parallel through gate structures.

12. The memory device structure of claim 1 further comprising a memory cell at each cross point between the first and third plurality of line structures.

13. A semiconductor device comprising: a first plurality of line structures, each of said first plurality of line structures having a first transistor channel; a second plurality of line structures substantially orthogonal to the first plurality of line structures, each individual line structure of the second plurality of line structures having a second transistor channel; a memory cell at each cross point between the first plurality of line structures and the second plurality of line structures; Equipped with Each of the first plurality of line structures and each of the second plurality of line structures comprises: a first portion and a second portion, each of the first portion and the second portion comprising a metal; a third portion between the first portion and the second portion, the third portion including the metal and oxygen; and The memory device structure, wherein each of the first transistor channel and the second transistor channel is adjacent a sidewall of a corresponding third portion.

14. A semiconductor device comprising: a first plurality of line structures, each of said first plurality of line structures having a first transistor channel; a second plurality of line structures substantially orthogonal to the first plurality of line structures, each individual line structure of the second plurality of line structures having a second transistor channel; a memory cell at each cross point between the first plurality of line structures and the second plurality of line structures; Equipped with Each of the first plurality of line structures and each of the second plurality of line structures comprises: a first portion and a second portion, each of which comprises a metal; a third portion between the first portion and the second portion, the third portion including a material of a corresponding one of the first transistor channel and the second transistor channel; and 1. A memory device structure comprising:

15. 15. The memory device structure of claim 1, wherein the memory cell comprises a non-volatile memory element coupled to a selector element.

16. a processor; A memory device structure according to any one of claims 1 to 15. A system comprising:

17. 17. The system of claim 16, further comprising a memory controller coupled with the memory device structure.

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