Signal generating device and signal generating method

Abstract

To provide a signal generating device and a signal generating method that can significantly increase an adjustable maximum phase difference between signals output from a plurality of transceivers.SOLUTION: A signal generating device includes a phase acquisition processing unit 31b for acquiring a voltage value measured by a phase detection unit while changing, from an initial value, the phase of a toggle pattern output from each transceiver, a phase difference calculation processing unit 31c for calculating an initial phase difference between a divided clock or external clock selected by a clock selection unit and an initial value of the phase of the toggle pattern based on the relationship between the voltage value acquired by the phase acquisition processing unit 31b and the amount of change from the initial value of the phase of the toggle pattern, and a phase movement processing unit 31d for moving the phase of the toggle pattern from the initial value by the initial phase difference such that the phase difference between the divided clock or external clock selected by the clock selection unit and the toggle pattern is within a predetermined range.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a signal generating device and a signal generating method, and more particularly to a signal generating device and a signal generating method that include a transceiver that converts parallel data into high-speed serial data and outputs the converted data. [Background technology]

[0002] As communication standards such as Ethernet® 800GbE (Gigabit Ethernet) and PCIe® (Peripheral Component Interconnect Express) Gen (Generation) 6 become faster, signal transmission methods are no longer simple binary digital signals such as NRZ (Non Return to Zero), but are now typified by PAM (Pulse Amplitude Modulation) 4. It is expected that transmission methods such as PAM8 and PAM16 will be standardized in the future. When developing or testing products that use these signals, a test signal source is required.

[0003] Such signal sources should naturally be able to generate signals such as PAM4 and PAM8, but it is also desirable that they be able to generate signals that have passed through a specific transmission path, or signals that have been subjected to emphasis or filtering. Therefore, there is a demand for an arbitrary waveform generator (AWG) that can generate arbitrary waveforms in an analog manner and has a high speed of over 100 Gsps (G Symbol / s).

[0004] An AWG must allow the user to freely set the analog waveform to be output. Naturally, since it is required to generate any desired signal, it must also be possible to set the waveform using numerical data. Therefore, an AWG must have a mechanism inside it to convert the digital data output from an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) into analog data. This conversion can be achieved using a Digital-to-Analog Converter (DAC).

[0005] However, when the required analog data output rate is high, not only does it become necessary to input signals multiplexed by a multiplexer (MUX) at higher speeds to the DAC, but the effects of phase differences between the multiple input signals input to the DAC and the MUX in the preceding stage cannot be ignored.For example, if the FPGA output rate is 32 Gbps and the DAC bit resolution is 8 bits, it is desirable that the maximum phase difference between all signals input to the MUX be less than 0.1 UI (Unit Interval) (3.125 ps).

[0006] Here, by using the technique described in Patent Document 1, it is possible to adjust the maximum phase difference between all signals input to the MUX to a value less than or close to 0.1 UI. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6346212 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the technology described in Patent Document 1 may adjust the phase between signals input to the MUX at a position that is shifted by one clock (1 UI), which occurs when there is a large phase shift between the signals before the adjustment.

[0009] Specifically, the technology described in Patent Document 1 cannot handle cases where a phase difference of more than 1 UI occurs between signals before adjustment. Furthermore, even if the phase difference between signals before adjustment is suppressed to within 1 UI by other means, there are technical and cost issues, such as the need for an additional mechanism to adjust the clock phase provided to the FPGA transceiver, etc., and the need to measure the phase adjustment amount, which varies depending on the frequency. In the case of an FPGA, the phase difference between transceivers may change every time the device is started or reset, which requires re-measurement of the phase adjustment amount. Furthermore, depending on the FPGA used, it may not be possible to suppress the phase difference between output signals to within 1 UI in the first place.

[0010] In this case, when signals are multiplexed using a MUX, unintended data is generated. For example, if this data is used as a test signal for a Bit Error Rate Tester (BERT), the test signal itself will contain errors, making it impossible to measure the correct error rate.

[0011] The present invention has been made to solve the above-mentioned conventional problems, and has as its object to provide a signal generating device and a signal generating method that can significantly increase the adjustable maximum phase difference between signals output from multiple transceivers. [Means for solving the problem]

[0012] In order to solve the above problem, a signal generating device according to the present invention has a parallel data output unit (11) that outputs parallel data of multiple bits, a FIFO (21) that stores N-bit parallel data of the parallel data of multiple bits output from the parallel data output unit, and a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data, a phase synchronization control unit (31) that controls the phase of the 1-bit serial data converted by each of the transceivers, a frequency-divided clock output unit (14) that outputs a frequency-divided clock obtained by dividing the frequency of an external clock, a division ratio setting unit (33) that sets a division ratio of the frequency-divided clock in the frequency-divided clock output unit, a clock selection unit (17) that selects either the external clock or the frequency-divided clock, a rate control unit (34) that controls each of the transceivers to output, as the 1-bit serial data, a toggle pattern of a frequency that is half the frequency of the frequency-divided clock or the external clock selected by the clock selection unit, and and a phase detection unit (40) that measures a voltage value corresponding to a phase difference between the external clock and the toggle pattern, and the phase synchronization control unit includes a phase acquisition processing unit (31b) that executes a phase acquisition process to acquire the voltage value measured by the phase detection unit while changing the phase of the toggle pattern from an initial value, and a phase synchronization control unit that executes a phase acquisition process to acquire the voltage value measured by the phase detection unit while changing the phase of the toggle pattern from an initial value, and a phase synchronization control unit that executes a phase acquisition process to acquire the voltage value measured by the phase detection unit while changing the phase of the toggle pattern from an initial value, and a phase difference calculation processing unit (31c) that executes a phase difference calculation process that calculates an initial phase difference between the initial value and the external clock, and a phase shift processing unit (31d) that executes a phase shift process that shifts the phase of the toggle pattern from the initial value by the amount of the initial phase difference so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range, wherein the phase synchronization control unit repeatedly executes the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually decreasing the frequency division ratio using the frequency division ratio setting unit,The clock selection unit is configured to select the external clock instead of the divided clock after the phase acquisition process, the phase difference calculation process, and the phase shift process are executed when the frequency division ratio is a predetermined minimum value.

[0013] With this configuration, the signal generating device according to the present invention can reduce the maximum phase difference between the serial data output from the plurality of transceivers to 0.1 UI or less relative to the external clock.

[0014] Furthermore, the signal generating device according to the present invention can significantly increase the adjustable maximum phase difference between the serial data output from each of the multiple transceivers after startup or resetting.

[0015] Furthermore, the signal generator according to the present invention does not require an additional mechanism, such as a delay circuit external to the FPGA, to limit the phase difference between pre-adjusted serial data to within 1 UI in advance, eliminating the need to investigate the parameters to be given to the additional mechanism after the product has been manufactured.

[0016] Furthermore, the signal generating device according to the present invention may be configured such that the division ratio is an integer that is a power of two, and the clock selection unit selects the external clock instead of the divided clock after the phase acquisition process, the phase difference calculation process, and the phase shift process are executed when the division ratio is two.

[0017] Furthermore, in a signal generating device according to the present invention, each of the transceivers includes a PISO (22) that converts the N-bit parallel data read from the FIFO in response to a read clock signal into the 1-bit serial data, a usage determination unit (23) that executes first and second usage determination processes to determine whether the usage of the FIFO is equal to or greater than a usage threshold, and a phase adjustment unit (24) that executes a first phase adjustment process to decrease the phase of the read clock signal by a predetermined amount and a second phase adjustment process to increase the phase of the read clock signal by a predetermined amount, and the phase synchronization control unit further includes a usage control processing unit (31 a) that executes usage control processing to control the usage of the FIFO, and the usage control processing unit causes the usage determination unit to execute the first usage determination process on condition that output of the serial data from each of the transceivers has started, and the usage control processing unit calculates the usage of each of the transceivers by the first usage determination process. the usage control processing unit causes the phase adjustment unit to execute the first phase adjustment process on condition that it is determined that the usage of the FIFO of each of the transceivers is less than the usage threshold, the usage control processing unit causes the usage determination unit to execute the second usage determination process on condition that the number of consecutive times it is determined by the first usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold reaches a first determination number, the usage control processing unit causes the phase adjustment unit to execute the second phase adjustment process on condition that it is determined by the second usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold, and the usage control processing unit causes the phase adjustment unit to terminate adjustment of the phase of the read clock signal on condition that the number of consecutive times it is determined by the second usage determination process that the usage of the FIFO of each of the transceivers is greater than or equal to the usage threshold reaches a second determination number.

[0018] That is, the signal generating device according to the present invention is configured to execute a usage control process to halve the FIFO usage of all lanes before starting the phase acquisition process, phase difference calculation process, and phase shift process. With this configuration, the signal generating device according to the present invention can shift the phase of the toggle pattern in both positive and negative directions within a range of up to -1 UI to +1 UI during the phase acquisition process, for example, when the FIFO usage corresponds to 2 UI of the divided clock with the maximum division ratio.

[0019] A signal generation method according to the present invention is a signal generation method for controlling the phase of the 1-bit serial data converted by each of the transceivers using a signal generator (1) including: a parallel data output unit (11) that outputs parallel data of multiple bits; a FIFO (21) that stores N-bit parallel data of the parallel data of multiple bits output from the parallel data output unit; a plurality of transceivers (20) that convert the N-bit parallel data stored in the FIFO into 1-bit serial data; a frequency-divided clock output unit (14) that outputs a frequency-divided clock obtained by dividing the frequency of an external clock; a clock selection unit (17) that selects either the external clock or the frequency-divided clock; and a phase detection unit (40) that measures a voltage value corresponding to a phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the 1-bit serial data, the signal generation method comprising: a frequency-dividing ratio setting step (S14, S20) of setting a frequency-dividing ratio of the frequency-divided clock in the frequency-divided clock output unit; a rate control step (S15, S22) of outputting, as data, a toggle pattern having a frequency that is half the frequency of the frequency-divided clock or the external clock selected by the clock selection unit from each of the transceivers; a phase acquisition processing step (S16, S23) of executing a phase acquisition process of acquiring the voltage value measured by the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing step (S17, S24) of executing a phase difference calculation process of calculating an initial phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the relationship between the voltage value acquired in the phase acquisition processing step and the amount of change in the phase of the toggle pattern from the initial value; and a phase movement processing step (S18, S29) of executing a phase movement process of moving the phase of the toggle pattern from the initial value by the amount of the initial phase difference so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern becomes a value within a predetermined range.S25), a step (S15 to S20) of repeatedly executing the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually decreasing the frequency division ratio by the frequency division ratio setting step, and an external clock selection step (S21) of selecting the external clock instead of the frequency-divided clock by the clock selection unit after the phase acquisition process, the phase difference calculation process, and the phase shift process are executed when the frequency division ratio is a predetermined minimum value.

[0020] Furthermore, in the signal generation method according to the present invention, the division ratio may be an integer that is a power of two, and the external clock selection step may select the external clock instead of the divided clock after the phase acquisition process, the phase difference calculation process, and the phase shift process are executed when the division ratio is two. [Effects of the Invention]

[0021] The present invention provides a signal generating device and a signal generating method that can significantly increase the adjustable maximum phase difference between signals output from a plurality of transceivers. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a block diagram showing a configuration of a signal generating device according to an embodiment of the present invention. [Figure 2] 2 is a block diagram showing a part of the configuration of a data output unit included in the signal generating device of FIG. 1. FIG. [Figure 3] 2 is a schematic diagram of a phase detection unit included in the signal generating device of FIG. 1. [Figure 4] FIG. 2 is a block diagram showing the configuration of one lane of the transceiver section. [Figure 5] 2 is a state transition diagram for explaining a phase synchronization process performed by the signal generating device of FIG. 1. FIG. [Figure 6] 10 is a block diagram showing the configuration of an FPGA control unit included in the data output unit. FIG. [Figure 7]FIG. 10 is a diagram showing the relationship between a toggle pattern output from one lane of a data output unit and a clock. [Figure 8] 10 is a graph showing the relationship between a voltage value according to a duty ratio of a phase detection signal measured by a phase detection unit and the amount of change in the phase of a toggle pattern from an initial value. [Figure 9] This figure explains the phase shift processing of the toggle patterns of each lane by the phase synchronization control unit provided in the FPGA control unit, where (a) shows a case where the initial phase differences of the toggle patterns of all lanes are distributed in positive directions, (b) shows a case where the initial phase differences of the toggle patterns of each lane are distributed in either positive or negative directions, and (c) shows a case where the initial phase differences of the toggle patterns of each lane are distributed in either positive or negative directions, with the positive distribution and negative distribution separated by 0.5 UI or more. [Figure 10] 10 is a diagram showing the amount of phase shift of the toggle pattern by the phase synchronization control unit for each division ratio. FIG. [Figure 11] 2 is a flowchart showing the process of a signal generation method using the signal generation device of FIG. 1. [Figure 12] FIG. 10 is a diagram showing the phase relationship of the toggle patterns of each lane after the usage control process. [Figure 13] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when the division ratio of the divided clock is 64, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. [Figure 14] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when the division ratio of the divided clock is 4, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. [Figure 15]10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when the division ratio of the divided clock is 2, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. [Figure 16] 10A and 10B are diagrams showing the phase relationship of the toggle patterns of each lane when an external clock is selected by the clock selection unit, in which (a) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the initial phase difference is calculated by the phase difference calculation process, and (b) is a simplified diagram showing the timing of the toggle patterns from the transceivers of each lane immediately after the phase is shifted by the phase shift process. DETAILED DESCRIPTION OF THE INVENTION

[0023] DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a signal generating device and a signal generating method according to the present invention will be described with reference to the drawings.

[0024] 1 includes a data output unit 10, a clock selection unit 17, a phase detection unit 40, a MUX 50, an amplifier 52, an ADC 55, a DAC 60, an operation unit 65, and a control unit 70. The data output unit 10 is configured on, for example, an FPGA or an ASIC, but the following description will be given assuming that these are configured on an FPGA.

[0025] The data output unit 10 includes a parallel data output unit 11, a plurality of transceiver units 12-1 to 12-p, a clock generation unit 13, a frequency-divided clock output unit 14, and an FPGA control unit 15.

[0026] The parallel data output unit 11 has an internal memory (not shown) that stores a series of data strings of a predetermined pattern in advance, or an arithmetic circuit (not shown) that generates the data strings. For example, in the example shown in Fig. 2, the parallel data output unit 11 is configured to output 32 x N-bit parallel data.

[0027] The parallel data output unit 11 is configured to output, for example, a PAM signal pattern consisting of a multi-value K (K is an integer equal to or greater than 2) of two or more as 32×N-bit parallel data based on pattern information input from the operation unit 65. The parallel data output unit 11 generates a PAM signal pattern consisting of any multi-value K, such as an NRZ signal (K=2), a PAM3 signal (K=3), a PAM4 signal (K=4), a PAM5 signal (K=5), a PAM6 signal (K=6), a PAM7 signal (K=7), or a PAM8 signal (K=8). Here, the pattern information refers to information on the PAM signal pattern, such as the value of K and the type of pattern (for example, a Pseudo Random Binary Sequence (PRBS) pattern, a Short Stress Pattern Random Quaternary (SSPRQ) pattern, or any pattern).

[0028] The data output unit 10 includes p transceiver units 12-1 to 12-p. Although Figures 1 and 2 show an example where p=8, in the present invention, the number of transceiver units 12 is not limited to eight and may be any number.

[0029] As shown in FIG. 2, the clock signal generated by the clock generating unit 13 is distributed to each transceiver unit 12.

[0030] Each transceiver unit 12 includes, for example, four transceivers 20-0 to 20-3. Each transceiver 20 is an output unit of an FPGA and outputs a digital signal of 0 or 1. Each transceiver 20 converts, in synchronization with the clock signal generated by the clock generation unit 13, N-bit parallel data stored in a FIFO 21 (described later) out of the 32×N-bit parallel data output from the parallel data output unit 11, into 1-bit serial data. Here, N is an integer equal to or greater than 2.

[0031] That is, each transceiver unit 12 converts the 4×N-bit parallel data output from the parallel data output unit 11 into 4-bit parallel data and outputs it. That is, the data output unit 10 outputs 8 channels of 4-bit parallel data, in other words, 32 lanes of serial data.

[0032] The divided clock output unit 14 outputs a divided clock obtained by dividing the frequency of the external clock. The maximum frequency of the divided clock is half the frequency of the external clock. For example, the divided clock output unit 14 may be implemented by a transceiver having a similar configuration to each of the transceivers 20.

[0033] The clock selector 17 selects either the external clock or the divided clock in response to a clock selection signal output from a clock selection signal output unit 35 (described later). In this specification, the divided clock and the external clock are collectively referred to simply as the "clock." The external clock is, for example, a 32 GHz pulse signal.

[0034] The phase detector 40 measures a voltage value corresponding to the phase difference between the divided clock or external clock selected by the clock selector 17 and the toggle pattern output from each transceiver 20. The toggle pattern is 1-bit serial data in which "0" and "1" are repeated alternately, and is output from each transceiver 20 when the phase acquisition process, phase difference calculation process, and phase shift process described below are executed. One phase detector 40 is disposed downstream of each transceiver 20. Since the phase detector 40 is used to check the phase of the toggle pattern output from each transceiver 20, it may be incorporated into the MUX 50 or may be disposed independently upstream of the MUX 50.

[0035] A schematic diagram of the phase detection unit 40 for one lane is shown in Fig. 3. As shown in the figure, the phase detection unit 40 includes, for example, a D flip-flop 41, an EXOR circuit 42, and an averaging circuit 43.

[0036] The D flip-flop 41 has two input terminals, a D terminal and a CLK terminal, and one output terminal, a Q terminal. A toggle pattern from the corresponding transceiver 20 is input to the D terminal, and a clock selected by the clock selection unit 17 is input to the CLK terminal.

[0037] The EXOR circuit 42 outputs a phase detection signal by taking the exclusive OR of the toggle pattern from the corresponding transceiver 20 and the output signal from the Q terminal of the D flip-flop 41. When a toggle pattern with a period twice that of the clock is input to the D terminal, the phase detection signal becomes a pulse-like signal with a duty ratio corresponding to the phase of the toggle pattern input to the D terminal.

[0038] The averaging circuit 43 is configured, for example, by a low-pass filter, and is configured to average the phase detection signal. When a toggle pattern with a period twice that of the clock is input to the D terminal, the averaging circuit 43 outputs a signal with a voltage value corresponding to the duty ratio of the phase detection signal. This makes it possible to obtain the phase of the toggle pattern from the corresponding transceiver 20 as a voltage value.

[0039] The amplifier 52 amplifies the signal from the phase detector 40 to a voltage level suitable for the ADC 55 at the subsequent stage, as required.

[0040] The ADC 55 samples the signal from the phase detector 40 amplified by the amplifier 52 at a predetermined sampling rate and converts it into digital data. That is, the ADC 55 outputs digital data of a voltage value corresponding to the phase difference between the divided clock or external clock selected by the clock selector 17 and the toggle pattern. Here, the predetermined sampling rate may be a value of several hundred ksps to several Msps, such as 500 ksps or 1 Msps. For this reason, an ADC with multiple input channels, such as a four-channel ADC, can also be used as the ADC 55.

[0041] The MUX 50 latches the m-bit parallel data output from each transceiver unit 12, selects n bits at a time in a predetermined order in synchronization with the external clock selected by the clock selection unit 17, and outputs n-bit data corresponding to the frequency of the external clock selected by the clock selection unit 17. Here, n is an integer greater than or equal to 1 and less than or equal to m-1. In the example shown in FIG. 1, n=1 and m=4. That is, the MUX 50 can multiplex the m-bit data from each transceiver unit 12 into n-bit data.

[0042] DAC 60 is an n×p-bit DAC that outputs an n×p-bit analog signal, i.e., a multi-value K PAM signal, corresponding to the n×p-bit data output from all MUXes 50. In the example shown in FIG. 1, n=1 and p=8.

[0043] The operation unit 65 is for accepting operation inputs by the user, and is configured, for example, as a touch panel equipped with a touch sensor for detecting a contact position by a touch operation on an input surface corresponding to a display screen of a display device (not shown). Alternatively, the operation unit 65 may be configured to include an input device such as a keyboard or a mouse. Operation inputs to the operation unit 65 are detected by the control unit 70.

[0044] The control unit 70 is composed of a control device such as a computer including, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA, a ROM (Read Only Memory), a RAM (Random Access Memory), and an HDD (Hard Disk Drive), and controls the operation of each of the above-mentioned components that make up the signal generating device 1.

[0045] 4 is a diagram showing the configuration of one lane of the data output unit 10. Each transceiver 20 has a FIFO (First-In First-Out) 21 that stores N-bit parallel data out of the 32×N-bit parallel data output from the parallel data output unit 11, a PISO (Parallel-In Serial-Out) 22 that converts the N-bit parallel data read from the FIFO 21 into 1-bit serial data in response to a read clock signal, a usage determination unit 23 that executes first and second usage determination processes to determine whether the usage of the FIFO 21 is equal to or greater than a usage threshold, a phase adjustment unit 24 that adjusts the phase of the read clock signal of the FIFO 21 so as to decrease or increase it, frequency dividers 25 and 26, and a subtractor 27.

[0046] That is, the transceiver 20 reads out the stored N-bit parallel data from the FIFO 21, performs parallel / serial conversion on the read parallel data in the PISO 22, and outputs the serial data.

[0047] In the signal generating device 1 of this embodiment, each transceiver unit 12 can be configured with a transceiver equipped with a function for adjusting the phase of a read clock signal, such as a TX Phase Interpolator PPM Controller (hereinafter referred to as "TXPI") provided by Xilinx. Furthermore, for example, an FPGA that configures the data output unit 10 can be an UltraScale+ FPGA equipped with a GTY transceiver manufactured by Xilinx. (registered trademark) and the like can be suitably used.

[0048] Generally, the timing at which multiple transceivers configured on an FPGA actually output data after they are started or reset does not necessarily match. Therefore, the usage amount of the FIFO 21 of each transceiver 20 is usually different when the data output starts. Furthermore, even when focusing on a single transceiver 20, the usage amount when the data output starts may differ each time the transceiver is started or reset.

[0049] The basic operation of TXPI will be described below with reference to FIG.

[0050] The FIFO 21 functions as a buffer for the parallel data output from the parallel data output unit 11 and is capable of storing up to M words of N-bit parallel data. The FIFO 21 writes or reads N-bit parallel data at the rising edge of an input write clock signal or read clock signal. The write clock signal and read clock signal are signals based on the clock signal generated by the clock generation unit 13, for example.

[0051] The frequency divider 25 divides the read clock signal by the maximum number of words M of the FIFO 21 to obtain a read address of the FIFO 21. On the other hand, the frequency divider 26 divides the write clock signal by the maximum number of words M of the FIFO 21 to obtain a write address of the FIFO 21.

[0052] The subtractor 27 outputs the difference between the read address and the write address output from the frequency dividers 25 and 26. The difference output from the subtractor 27 reflects the amount of FIFO 21 used.

[0053] The usage determination unit 23 executes first and second usage determination processes for determining, for each clock of the operation clock of the FPGA that constitutes the data output unit 10, whether the difference output from the subtractor 27 is equal to or greater than a usage threshold. The usage determination unit 23 constantly monitors the difference between the read address and write address of the FIFO 21 as the usage of the FIFO 21, and outputs 0 if this usage is less than the usage threshold, and 1 if it is equal to or greater than the usage threshold. For example, the usage threshold is M / 2, i.e., half the maximum number of words M of the FIFO 21. The usage of the FIFO 21 changes as the phase of the read clock signal changes.

[0054] The phase adjustment unit 24 executes a first phase adjustment process to decrease the phase of the read clock signal by a predetermined amount and a second phase adjustment process to increase the phase of the read clock signal by a predetermined amount in a usage control process described later. The first phase adjustment process is a process to decrease the usage of the FIFO 21, and the second phase adjustment process is a process to increase the usage of the FIFO 21.

[0055] The phase adjustment unit 24 can shift the read address value of the FIFO 21 by adjusting the phase of the read clock signal of the FIFO 21. This shifts the phase of the parallel data output from the FIFO 21. However, the phase adjustment unit 24 cannot adjust the phase of the parallel data output from the FIFO 21 to an arbitrary value, and the phase adjustment width and maximum adjustment amount that can be adjusted at one time are also limited. For example, when the output data rate of the transceiver 20 is 32 Gbps, the phase adjustment width that the phase adjustment unit 24 can adjust is 1 / 64 UI step width, and the maximum adjustment amount that the phase adjustment unit 24 can adjust is 64 UI.

[0056] The following describes the usage control process executed by the usage control processor 31a of the phase synchronization controller 31 (see FIG. 6) included in the FPGA controller 15, with reference to the state transition diagram in FIG. 5. The usage control process of the usage control processor 31a controls the usage of the FIFO 21 of each transceiver 20, and is executed independently for each lane, i.e., for each transceiver 20.

[0057] 5, the usage control processor 31a includes eight states S1 to S7, namely, an initial state, a PRESET state, a BUFCHK1 state, a TXPI_DEC state, a TXPI_INC state, a BUFCHK2 state, and a PHASEADJ state. Arrows between states indicate transitions and their directions.

[0058] First, the usage control processor 31a transitions from the initial state S1 to the PRESET state S2. The PRESET state S2 is a standby state until each transceiver 20 starts outputting serial data. Here, each transceiver 20 starts generating a clock in a clock generation circuit (not shown) when it is ready to start outputting serial data after startup or reset. The usage control processor 31a can detect the rising edge of this clock to determine when each transceiver 20 starts outputting serial data.

[0059] When the usage control processing unit 31a detects that each transceiver 20 has started outputting serial data, it transitions from the PRESET state S2 to the BUFCHK1 state S3. The BUFCHK1 state S3 is a state in which the usage control processing unit 31a causes the usage determination unit 23 to execute the first usage determination process.

[0060] The usage control processing unit 31a transitions from the BUFCHK1 state S3 to the TXPI_DEC state S4 on the condition that the first usage determination process determines that the usage of the FIFO 21 of each transceiver 20 is equal to or greater than the usage threshold. The TXPI_DEC state S4 is a state in which the usage control processing unit 31a causes the phase adjustment unit 24 to execute the first phase adjustment process.

[0061] The usage control processor 31a transitions from the TXPI_DEC state S4 back to the BUFCHK1 state S3 on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 has been decreased by a predetermined amount by the first phase adjustment process.

[0062] The usage control processor 31a transitions from the BUFCHK1 state S3 to the TXPI_INC state S5 when the number of consecutive times that the usage of the FIFO 21 of each transceiver 20 is determined to be less than the usage threshold by the first usage determination process reaches the first determination count. The TXPI_INC state S5 is a state in which the usage control processor 31a causes the phase adjuster 24 to execute the second phase adjustment process.

[0063] The usage control processor 31a transitions from the TXPI_INC state S5 to the BUFCHK2 state S6 on the condition that the phase of the read clock signal of the FIFO 21 of each transceiver 20 has been increased by a predetermined amount by the second phase adjustment process. The BUFCHK2 state S6 is a state in which the usage control processor 31a causes the usage determiner 23 to execute the second usage determination process.

[0064] The usage control processing unit 31a transitions from the BUFCHK2 state S6 back to the TXPI_INC state S5 on the condition that it is determined in the second usage determination process that the usage of the FIFO 21 of each transceiver 20 is less than the usage threshold.

[0065] The usage control processor 31a transitions from the BUFCHK2 state S6 to the PHASEADJ state S7 on the condition that the number of consecutive times that the usage of the FIFO 21 of each transceiver 20 is determined to be equal to or greater than the usage threshold value in the second usage determination process reaches the second determination count. The PHASEADJ state S7 is a state in which the usage control processor 31a causes the phase adjuster 24 to finish adjusting the phase of the read clock signal and waits until a reset signal is input to each transceiver 20.

[0066] 5 for all transceivers 20, the usage control processing unit 31a can halve the usage of the FIFO 21 of all lanes, thereby aligning the data latency of all lanes. Since the phase of the 32×N-bit parallel data output from the parallel data output unit 11 is the same for all lanes, the phase of the serial data output from all transceivers 20 will also be approximately the same.

[0067] 5, when the phase adjustment width by phase adjustment unit 24 is 1 / 64 UI, the phase of the serial data output from transceiver 20 can be adjusted with a calculated accuracy of ±0.008 UI (theoretical limit value). Note that the first and second determination counts may be equal or different from each other.

[0068] 5, if the transitions from BUFCHK1 state S3 to TXPI_DEC state S4, from BUFCHK2 state S6 to TXPI_INC state S5, from BUFCHK1 state S3 to TXPI_INC state S5, and from BUFCHK2 state S6 to PHASEADJ state S7 are executed if the respective conditions for their transitions are satisfied once, the maximum phase difference between the serial data output from all transceivers 20 after phase adjustment is complete will be greater than the theoretical limit value. This is thought to be because the usage of FIFO 21 constantly fluctuates due to jitter components in the write clock signal and read clock signal, which causes fluctuations in the results of the first and second usage determination processes performed by usage determiner 23.

[0069] Therefore, in the processing of the usage control processing unit 31a shown in Figure 5, the signal generating device 1 of this embodiment specifies the first and second number of judgments that must be made consecutively to satisfy the transition conditions for the transition from the BUFCHK1 state S3 to the TXPI_INC state S5 and the transition from the BUFCHK2 state S6 to the PHASEADJ state S7, and executes the transition only if the transition conditions are met for those number of consecutive judgments.

[0070] As shown in FIG. 6, the FPGA control unit 15 includes a phase synchronization control unit 31, a frequency division ratio setting unit 33, a rate control unit , and a clock selection signal output unit .

[0071] The phase synchronization control section 31 controls the phase of the toggle pattern, which is 1-bit serial data converted by each transceiver 20.

[0072] The phase synchronization control unit 31 includes the already-mentioned usage control processing unit 31a, phase acquisition processing unit 31b, phase difference calculation processing unit 31c, and phase movement processing unit 31d.

[0073] The phase acquisition processing unit 31b executes a phase acquisition process to acquire the voltage value measured by the phase detection unit 40 while controlling the phase adjustment unit 24 of each transceiver 20 to change the phase of the toggle pattern output from each transceiver 20 from its initial value. Here, digital data of the voltage value measured by the phase detection unit 40 is input from the ADC 55 to the phase acquisition processing unit 31b.

[0074] A specific example of the phase acquisition process by the phase acquisition processor 31b will be described below. Fig. 7 shows the relationship between the toggle pattern output from the transceiver 20 of one lane of the data output unit 10 and the clock.

[0075] First, the phase acquisition processing unit 31b acquires the voltage value measured by the phase detection unit 40 at the start of the phase acquisition process. Here, the phase of the toggle pattern at the start is set to 0 UI. Furthermore, the phase synchronization control unit 31 acquires the voltage value measured by the phase detection unit 40 while moving the phase of the toggle pattern within a range of -0.75 UI to +0.75 UI, with one clock cycle at that time being set to 1 UI. For example, as shown by the arrows in FIG. 7, the phase synchronization control unit 31 moves the phase of the toggle pattern from 0 UI, which is the initial value, to -0.75 UI, then from -0.75 UI to +0.75 UI, and finally from +0.75 UI to 0 UI, which is the start point.

[0076] This means that, for example, every time the phase of the toggle pattern is shifted by about 0.1 UI, measurement is performed by the phase detection unit 40. This allows the results shown in Figure 8 to be obtained. In the graph of Figure 8, the horizontal axis represents the amount of change [UI] in the phase of the toggle pattern from its initial value, and the vertical axis represents the voltage value [V] measured by the phase detection unit 40.

[0077] Since TXPI adjusts the phase of the serial data from each transceiver 20 based on the usage of the FIFO 21, if the usage is uneven in the initial state, it may not be possible to ensure an adjustment range of ±0.75 UI. For this reason, the phase synchronization control unit 31 performs the usage control process described above, so that the phase of the toggle pattern can be moved within a range of ±0.75 UI.

[0078] In the above description, the range of phase change of the toggle pattern is -0.75 UI to +0.75 UI, but the present invention is not limited to this. The range of phase change of the toggle pattern needs to be at least 1 UI, and the phase of the toggle pattern may be changed within the range of -0.5 UI to +0.5 UI, for example.

[0079] The phase difference calculation processing unit 31c calculates an initial phase difference P between the divided clock or the external clock selected by the clock selection unit 17 and the initial value of the toggle pattern phase, based on the relationship between the voltage value acquired by the phase acquisition processing unit 31b and the amount of change from the initial value of the toggle pattern phase. C The phase difference calculation process is executed to calculate the following.

[0080] The phase difference calculation processing unit 31c calculates the initial phase difference P of the toggle pattern at the start of the phase acquisition process using the measurement results shown in FIG. 8 and the following equation (1): C In equation (1), V0 is the voltage value acquired by the phase acquisition processing unit 31b at the start of the phase acquisition process, V H is the maximum voltage value acquired by the phase acquisition processing unit 31b, V L is the minimum value of the voltage value acquired by the phase acquisition processing unit 31b. Each value in equation (1) does not have to be the actual measured value as it is, but may be a value corrected based on the linearity of the relationship between phase and voltage.

[0081]

number

[0082] The phase synchronization control unit 31 performs the same phase acquisition process and phase difference calculation process for all toggle patterns for 32 lanes simultaneously or sequentially. As a result, for example, the lane numbers and initial phase differences P C The correspondence is obtained.

[0083] Here, lane numbers 1 to 4 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-1, respectively. Lane numbers 5 to 8 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-2, respectively. Lane numbers 9 to 12 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-3, respectively. Lane numbers 13 to 16 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-4, respectively. Lane numbers 17 to 20 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-5, respectively. Lane numbers 21 to 24 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-6, respectively. Lane numbers 25 to 28 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-7, respectively. Lane numbers 29 to 32 correspond to the four transceivers 20-0 to 20-3 of the transceiver unit 12-8, respectively.

[0084] The phase shift processing unit 31d controls the phase adjustment unit 24 of each transceiver 20 to shift the phase of the toggle pattern output from each transceiver 20 from the initial value to the initial phase difference P so that the phase difference between the divided clock or the external clock selected by the clock selection unit 17 and the toggle pattern is within a predetermined range. C Here, the value (phase difference) within the predetermined range is the value closest to 0 within the precision of the phase adjustment width that the phase adjustment unit 24 can adjust.

[0085] Hereinafter, the phase shift processing of the toggle pattern of each lane performed by the phase shift processing unit 31d will be described with reference to FIGS. 9(a) to 9(c).

[0086] FIG. 9(a) shows the initial phase difference P C In this case, the phase shift processing unit 31d shifts the phase of the toggle pattern of all lanes toward 0 by -P C The initial phase difference P C The same is true if is negatively distributed.

[0087] FIG. 9(b) shows the initial phase difference P C is distributed either positively or negatively, and the distribution width is less than 0.5 UI. In this case, the phase shift processing unit 31d shifts the phase of the toggle pattern that is distributed positively toward 0 by -P C The phase of the toggle pattern shifts negatively towards 0. C Move only.

[0088] FIG. 9(c) shows the initial phase difference P C is distributed in either positive or negative directions, and the positive distribution and the negative distribution are separated by 0.5 UI or more. In this case, the initial phase difference P C It is considered that a part of the distribution of 1+P appears to be shifted by 1 UI. For this reason, the phase shift processing unit 31d shifts the phase of the toggle pattern that is positively distributed in the positive direction toward 0 by, for example, 1+P C and shifts the phase of the negatively distributed toggle pattern towards 0 in the positive direction -P C Move only.

[0089] As can be seen from FIGS. 9(a) to 9(c), the four transceivers 20 included in the same transceiver unit 12 have the same initial phase difference P C In such a case, the phase acquisition process and the phase difference calculation process are performed for only one transceiver 20 included in each transceiver unit 12, and the obtained initial phase difference P Cmay be regarded as an initial phase difference common to the four transceivers 20 included in each transceiver unit 12.

[0090] The division ratio setting unit 33 is configured to set the division ratio of the divided clock based on the external clock to the divided clock output unit 14. The phase synchronization control unit 31 repeatedly executes the phase acquisition process, phase difference calculation process, and phase shift process while the division ratio setting unit 33 gradually decreases the division ratio. For example, the division ratio is an integer that is a power of 2, with a maximum value of 64 and a minimum value of 2. In this case, the division ratio setting unit 33 repeatedly halves the division ratio, changing it in the order of 64, 32, 16, 8, 4, and 2.

[0091] 10 is a diagram showing the amount of phase shift of the toggle pattern by the phase acquisition process for each division ratio when the toggle pattern phase is shifted within a range of -0.75 UI to +0.75 UI relative to 1 UI of the divided clock, as a percentage of the capacity of FIFO 21. For example, the capacity of FIFO 21 is equivalent to 128 UI when 1 clock of the external clock is 1 UI, and is equivalent to 2 UI (±1 UI) for a divided clock obtained by dividing the external clock by a maximum of 64.

[0092] When the division ratio is 64, 75% of the capacity of FIFO 21 is used to shift the phase of the toggle pattern. Thereafter, the amount of shift is halved each time the division ratio is halved, and when the division ratio is 1, the amount of shift is equivalent to 1.17% of the capacity of FIFO 21.

[0093] The rate control unit 34 controls each transceiver 20 to output, as 1-bit serial data from each transceiver 20, a toggle pattern having a frequency that is half the frequency of the divided clock or external clock selected by the clock selection unit 17. For example, the rate control unit 34 controls the parallel data output unit 11 to output N-bit parallel data such that the frequency of the toggle pattern output from each transceiver 20 is half the frequency of the divided clock or external clock.

[0094] The clock selection signal output unit 35 outputs a clock selection signal for selecting either the external clock or the divided clock to the clock selection unit 17. Specifically, when the division ratio set by the division ratio setting unit 33 is at a predetermined minimum value, the clock selection signal output unit 35 outputs a clock selection signal for selecting the external clock instead of the divided clock after the phase acquisition process, phase difference calculation process, and phase shift process are performed. The minimum value of the division ratio is, for example, 2.

[0095] An example of the process of a signal generating method using the signal generating device 1 of this embodiment will be described below with reference to the flowchart in Fig. 11. Note that descriptions that overlap with the description of the configuration of the signal generating device 1 described above will be omitted as appropriate.

[0096] When each transceiver unit 12 is started or reset (step S11: YES), the phase synchronization control unit 31 executes a usage control process (step S12). For example, when the bit rate of the PAM signal output from the signal generating device 1 is changed by a user's operation input to the operation unit 65, each transceiver unit 12 is reset. By the usage control process, the usage of the FIFO 21 of each transceiver 20 is halved.

[0097] FIG. 12 is a simplified diagram showing an example of the phase relationship of the toggle patterns output from the transceiver 20 of each lane after the usage control process. The vertical dashed lines in the diagram indicate the rising edges of the external clock. Each transceiver unit 12 has four lanes, Lane 0 to Lane 3. "Ch1 Lane 0," "Ch1 Lane 2," "Ch4 Lane 0," and "Ch7 Lane 3" in the diagram represent Lane 0 of the transceiver unit 12-1, Lane 2 of the transceiver unit 12-1, Lane 0 of the transceiver unit 12-4, and Lane 3 of the transceiver unit 12-7, respectively. Data indicated by "0" in the toggle pattern of each lane is data that should be in phase across all lanes. This notation is used in subsequent figures. After the usage control process, the phases of the toggle patterns of each lane are usually shifted by more than one clock of the external clock.

[0098] Next, the clock selection unit 17 selects a divided clock (divided clock selection step S13).

[0099] Next, the frequency division ratio setting unit 33 sets the value of the frequency division ratio of the frequency-divided clock in the frequency-divided clock output unit 14 to 64 (frequency division ratio setting step S14). At this time, there is a phase difference between the frequency-divided clock and the external clock, but this does not need to be taken into consideration at this point.

[0100] Next, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the divided clock having the division ratio set in the division ratio setting step S14 (rate control step S15).

[0101] Next, the phase acquisition processing unit 31b executes a phase acquisition process to acquire the voltage value measured by the phase detection unit 40 while changing the phase of the toggle pattern output from each transceiver 20 from the initial value (phase acquisition process step S16).

[0102] Next, the phase difference calculation processing unit 31c calculates an initial phase difference P between the divided clock selected in the divided clock selection step S13 and the initial value of the toggle pattern phase based on the relationship between the voltage value acquired in the phase acquisition processing step S16 and the amount of change from the initial value of the toggle pattern phase. C A phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S17).

[0103] FIG. 13(a) shows the initial phase difference P C 1 is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the calculation of . At this time, if the maximum phase difference between the toggle patterns of each lane is 32 UI or less based on the external clock, the subsequent phase shift process can be executed without error.

[0104] Next, the phase shift processing unit 31d shifts the phase of the toggle pattern from the initial value to the initial phase difference P so that the phase difference between the frequency-divided clock selected in the frequency-divided clock selection step S13 and the toggle pattern falls within a predetermined range. C Then, a phase shift process is performed to shift the phase by the amount of (phase shift process step S18).

[0105] 13(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the phase shift process when the division ratio of the divided clock is 64. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock, that is, 6.4 UI or less (0.1 UI × 64 division) based on the external clock.

[0106] If the current division ratio is greater than 2 (step S19: NO), the division ratio setting unit 33 sets the division ratio of the divided clock in the divided clock output unit 14 to half the current value (division ratio setting step S20). Then, the processing from step S15 onwards is executed again.

[0107] That is, steps S15 to S20 are steps for repeatedly executing the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually decreasing the frequency division ratio in the frequency division ratio setting step S20.

[0108] 14(a) shows that when the division ratio of the divided clock is reduced by half to 32, 16, 8, and finally reaches 4 by the division ratio setting unit 33, the initial phase difference P C FIG. 10 is a simplified diagram showing the timing of the toggle pattern of each lane immediately after the calculation of

[0109] 14(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the phase shift process when the division ratio of the divided clock is 4. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock, that is, 0.4 UI or less (0.1 UI × 4 division) based on the external clock.

[0110] 15(a) shows that when the division ratio of the divided clock reaches 2 by the division ratio setting unit 33, the initial phase difference P C FIG. 10 is a simplified diagram showing the timing of the toggle pattern of each lane immediately after the calculation of

[0111] 15(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the phase shift process when the division ratio of the divided clock is 2. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI or less based on the divided clock, that is, 0.2 UI or less (0.1 UI × 2 division) based on the external clock.

[0112] On the other hand, if the current division ratio is 2 (step S19: YES), the clock selection unit 17 selects the external clock instead of the divided clock (external clock selection step S21). The external clock corresponds to a divided clock with a division ratio of 1, but its phase does not match that of the normal divided clock.

[0113] Next, the rate control unit 34 causes each transceiver 20 to output a toggle pattern having a frequency that is half the frequency of the external clock (rate control step S22).

[0114] Next, the phase acquisition processing unit 31b executes a phase acquisition process to acquire the voltage value measured by the phase detection unit 40 while changing the phase of the toggle pattern output from each transceiver 20 from the initial value (phase acquisition process step S23).

[0115] Next, the phase difference calculation processing unit 31c calculates an initial phase difference P between the external clock selected in the external clock selection step S21 and the initial value of the toggle pattern phase based on the relationship between the voltage value acquired in the phase acquisition processing step S23 and the amount of change from the initial value of the toggle pattern phase. C A phase difference calculation process is executed to calculate the phase difference (phase difference calculation process step S24).

[0116] FIG. 16(a) shows the initial phase difference P C FIG. 10 is a simplified diagram showing the timing of the toggle pattern of each lane immediately after the calculation of

[0117] Next, the phase shift processing unit 31d shifts the phase of the toggle pattern from the initial value to the initial phase difference P so that the phase difference between the external clock selected in the external clock selection step S21 and the toggle pattern falls within a predetermined range. C Then, a phase shift process is performed to shift the phase by the amount of (phase shift process step S25).

[0118] 16(b) is a simplified diagram showing the timing of the toggle patterns of each lane immediately after the phase is shifted by the phase shift process when the external clock is selected by the clock selection unit 17. At this time, the maximum phase difference between the toggle patterns of all lanes is adjusted to 0.1 UI (0.1 UI × 1 division) or less based on the external clock.

[0119] Then, the phase synchronization control unit 31 goes into a standby state until each transceiver unit 12 is activated or reset again (step S11).

[0120] In step S11, the transceiver units 12 are started or reset, so that the processes from step S12 onward are automatically executed, but the present invention is not limited to this. For example, in step S11, the user may press an execute button provided on an operation screen (not shown) of the signal generating device 1 via the operation unit 65, so that the user can execute the processes from step S12 onward at any timing.

[0121] When the phase adjustment of the toggle pattern output from each transceiver 20 is completed in step S25, the FPGA control unit 15 automatically transitions to a mode for generating a PAM signal during normal operation, and causes the parallel data output unit 11 to output N-bit parallel data for normal operation according to the frequency of the external clock.

[0122] In this way, the signal generation method using the signal generating device 1 of this embodiment initially uses a divided clock with a large division ratio to roughly adjust the phase of the toggle pattern of each lane with a large amount of movement, and finally uses an external clock with a division ratio equivalent to 1 to finely adjust the phase of the toggle pattern of each lane with a small amount of movement.

[0123] As described above, the signal generating device 1 according to this embodiment is configured to repeatedly execute the phase acquisition process, the phase difference calculation process, and the phase movement process while gradually decreasing the division ratio of the divided clock by the division ratio setting unit 33.

[0124] With this configuration, the signal generating device 1 according to this embodiment can reduce the maximum phase difference between the serial data output from the plurality of transceivers 20 to 0.1 UI or less relative to the external clock.

[0125] Furthermore, the signal generating device 1 according to this embodiment can significantly increase the adjustable maximum phase difference between the serial data output from the plurality of transceivers 20 after startup or resetting.

[0126] For example, the signal generating device 1 according to this embodiment can adjust the maximum phase difference between the serial data from each transceiver 20 to 32 UI based on the external clock. This value corresponds to 1000 ps at 32 Gbps, for example. (registered trademark) The phase error on the data sheet of the GTY transceiver is 500 ps, ​​so the signal generating device 1 according to this embodiment can converge this phase error.

[0127] Furthermore, the signal generating device 1 according to this embodiment does not require an additional mechanism such as a delay circuit external to the FPGA to limit the phase difference between pre-adjusted serial data to within 1 UI in advance, so there is no need to investigate the parameters to be given to the additional mechanism after the product is manufactured.

[0128] Although the signal generating device 1 according to this embodiment requires an ADC 55 for each lane, the required speed performance is low (several hundred ksps to several Msps), so an ADC with multiple input channels can be used, and the ADC peripheral circuitry can be made smaller. Furthermore, the signal generating device 1 according to this embodiment does not require an external delay circuit, so the circuit scale and board size can also be reduced.

[0129] Furthermore, the signal generating device 1 according to this embodiment is configured to execute a usage control process to halve the usage of the FIFO 21 of all lanes before starting the phase acquisition process, phase difference calculation process, and phase shift process. As a result, the signal generating device 1 according to this embodiment can shift the phase of the toggle pattern in both positive and negative directions within a range of up to -1 UI to +1 UI during the phase acquisition process, for example, when the usage of the FIFO 21 corresponds to 2 UI of the divided clock with the maximum division ratio. [Explanation of symbols]

[0130] 1. Signal Generator 10 Data output section 11 Parallel data output section 12, 12-1 to 12-8 Transceiver section 13 Clock generation unit 14-divided clock output section 15 FPGA control unit 17 Clock selection section 20,20-0~20-3 Transceiver 21 FIFO 22 PISO 23 Usage amount determination section 24 Phase adjustment section 25,26 frequency divider 27 Subtractor 31 Phase synchronization control section 31a Usage control processing unit 31b Phase acquisition processing unit 31c Phase difference calculation processing unit 31d Phase shift processing section 33 Division ratio setting section 34 Rate control section 40 Phase detection section 41 D Flip-Flop 42 EXOR circuit 43 Averaging circuit 50 MUX 52 Amplifier 55 ADC 60 DAC 65 Operation section 70 Control Unit

Claims

1. a parallel data output unit (11) that outputs parallel data of multiple bits; a plurality of transceivers (20) each having a FIFO (21) for storing N-bit parallel data among the multiple-bit parallel data output from the parallel data output unit, and for converting the N-bit parallel data stored in the FIFO into 1-bit serial data; a phase synchronization control unit (31) for controlling the phase of the 1-bit serial data converted by each of the transceivers; a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; a division ratio setting unit (33) that sets the division ratio of the divided clock to the divided clock output unit; a clock selection unit (17) that selects either the external clock or the divided clock; a rate control unit (34) that controls each of the transceivers to output, as the 1-bit serial data, a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit; a phase detection unit (40) that measures a voltage value corresponding to a phase difference between the divided clock or the external clock selected by the clock selection unit and the toggle pattern, The phase synchronization control unit a phase acquisition processing unit (31b) that executes a phase acquisition process to acquire the voltage value measured by the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing unit (31c) that executes a phase difference calculation process that calculates an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern, based on a relationship between the voltage value acquired by the phase acquisition processing unit and a change amount of the phase of the toggle pattern from the initial value; a phase shift processing unit (31d) that executes a phase shift process to shift the phase of the toggle pattern from the initial value by the amount of the initial phase difference so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern becomes a value within a predetermined range, the phase synchronization control unit repeatedly executes the phase acquisition process, the phase difference calculation process, and the phase shift process while the division ratio setting unit gradually decreases the division ratio; a clock selector that selects the external clock instead of the divided clock after the phase acquisition process, the phase difference calculation process, and the phase shift process are executed when the division ratio is at a predetermined minimum value.

2. the division ratio is an integer that is a power of 2, 2. The signal generating device according to claim 1, wherein the clock selection unit selects the external clock instead of the divided clock after the phase acquisition process, the phase difference calculation process, and the phase shift process are executed when the division ratio is 2.

3. Each of the transceivers comprises: a PISO (22) that converts the N-bit parallel data read from the FIFO into the 1-bit serial data in response to a read clock signal; a usage determination unit (23) that executes first and second usage determination processes to determine whether the usage of the FIFO is equal to or greater than a usage threshold; a phase adjustment unit (24) that executes a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount, the phase synchronization control unit further includes a usage control processing unit (31 a) that executes usage control processing to control the usage of the FIFO; the usage control processing unit causes the usage determination unit to execute the first usage determination process on condition that output of the serial data from each of the transceivers has started; the usage control processing unit causes the phase adjustment unit to execute the first phase adjustment process on condition that it is determined by the first usage determination process that the usage of the FIFO of each of the transceivers is equal to or greater than the usage threshold; the usage control processing unit causes the usage determination unit to execute the second usage determination process on condition that the number of consecutive times that it is determined in the first usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold reaches a first determination number; the usage control processing unit causes the phase adjustment unit to execute the second phase adjustment process on condition that it is determined by the second usage determination process that the usage of the FIFO of each of the transceivers is less than the usage threshold; 3. The signal generating device according to claim 1, wherein the usage control processing unit causes the phase adjustment unit to terminate adjustment of the phase of the read clock signal on the condition that the number of consecutive times that the usage of the FIFO of each transceiver is determined to be equal to or greater than the usage threshold value by the second usage determination process reaches a second determination number.

4. a parallel data output unit (11) that outputs parallel data of multiple bits; a plurality of transceivers (20) each having a FIFO (21) for storing N-bit parallel data among the multiple-bit parallel data output from the parallel data output unit, and for converting the N-bit parallel data stored in the FIFO into 1-bit serial data; a divided clock output unit (14) that outputs a divided clock obtained by dividing the frequency of an external clock; a clock selection unit (17) that selects either the external clock or the divided clock; a phase detection unit (40) that measures a voltage value corresponding to a phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the 1-bit serial data, the signal generation method controlling the phase of the 1-bit serial data converted by each of the transceivers, a division ratio setting step (S14, S20) of setting the division ratio of the divided clock to the divided clock output unit; a rate control step (S15, S22) of outputting, as the 1-bit serial data, a toggle pattern having a frequency that is half the frequency of the divided clock or the external clock selected by the clock selection unit from each of the transceivers; a phase acquisition processing step (S16, S23) of executing a phase acquisition process to acquire the voltage value measured by the phase detection unit while changing the phase of the toggle pattern from an initial value; a phase difference calculation processing step (S17, S24) of executing a phase difference calculation processing to calculate an initial phase difference between the divided clock or the external clock selected by the clock selection unit and the initial value of the phase of the toggle pattern based on the relationship between the voltage value acquired in the phase acquisition processing step and the amount of change in the phase of the toggle pattern from the initial value; a phase shift processing step (S18, S25) of executing a phase shift processing to shift the phase of the toggle pattern from the initial value by the initial phase difference so that the phase difference between the frequency-divided clock or the external clock selected by the clock selection unit and the toggle pattern falls within a predetermined range; a step (S15 to S20) of repeatedly executing the phase acquisition process, the phase difference calculation process, and the phase shift process while gradually decreasing the frequency division ratio in the frequency division ratio setting step; an external clock selection step (S21) of selecting the external clock instead of the divided clock by the clock selection unit after the phase acquisition process, the phase difference calculation process, and the phase movement process are executed when the frequency division ratio is a predetermined minimum value.

5. the division ratio is an integer that is a power of 2, 5. The signal generating method according to claim 4, wherein the external clock selection step selects the external clock instead of the divided clock after the phase acquisition process, the phase difference calculation process, and the phase movement process are executed when the division ratio is 2.

Images