Semiconductor Devices

Abstract

To provide a vertical type semiconductor device capable of preventing occurence of a defective phenomenon to be not-open generated from word line cuts.SOLUTION: A semiconductor device according to the present invention includes: a substrate including a cell region and an extension region; a plurality of channel structures arranged in the cell region and extended in a first direction substantially vertical to an upper surface of the substrate; a plurality of gate electrode layers surrounding the channel structures, separated from each other along the first direction and extended in a second direction substantially orthogonal to the first direction; and a plurality of word line cuts cutting the gate electrode layers in the first direction and continuously extended in the second direction. At least one of the word line cuts is an expansion word line cut including an expansion part having an area different from respective areas of the remaining work line cuts located on the same level in a first predetermined region extended in the second direction.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a vertical semiconductor device in which gate electrode layers are stacked in the vertical direction and which includes a word line cut. [Background technology]

[0002] In recent years, in order to increase the integration density of memory devices, vertical memory devices have been developed in which memory cells are stacked vertically from the surface of a substrate. In a vertical memory device, a pillar-shaped or cylindrical channel protruding vertically from the upper surface of a substrate is provided, and a plurality of gate lines and insulating films are stacked in contact with the channel. In order to further increase the capacity of vertical memory devices, development is underway to stack more gate lines and insulating films in the vertical direction.

[0003] However, stacking more gate lines and insulating films in the vertical direction may cause a defect called "not-open" that occurs due to a word line cut. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 7,679,133 [Patent Document 2] U.S. Patent No. 8,553,466 [Patent Document 3] U.S. Patent No. 8,654,587 [Patent Document 4] U.S. Patent No. 8,559,235 [Patent Document 5] US Patent Application Publication No. 2011 / 0233648 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the problems of the conventional vertical memory devices described above, and an object of the present invention is to provide a vertical semiconductor device that can prevent a defect called "NOT-OPEN" that occurs due to a word line cut. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention provides a semiconductor device comprising: a substrate including a cell region and an extension region; a bit line on the cell area; The cell region is disposed in a first direction substantially perpendicular to the upper surface of the substrate. and electrically connected to the bit line. a plurality of channel structures; a dummy channel structure disposed in the extension region, extending in the first direction, and not electrically connected to the bit line; a plurality of gate electrode layers surrounding the channel structure, spaced apart from one another along the first direction, and extending in a second direction substantially perpendicular to the first direction; and cutting the gate electrode layers in the first direction; Over the cell region and the extension region and a plurality of word line cuts extending continuously in the second direction, each of the plurality of word line cuts including a first word line cut extending in the second direction and a second word line cut spaced apart from the first word line cut in a third direction perpendicular to the first and second directions, Record number The one word line cut has a first portion having a first width in the third direction and a second width in the third direction that is greater than the first width. and extending from the cell region to the extension region in the second direction. Extensions and a portion of the extension overlaps with the channel structure in the third direction, and a remaining portion of the extension overlaps with the dummy channel structure in the third direction; and a width of the extension of the first word line cut in the third direction is greater than a width of the second word line cut in the third direction. It is characterized by:

[0007] In order to achieve the above object, a semiconductor device according to the present invention includes a substrate including a cell region and an extension region; a plurality of cell channel structures disposed in the cell region, extending in a first direction substantially perpendicular to an upper surface of the substrate, and electrically connected to bit lines; a dummy channel structure disposed in the extension region, extending in the first direction, and not connected to the bit lines; a plurality of gate electrode layers surrounding the channel structures, stacked in a stepped manner to be spaced apart from each other along the first direction, and extending in a second direction substantially perpendicular to the first direction; and a gate electrode layer cut in the first direction to form a gate electrode layer across the cell region and the extension region. a plurality of word line cuts extending in the second direction and a connection portion connecting gate electrode layers disposed in the same layer and protruding from the gate electrode layers, each of the plurality of word line cuts including a first word line cut extending in the second direction and a second word line cut spaced apart from the first word line cut in a third direction perpendicular to the first and second directions, the first word line cut including a first portion having a first width in the third direction and an extension portion having a second width in the third direction greater than the first width and extending from the cell region to the extension region in the second direction, extension area a second isolation word line cut extending in the second direction toward the first isolation word line cut; Cell Area and a (2-2) isolation word line cut extending in the second direction toward the (2-2) isolation word line cut, wherein the extension overlaps the (2-2) isolation word line cut in a third direction substantially perpendicular to the first and second directions, a portion of the extension overlaps the channel structure in the third direction, and a remaining portion of the extension overlaps the dummy channel structure in the third direction, and a width of the extension of the first word line cut in the third direction is greater than a width of the (2-2) isolation word line cut in the third direction. [Effects of the Invention]

[0009] According to the semiconductor device of the present invention, a plurality of word lines formed in the same layer are connected to each other by a connection portion, and the semiconductor device includes an extension portion at a position that is affected by loading due to the connection portion during a process of forming a word line cut, thereby preventing the not-open phenomenon. This reduces the number of contacts and / or wiring structures of the semiconductor device through the connection portion, thereby increasing the capacity and integration density of the semiconductor device and improving the reliability of the semiconductor device. In addition, by increasing only the area of ​​the extension portion without increasing the entire area of ​​the word line cut, the overall separation distance between the word line cut and the channel can be secured, thereby ensuring the reliability of the semiconductor device. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 is a plan view showing a schematic layout of a semiconductor device according to a first embodiment of the present invention. [Figure 1B] FIG. 10 is a plan view showing a schematic layout of a semiconductor device according to a second embodiment of the present invention. [Figure 2] FIG. 1B is a cross-sectional view taken along line II' in FIG. 1A. [Figure 3] FIG. 1B is a cross-sectional view taken along line II-II' in FIG. 1A. [Figure 4] FIG. 1B is a cross-sectional view taken along line III-III' in FIG. 1A. [Figure 5] FIG. 4 is an enlarged view of region E in FIG. 3. [Figure 6] 1B is a plan view showing a part of the gate electrode layer shown in FIG. 1A. [Figure 7] 1B is a plan view showing a part of the gate electrode layer shown in FIG. 1A. [Figure 8A] 1B is a plan view showing a part of the gate electrode layer shown in FIG. 1A. [Figure 8B] 1B is a plan view showing a part of the gate electrode layer shown in FIG. 1A. [Figure 9A] FIG. 10 is a plan view showing a schematic layout of a semiconductor device according to a third embodiment of the present invention. [Figure 9B] FIG. 9B is a perspective view of area F in FIG. 9A. [Figure 10] FIG. 9B is a cross-sectional view taken along line IV-IV′ in FIG. 9A. [Figure 11] FIG. 9B is a cross-sectional view taken along line VV' in FIG. 9A. [Figure 12] FIG. 10 is a plan view showing a schematic layout of a semiconductor device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Next, specific examples of embodiments for carrying out the semiconductor device according to the present invention will be described with reference to the drawings.

[0012] The same reference numerals refer to the same elements throughout the accompanying drawings. Unless the context clearly indicates otherwise, the description of a feature or aspect in each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. As used herein, the singular includes the plural unless the context clearly dictates otherwise. Spatially relative terms such as "below," "under," "above," and "above" are used herein to easily describe the relationship of one element or feature to another element or feature shown in the drawings. Spatially relative terms are intended to be understood to include different orientations during use or operation of the device in addition to the orientation depicted in the drawings. For example, if the device in the figures is turned over, components described as being "on top" of other components or features would then be "under" the other components or features. The exemplary term "on" can, therefore, encompass both an orientation of "above" and "below." When an element, such as a region or layer, is referred to as being "on," "connected," "coupled," or "adjacent" to another element, it means that it is directly connected to, coupled to, adjacent to, or has an intervening relationship with the other element. Furthermore, when a reference is made to an element being between two elements, it can be construed that the element is the only element between the two elements, or that there are one or more intervening elements between the two elements.

[0013] 1A and 1B are plan views showing the schematic layout of semiconductor devices according to the first and second embodiments of the present invention, FIG. 2 is a cross-sectional view taken along line II' in FIG. 1A, FIG. 3 is a cross-sectional view taken along line II-II' in FIG. 1A, FIG. 4 is a cross-sectional view taken along line III-III' in FIG. 1A, and FIG. 5 is an enlarged view of region E in FIG. 3.

[0014] Referring to FIG. 1A, a semiconductor device 100 includes a cell region CEL where memory cells are formed, and an extension region EXT for connecting the memory cells to wiring. FIG. 1A shows a part of the cell region CEL. Although the extension region EXT is shown disposed on one side of the cell region CEL in the drawing, the present invention is not limited to this. For example, in one embodiment, the extension regions EXT are disposed on both sides of the cell region CEL. On the other hand, a peripheral circuit region is arranged outside the extension region EXT, and a plurality of transistors constituting a drive circuit, a read / write circuit, and a control circuit are arranged in the peripheral circuit region. Alternatively, the peripheral circuit region is also disposed below the cell region CEL and the extension region EXT.

[0015] 1A, 1B, and 2 to 4, the semiconductor device 100 includes a substrate 101, a gate structure GS, a cell channel structure CH, a dummy channel structure DCH, a word line cut WLC, a common source line 50, an insulating spacer 53, a contact CNT, an isolation insulating pattern SSC, a mold insulating layer 40, an upper insulating layer (41, 42, 43, 44), a bit line BL, and a connecting line CL.

[0016] The substrate 101 is a semiconductor substrate. For example, the substrate 101 comprises a silicon wafer, an epitaxially grown SiGe wafer, or an SOI wafer. A gate structure GS is disposed on the substrate 101 . The gate structure GS is formed by alternately stacking gate electrode layers 10 (10a to 10l) and interlayer insulating layers 20 in a direction substantially perpendicular to the substrate. The gate electrode layers 10 are electrically isolated from one another by interlayer insulating layers 20 .

[0017] Herein, when a first component is described as extending in a direction substantially perpendicular (or orthogonal) to or parallel to a second component or direction, it can be understood that the first component extends in a direction exactly perpendicular to or parallel to the second component or direction, or that the first component extends in a direction approximately perpendicular to or parallel to the second component or direction within measurement error, as would be understood by one skilled in the art.

[0018] The gate electrode layer 10 forms a pair with the interlayer insulating layer 20 and extends in a first direction to different lengths to provide a stepped pad region PAD. In one embodiment, the pad area PAD forms a staircase structure along the first direction. A contact CNT is connected to the pad area PAD. The cell channel structure CH extends in a first direction substantially perpendicular to the upper surface of the substrate 101 .

[0019] The gate electrode layer 10 provides the lowest ground selection line GSL closest to the substrate 101, word lines WL (10b to 10j) arranged on the ground selection line GSL, and string selection lines SSL arranged on the word lines WL. The ground selection line GSL and the string selection line SSL each have a multi-layer structure. The gate electrode layer 10 further includes dummy word lines between the top word line 10j farthest from the substrate 101 and the string select line SSL (10k), and / or between the bottom word line 10b closest to the substrate 101 and the ground select line GSL (10a). The gate electrode layer 10 includes a metallic material such as, for example, tungsten, copper, or a metal silicide. The interlayer insulating layer 20 includes an oxide-based material such as silicon oxide, silicon oxycarbide, or silicon oxynitride.

[0020] The cell channel structure CH extends substantially perpendicular to the upper surface of the substrate 101 in the cell region CEL, and penetrates the gate electrode layer 10 and the interlayer insulating layer 20 . The cell channel structures CH are arranged along a second direction to define a pad row, and a plurality of pad rows are arranged along a third direction. The cell channel structures CH are arranged in a zigzag pattern on a plane. In one embodiment, a semiconductor pattern is further provided between the cell channel structure CH and the upper surface of the substrate 101 . The semiconductor pattern includes, for example, monocrystalline silicon or polysilicon.

[0021] In this specification, terms such as "first," "second," and "third" are used to distinguish one component from another, and the components are not limited by these terms. Thus, a "first" configuration in one exemplary embodiment may be described as a "second" configuration in another exemplary embodiment.

[0022] A gate electrode layer 10 surrounds the cell channel structure CH. Furthermore, the gate electrode layers 10 are spaced apart from each other in the first direction. Furthermore, the gate electrode layer 10 extends in a second direction substantially perpendicular to the first direction.

[0023] Referring to FIG. 5, the cell channel structure CH includes a channel 31 , a dielectric film structure 32 and a buried insulating pattern 33 . The channel 31 has a hollow cylinder or cup shape. For example, channel 31 includes an exterior surface that defines an open interior space. The channel 31 includes polysilicon or single crystal silicon, and includes p-type impurities such as boron (B) in a partial region. The buried insulating pattern 33 is arranged in the inner space of the channel in the shape of a pillar or a solid cylinder.

[0024] In one embodiment, the buried insulating pattern 33 fills the interior space of the channel 31 . The buried insulating pattern 33 includes an insulating material such as silicon oxide. In one embodiment, the channel 31 has a pillar-like or solid cylindrical shape. For example, channel 31 does not include an open interior space. In this case, the buried insulating pattern 33 is omitted. The dielectric membrane structure 32 surrounds the outer wall of the channel and has a substantially straw-like or cylindrical shell-like shape.

[0025] The dielectric film structure 32 includes a tunnel insulating film 32T, a charge storage film 32E, and a blocking film 32B, which are sequentially stacked on the outer wall of the channel 31. The blocking film 32B includes a metal oxide such as silicon oxide, hafnium oxide, or aluminum oxide. The charge storage layer 32E includes a nitride such as silicon nitride or a metal oxide, and the tunnel insulating layer 32T includes an oxide such as silicon oxide. In one embodiment, the dielectric film structure 32 has an ONO (Oxide-Nitride-Oxide) stacked structure in which an oxide film, a nitride film, and an oxide film are stacked in this order.

[0026] In one embodiment, the gate structure GS further includes an interface pattern 32BK2 surrounding the outer wall of the gate electrode layer 10. For example, the interface pattern 32BK2 includes a metal oxide, such as aluminum oxide, and / or a metal nitride, such as tungsten nitride, titanium nitride, or tantalum nitride.

[0027] Referring again to FIGS. 1A, 1B, and 2 to 4, a pad 34 is formed on the cell channel structure CH. The pad 34 is electrically connected to, for example, a bit line BL, and functions as a source / drain for transferring charges within the channel 31 . The pad 34 includes polysilicon or single crystal silicon and further includes n-type impurities such as phosphorus (P) or arsenic (As).

[0028] The dummy channel structure DCH extends in the extension region EXT along a direction substantially perpendicular to the upper surface of the substrate 101 and penetrates the gate electrode layer 10 and the mold insulating layer 40 . The dummy channel structure DCH has a structure similar to that of the cell channel structure CH. The dummy channel structure DCH is different from the cell channel structure CH and is electrically isolated from the bit line BL. The dummy channel structure DCH is provided to ensure structural stability during the manufacturing process. That is, in one embodiment, the cell channel structure CH is electrically connected to the bit line BL, and the dummy channel structure DCH is not electrically connected to the bit line BL but provides structural stability.

[0029] The word line cuts WLC are arranged substantially parallel to each other in the third direction. For example, the word line cuts WLC are arranged adjacent to each other in the third direction. At least some of the word line cuts WLC have the same shape as each other, and portions corresponding to each other in the third direction have the same width in the third direction.

[0030] The word line cut WLC extends in the second direction and cuts the gate structure GS and the mold insulating layer 40 in the second direction. For example, the word line cut WLC has a length that extends in the second direction. The word line cut WLC extends continuously in the second direction. For example, the word line cut WLC extends continuously in the second direction without any gap or opening therein. The gate electrode layer 10 and the interlayer insulating layer 20 are divided into a plurality of blocks (BK1, BK2) by the word line cut WLC. Within each block (BK1, BK2), the gate electrode layer 10 providing the word line is separated into two unit electrodes (UA1, UA2) and (UA3, UA4) by a word line cut WLC. For example, nine channel rows are arranged on one unit electrode. The word line cut WLC cuts the gate electrode layer 10 in the first direction.

[0031] In one embodiment, the identical extended word line cuts WLC1 are arranged substantially parallel to and alternate with the remaining word line cuts WLC other than the extended word line cuts WLC1 in the second direction. A common source line 50 is disposed within the word line cut WLC. Insulating spacers 53 are formed on the sidewalls of the common source line 50 and extend in the second direction together with the common source line 50 . A common source line 50 is connected to the source regions of the substrate 101 . The source region is formed by implanting impurities of a particular conductivity type into the substrate 101, and is, for example, a region doped with n-type impurities.

[0032] The isolation insulating pattern SSC separates some of the gate electrode layers 10 arranged at the top among the gate electrode layers 10 in the third direction. For example, the isolation insulating pattern SSC separates the two uppermost gate electrode layers (10k, 10l) in the third direction. The separation insulating pattern SSC separates one unit electrode (UA1, UA2, UA3, UA4) into two lower unit electrodes. Each block (BK1, BK2) including two unit electrodes (UA1, UA2) and (UA3, UA4) includes four lower unit electrodes. Four lower unit electrodes separated from each other provide four string selection lines SSL for each block (BK1, BK2).

[0033] The contact CNT is placed in the extension region EXT. The contact CNTs penetrate the mold insulating layer 40 and the interlayer insulating layer 20 and are connected to the pad regions PAD of the gate electrode layer 10, respectively. In FIG. 1A, contacts CNT are arranged for each pad area PAD, but the present invention is not limited to this, and some of the contacts CNT can be omitted. Therefore, in one embodiment, some pad areas PAD may have contact CNTs disposed therein, and one or more pad areas PAD may not have contact CNTs disposed therein.

[0034] The word line cut WLC includes at least one first word line cut WLC1 and a plurality of second word line cuts WLC2. The first word line cut WLC1 includes an extension 60 whose width in the third direction is expanded in a partial region. For example, the first word line cut WLC1 has a length extending in the second direction and a width extending in the third direction. The first word line cut WLC1 has substantially the same width in the second direction except for the extension 60, which has a different width than the remainder of the first word line cut WLC1. For example, the width of the extension 60 in the third direction is larger than the width of the remaining part of the first word line cut WLC1 in the third direction.

[0035] In one embodiment, the extensions 60 of the multiple first word line cuts WLC1 are aligned with each other in the third direction. In one embodiment, the extension portion 60 is disposed in a region within the cell region CEL that is close to the extension region EXT. For example, the extension portion 60 is disposed in the cell region CEL adjacent to the extension region EXT. The region in the cell region CEL where the extension portion 60 is arranged is either directly adjacent to the extension region EXT, or there is a space between the region and the extension region EXT. Hereinafter, the first word line cut WLC1 will also be referred to as the extended word line cut WLC1.

[0036] Herein, when two or more elements or values ​​are described as being substantially identical or nearly identical, the elements or values ​​are identical to each other or indistinguishable from each other. Alternatively, they may be distinguishable from one another but are functionally identical to one another as would be understood by one of ordinary skill in the art. For example, if two or more elements or values ​​are substantially identical or nearly identical but do not coincide with each other, the two or more elements or values ​​are nearly identical or identical within what one of ordinary skill in the art would understand to be measurement error.

[0037] In one embodiment, the first word line cut WLC1 including the extension 60 is disposed adjacent to both sidewalls of the gate structure GS, as shown in FIG. 1A. The word line cuts WLC disposed adjacent to both side walls of the gate structure GS are prone to not-open. The not-open phenomenon refers to a phenomenon in which the word line cut WLC attempts to provide an opening (or space) between adjacent structures, but the opening (or space) is not formed or maintained during and / or after the manufacturing process.

[0038] In FIG. 1A, one extended word line cut WLC1 is disposed on each side wall of the gate structure GS, but the present invention is not limited thereto. The extended word line cuts WLC1 may be arranged in a regular pattern along the third direction, or may be arranged in an irregular pattern. For example, referring to FIG. 1B, in the semiconductor device, an extended word line cut WLC1 including an extended portion 60 and a second word line cut WLC2 not including an extended portion 60 are alternately arranged parallel to each other in the third direction. In one embodiment, in a plan view, the extended word line cuts WLC1 are disposed adjacent to both sidewalls of each gate electrode layer 10 spaced apart from each other in a third direction substantially perpendicular to the second direction.

[0039] In one embodiment, the common source lines 50 include at least one first common source line 51 and a plurality of second common source lines 52 . The first common source line 51 is disposed in a first word line cut WLC1, and the second common source line 52 is disposed in a second word line cut WLC2. The first common source line 51 includes an extension pattern having an area (or width in the third direction) different from that of the other common source lines 50 at a predetermined position.

[0040] In one embodiment, the extension portion 60 of the first word line cut WLC1 and the extension pattern of the first common source line 51 disposed within the extension portion 60 are disposed near the contact point between the cell region CEL and the extension region EXT. The position where the extension portion 60 of the first word line cut WLC1 is formed is a position where not-opens are likely to occur during the etching process for forming the word line cut WLC.

[0041] 6, 7, 8A, and 8B are plan views showing a part of the gate electrode layer shown in FIG. 1A. The same reference symbols in FIGS. 1A, 1B, 2 to 7, 8A, and 8B indicate the same components, and in the following, for simplicity, redundant explanations of these will be omitted.

[0042] Referring to FIG. 6, word line cuts (WLC1l, WLC2l), a common source line 50 disposed within the word line cuts (WLC1l, WLC2l), and an isolation insulating pattern SSC divide the top gate electrode layer 10l, which serves as a string select line SSL, into a plurality of lower unit electrodes (11l, 12l, 13l). In one embodiment, the extended word line cut WLC1 includes a first portion and a second portion having different widths in the third direction. For example, the first portion has a relatively narrow first width W1, and the second portion has a relatively wide second width W2. For example, the first width W1 is smaller than the second width W2. The second portion having the second width W2 corresponds to the extension 60 described above.

[0043] In the gate structure GS, the region where the first portion is disposed is divided into a first region, and the region where the second portion is disposed is divided into a second region. For example, a second portion (e.g., extension 60) of the extended word line cut WLC1 having a second width W2 is disposed in the second region, and the remaining portion of the extended word line cut WLC1 having a first width W1 is disposed in the first region. The first width W1 of the first portion (or the area of ​​the first portion) is substantially the same as the width Wkl (or the area) of the portion located in the first region of the other (second) word line cut WLC2 that does not include the extension portion 60. The second width W2 of the second portion (or the area of ​​the second portion) is different from the width Wkl (or the area thereof) of the portion of the other (second) word line cut WLC2 disposed in the second region. For example, the area of ​​the second portion of the extended word line cut WLC1 is relatively larger than the area of ​​the portion corresponding to the second portion of another (second) word line cut WLC2 in the third direction.

[0044] In one embodiment, the top extension word line cut WLC1 includes a top extension portion 60 located at the same level as the topmost one of the gate electrode layers 10 . The lowest extended word line cut WLC1 is located at the same level as the lowest gate electrode layer 10 located at the lowest level among the gate electrode layers 10, and has a relatively smaller area than the uppermost extended portion 60. The lowest extension 60 has a width equal to or greater than the width of the portion of the word line cut WLC located at the same level as the lowest extension 60 except for a predetermined region.

[0045] Referring to FIG. 7, the word line cuts (WLC1k, WLC2k), the common source line 50, and the isolation insulating pattern SSC divide the upper gate electrode layer 10k, which serves as the string select line SSL, into a plurality of lower unit electrodes (11k, 12k, 13k). As shown in FIG. 6, the extended word line cut WLC1k includes a third portion and a fourth portion having different widths in the third direction. The third portion is disposed in the first region, and the fourth portion is disposed in the second region. The fourth portion having a fourth width corresponds to the extension 60 described above. The third portion has a relatively narrow third width W3, and the fourth portion has a relatively wide fourth width W4. For example, the third width W3 is smaller than the fourth width W4. Referring to Figures 6 and 7, the value of W4 / W3 is substantially the same as or smaller than the value of W2 / W1.

[0046] 1A and 8A, word line cuts (WLC1a, WLC2a) and a common source line 50 divide the lowest gate electrode layer 10a, which serves as a ground selection line GSL, into a plurality of unit electrodes UA1, 11a, and UA2. In one embodiment, the extended word line cut WLC1a includes a fifth portion and a sixth portion that have different widths in the third direction. The fifth portion is disposed in the first region, and the sixth portion is disposed in the second region. For example, the fifth portion has a relatively narrow fifth width W5, and the sixth portion has a relatively wide sixth width W6. The sixth portion having a sixth width W6 corresponds to the extension 60 described above. The fifth width W5 is smaller than the sixth width W6. The fifth width W5 is substantially the same as or narrower than the first width W1 (see FIG. 6) and / or the third width W3 (see FIG. 7). The sixth width W6 is narrower than the second width W2 (see FIG. 6) and / or the fourth width W4 (see FIG. 7). The fifth width W5 is substantially the same as the width Wka of the (second) word line cut WLC2a. Referring to FIG. 6 and FIG. 8A, the value of W6 / W5 is smaller than W2 / W1.

[0047] Referring to FIG. 8B, in one embodiment, the extended word line cut WLC1a located at the same level as the lowest gate electrode layer 11a has a width W7 of the portion located in the first region and a width W8 of the portion located in the second region that are substantially the same. The seventh width W7 and the eighth width W8 are substantially the same as the width Wka of the (second) word line cut WLC2a.

[0048] 9A is a plan view showing a schematic layout of a semiconductor device according to a third embodiment of the present invention, FIG. 9B is a perspective view of region F in FIG. 9A, FIG. 10 is a cross-sectional view along line IV-IV' in FIG. 9A, and FIG. 11 is a cross-sectional view along line V-V' in FIG. 9A. In FIG. 9B, for ease of explanation, some of the components shown in area F in FIG. 9A are omitted. The same reference symbols in Figures 1A, 1B, 2 to 7, 8A, 8B, 9A, 9B, 10, and 11 indicate the same components, and in the following, for the sake of simplicity, redundant explanations of these will be omitted.

[0049] 9A, 9B, 10, and 11, the semiconductor device includes a gate structure GS, a connection portion 70, a cell channel structure CH, a dummy channel structure DCH, an extended word line cut WLC1, an isolated word line cut WLC3, a common source line 50, and a contact CNT.

[0050] In one embodiment, the gate structure GS is formed by alternately stacking gate electrode layers 10 and interlayer insulating layers 20 in a first direction substantially perpendicular to the substrate 101 . The gate structure GS is divided into a plurality of blocks BK1 and BK2 by word line cuts WLC1 and WLC3 extending in the second direction. A common source line 50 and an insulating spacer 53 are disposed within the word line cuts (WLC1, WLC3).

[0051] The gate electrode layer 10 is paired with the interlayer insulating layer 20 and extends in the second direction to different lengths to provide stepped pad regions PAD (PAD1 to PAD4). A part of the pad area PAD has a step in both the second direction and the third direction. The pad region PAD forms a first staircase structure along the second direction. As shown in FIGS. 9B and 11, the third pad region PAD3 has a step with another adjacent third pad region PAD3, forming a second staircase structure in the third direction. The fourth pad region PAD4 also has a step with another adjacent fourth pad region PAD4, forming a second staircase structure in the third direction.

[0052] The gate structure GS includes a first block BK1 and a second block BK2. The first block BK1 and the second block BK2 have mirror symmetry in the structures of the pad areas PAD. In one embodiment, the first block BK1 and the second block BK2 have the same structure of the pad area PAD.

[0053] The isolation word line cut WLC3 includes a first isolation word line cut WLC3a and a second isolation word line cut WLC3b. A connection portion 70 is disposed between the first isolation word line cut WLC3a and the second isolation word line cut WLC3b. No. 2 Separation Word Line Cut WLC3b extends long from the connection portion 70 to the cell region CEL along the second direction, No. 1 Separation Word Line Cut WLC3a extends from the connecting portion 70 along the second direction to the extension region EXT. The extended word line cut WLC1 is disposed between two isolation word line cuts adjacent in the second direction (for example, the first isolation word line cut WLC3a and the second isolation word line cut WLC3b).

[0054] The connection portion 70 divides the isolation word line cut WLC3 into a first isolation word line cut WLC3a and a second isolation word line cut WLC3b. The connection portion 70 is formed to protrude in the third direction from the gate electrode layers (10a to 10j) that extend in the second direction. The connection portion 70 connects two unit electrodes (UA1, UA2) and two unit electrodes (UA3, UA4) located at the same level in the gate electrode layers (10a to 10j) to each other. In one embodiment, the connection portion 70 is arranged in a region corresponding to the second pad region PAD2 along the third direction in plan view. The connection portion 70 is not connected to the gate electrode layer (10l, 10k) in the gate structure GS, which serves as the string selection line SSL.

[0055] The extended word line cut WLC1 includes an extension 60. The extension 60 has a width and area in the third direction that are larger than those of the portion of the isolation word line cut WLC3 that corresponds to the extension 60 in the third direction. If the semiconductor device does not include the extended word line cut WLC1, i.e., does not have the extension portion 60, a loading effect occurs due to a mask pattern disposed on the connection portion 70 during the word line cut formation process. Due to the loading effect, a not-open phenomenon occurs in the lowest gate electrode layer (ground selection line GSL). Therefore, the semiconductor device of the present invention can prevent the not-open phenomenon by forming the expansion portion 60 having a large area at the position where the loading effect occurs due to the connection portion 70.

[0056] As shown in FIG. 9B, in one embodiment, the extension portion 60 of the extended word line cut WLC1 has an area (or width) different from that of the remaining word line cuts (e.g., WLC3b) that are not extended word line cuts and are located at the same level in a predetermined region in the second direction. Such a configuration can also be applied to the word line cuts shown in FIGS. 1A, 1B, 2 to 7, 8A, and 8B. As shown in FIG. 9B, the gate electrode layers 10 are stacked in a cascade (step-like) pattern so as to be spaced apart in the first direction and extend in a second direction substantially perpendicular to the first direction.

[0057] FIG. 12 is a plan view showing a schematic layout of a semiconductor device according to a fourth embodiment of the present invention. The same reference symbols in Figures 1A, 1B, 2 to 7, 8A, 8B, 9A, 9B, and 10 to 12 indicate the same components, and in the following, for the sake of simplicity, redundant explanations of these will be omitted.

[0058] Referring to FIG. 12, the semiconductor device includes an extended isolation word line cut WLC4 whose width in the third direction gradually increases, a common source line 50 disposed within the extended isolation word line cut WLC4, and an insulating spacer 53. The extended isolation word line cut WLC4 includes a first extended isolation word line cut WLC4a and a second extended isolation word line cut WLC4b. A connection portion 70 is disposed between the first extended isolation word line cut WLC4a and the second extended isolation word line cut WLC4b. The first extended isolation word line cut WLC4a extends from the connection portion 70 along the second direction to the cell region CEL, and the second extended isolation word line cut WLC4b extends from the connection portion 70 along the second direction to the extension region EXT.

[0059] In one embodiment, at least one of the first extended isolation word line cut WLC4a and the second extended isolation word line cut WLC4b has a width that gradually increases in the third direction as it approaches the connection portion 70 in the second direction. For example, at least one of the first extended isolation word line cut WLC4a and the second extended isolation word line cut WLC4b is extended long in the second direction toward the connection portion 70, and therefore its width gradually increases in the third direction. Although FIG. 12 shows that only the first extended isolation word line cut WLC4a has a gradually increasing width in the third direction, the present invention is not limited to this. For example, in one embodiment, the width of the second extended isolation word line cut WLC4b in the third direction also gradually increases. A step is formed in the extended isolation word line cut WLC4, and the width in the third direction of a portion close to the connection portion 70 around the step is wider than the width in the third direction of a portion far from the connection portion 70.

[0060] The common source line 50 disposed in the extended isolation word line cut WLC4 whose width in the third direction gradually increases also has a width in the third direction gradually increasing as it approaches the connection portion 70 in the second direction. A step is also formed on the sidewall of the common source line 50, and the width in the third direction of a portion close to the connection portion 70 around the step is wider than the width in the third direction of a portion far from the connection portion 70.

[0061] In an embodiment of the present invention, a three-dimensional (3D) memory array is provided. A 3D memory array is monolithically formed in one or more physical levels of memory cell arrays having active areas disposed on a silicon substrate and circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate. The term "monolithic" means that the layers at each level of the array are deposited directly onto the layers at each lower level of the array.

[0062] In an embodiment of the present invention, the 3D memory array includes vertical NAND strings that are oriented vertically such that at least one memory cell is located above another memory cell. At least one memory cell includes a charge trapping layer. The prior art documents cited herein by reference, Patent Documents 1 to 5, describe suitable configurations for three-dimensional memory arrays, where the three-dimensional memory arrays described therein are organized as multiple levels with word lines and / or bit lines shared between the levels.

[0063] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0064] 10(10a-10l) Gate electrode layer 20 Interlayer insulating layer 31 channels 32 Dielectric film structure 32B Blocking Membrane 32BK2 interface pattern 32E Charge storage membrane 32T tunnel insulating film 33 Buried insulation pattern 34 Pad 40 mold insulation layer 41~44 Upper insulating layer 50 Common Source Line 51 First common source line 52 Second common source line 53 Insulating spacer 60 Extension 70 Connection 100 Semiconductor device 101 Substrate BK1, BK2 blocks CH Cell Channel Structure CNT Contact DCH Dummy Channel Structure GS Gate Structure SSC isolation insulating pattern UA1, UA2, UA3, UA4 unit electrodes WLC Word Line Cut WLC1 1st word line cut (extended word line cut) WLC2 Second word line cut

Claims

1. a substrate including a cell region and an extension region; a bit line on the cell area; a plurality of channel structures disposed in the cell region, extending in a first direction substantially perpendicular to an upper surface of the substrate, and electrically connected to the bit lines; a dummy channel structure disposed in the extension region, extending in the first direction, and not electrically connected to the bit line; a plurality of gate electrode layers surrounding the channel structure, spaced apart from one another along the first direction, and extending in a second direction substantially perpendicular to the first direction; a plurality of word line cuts that cut the gate electrode layer in the first direction and extend continuously in the second direction across the cell region and the extension region; Each of the plurality of word line cuts includes: a first word line cut extending in the second direction; a second word line cut spaced apart from the first word line cut in a third direction perpendicular to the first and second directions, The first word line cut is a first portion having a first width in the third direction; an extension portion having a second width greater than the first width in the third direction and extending from the cell region to the extension region in the second direction, a portion of the extension overlaps with the channel structure in the third direction, and a remaining portion of the extension overlaps with the dummy channel structure in the third direction; The semiconductor device according to claim 1, wherein the width of the extension of the first word line cut in the third direction is greater than the width of the second word line cut in the third direction.

2. 2. The semiconductor device according to claim 1, wherein the first word line cut is disposed adjacent to both sidewalls of the gate electrode layer spaced apart in the third direction in a plan view.

3. 2. The semiconductor device according to claim 1, wherein the first word line cuts and the second word line cuts are alternately arranged in the third direction and are parallel to the second direction.

4. 2. The semiconductor device according to claim 1, wherein the first width is substantially equal to a width of the second word line cut in the third direction.

5. The extension portion includes a top extension portion located at the same level as a top gate electrode layer located at the top level of the gate electrode layers; 2. The semiconductor device according to claim 1, further comprising: a lowest extension portion located at the same level as a lowest gate electrode layer located at the lowest level among the gate electrode layers, the lowest extension portion having a relatively smaller area than the highest extension portion.

6. 6. The semiconductor device of claim 5, wherein the bottom extension has a width equal to or greater than a width of the second word line cut located at the same level in the third direction.

7. a substrate including a cell region and an extension region; a plurality of cell channel structures disposed in the cell region, extending in a first direction substantially perpendicular to an upper surface of the substrate, and electrically connected to bit lines; a dummy channel structure disposed in the extension region, extending in the first direction, and not connected to the bit line; a plurality of gate electrode layers surrounding the channel structure, stacked in a stepped pattern spaced apart from each other along the first direction, and extending in a second direction substantially perpendicular to the first direction; a plurality of word line cuts that cut the gate electrode layer in the first direction and extend in the second direction across the cell region and the extension region; a connection portion that connects gate electrode layers arranged in the same layer and protrudes from the gate electrode layers, Each of the plurality of word line cuts includes: a first word line cut extending in the second direction; a second word line cut spaced apart from the first word line cut in a third direction perpendicular to the first and second directions, The first word line cut is a first portion having a first width in the third direction; an extension portion having a second width greater than the first width in the third direction and extending from the cell region to the extension region in the second direction, the second word line cut includes a (2-1)th isolation word line cut extending in the second direction from the connection portion toward the extension region, and a (2-2)th isolation word line cut extending in the second direction from the connection portion toward the cell region, the extension overlaps the (2-2) isolation word line cut in a third direction substantially perpendicular to the first and second directions; a portion of the extension overlaps with the channel structure in the third direction, and a remaining portion of the extension overlaps with the dummy channel structure in the third direction; The semiconductor device is characterized in that the width of the extension portion of the first word line cut in the third direction is larger than the width of the (2-2) isolation word line cut in the third direction.

8. The semiconductor device of claim 7 , wherein the first word line cut is disposed between the second word line cuts spaced apart in the third direction.

9. 8. The semiconductor device according to claim 7, wherein the connection portion is disposed in the extension region.

10. the gate electrode layer includes a ground selection line, a word line, and a string selection line, which are sequentially stacked in the first direction from an upper surface of the substrate; The string selection lines arranged in the same layer are separated from each other and extend, 8. The semiconductor device according to claim 7, wherein the word lines arranged in the same layer are connected to each other by the connecting portion and extended.

11. 11. The semiconductor device of claim 10, wherein the extension portion located at the same level as the string selection line has a relatively larger area than the extension portion located at the same level as the ground selection line.

12. 12. The semiconductor device of claim 11, wherein the width in the third direction of the extension portion located at the same level as the ground selection line is equal to or greater than the width in the third direction of a portion of the second word line cut located at the same level as the string selection line and corresponding to the extension portion in the third direction.

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