Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure and the semiconductor structure are described. The method includes patterning a substrate to form a first opening and a second opening, the substrate comprising an n-transistor and a p-transistor, the first opening being on the n-transistor and the second opening being on the p-transistor, pre-cleaning the substrate, depositing a titanium silicide (TiSi) layer on the n-transistor and on the p-transistor by plasma enhanced chemical vapor deposition (PECVD), optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p-transistor, selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n-transistor and the p-transistor, forming a second barrier layer on the molybdenum silicide (MoSi) layer, and annealing the semiconductor structure. The method can be carried out in a processing chamber without breaking vacuum.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device fabrication. More particularly, embodiments of the present disclosure relate to methods for selectively forming silicide layers with ohmic and quasi-ohmic contacts. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] Transistors are key components of most integrated circuits. Because the drive current, and therefore speed, of a transistor is proportional to the transistor's gate width, faster transistors generally require larger gate widths. This creates a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. finFETs feature a fin-shaped channel region that significantly increases the size of transistors without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, finFETs have their own drawbacks.

[0004] As transistor device feature sizes continue to shrink to achieve higher circuit density and higher performance, there is a need to improve transistor device structures to improve capacitive coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (finFET) structures, and gate-all-around (GAA) structures. Logic gate performance is related to the properties of the materials used and the thickness and area of ​​the structural layers. However, challenges arise as some gate characteristics are adjusted to accommodate device scaling.

[0005] Ohmic or pseudo-ohmic contacts are key elements in achieving low contact resistance at source / drain contacts in transistors. There is a need in the art for methods to selectively form ohmic and pseudo-ohmic contacts on both nFET and pFET contacts. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor structure, the method comprising: patterning a substrate to form a first opening and a second opening, the substrate comprising an n-transistor and a p-transistor, the first opening being over the n-transistor and the second opening being over the p-transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n-transistor and on the p-transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p-transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer over the n-transistor and the p-transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure.

[0007] Another embodiment of the present disclosure is directed to a method of forming a semiconductor structure, the method comprising: patterning a substrate to form a first opening, the substrate comprising an n-transistor and a p-transistor, the first opening overlying the n-transistor, pre-cleaning the substrate, depositing a titanium silicide (TiSi) layer on the n-transistor by plasma-enhanced chemical vapor deposition (PECVD), filling the first opening with a first gap-fill material, forming a mask layer on a top surface of the n-transistor, patterning the substrate to form a second opening over the p-transistor, selectively forming a molybdenum silicide (MoSi) layer on the p-transistor, annealing the semiconductor structure, and filling the second opening with a second gap-fill material.

[0008] A further embodiment of the present disclosure is directed to a semiconductor structure comprising an n-transistor and a p-transistor, a titanium silicide (TiSi) layer on one or both of the n-transistor and the p-transistor, a molybdenum silicide (MoSi) layer on one or both of the n-transistor and the p-transistor, optionally a barrier layer on one or both of the titanium silicide (TiSi) layer and the molybdenum silicide (MoSi) layer, and a gap fill material.

[0009] So that the above-recited features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, since the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0010] [Figure 1A]1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 1B] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 1C] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 1D] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 1E] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 1F] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 2A] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 2B] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 2C] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 2D] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 2E] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 2F] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 2G] 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 3] FIG. 1 is a process flow diagram of a method according to one or more embodiments of the present disclosure. [Figure 4] FIG. 1 is a process flow diagram of a method according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the accompanying figures, similar components and / or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. When only a first reference label is used herein, the description is applicable to any of the similar components having the same first reference label, regardless of the second reference label.

[0012] Before describing several example embodiments of the invention, it is to be understood that the invention is not limited to the details of construction or process steps set forth in the following description. The invention is capable of other embodiments and of being practiced or of being carried out in various ways.

[0013] As used herein, the term "substrate" refers to a surface, or portion of a surface, on which a process acts. Those skilled in the art will also understand that a reference to a substrate can refer to only a portion of a substrate, unless the context clearly dictates otherwise. Additionally, a reference to depositing on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0014] Additionally, the term "substrate" as used herein refers to a substrate or a material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatments may be performed include materials such as silicon, silicon oxide, strained silicon (developed by IBM), silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material, such as a metal, metal nitride, metal alloy, dielectric material, other conductive material, or combinations thereof, depending on the application. In some embodiments, the substrate comprises silicon (Si), ruthenium (Ru), cobalt (Co), tungsten (W), silicon phosphide (SiP), titanium silicon (TiSi), titanium nitride (TiN), titanium aluminide (TiAl), silicon germanium (SiGe), silicon germanium boron (SiGeB), hafnium oxide (HfO), aluminum oxide (AlO), or combinations thereof. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatments performed directly on the substrate surface itself, in the present disclosure, any of the disclosed film treatment steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include underlayers as the context dictates.

[0015] According to one or more embodiments, the term "on" with respect to a film or layer of a film includes the film or layer being directly on a surface, e.g., a substrate surface, as well as having one or more underlying layers between the film or layer and the surface, e.g., a substrate surface. Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on" refers to a layer or film in contact with a surface, e.g., a substrate surface, without an intervening layer. Thus, the phrase "a layer directly on the substrate surface" refers to a layer in direct contact with the substrate surface, without an intervening layer.

[0016] As used herein, the term "substrate surface" refers to any substrate surface on which a layer may be formed. A substrate surface may have one or more features formed therein, one or more layers formed thereon, and combinations thereof. The shape of the feature may be any suitable shape, including, but not limited to, a peak, a trench, and a cylindrical via. As used in this regard, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include, but are not limited to, a trench having a top, two sidewalls, and a bottom; a peak having a top and two sidewalls extending upward from the surface; and a via having a sidewall extending downward from the surface with an open bottom.

[0017] As used herein, the term "processing chamber" includes a portion of the processing chamber adjacent to the substrate surface, but not necessarily encompassing the entire interior volume of the processing chamber. For example, in spatially separated processing chamber sectors, the portion of the processing chamber adjacent to the substrate surface is purged by any suitable technique, including, but not limited to, moving the substrate through a gas curtain to a portion or sector of the processing chamber that contains no or substantially no reactive compounds.

[0018] As used herein, the term "atomic layer deposition" or "cyclic deposition" refers to sequential exposure to two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate, or portions of the substrate surface, are sequentially exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. The sequential exposure of the reactive gases prevents or minimizes gas-phase reactions between the reactive gases. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds such that a given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used herein and in the appended claims, the term "substantially" used in this context means that, as understood by those skilled in the art, small portions of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and simultaneous exposure is not intended.

[0019] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B is pulsed into the reaction zone, followed by a second time delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove residual reactive compounds or byproducts from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process, with only the purge gas flowing during the time delay between pulses of reactive compounds. The reactive compounds are alternately pulsed until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle can begin with either compound A or compound B and continue with each order of the cycle until a film with the desired thickness is achieved. In one or more embodiments, a time-domain ALD process can be performed with three or more reactive compounds in a predetermined order.

[0020] In aspects of spatial ALD processes, a first reactive gas and a second reactive gas are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply system so that a given point on the substrate is exposed to the first reactive gas and the second reactive gas. In one or more embodiments, a spatial ALD process can be performed with three or more reactive compounds in a predetermined order.

[0021] In some embodiments, the substrate surface is exposed to the first reactive compound and the second reactive compound substantially continuously. As used herein throughout this specification, "substantially continuously" means that the majority of the duration of the first reactive compound exposure does not overlap with the second reactive compound exposure, although there may be some overlap.

[0022] As used herein, the term "chemical vapor deposition" refers to the exposure of at least one reactive compound to deposit a layer of material on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process comprises mixing two or more reactive compounds in a processing chamber to allow gas-phase reaction and deposition of the reactive compounds. In some embodiments, the CVD process comprises exposing the substrate surface to two or more reactive compounds simultaneously. In some embodiments, the CVD process comprises exposing the substrate surface to a first reactive compound continuously with intermittent exposure to a second reactive compound. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a film having a predetermined thickness. In a CVD process, the film can be deposited in a single exposure to the mixed reactive compounds or can be multiple exposures to the mixed reactive compounds with purges in between. In some embodiments, the substrate surface is exposed to the first reactive compound and the second reactive compound substantially simultaneously.

[0023] As used herein throughout the specification, "substantially simultaneously" means that the majority of the duration of the first reactive compound exposure overlaps with the second reactive compound exposure.

[0024] As used herein, the term "purging" includes any suitable purging process that removes unreacted precursors, reaction products, and by-products from the process region. A suitable purging process includes moving the substrate through a gas curtain to a portion or sector of the processing region that contains no or substantially no reactants. In one or more embodiments, purging the processing chamber comprises applying a vacuum. In some embodiments, purging the processing region comprises flowing a purge gas over the substrate. In some embodiments, the purge process comprises flowing an inert gas. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N), helium (He), and argon (Ar). In some embodiments, the first reactive compound is purged from the reaction chamber for a duration in the range of 0.2 seconds to 30 seconds, 0.2 seconds to 10 seconds, 0.2 seconds to 5 seconds, 0.5 seconds to 30 seconds, 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds prior to exposing the substrate to the second reactive compound.

[0025] Plasma-enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to its cost-effectiveness and versatility in film properties. In a PECVD process, a hydrocarbon source, such as a gaseous hydrocarbon or a liquid-phase hydrocarbon vapor entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-initiating gas, typically helium, is also introduced into the chamber. A plasma is then initiated in the chamber to create excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate placed in the chamber, forming a desired film on the surface of the substrate. The embodiments described herein with respect to PECVD processes can be performed using any suitable thin film deposition system. Any apparatus description described herein should not be construed or interpreted as limiting the scope of the embodiments described herein.

[0026] As used herein, the term "liner" or "barrier layer" refers to a layer conformally formed along at least a portion of the sidewalls and / or lower surface of an opening such that a substantial portion of the opening prior to deposition of the layer remains unfilled after deposition of the layer. The liner may be formed along the entire sidewalls and lower surface of the opening. The liner may be formed by any process known to those skilled in the art. In some embodiments, the liner comprises a metal nitride, a PVD metal, or a combination thereof.

[0027] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). A MOSFET has an insulated gate, the voltage across which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals.

[0028] Generally, a transistor includes a gate formed between a source region and a drain region. The source and drain regions may include doped regions of a substrate and may exhibit a doping profile suitable for a particular application. The gate is disposed above a channel region and may include a gate dielectric interposed in the substrate between the gate electrode and the channel region.

[0029] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field across the device, created by the voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers exit the channel; and the gate (G), i.e., the terminal that modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is known as I S The current entering the channel at the drain (D) is expressed as I D The drain-source voltage is expressed as V DS By applying a voltage to the gate (G), a current (i.e., I D ) can be controlled.

[0030] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). MOSFETs have an insulated gate, the voltage across which determines the device's conductivity. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on modulation of charge concentration through metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body, insulated from all other device regions by a gate dielectric layer. Compared to MOS capacitors, MOSFETs contain two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be either p-type or n-type, but they can both be of the same type or the opposite type to the body region. The source and drain (unlike the body) are highly doped, as indicated by the "+" sign after the doping type.

[0031] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; analogously, the drain is where the charge carriers exit the channel.

[0032] Embodiments of the present disclosure provide semiconductor structures and methods for forming semiconductor structures. Ohmic and / or pseudo-ohmic contacts are key factors in achieving low contact resistance for source / drain contacts. One or more embodiments advantageously provide an integration scheme for providing dual silicides to create ohmic / pseudo-ohmic contacts on both nFET and pFET contacts.

[0033] Embodiments of the present disclosure will be described through diagrams illustrating processes for forming dual silicide on ohmic / pseudo-ohmic contacts on both nFET and pFET contacts. Referring to FIGS. 1A-1E, a semiconductor structure 100 is shown. The semiconductor structure 100 comprises an n-transistor 102 and a p-transistor 104. In one or more embodiments, the n-transistor 102 and the p-transistor 104 each comprise a dielectric material 110, a source / drain material 120, and a substrate 130.

[0034] In one or more embodiments, the dielectric material 110 may comprise any suitable dielectric material known to those skilled in the art. In some embodiments, the dielectric material 110 comprises one or more of silicon, silicon oxide, silicon nitride, silicon carbide, and a low-k dielectric. As used herein, terms such as “silicon oxide” and “silicon nitride” refer to materials comprising silicon and oxygen or materials comprising silicon and nitrogen. “Silicon oxide” and “silicon nitride” should not be understood to imply any stoichiometric ratio. In other words, a dielectric material comprising silicon oxide or silicon nitride can be stoichiometric or non-stoichiometric, and can be silicon-rich or silicon-poor. In some embodiments, the dielectric material 110 comprises silicon oxide (SiO2).

[0035] In some embodiments, n-transistor 102 and p-transistor 104 comprise source and drain contacts. In one or more embodiments, source / drain material 120 can have two or more layers. In some embodiments, source / drain material 120 comprises a layer of silicon (e.g., SiGe, SiP, etc.) with doped epi, a second layer of silicide that may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, etc.

[0036] In one or more particular embodiments, the source / drain material 120 of the n-transistor 102 comprises silicon (Si) doped with phosphorus (P). In one or more embodiments, the source / drain material 120 of the n-transistor 102 has a bandgap in the range of about 1.0 eV to about 1.2 eV.

[0037] In one or more embodiments, the source / drain material 120 of the p-transistor 104 comprises silicon germanium (SiGe) doped with boron (B). In one or more embodiments, the source / drain material 120 of the p-transistor 104 has a bandgap in the range of about 0.5 eV to about 1.0 eV.

[0038] 1A-1D , a first opening 106 is located above the n-transistor 102, and a second opening 108 is located above the p-transistor 104. The first and second openings can have any suitable aspect ratio (ratio of opening depth to opening width). In one or more embodiments, the first and second openings can independently have an aspect ratio in the range of 3:1 to 15:1, 6:1 to 15:1, 9:1 to 15:1, 12:1 to 15:1, or greater than 10:1.

[0039] In one or more embodiments, the structure (or surface of the structure) 100 is cleaned. In some embodiments, cleaning the structure 100 removes oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a substantially oxide-free surface. As used in this manner, the term "substantially oxide-free" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, an anisotropic etch is used to remove oxide from the surface. In one or more embodiments, the anisotropic etch removes more oxide from the surface of the source / drain material 120 than from the surface of the dielectric material 110. In one or more embodiments, cleaning the structure forms a substantially oxide-free source / drain material 120.

[0040] 1B , a titanium silicide (TiSi) layer 140 is deposited on each of the n-transistor 102 and the p-transistor 104. The titanium silicide layer 140 may have any suitable thickness. In some embodiments, the titanium silicide layer 140 has a thickness in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, the titanium silicide (TiSi) layer 140 on the n-transistor 102 has a Schottky barrier height in the range of about 0.4 eV to about 0.55 eV.

[0041] 1C , an optional first barrier layer 150 is deposited on each of the n-transistor 102 and the p-transistor 104. In one or more embodiments, the optional first barrier layer 150 comprises a metal. In one or more embodiments, the optional first barrier layer 150 comprises a metal nitride. In one or more embodiments, the optional first barrier layer 150 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN). In one or more embodiments, the n-transistor 102 with the optional first barrier layer 150 has a lower Schottky barrier height than an n-transistor without the optional first barrier layer.

[0042] 1D , when present, the first barrier layer 150 on the p-transistor 104 is selectively removed from the p-transistor 104 and not from the n-transistor. The first barrier layer 150 may be removed by any suitable technique known to those skilled in the art. In one or more embodiments, the first barrier layer 150 is removed by one or more of etching, chemical mechanical polishing (CMP), planarization, etc.

[0043] 1E, a molybdenum silicide (MoSi) layer 160 is formed on the titanium silicide (TiSi) layer 140 on each of the n-transistor 102 and the p-transistor 104. In one or more embodiments, the molybdenum silicide (MoSi) layer 160 is formed on the optional first barrier layer 150 on the n-transistor 102. The molybdenum silicide (MoSi) layer 160 can have any suitable thickness. In some embodiments, the molybdenum silicide (MoSi) layer 160 has a thickness in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, the molybdenum silicide (MoSi) layer 160 has a thickness of about 40 Å.

[0044] Molybdenum silicide (MoSi) layer 160 may be formed according to any suitable process known to those skilled in the art. In one or more embodiments, structure 100 is first cleaned to remove oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a substantially oxide-free surface. As used in this manner, the term "substantially oxide-free" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, an anisotropic etch is used to remove oxide from the surface.

[0045] In one or more embodiments, a metal film is selectively formed on titanium silicide (TiSi) layer 140 to form molybdenum silicide (MoSi) layer 160. In some embodiments, structure 100 is exposed to a metal precursor and a reactant. The metal film can be deposited by an ALD deposition process, a CVD deposition process, or a combination thereof. In some embodiments, the metal film comprises a molybdenum silicide (MoSi) film.

[0046] In one or more embodiments, the metal precursor comprises a molybdenum precursor. In some embodiments, the molybdenum precursor comprises a molybdenum halide. In some embodiments, the molybdenum halide comprises molybdenum fluoride, molybdenum chloride, or a combination thereof. In certain embodiments, the molybdenum precursor comprises molybdenum fluoride. In other specific embodiments, the molybdenum precursor comprises molybdenum chloride. In one or more embodiments, the precursor is flowed over the surface using a carrier gas. In some embodiments, the carrier gas is flowed through an ampoule containing the precursor. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N2, Ar, and He.

[0047] In one or more embodiments, the reactant comprises an oxidizing agent, a reducing agent, or a combination thereof. In some embodiments, the reactant comprises hydrogen (H), ammonia (NH), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher silanes, and substituted silanes. In particular embodiments, the reactant comprises silane to form a molybdenum silicide (MoSi) layer 160. In one or more embodiments, the reactant is flowed over the surface using a carrier gas. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N, Ar, and He. In other embodiments, the reactant gas may be flowed continuously, and the flow of the molybdenum precursor into the chamber is turned on and off.

[0048] 1E, a second barrier layer 170 is formed on each of the n-transistor 102 and the p-transistor 104. The second barrier layer 170 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the second barrier layer 170 comprises a PVD metal film. In one or more embodiments, the second barrier layer 170 comprises nitrided molybdenum silicide (MoSiN). In one or more embodiments, the second barrier layer 170 comprises molybdenum nitride (MoN). In one or more embodiments, the second barrier layer 170 prevents oxide formation on the molybdenum silicide (MoSi) layer 160. In one or more embodiments, the n-transistor 102 having the second barrier layer 170 formed thereon has a lower Schottky barrier height than an n-transistor without the second barrier layer formed thereon. In one or more embodiments, a p-transistor 104 having a second barrier layer 170 formed thereon has a lower Schottky barrier height than a p-transistor that does not have a second barrier layer formed thereon.

[0049] The second barrier layer 170 may be formed by any process known to those skilled in the art. In some embodiments, the second barrier layer 170 is formed on the molybdenum silicide (MoSi) layer 160. In some embodiments, the molybdenum silicide (MoSi) layer 160 is treated to form the second barrier layer 170. In some embodiments, the second barrier layer 170 is formed by nitriding the molybdenum silicide (MoSi) layer 160 or a portion thereof. In some embodiments, the second barrier layer 170 is formed by nitriding the molybdenum silicide (MoSi) layer 160 using ammonia (NH). In some embodiments, the second barrier layer 170 is formed by treating the molybdenum silicide (MoSi) layer 160 with a plasma to nitride the molybdenum silicide (MoSi) layer 160. In some embodiments, the plasma treatment comprises a nitrogen (N) plasma treatment. In some embodiments, the second barrier layer 170 comprises a metal nitride, a PVD metal, or a combination thereof.

[0050] 1F , first opening 106 over n-transistor 102 and second opening 108 over p-transistor 104 are independently filled with gap fill material 180 and gap fill material 182, respectively. In one or more embodiments, gap fill material 180 is substantially void or seam-free. Gap fill material 180 and gap fill material 182 may independently comprise any suitable gap fill material known to those skilled in the art. In one or more embodiments, gap fill material 180 and gap fill material 182 independently comprise one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, gap fill material 180 in first opening 106 over n-transistor 102 is the same as gap fill material 182 in second opening 108 over p-transistor 104. In one or more embodiments, the gap fill material 180 in the first opening 106 over the n-transistor 102 is different from the gap fill material 182 in the second opening 108 over the p-transistor 104 .

[0051] The gap filling process may comprise any suitable gap filling process known to those skilled in the art. In one or more embodiments, the gap filling process comprises exposing the semiconductor structure 100 to a metal precursor and a reactant. In some embodiments, the metal precursor comprises one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0052] In some embodiments, the gap filling process is a bottom-up gap filling process. In other embodiments, the gap filling process comprises a conformal gap filling process.

[0053] 2A-2G illustrate a semiconductor structure 200. The semiconductor structure 200 comprises an n-transistor 202 and a p-transistor 204. The n-transistor 202 and the p-transistor 204 each comprise a dielectric material 210, a source / drain material 220, and a substrate 230.

[0054] In one or more embodiments, dielectric material 210 may comprise any suitable material known to those skilled in the art. In some embodiments, dielectric material 210 comprises one or more of silicon, silicon oxide, silicon nitride, silicon carbide, and low-k dielectrics. In some embodiments, dielectric material 210 comprises silicon oxide (SiO2).

[0055] In some embodiments, n-transistor 202 and p-transistor 204 comprise source and drain contacts. In one or more embodiments, source / drain material 220 can have two or more layers. In some embodiments, source / drain material 220 comprises a layer of silicon (e.g., SiGe, SiP, etc.) with doped epi, a second layer of silicide that may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, etc.

[0056] In one or more embodiments, the source / drain material 220 of the n-transistor 202 comprises silicon (Si) doped with phosphorus (P). In one or more embodiments, the source / drain material 220 of the n-transistor 202 has a bandgap in the range of about 1.0 eV to about 1.2 eV.

[0057] In one or more embodiments, the source / drain material 220 of the p-transistor 204 comprises silicon germanium (SiGe) doped with boron (B). In one or more embodiments, the source / drain material 220 of the p-transistor 204 has a bandgap in the range of about 0.5 eV to about 1.0 eV.

[0058] 2A-2B , a first opening 206 is located above n-transistor 202 and a second opening 208 is located above p-transistor 204. First opening 206 and second opening 208 can have any suitable aspect ratio (ratio of opening depth to opening width). In one or more embodiments, first opening 206 and second opening 208 can independently have an aspect ratio in the range of 3:1 to 15:1, 6:1 to 15:1, 9:1 to 15:1, 12:1 to 15:1, or greater than 10:1.

[0059] 2B, a titanium silicide (TiSi) layer 240 is deposited on n-transistor 202. Titanium silicide (TiSi) layer 240 can have any suitable thickness. In some embodiments, titanium silicide (TiSi) layer 240 has a thickness in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, titanium silicide (TiSi) layer 240 has a thickness of about 40 Å.

[0060] 2C, an optional barrier layer 250 is formed on the titanium silicide (TiSi) layer 240 on the n-transistor 202. In one or more embodiments, the optional first barrier layer 250 comprises a metal. In one or more embodiments, the optional first barrier layer 250 comprises a metal nitride. In one or more embodiments, the optional first barrier layer 250 comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

[0061] In one or more embodiments, the first opening 206 over the n-transistor 202 is filled with a first gap fill material 280. In one or more embodiments, the first gap fill material 280 is substantially void or seam free. In one or more embodiments, the first gap fill material 280 comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0062] The gap filling process may comprise any suitable gap filling process known to those skilled in the art. In one or more embodiments, the gap filling process comprises exposing the semiconductor structure 200 to a metal precursor and a reactant. In some embodiments, the metal precursor comprises one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0063] 2D , a mask layer 270 is formed on the top surfaces of n-transistor 202 and p-transistor 204. In one or more embodiments, mask layer 270 comprises one or both of a hard mask layer 272 and a photoresist layer 274. Hard mask layer 272 may comprise any suitable material known to those skilled in the art. In one or more embodiments, hard mask layer 272 comprises silicon dioxide (SiO 2 ). Photoresist layer 274 may comprise any suitable material known to those skilled in the art. As will be appreciated by those skilled in the art, photoresist layer 274 is shown as being absent from the p-transistor for ease of illustration only. Those skilled in the art will understand that hard mask layer 272 and photoresist layer 274 are formed on the top surfaces of both n-transistor 202 and p-transistor 204. Processing to form second opening 208 removes photoresist layer 274. In one or more embodiments, second opening 208 is formed over p-transistor 204. The second opening 208 may be formed by any suitable process known to those skilled in the art. In one or more embodiments, the second opening 208 is formed by etching.

[0064] The second opening 208 can have any suitable aspect ratio. In one or more embodiments, the second opening can have an aspect ratio in the range of 3:1 to 15:1, 6:1 to 15:1, 9:1 to 15:1, 12:1 to 15:1, or greater than 10:1.

[0065] 2E, photoresist layer 274 is removed from mask layer 270 of n-transistor 202. Photoresist layer 274 may be removed by any suitable means known to those skilled in the art. In one or more embodiments, photoresist layer 274 is removed by stripping.

[0066] 2F, a molybdenum silicide (MoSi) layer 245 is selectively formed on the source / drain material 220 of the p-transistor 204. The molybdenum silicide (MoSi) layer 245 may be formed by any suitable process known to those skilled in the art. The molybdenum silicide (MoSi) layer 245 may have any suitable thickness. In some embodiments, the molybdenum silicide (MoSi) layer 245 has a thickness in the range of 20 Å to about 100 Å, or in the range of about 30 Å to about 90 Å, or in the range of about 40 Å to about 80 Å, or in the range of about 50 Å to about 70 Å. In one or more embodiments, the molybdenum silicide (MoSi) layer 245 has a thickness of about 40 Å.

[0067] Molybdenum silicide (MoSi) layer 245 may be formed according to any suitable process known to those skilled in the art. In one or more embodiments, structure 200 is first cleaned to remove oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a substantially oxide-free surface. As used in this manner, the term "substantially oxide-free" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, an anisotropic etch is used to remove oxide from the surface.

[0068] In one or more embodiments, a metal film is selectively formed on the source / drain material 220 to form a molybdenum silicide (MoSi) layer 245. In some embodiments, the semiconductor structure 200 is exposed to a metal precursor and a reactant. The metal film may be deposited by an ALD deposition process, a CVD deposition process, or a combination thereof. In some embodiments, the metal film comprises a molybdenum silicide film.

[0069] In one or more embodiments, the metal precursor comprises a molybdenum precursor. In some embodiments, the molybdenum precursor comprises a molybdenum halide. In some embodiments, the molybdenum halide comprises molybdenum fluoride, molybdenum chloride, or a combination thereof. In certain embodiments, the molybdenum precursor comprises molybdenum fluoride. In other specific embodiments, the molybdenum precursor comprises molybdenum chloride. In one or more embodiments, the precursor is flowed over the surface using a carrier gas. In some embodiments, the carrier gas is flowed through an ampoule containing the precursor. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N2, Ar, and He.

[0070] In one or more embodiments, the reactant comprises an oxidizing agent, a reducing agent, or a combination thereof. In some embodiments, the reactant comprises hydrogen (H), ammonia (NH), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher silanes, and substituted silanes. In particular embodiments, the reactant comprises silane to form a molybdenum silicide (MoSi) layer 245. In one or more embodiments, the reactant is flowed over the surface using a carrier gas. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas comprises one or more of N, Ar, and He. In other embodiments, the reactant gas may be flowed continuously, and the flow of the molybdenum precursor into the chamber is turned on and off.

[0071] 2G, the mask layer 270 formed on each of the top surfaces of the n-transistor 202 and the p-transistor 204 is removed. The mask layer 270 may be removed by any suitable means known to those skilled in the art. In some embodiments, the mask layer 270 is removed by etching or planarization.

[0072] In one or more embodiments, second opening 208 above p transistor 204 is filled with second gap fill material 282. In one or more embodiments, second gap fill material 282 is substantially void or seam-free. First gap fill material 280 and second gap fill material 282 may independently comprise any suitable gap fill material known to those skilled in the art. In one or more embodiments, second gap fill material 282 comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, gap fill material 280 above n transistor 202 is the same as gap fill material 282 above p transistor 204. In one or more embodiments, gap fill material 280 is different from gap fill material 282.

[0073] The gap filling process may comprise any suitable gap filling process known to those skilled in the art. In one or more embodiments, the gap filling process comprises exposing the semiconductor structure 200 to a metal precursor and a reactant. In some embodiments, the metal precursor comprises one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor.

[0074] In some embodiments, the gap filling process is a bottom-up gap filling process. In other embodiments, the gap filling process comprises a conformal gap filling process.

[0075] Figure 3 illustrates a process flow diagram of a method 300 of forming a semiconductor structure. Figure 3 illustrates a method of forming any of the semiconductor structures of one or more embodiments shown in Figures 1A-1F and 2A-2G.

[0076] In one or more embodiments, a method 300 for forming a semiconductor structure comprises, in operation 310, patterning a substrate to form a first opening and a second opening, the substrate comprising an n-transistor and a p-transistor, the first opening being over the n-transistor and the second opening being over the p-transistor. In operation 320, the method 300 comprises pre-cleaning the substrate. In operation 330, the method 300 comprises depositing a titanium silicide (TiSi) layer on the n-transistor and on the p-transistor by plasma-enhanced chemical vapor deposition (PECVD). In operation 340, the method 300 optionally includes depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p-transistor. In operation 350, the method 300 comprises selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer over the n-transistor and the p-transistor. In operation 360, the method 300 comprises forming a second barrier layer on the molybdenum silicide (MoSi) layer. In operation 370, the method 300 comprises annealing the semiconductor structure.

[0077] At operation 310, method 300 comprises patterning the substrate to form at least one of a first opening and a second opening. In one or more embodiments, patterning the substrate comprises using one or more patterning techniques known to those skilled in the art of microelectronic device fabrication.

[0078] In operation 320, method 300 comprises pre-cleaning the substrate. In one or more embodiments, keeping the pre-cleaning process under vacuum ensures that oxides are not introduced / formed on the substrate surface during method 300. In some embodiments, pre-cleaning the substrate (or the surface of the substrate) removes oxides from the surface. In some embodiments, the oxides are native oxides. In some embodiments, cleaning the surface forms a substantially oxide-free surface. As used in this manner, the term "substantially oxide-free" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, the anisotropic etching removes more oxides from the surface of the source / drain material than from the dielectric material. In one or more embodiments, pre-cleaning the surface forms a substantially oxide-free source / drain material.

[0079] In operation 330, method 300 comprises depositing a titanium silicide (TiSi) layer on the n-transistor and the p-transistor by plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, after depositing the titanium silicide (TiSi) layer on the n-transistor and the p-transistor, a rapid thermal process (RTP) is performed. In one or more embodiments, the rapid thermal process (RTP) comprises heating the titanium silicide (TiSi) layer to a temperature in a range from about 500°C to about 700°C. In one or more embodiments, the rapid thermal process (RTP) is performed for about 1 minute. In one or more embodiments, the rapid thermal process (RTP) removes unreacted metal from the titanium silicide (TiSi) layer.

[0080] In operation 340, method 300 optionally includes depositing a first barrier layer on the titanium silicide (TiSi) layer on the n-transistor and selectively removing the first barrier layer from the p-transistor. In one or more embodiments, selectively removing the first barrier layer from the p-transistor allows the molybdenum silicide (MoSi) layer on the p-transistor to form an ohmic contact with the titanium silicide (TiSi) layer on the p-transistor.

[0081] In some embodiments, the titanium silicide (TiSi) layers on the n-transistor and on the p-transistor are protected from oxide formation by a first barrier layer. The first barrier layer can be formed by any process known to those skilled in the art. In one or more embodiments, in operation 340, the first barrier layer is formed by an atomic layer deposition (ALD) process. In one or more embodiments, in operation 340, the first barrier layer is formed by a physical vapor deposition (PVD) process.

[0082] In some embodiments, a first barrier layer is formed on a titanium silicide (TiSi) layer. In some embodiments, the titanium silicide (TiSi) layer is treated to form the first barrier layer. In some embodiments, the first barrier layer is formed by nitriding the titanium silicide (TiSi) layer. In some embodiments, the first barrier layer is formed by nitriding the titanium silicide (TiSi) layer using ammonia (NH3). In some embodiments, the first barrier layer is formed by treating the titanium silicide (TiSi) layer with a plasma to nitride the titanium silicide (TiSi) layer. In some embodiments, the plasma treatment comprises a nitrogen (N2) plasma treatment.

[0083] In one or more embodiments, forming a first barrier layer by nitriding a titanium silicide (TiSi) layer forms a titanium silicon nitride (TiSiN) layer. In one or more embodiments, a semiconductor structure having a titanium silicon nitride (TiSiN) layer has a reduced Schottky barrier height compared to a semiconductor structure without a titanium silicon nitride (TiSiN) layer. In one or more embodiments, a semiconductor structure having a titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.50 eV to about 0.55 eV. In one or more embodiments, a semiconductor structure without a titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.6 eV to about 0.7 eV.

[0084] In some embodiments, in operation 350, method 300 comprises selectively forming a molybdenum silicide (MoSi) layer on a titanium silicide (TiSi) layer on the n-transistor and the p-transistor. In one or more embodiments, the molybdenum silicide (MoSi) layer is formed on a boron (B)-doped silicon germanium (SiGe) substrate of the p-transistor. In one or more embodiments, after selectively forming the molybdenum silicide (MoSi) layer on the p-transistor, a rapid thermal process (RTP) is performed. In one or more embodiments, the rapid thermal process (RTP) comprises heating the molybdenum silicide (MoSi) layer to a temperature in a range from about 500°C to about 700°C. In one or more embodiments, the rapid thermal process (RTP) is performed for about 1 minute. In one or more embodiments, the rapid thermal process (RTP) removes unreacted metal from the molybdenum silicide (MoSi) layer.

[0085] In another aspect of the present disclosure, a method 300 for forming a semiconductor structure includes reducing contact resistance of the semiconductor structure. In some embodiments, annealing the semiconductor structure in operation 370 reduces the contact resistance. In one or more embodiments, annealing the semiconductor structure results in a smooth surface. In one or more embodiments, annealing the semiconductor structure in operation 370 forms one or both of ohmic contacts and pseudo-ohmic contacts on the n-transistor and on the p-transistor.

[0086] The semiconductor structure may be annealed by any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by rapid thermal processing (RTP). In one or more embodiments, the rapid thermal processing (RTP) comprises annealing the semiconductor structure to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, the rapid thermal processing (RTP) comprises annealing the semiconductor structure to a temperature of about 600°C.

[0087] In some embodiments, the annealed semiconductor structure has a root-mean-square (RMS) roughness in the range of from 4% to less than 30%, from 4% to less than 20%, from 4% to less than 10%, from 10% to less than 30%, from 10% to less than 20%, or from 20% to less than 30%.

[0088] In some embodiments, method 300 comprises performing a gap fill process. In one or more embodiments, the gap fill process comprises independently filling a first opening over the n-transistor and a second opening over the p-transistor. In some embodiments, the gap fill process is a bottom-up gap fill process. In other embodiments, the gap fill process comprises a conformal gap fill process. In one or more embodiments, method 300 comprises filling a first opening over the n-transistor with a first gap fill material and filling a second opening over the p-transistor with a second gap fill material. In one or more embodiments, each of the first gap fill material and the second gap fill material is substantially void or seam-free. In one or more embodiments, each of the first gap fill material and the second gap fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0089] In one or more embodiments, the method 300 includes optional post-processing steps.

[0090] Figure 4 illustrates a process flow diagram of a method 400 of forming a semiconductor structure. Figure 4 illustrates a method of forming any of the semiconductor structures of one or more embodiments shown in Figures 1A-1F and 2A-2G.

[0091] In some embodiments, a method 400 for forming a semiconductor structure comprises, in operation 410, patterning a substrate to form a first opening, the substrate comprising an n-transistor and a p-transistor, the first opening being over the n-transistor. In operation 420, the method 400 comprises pre-cleaning the substrate. In operation 430, the method 400 comprises depositing a titanium silicide (TiSi) layer on the n-transistor by plasma-enhanced chemical vapor deposition (PECVD). In operation 430, the method 400 optionally includes forming a barrier layer on the titanium silicide (TiSi) layer over the n-transistor. In operation 440, the method 400 comprises filling the first opening with a first gap-fill material. In operation 450, the method 400 comprises forming a mask layer on the top surface of the n-transistor. In operation 460, the method 400 comprises patterning the substrate to form a second opening over the p-transistor. In one or more embodiments, method 400 optionally includes depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p-transistor. In operation 470, method 400 comprises selectively forming a molybdenum silicide (MoSi) layer on the p-transistor. In operation 480, method 400 comprises annealing the semiconductor structure. In operation 490, method 400 comprises filling the second opening with a second gap-fill material.

[0092] At operation 410, method 400 comprises patterning the substrate to form a first opening over the n-transistor. In one or more embodiments, patterning the substrate comprises using one or more patterning techniques known to those skilled in the art of microelectronic device fabrication.

[0093] In operation 420, method 400 comprises pre-cleaning the substrate. In one or more embodiments, keeping the pre-cleaning process under vacuum ensures that oxides are not introduced / formed on the substrate surface during method 400. In some embodiments, pre-cleaning the substrate (or the surface of the substrate) removes oxides from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a substantially oxide-free surface. As used in this manner, the term "substantially oxide-free" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, the anisotropic etching removes more oxides from the surface of the source / drain material than from the dielectric material. In one or more embodiments, pre-cleaning the surface forms a substantially oxide-free source / drain material.

[0094] In operation 430, the method 400 comprises depositing a titanium silicide (TiSi) layer on the n-transistor by plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, after depositing the titanium silicide (TiSi) layer on the n-transistor, a rapid thermal process (RTP) is performed. In one or more embodiments, the rapid thermal process (RTP) comprises heating the titanium silicide (TiSi) layer to a temperature in a range from about 500°C to about 700°C. In one or more embodiments, the rapid thermal process (RTP) is performed for about 1 minute. In one or more embodiments, the rapid thermal process (RTP) removes unreacted metal from the titanium silicide (TiSi) layer.

[0095] In operation 435, method 400 optionally includes depositing a first barrier layer on the titanium silicide (TiSi) layer on the n-transistor. In some embodiments, the titanium silicide (TiSi) layer on the n-transistor is protected from oxide formation by the first barrier layer. The first barrier layer can be formed by any process known to those skilled in the art. In one or more embodiments, in operation 435, the first barrier layer is formed by an atomic layer deposition (ALD) process. In one or more embodiments, in operation 435, the first barrier layer is formed by a physical vapor deposition (PVD) process.

[0096] In some embodiments, a first barrier layer is formed on a titanium silicide (TiSi) layer. In some embodiments, the titanium silicide (TiSi) layer is treated to form the first barrier layer. In some embodiments, the first barrier layer is formed by nitriding the titanium silicide (TiSi) layer. In some embodiments, the first barrier layer is formed by nitriding the titanium silicide (TiSi) layer using ammonia (NH3). In some embodiments, the first barrier layer is formed by treating the titanium silicide (TiSi) layer with a plasma to nitride the titanium silicide (TiSi) layer. In some embodiments, the plasma treatment comprises a nitrogen (N2) plasma treatment.

[0097] In one or more embodiments, forming a first barrier layer by nitriding a titanium silicide (TiSi) layer forms a titanium silicon nitride (TiSiN) layer. In one or more embodiments, a semiconductor structure having a titanium silicon nitride (TiSiN) layer has a reduced Schottky barrier height compared to a semiconductor structure without a titanium silicon nitride (TiSiN) layer. In one or more embodiments, a semiconductor structure having a titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.50 eV to about 0.55 eV. In one or more embodiments, a semiconductor structure without a titanium silicon nitride (TiSiN) layer has a Schottky barrier height in the range of about 0.6 eV to about 0.7 eV.

[0098] At operation 440, method 400 comprises filling the first opening with a first gap fill material. In some embodiments, filling the first opening comprises a bottom-up gap fill process. In other embodiments, filling the first opening comprises a conformal gap fill process. In one or more embodiments, the first gap fill material is substantially void or seam-free. In one or more embodiments, the first gap fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0099] In some embodiments, at operation 450, method 400 comprises forming a mask layer on the top surface of the n-transistor. In one or more embodiments, the mask layer comprises one or both of a hard mask layer and a photoresist layer. The hard mask layer may comprise any suitable material known to those skilled in the art. In one or more embodiments, the hard mask layer comprises silicon dioxide (SiO2). The photoresist layer may comprise any suitable material known to those skilled in the art.

[0100] At operation 460, method 400 comprises patterning the substrate to form a second opening over the p-transistor. In one or more embodiments, patterning the substrate comprises using one or more patterning techniques known to those skilled in the art of microelectronic device fabrication.

[0101] In operation 470, the method 400 comprises selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the p-transistor. In one or more embodiments, after selectively forming the molybdenum silicide (MoSi) layer on the p-transistor, a rapid thermal process (RTP) is performed. In one or more embodiments, the rapid thermal process (RTP) comprises heating the molybdenum silicide (MoSi) layer to a temperature in a range between about 500°C and about 700°C. In one or more embodiments, the rapid thermal process (RTP) is performed for about 1 minute. In one or more embodiments, the rapid thermal process (RTP) removes unreacted metal from the molybdenum silicide (MoSi) layer.

[0102] In another aspect of the present disclosure, a method 400 of forming a semiconductor structure includes reducing contact resistance of the semiconductor structure. In some embodiments, annealing the semiconductor structure in operation 480 reduces the contact resistance. In one or more embodiments, annealing the semiconductor structure results in a smooth surface. In one or more embodiments, annealing the semiconductor structure in operation 480 forms one or both of an ohmic contact and a pseudo-ohmic contact on the n-transistor and on the p-transistor.

[0103] The semiconductor structure may be annealed by any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by rapid thermal processing (RTP). In one or more embodiments, the rapid thermal processing (RTP) comprises annealing the semiconductor structure to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, the rapid thermal processing (RTP) comprises annealing the semiconductor structure to a temperature of about 600°C.

[0104] In some embodiments, the annealed semiconductor structure has a root-mean-square (RMS) roughness in the range of from 4% to less than 30%, from 4% to less than 20%, from 4% to less than 10%, from 10% to less than 30%, from 10% to less than 20%, or from 20% to less than 30%.

[0105] At operation 490, method 400 comprises filling the second opening with a second gap fill material. In some embodiments, filling the second opening comprises a bottom-up gap fill process. In other embodiments, filling the second opening comprises a conformal gap fill process. In one or more embodiments, the second gap fill material is substantially void or seam-free. In one or more embodiments, the second gap fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0106] In one or more embodiments, the method 400 includes an optional post-processing step.

[0107] Spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as depicted in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device during use or processing in addition to the orientation depicted in the figures. For example, if a device in the figures were turned over, elements described as "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an upper and lower orientation. A device may be oriented differently (rotated 90 degrees or at another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0108] The use of the terms "a," "an," and "the" and similar referents in the context of describing the materials and methods discussed herein (particularly in the context of the claims below) should be construed to cover both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples or illustrative language (e.g., "etc.") provided herein is intended merely to better clarify the materials and methods and does not impose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0109] References throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0110] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. It is hereby intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor structure, comprising: patterning a substrate to form a first opening and a second opening, the substrate comprising an n-transistor and a p-transistor, the first opening being over the n-transistor and the second opening being over the p-transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n-transistor and on the p-transistor by plasma-enhanced chemical vapor deposition (PECVD); Optionally, depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p-transistor; forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n-transistor and the p-transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; annealing the semiconductor structure; A method comprising:

2. 10. The method of claim 1, wherein the n-transistor comprises silicon (Si) doped with phosphorus (P) and the p-transistor comprises silicon germanium (SiGe) doped with boron (B).

3. 10. The method of claim 1, wherein the first barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

4. The method of claim 3 , wherein the first barrier layer is formed by one or both of an atomic layer deposition (ALD) process or a physical vapor deposition (PVD) process.

5. 10. The method of claim 1, wherein the second barrier layer comprises molybdenum nitride (MoN), nitrided molybdenum silicide (MoSi), and a PVD metal film.

6. The method of claim 1 , further comprising independently filling the first opening and the second opening with a gap-filling material.

7. The method of claim 6 , wherein the gap filling material is substantially free of voids or seams.

8. The method of claim 6 , wherein the gap fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

9. The method of claim 1 , wherein annealing the semiconductor structure forms one or both of an ohmic contact and a pseudo-ohmic contact on the n-transistor and on the p-transistor.

10. 10. The method of claim 1, wherein the titanium silicide (TiSi) layer on the n-transistor has a Schottky barrier height in the range of about 0.4 eV to about 0.55 eV.

11. 1. A method of forming a semiconductor structure, comprising: patterning a substrate to form a first opening, the substrate comprising an n-transistor and a p-transistor, the first opening overlying the n-transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n-transistor by plasma-enhanced chemical vapor deposition (PECVD); filling the first opening with a first gap-filling material; forming a mask layer on a top surface of the n-transistor; patterning the substrate to form a second opening over the p-transistor; forming a molybdenum silicide (MoSi) layer on the p-transistor; annealing the semiconductor structure; filling the second opening with a second gap-filling material; and A method comprising:

12. The method of claim 11 , wherein the mask layer comprises one or both of a hard mask layer and a photoresist layer.

13. 12. The method of claim 11, further comprising forming a barrier layer on the titanium silicide (TiSi) layer on the n-transistor.

14. 14. The method of claim 13, further comprising depositing the barrier layer on the molybdenum silicide (MoSi) layer on the p-transistor and selectively removing the barrier layer from the p-transistor.

15. 14. The method of claim 13, wherein the barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

16. 12. The method of claim 11, wherein the first gap fill material and the second gap fill material independently comprise one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

17. an n-transistor including a dielectric sidewall defining a first opening over a first source / drain material on a substrate; a p-transistor including a dielectric sidewall defining a second opening over a second source / drain material on the substrate; a first gap-fill material in the first opening over the first source / drain material of the n-transistor; a second gap-fill material in the second opening over the second source / drain material of the p-transistor; a titanium silicide (TiSi) layer on the first source / drain material and on the second source / drain material; a molybdenum silicide (MoSi) layer on the dielectric sidewalls and on the titanium silicide (TiSi) layer in the first opening and in the second opening; 1. A semiconductor structure comprising:

18. 20. The semiconductor structure of claim 17, further comprising a barrier layer on the titanium silicide (TiSi) layer and on the dielectric sidewalls of the n-transistor and on the dielectric sidewalls of the p-transistor.

19. 20. The semiconductor structure of claim 17, further comprising a barrier layer on said titanium silicide (TiSi) layer and on said dielectric sidewalls of said n-transistor.

20. 20. The semiconductor structure of claim 17, further comprising a barrier layer on the molybdenum silicide (MoSi) layer and on the dielectric sidewalls of the n-transistor and on the dielectric sidewalls of the p-transistor.

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