Oscillator manufacturing method and oscillator group

Abstract

To provide a manufacturing method for manufacturing a plurality of types of oscillators different in function related to an output frequency efficiently at low cost, and an oscillator.SOLUTION: A method for manufacturing an oscillator includes: storing a first vibrator and a first integrated circuit device oscillating the first vibrator in a first container to manufacture a first oscillator; and storing a second vibrator and a second integrated circuit device oscillating the second vibrator in a second container to manufacture a second oscillator. The first integrated circuit device includes a first oscillation circuit oscillating the first vibrator to output a first oscillation signal, and does not include a PLL circuit. The second integrated circuit device includes a second oscillation circuit oscillating the second vibrator to output a second oscillation signal, and a PLL circuit receiving input of the second oscillation signal and outputting a third oscillation signal. The first container and the second container are the containers of the same type.SELECTED DRAWING: Figure 19

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing an oscillator and to an oscillator. [Background technology]

[0002] Patent Document 1 describes a crystal oscillator in which a crystal resonator element and an IC chip are housed in a ceramic package, and the crystal resonator element is fixed to a mount base that is fixed inside the ceramic package with an adhesive. According to the crystal oscillator described in Patent Document 1, by changing the position at which the mount base is fixed inside the package, multiple types of crystal resonator elements and IC chips of different sizes can be housed in a common package, thereby improving design freedom regarding the sizes of the crystal resonator element and IC chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-232150 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the method described in Patent Document 1 leaves room for improvement in order to efficiently manufacture a plurality of types of oscillators with different functions related to output frequency at low cost. [Means for solving the problem]

[0005] One aspect of the method for manufacturing an oscillator according to the present invention is to A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, but does not include a PLL circuit; the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal; The first container and the second container are the same type of container.

[0006] One aspect of the oscillator according to the present invention is An oscillator included in an oscillator group consisting of multiple types of oscillators, a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, but does not include a PLL circuit; another oscillator included in the oscillator group includes a second vibrator, a second integrated circuit device that causes the second vibrator to oscillate, and a second container that houses the second vibrator and the second integrated circuit device; The second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal. and The first container and the second container are the same type of container.

[0007] Another aspect of the oscillator according to the present invention is An oscillator included in an oscillator group consisting of multiple types of oscillators, a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal; Another oscillator included in the oscillator group includes a first vibrator, a first integrated circuit device that causes the first vibrator to oscillate, and a first container that accommodates the first vibrator and the first integrated circuit device; the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, but does not include a PLL circuit; The first container and the second container are the same type of container. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram showing the configuration of an oscillator group 1. [Figure 2] FIG. 2 is a functional block diagram of a first oscillator. [Figure 3] FIG. 2 is a diagram showing a configuration example of a bias circuit. [Figure 4] FIG. 2 is a diagram showing a configuration example of an oscillation circuit of a first oscillator. [Figure 5] FIG. 2 is a diagram showing a configuration example of a temperature compensation circuit of a first oscillator. [Figure 6] FIG. 2 is a diagram showing a configuration example of an output circuit. [Figure 7] FIG. 10 is a diagram showing an example of a timing chart for writing and reading data to and from a nonvolatile memory. [Figure 8] FIG. 2 is a functional block diagram of a second oscillator. [Figure 9] FIG. 2 is a diagram showing a configuration example of an oscillation circuit of a second oscillator. [Figure 10] FIG. 10 is a diagram showing a configuration example of a temperature compensation circuit of a second oscillator. [Figure 11] FIG. 2 is a diagram showing an example of the configuration of a PLL circuit. [Figure 12] FIG. 2 is a diagram showing an example of a layout arrangement of a first integrated circuit device. [Figure 13] FIG. 10 is a diagram showing an example of a layout arrangement of a second integrated circuit device. [Figure 14] FIG. 10 is a diagram showing an example of frequency temperature characteristics. [Figure 15] FIG. 10 is a diagram showing an example of phase noise. [Figure 16] FIG. 2 is a perspective view of a first oscillator and a second oscillator. [Figure 17] FIG. 2 is a cross-sectional view of a first oscillator and a second oscillator. [Figure 18] FIG. 4 is a plan view showing a plurality of electrodes formed on the first container and the second container. [Figure 19] FIG. 4 is a flowchart showing an example of a procedure for a method for manufacturing an oscillator according to the present embodiment. [Figure 20] FIG. 20 is a flowchart showing an example of the detailed procedure of step S2 in FIG. 19. [Figure 21] FIG. 20 is a flowchart showing an example of the detailed procedure of step S4 in FIG. 19. [Figure 22] FIG. 10 is a diagram showing an example of the configuration of a temperature compensation circuit of a first oscillator in a second embodiment. [Figure 23] FIG. 10 is a diagram showing an example of phase noise in the second embodiment. [Figure 24] FIG. 10 is a diagram showing an example of a layout arrangement of a first integrated circuit device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below are not intended to unduly limit the scope of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. First embodiment 1-1. Oscillators FIG. 1 is a diagram showing the configuration of an oscillator group 1 of this embodiment. The oscillator group 1 is composed of multiple oscillators, each of which has a resonator and an integrated circuit device housed in a container. The multiple oscillators include a first oscillator 2a and a second oscillator 2b. The first oscillator 2a includes a first oscillator 5a, a first integrated circuit device 4a that causes the first oscillator 5a to oscillate, and a first container 3a that houses the first oscillator 5a and the first integrated circuit device 4a. The second oscillator 2b includes a second oscillator 5b, a second integrated circuit device 4b that causes the second oscillator 5b to oscillate, and a second container 3b that houses the second oscillator 5b and the second integrated circuit device 4b.

[0011] The first container 3a and the second container 3b are the same type of container. Specifically, the first container 3a and the second container 3b have the same shape of the container itself, and the same shapes, positions, and numbers of electrodes and wiring patterns formed on the containers, ignoring manufacturing errors. For example, the first container 3a and the second container 3b may be ceramic packages with the same model number.

[0012] The first integrated circuit device 4a and the second integrated circuit device 4b have different circuit configurations, which causes the first oscillator 2a and the second oscillator 2b to have different functions. In this embodiment, the first integrated circuit device 4a includes a first oscillation circuit that oscillates the first oscillator 5a to output a first oscillation signal, but does not include a PLL circuit. On the other hand, the second integrated circuit device 4b includes a second oscillation circuit that oscillates the second oscillator 5b to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal.

[0013] In this way, the oscillator group 1 is composed of a plurality of oscillators each having a resonator and an integrated circuit device housed in the same type of container and each having different functions. The integrated circuit devices included in the plurality of oscillators constituting the oscillator group 1 constitute an integrated circuit device group, and the first integrated circuit device 4a and the second integrated circuit device 4b are included in the plurality of integrated circuit devices constituting the integrated circuit device group.

[0014] 1-2. Functional configuration of the first oscillator 2 is a functional block diagram of the first oscillator 2a. As shown in FIG. 2, the first oscillator 2a includes a first resonator 5a and a first integrated circuit device 4a. The first integrated circuit device 4a has, as external connection terminals, a VDD terminal, a VSS terminal, an OUT terminal, an OE terminal, an XI terminal, and an XO terminal. The VDD terminal, the VSS terminal, the OUT terminal, and the OE terminal are electrically connected to the VDD1 terminal, the VSS1 terminal, the OUT1 terminal, and the OE1 terminal, which are multiple external terminals of the first oscillator 2a, respectively. The XI terminal is electrically connected to one end of the first resonator 5a, and the XO terminal is electrically connected to the other end of the first resonator 5a.

[0015] In this embodiment, the first integrated circuit device 4a includes a bias circuit 110, an oscillation circuit 120, a temperature compensation circuit 130, an output circuit 140, a logic circuit 150, and a non-volatile memory 160. Note that the first integrated circuit device 4a may be configured such that some of these elements are omitted or modified, or other elements are added.

[0016] The bias circuit 110 generates a constant power supply voltage Vreg based on a power supply voltage VDD supplied from the outside via the VDD1 terminal and the VDD terminal and a ground voltage VSS supplied from the outside via the VSS1 terminal and the VSS terminal, and supplies the voltage to each circuit. The bias circuit 110 may also generate various reference voltages and supply them to each circuit as appropriate.

[0017] Fig. 3 is a diagram showing an example of the configuration of the bias circuit 110. In the example of Fig. 3, the bias circuit 110 includes a bandgap reference circuit 111, an operational amplifier 112, a resistive element 113, a capacitive element 114, an N-channel MOS transistor 115, and resistive elements 116 and 117.

[0018] The bandgap reference circuit 111 uses the bandgap voltage of silicon to generate a constant reference voltage independent of the power supply voltage VDD or temperature.

[0019] The MOS transistor 115 and the resistor elements 116 and 117 are connected in series between a node to which a power supply voltage VDD is supplied and a node to which a ground voltage VSS is supplied.

[0020] A reference voltage output from the bandgap reference circuit 111 is input to a non-inverting input terminal of the operational amplifier 112, and a voltage obtained by dividing the power supply voltage VDD by resistor elements 116 and 117 is input to an inverting input terminal of the operational amplifier 112. The output terminal of the operational amplifier 112 is connected to the gate of the MOS transistor 115 via a resistor element 113.

[0021] The capacitance element 114 is connected between the gate of the MOS transistor 115 and a node to which the ground voltage VSS is supplied, and the resistance element 113 and the capacitance element 114 form a filter that smoothes the output signal of the operational amplifier 112. The voltage at the drain of the MOS transistor 115 is output as the power supply voltage Vreg.

[0022] 2, the oscillator circuit 120 is electrically connected to both ends of the first oscillator 5a via the XI terminal and the XO terminal, and causes the first oscillator 5a to oscillate at a desired frequency to output an oscillation signal Vosc. Specifically, the oscillator circuit 120 receives the signal output from the first oscillator 5a via the XO terminal, amplifies the signal, and supplies the amplified signal to the first oscillator 5a via the XI terminal.

[0023] Fig. 4 is a diagram showing an example configuration of the oscillator circuit 120. In the example of Fig. 4, the oscillator circuit 120 includes P-channel MOS transistors 121 and 122, an N-channel MOS transistor 123, an NPN bipolar transistor 124, and variable capacitance elements 125 and 126. The MOS transistors 121 and 122 are enhancement type, and the MOS transistor 123 is depletion type.

[0024] The gate of the MOS transistor 121 is electrically connected to the drain of the MOS transistor 121, the gate of the MOS transistor 122, and the drain of the MOS transistor 123. The power supply voltage Vreg is supplied to the sources of the MOS transistor 121 and the MOS transistor 122. The gate and source of the MOS transistor 123 are grounded and supplied with the ground voltage VSS. The drain of the MOS transistor 122 is electrically connected to the collector of the bipolar transistor 124, one end of the variable capacitance element 126, and the XI terminal. The base of the bipolar transistor 124 is electrically connected to one end of the variable capacitance element 125 and the XO terminal. The emitter of the bipolar transistor 124, the other end of the variable capacitance element 125, and the other end of the variable capacitance element 126 are grounded and supplied with the ground voltage VSS. The capacitance values ​​of the variable capacitance elements 125 and 126 change according to the voltage of the temperature compensation signal Vcmp.

[0025] In the oscillator circuit 120 configured as described above, a constant current Iref flows through the drain of the MOS transistor 122, and the bipolar transistor 124 is supplied with the current Iref and performs an amplification operation. The collector signal of the bipolar transistor 124 is output as the oscillation signal Vosc. That is, the bipolar transistor 124: An amplifier circuit 128 is configured to amplify the signal from the first oscillator 5a and output an oscillation signal Vosc. MOS transistors 121, 122, and 123 are configured to a current source 127 that supplies a current Iref to the amplifier circuit 128. Variable capacitance elements 125 and 126 function as load capacitances for the first oscillator 5a, and the frequency of the oscillation signal Vosc depends on the capacitance values ​​of the variable capacitance elements 125 and 126.

[0026] Returning to the description of FIG. 2, the first integrated circuit device 4a may be able to set whether to operate the temperature compensation circuit 130. When the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN, the temperature compensation circuit 130 generates a temperature compensation signal Vcmp for compensating for the frequency-temperature characteristics of the oscillation signal Vosc output from the oscillation circuit 120 based on temperature compensation data cmpDT corresponding to the frequency-temperature characteristics of the first resonator 5a, and outputs the generated signal to the oscillation circuit 120. The temperature compensation data cmpDT includes, for example, coefficient values ​​of each order of a temperature compensation function that compensates for the frequency-temperature characteristics of the first resonator 5a. Furthermore, when the temperature compensation function is disabled by the temperature compensation function setting bit cmpEN, the temperature compensation circuit 130 stops operating, thereby reducing current consumption. The temperature compensation data cmpDT is generated during the manufacturing process of the first oscillator 2a and written to the nonvolatile memory 160 together with the temperature compensation function setting bit cmpEN. When the first oscillator 2 a is in operation, the temperature compensation function setting bit cmpEN and the temperature compensation data cmpDT stored in the nonvolatile memory 160 are supplied to the temperature compensation circuit 130 via the logic circuit 150 .

[0027] Fig. 5 is a diagram showing an example of the configuration of the temperature compensation circuit 130. In the example of Fig. 5, the temperature compensation circuit 130 includes a temperature sensor 131, a zeroth-order component generating circuit 132, a first-order component generating circuit 133, a high-order component generating circuit 134, and an I / V conversion circuit 135.

[0028] The temperature sensor 131, the zeroth-order component generating circuit 132, the first-order component generating circuit 133, the high-order component generating circuit 134, and the I / V conversion circuit 135 operate when the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN, and stop operating when the temperature compensation function is disabled by the temperature compensation function setting bit cmpEN.

[0029] The temperature sensor 131 detects the temperature of the first integrated circuit device 4a and outputs a temperature signal with a voltage corresponding to the temperature, and is realized by, for example, a circuit that utilizes the temperature characteristics of a bandgap reference circuit.

[0030] The zeroth-order component generating circuit 132 outputs a current signal corresponding to the zeroth-order term of the temperature compensation function based on the zeroth-order coefficient value included in the temperature compensation data cmpDT.

[0031] The first-order component generating circuit 133 outputs a current signal corresponding to the first-order term of the temperature compensation function based on the temperature signal output from the temperature sensor 131 and the first-order coefficient value included in the temperature compensation data cmpDT.

[0032] The high-order component generating circuit 134 outputs current signals corresponding to each of the second-order and higher order terms of the temperature compensation function based on the temperature signal output from the temperature sensor 131 and each of the second-order and higher order coefficient values ​​included in the temperature compensation data cmpDT. For example, the high-order component generating circuit 134 outputs current signals corresponding to each of the second-order to seventh order terms of the temperature compensation function.

[0033] The I / V conversion circuit 135 converts into a voltage signal a current signal obtained by adding together the current signal output from the zeroth-order component generation circuit 132, the current signal output from the first-order component generation circuit 133, and the current signals output from the high-order component generation circuit 134. This voltage signal is output as the temperature compensation signal Vcmp.

[0034] The temperature compensation signal Vcmp causes the oscillation signal Vosc output by the oscillation circuit 120 to have a substantially constant frequency at any temperature within a predetermined temperature range.

[0035] Returning to the description of FIG. 2, the oscillation signal Vosc is input to the output circuit 140. When the output enable signal outEN supplied from the logic circuit 150 is at a high level, the output circuit 140 outputs an oscillation signal Vout based on the oscillation signal Vosc. When the output enable signal outEN is at a low level, the output circuit 140 outputs a signal of the ground voltage VSS or a high-impedance state. For example, the output circuit 140 may output the oscillation signal Vout obtained by dividing the oscillation signal Vosc by a division ratio set by the output setting data outDT. The output circuit 140 may also output the oscillation signal Vout of an output type set by the output setting data outDT. The output type of the oscillation signal Vout may be, for example, a CMOS output or a clipped sign output. CMOS stands for Complementary Metal Oxide Semiconductor. The output circuit 140 may also output the oscillation signal Vout of an output capability set by the output setting data outDT. The output setting data outDT is written to the nonvolatile memory 160 during the manufacturing process of the first oscillator 2a. When the first oscillator 2 a is in operation, the output setting data outDT stored in the nonvolatile memory 160 is supplied to the output circuit 140 via the logic circuit 150 .

[0036] 6 is a diagram showing an example of the configuration of the output circuit 140. In the example of FIG. 6, the output circuit 140 includes a waveform shaping buffer 141, a frequency divider circuit 142, a pre-buffer 143, and an output buffer 144.

[0037] The waveform shaping buffer 141 buffers the oscillation signal Vosc output from the oscillation circuit 120 and outputs an oscillation signal of a square wave.

[0038] The frequency divider circuit 142 outputs an oscillation signal obtained by dividing the oscillation signal output from the waveform shaping buffer 141 by the division ratio set by the output setting data outDT. When the division ratio is 1, the frequency divider circuit 142 outputs an oscillation signal obtained by buffering the oscillation signal output from the waveform shaping buffer 141. The oscillation signal output from the frequency divider circuit 142 is input to the pre-buffer 143.

[0039] The pre-buffer 143 outputs an oscillation signal obtained by buffering the oscillation signal output from the frequency divider circuit 142. The pre-buffer 143 also functions as a level shifter that outputs an oscillation signal with a voltage level that matches the input voltage level of the output buffer 144.

[0040] The output buffer 144 converts the oscillation signal output from the pre-buffer 143 into an oscillation signal Vout of the output type and output capacity set by the output setting data outDT. The output buffer 144 outputs the oscillation signal Vout when the output enable signal outEN is at a high level, and outputs a signal of the ground voltage VSS when the output enable signal outEN is at a low level.

[0041] Returning to the explanation of FIG. 2, the logic circuit 150 controls the operation of each circuit. Specifically, the logic circuit 150 sets the operation mode of the first oscillator 2a or the first integrated circuit device 4a to one of a plurality of modes including an external communication mode and a normal operation mode based on a control signal input to a predetermined external connection terminal of the first integrated circuit device 4a, and performs control according to the set operation mode. In this embodiment, when a control signal of a predetermined pattern is input from the OE terminal within a predetermined period after the supply of the power supply voltage VDD to the VDD terminal starts, the logic circuit 150 sets the operation mode to the external communication mode after the predetermined period has elapsed. For example, the logic circuit 150 may set the predetermined period to the period from when the first oscillator 5a starts oscillating due to the supply of the power supply voltage VDD until it detects that the oscillation has stabilized, or may set the predetermined period to the period from when the first oscillator 5a starts oscillating due to the supply of the power supply voltage VDD until it detects that the oscillation has stabilized. Alternatively, the logic circuit 150 may count the number of pulses of the oscillation signal Vosc and determine that the predetermined period has elapsed when the count value reaches a predetermined value. Alternatively, for example, the logic circuit 150 may measure the predetermined period based on the output signal of an RC time constant circuit that starts operating when the power supply voltage VDD is supplied.

[0042] In the external communication mode, the logic circuit 150 can perform data communication with an external device (not shown) connected to the OE1 and OUT1 terminals via the OE and OUT terminals. The external device outputs a serial clock signal to the OUT1 terminal in accordance with a predetermined communication standard, and outputs a serial data signal to the OE1 terminal in synchronization with the serial clock signal. Alternatively, the external device acquires a signal output from the logic circuit 150 to the OE1 terminal via the OE terminal. In the external communication mode, the logic circuit 150 samples the serial data signal as various commands at each edge of the serial clock signal, for example, in accordance with the I2C bus standard. I2C stands for Inter-Integrated Circuit. Based on the sampled commands, the logic circuit 150 sets the operating mode and performs processes such as writing and reading data to and from the non-volatile memory 160. In this embodiment, the logic circuit 150 communicates with an external device using a two-wire bus communication standard such as an I2C bus, but may also communicate with an external device using a three-wire or four-wire bus communication standard such as an SPI bus. SPI is an abbreviation for Serial Peripheral Interface.

[0043] For example, when the logic circuit 150 samples a write command to the nonvolatile memory 160 in the external communication mode, it writes data specified in the write command to the address in the nonvolatile memory 160 specified in the write command. Furthermore, when the logic circuit 150 samples a read command to the nonvolatile memory 160 in the external communication mode, it reads data from the address in the nonvolatile memory 160 specified in the read command, converts the data into serial data, and outputs it. Figure 7 shows an example of a timing chart for writing and reading data to and from the nonvolatile memory 160 in the external communication mode after the supply of the power supply voltage VDD to the VDD terminal starts and the mode is switched to the external communication mode.

[0044] Furthermore, for example, when the logic circuit 150 samples a normal operation mode setting command in the external communication mode, it transitions the operation mode from the external communication mode to the normal operation mode. In the normal operation mode, the logic circuit 150 supplies a signal input from outside the first oscillator 2a via the OE1 terminal and the OE terminal to the output circuit 140 as an output enable signal outEN. Therefore, in the normal operation mode, the output of the oscillation signal Vout from the OUT1 terminal is controlled based on the signal input to the OE1 terminal.

[0045] If a signal of a predetermined pattern is not input from the OE terminal within a predetermined period of time after the supply of the power supply voltage VDD starts, the logic circuit 150 does not set the operation mode to the external communication mode after the predetermined period of time has elapsed, but directly sets it to the normal operation mode.

[0046] The nonvolatile memory 160 is a memory that stores various types of information, such as a MONOS memory or an EEPROM. MONOS stands for Metal Oxide Nitride Oxide Silicon, and EEPROM stands for Electrically Erasable Programmable Read-Only Memory. During the manufacturing process of the first oscillator 2a, various types of information for controlling each circuit, such as a temperature compensation function setting bit cmpEN, temperature compensation data cmpDT, and output setting data outDT, are stored in the nonvolatile memory 160. When power is applied to the first oscillator 2a, the various types of information stored in the nonvolatile memory 160 are transferred to registers (not shown) in the logic circuit 150, and the various types of information stored in the registers are supplied to each circuit as appropriate.

[0047] The oscillator circuit 120 is an example of a "first oscillator circuit," and the oscillator signal Vosc output from the oscillator circuit 120 is an example of a "first oscillator signal." The amplifier circuit 128 is an example of a "first amplifier circuit," the current source 127 is an example of a "first current source," the MOS transistor 122 is an example of a "first transistor," and the current Iref supplied by the MOS transistor 122 to the amplifier circuit 128 is an example of a "first current." The temperature compensation circuit 130 is an example of a "first temperature compensation circuit," and the temperature compensation signal Vcmp output from the temperature compensation circuit 130 is an example of a "first temperature compensation signal."

[0048] 1-3. Functional configuration of the second oscillator 8 is a functional block diagram of the second oscillator 2b. As shown in FIG. 8, the second oscillator 2b includes a second resonator 5b and a second integrated circuit device 4b. Similar to the first integrated circuit device 4a, the second integrated circuit device 4b has external connection terminals: a VDD terminal, a VSS terminal, an OUT terminal, an OE terminal, an XI terminal, and an XO terminal. The VDD terminal, the VSS terminal, the OUT terminal, and the OE terminal are electrically connected to the VDD1 terminal, the VSS1 terminal, the OUT1 terminal, and the OE1 terminal, which are multiple external terminals of the second oscillator 2b, respectively. The XI terminal is electrically connected to one end of the second resonator 5b, and the XO terminal is electrically connected to the other end of the second resonator 5b.

[0049] In this embodiment, the second integrated circuit device 4b includes a bias circuit 210, an oscillation circuit 220, a temperature compensation circuit 230, a PLL circuit 240, an output circuit 250, a logic circuit 260, and a non-volatile memory 270. Note that the second integrated circuit device 4b may be configured such that some of these elements are omitted or modified, or other elements are added.

[0050] The bias circuit 210 generates a constant power supply voltage Vreg based on a power supply voltage VDD supplied from the outside via the VDD1 terminal and the VDD terminal and a ground voltage VSS supplied from the outside via the VSS1 terminal and the VSS terminal, and supplies the constant power supply voltage Vreg to each circuit. The bias circuit 210 also generates various reference voltages and supplies them to each circuit as appropriate. An example of the configuration of the bias circuit 210 is the same as that shown in FIG. 3, so illustration and description thereof will be omitted.

[0051] The oscillator circuit 220 is electrically connected to both ends of the second oscillator 5b via the XI terminal and the XO terminal, and causes the second oscillator 5b to oscillate at a desired frequency to output an oscillation signal Vosc. Specifically, the oscillator circuit 220 receives the signal output from the second oscillator 5b via the XO terminal, amplifies the signal, and supplies the amplified signal to the second oscillator 5b via the XI terminal.

[0052] Fig. 9 is a diagram showing an example of the configuration of the oscillation circuit 220. In the example of Fig. 9, the oscillation circuit 220 includes P-channel MOS transistors 221 and 222, an N-channel MOS transistor 223, an NPN bipolar transistor 224, and variable capacitance elements 225 and 226. The MOS transistors 221 and 222 are enhancement type, and the MOS transistor 223 is depletion type.

[0053] The gate of the MOS transistor 221 is electrically connected to the drain of the MOS transistor 221, the gate of the MOS transistor 222, and the drain of the MOS transistor 223. The source of the MOS transistor 221 and the source of the MOS transistor 222 are supplied with a power supply voltage Vreg. The gate and source of the MOS transistor 223 are grounded and supplied with a ground voltage VSS. The drain of the MOS transistor 222 is electrically connected to the collector of the bipolar transistor 224, one end of the variable capacitance element 226, and the XI terminal. The base of the bipolar transistor 224 is electrically connected to one end of the variable capacitance element 225 and the XO terminal. The emitter of the bipolar transistor 224, the other end of the variable capacitance element 225, and the variable capacitance element 226 The other end is grounded and is supplied with a ground voltage VSS. The capacitance values ​​of the variable capacitance elements 225 and 226 vary in accordance with the voltage of the temperature compensation signal Vcmp.

[0054] In the oscillator circuit 220 configured as described above, a constant current Iref flows through the drain of the MOS transistor 222, and the bipolar transistor 224 performs an amplification operation when supplied with the current Iref. The signal at the collector of the bipolar transistor 224 is output as the oscillation signal Vosc. That is, the bipolar transistor 224 constitutes an amplifier circuit 228 that amplifies the signal from the second oscillator 5b and outputs the oscillation signal Vosc. The MOS transistors 221, 222, and 223 constitute a current source 227 that supplies the current Iref to the amplifier circuit 228. The variable capacitance elements 225 and 226 function as load capacitances for the second oscillator 5b, and the frequency of the oscillation signal Vosc corresponds to the capacitance values ​​of the variable capacitance elements 225 and 226.

[0055] Returning to the explanation of FIG. 8, when the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN, the temperature compensation circuit 230 generates a temperature compensation signal Vcmp for compensating for the frequency-temperature characteristics of the oscillation signal Vosc output from the oscillation circuit 220 based on the temperature compensation data cmpDT corresponding to the frequency-temperature characteristics of the second oscillator 5b, and outputs the generated signal to the oscillation circuit 220. The temperature compensation data cmpDT includes, for example, coefficient values ​​of each order of a temperature compensation function that compensates for the frequency-temperature characteristics of the second oscillator 5b. Furthermore, when the temperature compensation function is disabled by the temperature compensation function setting bit cmpEN, the temperature compensation circuit 230 stops operating, thereby reducing current consumption. The temperature compensation data cmpDT is generated during the manufacturing process of the second oscillator 2b and written to the nonvolatile memory 270 together with the temperature compensation function setting bit cmpEN. When the second oscillator 2 b is in operation, the temperature compensation function setting bit cmpEN and the temperature compensation data cmpDT stored in the nonvolatile memory 270 are supplied to the temperature compensation circuit 230 via the logic circuit 260 .

[0056] 10 is a diagram showing an example of the configuration of the temperature compensation circuit 230. In the example of Fig. 10, the temperature compensation circuit 230 includes a temperature sensor 231, a zeroth-order component generating circuit 232, a first-order component generating circuit 233, a third-order component generating circuit 234, and an I / V conversion circuit 235.

[0057] The temperature sensor 231, the zeroth-order component generating circuit 232, the first-order component generating circuit 233, the third-order component generating circuit 234, and the I / V conversion circuit 235 operate when the temperature compensation function is enabled by the temperature compensation function setting bit cmpEN, and stop operating when the temperature compensation function is disabled by the temperature compensation function setting bit cmpEN.

[0058] The temperature sensor 231 detects the temperature of the second integrated circuit device 4b and outputs a temperature signal with a voltage corresponding to the temperature, and is realized by, for example, a circuit that utilizes the temperature characteristics of a bandgap reference circuit.

[0059] The zeroth-order component generating circuit 232 outputs a current signal corresponding to the zeroth-order term of the temperature compensation function based on the zeroth-order coefficient value included in the temperature compensation data cmpDT.

[0060] The first-order component generating circuit 233 outputs a current signal corresponding to the first-order term of the temperature compensation function based on the temperature signal output from the temperature sensor 231 and the first-order coefficient value included in the temperature compensation data cmpDT.

[0061] The third-order component generating circuit 234 outputs a current signal corresponding to the third-order term of the temperature compensation function based on the temperature signal output from the temperature sensor 231 and the third-order coefficient value included in the temperature compensation data cmpDT.

[0062] The I / V conversion circuit 235 converts into a voltage signal the current signal obtained by adding together the current signal output from the zeroth-order component generation circuit 232, the current signal output from the first-order component generation circuit 233, and the current signal output from the third-order component generation circuit 234. This voltage signal is output as the temperature compensation signal Vcmp.

[0063] The temperature compensation signal Vcmp causes the oscillation signal Vosc output by the oscillation circuit 220 to have a substantially constant frequency at any temperature within a predetermined temperature range.

[0064] Returning to the description of FIG. 8 , the PLL circuit 240 receives the oscillation signal Vosc and outputs the oscillation signal Vpll. The PLL circuit 240 generates the oscillation signal Vpll by performing feedback control so that the phase of the oscillation signal Vosc coincides with the phase of a signal obtained by dividing the oscillation signal Vpll by a division ratio set by the PLL setting data pllDT. Furthermore, the PLL circuit 240 may operate in either an integer PLL mode, which divides the oscillation signal Vpll by an integer division ratio, or a fractional PLL mode, which divides the oscillation signal Vpll by a fractional division ratio, depending on the PLL mode set by the PLL setting data pllDT. That is, the second integrated circuit device 4b may be able to set the operation of the PLL circuit 240 to either the integer PLL mode or the fractional PLL mode. The PLL setting data pllDT is written to the nonvolatile memory 270 during the manufacturing process of the second oscillator 2b. When the second oscillator 2 b is in operation, the PLL setting data pllDT stored in the nonvolatile memory 270 is supplied to the PLL circuit 240 via the logic circuit 260 .

[0065] Fig. 11 is a diagram showing an example of the configuration of the PLL circuit 240. In the example of Fig. 11, the PLL circuit 240 includes a phase comparator 241, a charge pump 242, a low-pass filter 243, a voltage-controlled oscillator circuit 244, a waveform shaping circuit 245, a frequency divider circuit 246, and a delta-sigma modulator circuit 247.

[0066] The phase comparator 241 compares the phase of the oscillation signal Vosc output from the oscillation circuit 220 with the phase of the signal output from the frequency divider circuit 246, and outputs the comparison result as a pulse voltage.

[0067] The charge pump 242 converts the pulse voltage output by the phase comparator 241 into a current, and the low-pass filter 243 smoothes and voltage-converts the current output by the charge pump 242 .

[0068] The voltage controlled oscillator circuit 244 outputs an oscillation signal whose frequency changes according to the control voltage, using the output voltage of the low pass filter 243 as a control voltage. The voltage controlled oscillator circuit 244 can be realized as various types of oscillation circuits, such as an LC oscillation circuit configured using an inductance element such as a coil and a capacitance element such as a capacitor, or an oscillation circuit using a piezoelectric oscillator such as a crystal oscillator.

[0069] The waveform shaping circuit 245 buffers the oscillation signal output from the voltage controlled oscillation circuit 244 and outputs an oscillation signal Vpll of a square wave.

[0070] The frequency divider circuit 246 outputs a signal obtained by dividing the oscillation signal Vpll output from the waveform shaping circuit 245 using the value of the frequency division ratio setting signal DIV output from the delta sigma modulation circuit 247 as the frequency division ratio.

[0071] The delta-sigma modulation circuit 247 outputs a division ratio setting signal DIV that sets the division ratio of the frequency divider circuit 246 in accordance with the division ratio Nf set by the PLL setting data pllDT. Specifically, when the fractional PLL method is set by the PLL setting data pllDT, the delta-sigma modulation circuit 247 operates, and the value of the division ratio setting signal DIV is set to its time average The frequency f of the oscillation signal Vosc is sequentially switched to one of a plurality of different integer values ​​so that the value matches the division ratio Nf set by the PLL setting data pllDT. Therefore, in a steady state where the phase of the oscillation signal Vosc and the phase of the signal output from the frequency divider circuit 246 are synchronized, osc and the frequency f of the oscillation signal Vpll pll The relationship between them is expressed by the following equation (1):

[0072]

number

[0073] On the other hand, when the integer PLL method is set by the PLL setting data pllDT, the delta-sigma modulation circuit 247 stops operating, and the value of the division ratio setting signal DIV is fixed to the integer division ratio N of the division ratio Nf set by the PLL setting data pllDT. Therefore, in a steady state where the phase of the oscillation signal Vosc and the phase of the signal output from the frequency divider circuit 246 are synchronized, the frequency f of the oscillation signal Vosc osc and the frequency f of the oscillation signal Vpll pll The relationship between them is expressed by the following equation (2):

[0074]

number

[0075] For example, frequency f osc is several MHz to several tens of MHz, and the frequency f pll The frequency may be several hundred MHz to several GHz.

[0076] Returning to the description of FIG. 8 , the oscillation signal Vpll is input to the output circuit 250. When the output enable signal outEN supplied from the logic circuit 260 is at a high level, the output circuit 250 outputs an oscillation signal Vout based on the oscillation signal Vpll. When the output enable signal outEN is at a low level, the output circuit 250 outputs a signal of the ground voltage VSS. For example, the output circuit 250 may output the oscillation signal Vout obtained by dividing the oscillation signal Vpll by a division ratio set in the output setting data outDT. The output circuit 250 may also output the oscillation signal Vout of an output type set in the output setting data outDT. The output type of the oscillation signal Vout may be, for example, a CMOS output or a clipped sign output. The output circuit 250 may also output the oscillation signal Vout of an output capability set in the output setting data outDT. The output setting data outDT is written to the nonvolatile memory 270 during the manufacturing process of the second oscillator 2b. When the second oscillator 2b is in operation, the output setting data outDT stored in the nonvolatile memory 270 is supplied to the output circuit 250 via the logic circuit 260. An example of the configuration of the output circuit 250 is the same as that shown in FIG. 6, and therefore its illustration and description will be omitted.

[0077] The logic circuit 260 controls the operation of each circuit. Specifically, the logic circuit 260 sets the operation mode of the second oscillator 2b or the second integrated circuit device 4b to one of a plurality of modes, including an external communication mode and a normal operation mode, based on a control signal input to a predetermined external connection terminal of the second integrated circuit device 4b, and performs control according to the set operation mode. In this embodiment, when a control signal of a predetermined pattern is input from the OE terminal within a predetermined period after the supply of the power supply voltage VDD to the VDD terminal starts, the logic circuit 260 sets the operation mode to the external communication mode after the predetermined period has elapsed. For example, the logic circuit 260 may determine the predetermined period as the period from when the second oscillator 5b starts oscillating due to the supply of the power supply voltage VDD to when it detects that the oscillation has stabilized, or it may count the number of pulses of the oscillation signal Vosc and determine that the predetermined period has elapsed when the count value reaches a predetermined value. Also, for example, the logic circuit 260 may determine that the predetermined period has elapsed when the supply of the power supply voltage VDD starts operation. The predetermined period may be measured based on the output signal of the starting RC time constant circuit.

[0078] In the external communication mode, the logic circuit 260 can perform data communication with an external device (not shown) connected to the OE1 and OUT1 terminals via the OE and OUT terminals. The external device outputs a serial clock signal to the OUT1 terminal in accordance with a predetermined communication standard, and outputs a serial data signal to the OE1 terminal in synchronization with the serial clock signal. Alternatively, the external device acquires a signal output from the logic circuit 260 to the OE1 terminal via the OE terminal. In the external communication mode, the logic circuit 260 samples the serial data signal as various commands at each edge of the serial clock signal, for example, in accordance with the I2C bus standard. Then, the logic circuit 260 performs processes such as setting the operating mode and writing and reading data to and from the non-volatile memory 270 based on the sampled commands. Note that in this embodiment, the logic circuit 260 communicates with the external device using a two-wire bus communication standard such as the I2C bus. However, the logic circuit 260 may also communicate with the external device using a three-wire or four-wire bus communication standard such as the SPI bus.

[0079] For example, when the logic circuit 260 samples a write command to the nonvolatile memory 270 in the external communication mode, it writes data specified in the write command to the address in the nonvolatile memory 270 specified in the write command. Also, when the logic circuit 260 samples a read command to the nonvolatile memory 270 in the external communication mode, it reads data from the address in the nonvolatile memory 270 specified in the read command, converts it to serial data, and outputs it. An example of a timing chart when data is written to and read from the nonvolatile memory 270 is the same as that shown in FIG.

[0080] Furthermore, for example, when the logic circuit 260 samples a normal operation mode setting command in the external communication mode, it transitions the operation mode from the external communication mode to the normal operation mode. In the normal operation mode, the logic circuit 260 supplies a signal input from outside the second oscillator 2b via the OE1 terminal and the OE terminal to the output circuit 250 as an output enable signal outEN. Therefore, in the normal operation mode, the output of the oscillation signal Vout from the OUT1 terminal is controlled based on the control signal input to the OE1 terminal.

[0081] If a signal of a predetermined pattern is not input from the OE terminal within a predetermined period of time after the supply of the power supply voltage VDD starts, the logic circuit 260 does not set the operation mode to the external communication mode after the predetermined period of time has elapsed, but directly sets it to the normal operation mode.

[0082] The nonvolatile memory 270 is a memory that stores various types of information, such as a MONOS-type memory or an EEPROM. During the manufacturing process of the second oscillator 2b, various types of information for controlling each circuit, such as a temperature compensation function setting bit cmpEN, temperature compensation data cmpDT, PLL setting data pllDT, and output setting data outDT, are stored in the nonvolatile memory 270. When power is applied to the second oscillator 2b, the various types of information stored in the nonvolatile memory 270 are transferred to registers (not shown) included in the logic circuit 260, and the various types of information stored in the registers are supplied to each circuit as appropriate.

[0083] The oscillator circuit 220 is an example of a "second oscillator circuit," and the oscillator signal Vosc output from the oscillator circuit 220 is an example of a "second oscillator signal." The oscillator signal Vpll output from the PLL circuit 240 is an example of a "third oscillator signal." The amplifier circuit 228 is an example of a "second amplifier circuit," the current source 227 is an example of a "second current source," the MOS transistor 222 is an example of a "second transistor," and the current Iref supplied by the MOS transistor 222 to the amplifier circuit 228 is an example of a "second current." Furthermore, the temperature compensation circuit 230 is an example of a "second temperature compensation circuit," and the temperature compensation signal Vcmp output from the temperature compensation circuit 230 is an example of a "second temperature compensation signal."

[0084] 1-4. Layout of the first integrated circuit device and the second integrated circuit device Fig. 12 is a diagram showing an example of the layout arrangement of the first integrated circuit device 4a. In the example of Fig. 12, the first integrated circuit device 4a has a rectangular semiconductor substrate 100 having four sides 100a, 100b, 100c, and 100d in a plan view. The bias circuit 110, the oscillation circuit 120, the temperature compensation circuit 130, the output circuit 140, the logic circuit 150, and the non-volatile memory 160 shown in Fig. 2 are formed on the semiconductor substrate 100.

[0085] The oscillation circuit 120 is arranged in a rectangular region along sides 100a, 100b, and 100c. The temperature compensation circuit 130 is arranged in an L-shaped region along sides 100a and 100c. The output circuit 140 is arranged in a convex region along side 100a. The logic circuit 150 is arranged in a rectangular region along sides 100c and 100d. The non-volatile memory 160 is arranged in a rectangular region between the arrangement region of the logic circuit 150 and the arrangement region of the temperature compensation circuit 130. The bias circuit 110 is arranged in a rectangular region along side 100d between the arrangement region of the logic circuit 150 and the arrangement region of the temperature compensation circuit 130.

[0086] Rectangular pad 185, which is the XO terminal, and rectangular pad 186, which is the XI terminal, are arranged along side 100b in the arrangement area of ​​oscillator circuit 120. Rectangular pad 181, which is the VDD terminal, and rectangular pad 183, which is the OUT terminal, are arranged so as to sandwich a part of output circuit 140 therebetween. Rectangular pad 184, which is the OE terminal, and rectangular pad 182, which is the VSS terminal, are arranged so as to sandwich nonvolatile memory 160 therebetween.

[0087] If the intersection of sides 100a and 100b is the origin, the direction along side 100a is the x direction, and the direction along side 100b is the y direction, the x coordinate value of the center point of pad 185 and the x coordinate value of the center point of pad 186 are both x11, and the y coordinate value y13 of the center point of pad 185 is greater than the y coordinate value y12 of the center point of pad 186. The x coordinate value of the center point of pad 181 and the x coordinate value of the center point of pad 184 are both x12 greater than x11, and the x coordinate value of the center point of pad 183 and the x coordinate value of the center point of pad 182 are both x13 greater than x12. The y coordinate value of the center point of pad 181 and the y coordinate value of the center point of pad 183 are both y11 smaller than y12, and the y coordinate value of the center point of pad 182 are both y14 greater than y13.

[0088] Fig. 13 is a diagram showing an example of the layout arrangement of the second integrated circuit device 4b. In the example of Fig. 13, the second integrated circuit device 4b has a rectangular semiconductor substrate 200 having four sides 200a, 200b, 200c, and 200d in a plan view. The bias circuit 210, the oscillation circuit 220, the temperature compensation circuit 230, the PLL circuit 240, the output circuit 250, the logic circuit 260, and the nonvolatile memory 270 shown in Fig. 8 are formed on the semiconductor substrate 200.

[0089] The oscillator circuit 220 is arranged in a rectangular region along sides 200a, 200b, and 200c. The PLL circuit 240 is arranged in an L-shaped region along sides 200a and 200c. The output circuit 250 is arranged in a convex region along side 200a. The temperature compensation circuit 230 is arranged in a rectangular region between the arrangement region of the oscillator circuit 220 and the arrangement region of the PLL circuit 240. The logic circuit 260 is arranged in a rectangular region along sides 200c and 200d. The non-volatile memory 270 is arranged in a rectangular region between the arrangement region of the logic circuit 260 and the arrangement region of the PLL circuit 240. The bias circuit 210 is arranged in a rectangular region along side 200d between the arrangement region of the logic circuit 260 and the arrangement region of the PLL circuit 240.

[0090] Rectangular pad 285, which is the XO terminal, and rectangular pad 286, which is the XI terminal, are arranged along side 200b in the arrangement area of ​​oscillator circuit 220. Rectangular pad 281, which is the VDD terminal, and rectangular pad 283, which is the OUT terminal, are arranged so as to sandwich a part of output circuit 250 therebetween. Rectangular pad 284, which is the OE terminal, and rectangular pad 282, which is the VSS terminal, are arranged so as to sandwich nonvolatile memory 270 therebetween.

[0091] If the intersection of sides 200a and 200b is the origin, the direction along side 200a is the x direction, and the direction along side 200b is the y direction, the x coordinate value of the center point of pad 285 and the x coordinate value of the center point of pad 286 are both x21, and the y coordinate value y23 of the center point of pad 285 is greater than the y coordinate value y22 of the center point of pad 286. The x coordinate value of the center point of pad 281 and the x coordinate value of the center point of pad 284 are both x22 greater than x21, and the x coordinate value of the center point of pad 283 and the x coordinate value of the center point of pad 282 are both x23 greater than x22. The y coordinate value of the center point of pad 281 and the y coordinate value of the center point of pad 283 are both y21 smaller than y22, and the y coordinate value of the center point of pad 284 and the y coordinate value of the center point of pad 282 are both y24 greater than y23.

[0092] In the examples of Figures 12 and 13, pads 181 and 281 have the same size and shape, pads 182 and 282 have the same size and shape, pads 183 and 283 have the same size and shape, pads 184 and 284 have the same size and shape, pads 185 and 285 have the same size and shape, and pads 186 and 286 have the same size and shape.

[0093] Furthermore, the first integrated circuit device 4a and the second integrated circuit device 4b are the same size, and the relative positional relationship between the pads 181 to 186 is the same as the relative positional relationship between the pads 281 to 286. In other words, when the center point of any two corresponding pads, for example, the pads 181 and 182, is assumed to be the origin, the coordinates of the center point of the pads 181 to 186 and the coordinates of the center point of the pads 281 to 286 match. In particular, in the examples of Figures 12 and 13, the coordinates (x12, y11) of the center point of pad 181 and the coordinates (x22, y21) of the center point of pad 281 are equal, the coordinates (x13, y14) of the center point of pad 182 and the coordinates (x23, y24) of the center point of pad 282 are equal, the coordinates (x13, y11) of the center point of pad 183 and the coordinates (x23, y21) of the center point of pad 283 are equal, the coordinates (x12, y14) of the center point of pad 184 and the coordinates (x22, y24) of the center point of pad 284 are equal, the coordinates (x11, y13) of the center point of pad 185 and the coordinates (x21, y23) of the center point of pad 285 are equal, and the coordinates (x11, y12) of the center point of pad 186 and the coordinates (x21, y22) of the center point of pad 286 are equal. That is, the first integrated circuit device 4a and the second integrated circuit device 4b have the same size, and the positions of the pads 181 to 186 on the first integrated circuit device 4a are the same as the positions of the pads 281 to 286 on the second integrated circuit device 4b.

[0094] Furthermore, the layout area of ​​the bias circuit 110 and the layout area of ​​the bias circuit 210 are the same or almost the same in size, shape, and position. The layout area of ​​the oscillator circuit 120 and the layout area of ​​the oscillator circuit 220 are the same or almost the same in size, shape, and position. The layout area of ​​the output circuit 140 and the layout area of ​​the output circuit 250 are the same or almost the same in size, shape, and position. The layout area of ​​the logic circuit 150 and the layout area of ​​the logic circuit 260 are the same or almost the same in size, shape, and position. The layout area of ​​the nonvolatile memory 160 and the layout area of ​​the nonvolatile memory 270 are the same or almost the same in size, shape, and position. Therefore, it is possible to standardize the layout of at least a part of the multiple wiring patterns connecting these multiple circuits. Furthermore, the layout areas of the oscillator circuit 120 and the oscillator circuit 220, the output circuit 140 and the output circuit 250, the bias circuit 110 and the bias circuit 210, and At least one pair of the logic circuits 150 and 260 may have the same circuit configuration. If the oscillator circuit 120 and the oscillator circuit 220 have the same circuit configuration, they can have a common layout; if the output circuit 140 and the output circuit 250 have the same circuit configuration, they can have a common layout; if the bias circuit 110 and the bias circuit 210 have the same circuit configuration, they can have a common layout; and if the logic circuit 150 and the logic circuit 260 have the same circuit configuration, they can have a common layout. Therefore, the number of development steps for the first integrated circuit device 4a or the second integrated circuit device 4b can be reduced.

[0095] Furthermore, the PLL circuit 240 is disposed in at least a portion of the second region A2 of the second integrated circuit device 4b, which corresponds to the first region A1 of the first integrated circuit device 4a in which the temperature compensation circuit 130 is disposed. The second region A2 has the same size, shape, and location as the first region A1. In this embodiment, as shown in FIGS. 12 and 13, the temperature compensation circuit 230 is smaller than the temperature compensation circuit 130, and the PLL circuit 240 and the temperature compensation circuit 230 are disposed in at least a portion of the second region A2. That is, since a large area is secured for the temperature compensation circuit 130 in the first integrated circuit device 4a, the number of bits of the temperature compensation data cmpDT can be increased to generate compensation signals corresponding to terms of each order of the temperature compensation function with high resolution, and a temperature compensation circuit 130 capable of generating compensation signals corresponding to terms of higher orders can be realized. Therefore, a first oscillator 2a capable of outputting an oscillation signal Vout having extremely high frequency-temperature characteristics can be realized. FIG. 14 shows an example of the frequency-temperature characteristic of the oscillation signal Vout output from the first oscillator 2a using a solid line. In FIG. 14, the dashed-dotted line indicates the frequency-temperature characteristic of the first oscillator 5a or the second oscillator 5b, and the dashed line indicates the frequency-temperature characteristic of the oscillation signal Vout output from the second oscillator 2b. In FIG. 14, the horizontal axis represents temperature, and the vertical axis represents frequency deviation from the target frequency. In the example shown in FIG. 14, the frequency deviation of the signal output from the first oscillator 5a or the second oscillator 5b varies within a range of approximately ±20 ppm in the temperature range from −40°C to +100°C. In the temperature range from −40°C to +100°C, the frequency deviation of the oscillation signal Vout output from the second oscillator 2b is within a range of approximately ±2 ppm, while the frequency deviation of the oscillation signal Vout output from the first oscillator 2a is within a range of less than approximately ±1 ppm.

[0096] Furthermore, since the first integrated circuit device 4a of the first oscillator 2a does not include a PLL circuit, current consumption and phase noise are reduced compared to the second oscillator 2b, which includes the second integrated circuit device 4b that includes the PLL circuit 240. FIG. 15 shows an example of the phase noise of the oscillation signal Vout output from the first oscillator 2a with a solid line. In FIG. 15, the dashed line shows an example of the phase noise of the oscillation signal Vout output from the second oscillator 2b. In FIG. 15, the horizontal axis represents the offset frequency with the target frequency set to 0, and the vertical axis represents the phase noise. In the example of FIG. 15, there is no difference in the phase noise between the two oscillators when the offset frequency is 10 kHz or less, but when the offset frequency is in the range of 10 kHz to 100 MHz, the phase noise of the first oscillator 2a is smaller.

[0097] On the other hand, the second oscillator 2b can set the oscillation signal Vout to a desired target frequency with high resolution over a wide frequency range because the second integrated circuit device 4b includes the PLL circuit 240. Furthermore, the temperature compensation circuit 230 has a simple configuration that does not generate signals corresponding to fourth-order or higher components of the temperature compensation function, but achieves good frequency-temperature characteristics of the oscillation signal Vout.

[0098] In this embodiment, the first integrated circuit device 4a and the second integrated circuit device 4b are of the same type and have the same size, shape, and pad positions. However, the first integrated circuit device 4a and the second integrated circuit device 4b may be of different types and have different sizes, shapes, and pad positions as long as they can be housed in the same type of first container 3a and second container 3b, respectively. At least one of the positions of the dots may be different.

[0099] 1-5. Structure of the first oscillator and the second oscillator 16, 17, and 18 are diagrams showing an example of the structure of the first oscillator 2a and the second oscillator 2b. FIG. 16 is a perspective view of the first oscillator 2a and the second oscillator 2b, and FIG. 17 is a cross-sectional view of the first oscillator 2a and the second oscillator 2b. FIG. 18 is a plan view showing a plurality of electrodes formed in the first container 3a and the second container 3b. Note that FIG. 17 is a cross-sectional view of the first oscillator 2a and the second oscillator 2b taken along line AA in FIG. 18.

[0100] 16 and 17, the first oscillator 2a has a first integrated circuit device 4a, a first vibrator 5a, a first container 3a that houses the first integrated circuit device 4a and the first vibrator 5a, and a first lid 6a that hermetically seals the housing space 7 that houses the first vibrator 5a. Similarly, the second oscillator 2b has a second integrated circuit device 4b, a second vibrator 5b, a second container 3b that houses the second integrated circuit device 4b and the second vibrator 5b, and a second lid 6b that hermetically seals the housing space 7 that houses the second vibrator 5b.

[0101] The first vibrator 5a and the second vibrator 5b are, for example, tuning-fork vibrators based on quartz crystal, and oscillate at a resonant frequency determined by their external shape and dimensions, thereby oscillating at a desired frequency. In this embodiment, the first vibrator 5a and the second vibrator 5b are of the same type and have the same size, shape, and terminal positions. However, the first vibrator 5a and the second vibrator 5b may be of different types and may differ in at least one of size, shape, and terminal positions, as long as they can be housed in the same type of first container 3a and second container 3b, respectively.

[0102] The first container 3a and the second container 3b are made of ceramic or the like, and are configured by laminating a substrate 31, a first frame substrate 32, and a second frame substrate 33, as shown in FIGS. 17 and 18. As shown in FIGS. 17 and 18, electrodes 41, 42, 43, 44, 45, and 46 are provided on a first surface 31a of the substrate 31, and a plurality of external terminals 8 are provided on a second surface 31b of the substrate 31. The plurality of external terminals 8 correspond to the VDD1 terminal, VSS1 terminal, OUT1 terminal, and OE1 terminal shown in FIG. 2 or 8, respectively. Each external terminal 8 and each electrode 41, 42, 43, and 44 are electrically connected by wiring (not shown).

[0103] 18, pads 181, 182, 183, 184, 185, and 186 of the first integrated circuit device 4a shown in FIG. 12 are electrically and mechanically connected to electrodes 41, 42, 43, 44, 45, and 46 provided on the first surface 31a of the substrate 31 via bonding members 61 such as conductive adhesive or gold bumps. The pads 181, 182, 183, 184, 185, and 186 correspond to the VDD terminal, VSS terminal, OUT terminal, OE terminal, XO terminal, and XI terminal of the first oscillator 2a shown in FIG. 2, respectively.

[0104] 18, the pads 281, 282, 283, 284, 285, and 286 of the second integrated circuit device 4b shown in FIG. 13 are electrically and mechanically connected to the electrodes 41, 42, 43, 44, 45, and 46 provided on the first surface 31a of the substrate 31 via bonding members 61 such as conductive adhesive or gold bumps. The pads 281, 282, 283, 284, 285, and 286 correspond to the VDD terminal, VSS terminal, OUT terminal, OE terminal, XO terminal, and XI terminal of the second oscillator 2b shown in FIG. 8, respectively.

[0105] 17 and 18, the first frame substrate 32 is an annular substrate from which a portion including the position of the first integrated circuit device 4a or the second integrated circuit device 4b has been removed. Electrodes 75 and 76 are provided on a first surface 32a of the first frame substrate 32, and a second surface 32b of the first frame substrate 32 is bonded to a second surface 31b of the substrate 31. As shown by the dashed line in FIG. 18, As shown, the terminals 55, 56 of the first vibrator 5a or the second vibrator 5b are electrically and mechanically connected to the electrodes 75, 76 provided on the first surface 32a of the first frame substrate 32 via bonding members 62 such as conductive adhesive or gold bumps. The electrodes 75, 76 provided on the first surface 32a of the first frame substrate 32 and the electrodes 45, 46 provided on the first surface 31a of the substrate 31 are electrically connected by wiring (not shown).

[0106] 17, the second frame substrate 33 is an annular substrate from which a portion including the position of the first vibrator 5a or the second vibrator 5b has been removed. The first lid 6a or the second lid 6b is made of metal, ceramic, glass, or the like, and is joined to the second frame substrate 33 via a joining member 63 such as a seal ring or low-melting-point glass, thereby forming an airtightly sealed housing space 7 that houses the first vibrator 5a or the second vibrator 5b. The housing space 7 is an airtight space and is in a reduced pressure state, preferably closer to a vacuum.

[0107] In this embodiment, the first container 3a and the second container 3b are the same type of container. Therefore, the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the first container 3a are the same as the shapes of the electrodes 41, 42, 43, 44, 45, and 46 provided in the second container 3b. Furthermore, the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the first container 3a are the same as the positions of the electrodes 41, 42, 43, 44, 45, and 46 in the second container 3b. Furthermore, as shown in FIGS. 12 and 13, the first integrated circuit device 4a and the second integrated circuit device 4b are the same size, and the positions of the pads 181 to 186 in the first integrated circuit device 4a are the same as the positions of the pads 281 to 286 in the second integrated circuit device 4b. 18, the positions where the pads 181-186 of the first integrated circuit device 4a are bonded to the electrodes 41-46 of the first container 3a are the same as the positions where the pads 281-286 of the second integrated circuit device 4b are bonded to the electrodes 41-46 of the second container 3b. That is, the first integrated circuit device 4a and the second integrated circuit device 4b can be mounted in the same type of first container 3a and second container 3b, respectively. Therefore, the number of steps required for determining mounting conditions and for designing the container are not required for either the first oscillator 2a or the second oscillator 2b, and the overall manufacturing cost of the first oscillator 2a and the second oscillator 2b is reduced.

[0108] The electrodes 41, 42, 43, 44, 45, and 46 of the first container 3a are an example of the "first to Nth electrodes," and the electrodes 41, 42, 43, 44, 45, and 46 of the second container 3b are an example of the "N+1th to 2Nth electrodes." The pads 181, 182, 183, 184, 185, and 186 of the first integrated circuit device 4a are an example of the "first to Nth pads," and the pads 281, 282, 283, 284, 285, and 286 of the second integrated circuit device 4b are an example of the "N+1th to 2Nth pads." In this embodiment, the integer N is 6.

[0109] 1-6. Oscillator manufacturing method 19 is a flow chart showing an example of the steps of the method for manufacturing the oscillator of this embodiment. For example, a manufacturing device (not shown) performs each step of FIG.

[0110] In the example of Figure 19, if a first oscillator 2a is to be manufactured in step S1, in step S2, the manufacturing equipment places a first resonator 5a and a first integrated circuit device 4a in a first container 3a to manufacture the first oscillator 2a.

[0111] Next, if the second oscillator 2b is to be manufactured in step S3, the manufacturing equipment houses the second resonator 5b and the second integrated circuit device 4b in the second container 3b in step S4 to manufacture the second oscillator 2b.

[0112] FIG. 20 is a flowchart showing an example of the detailed procedure of step S2 in FIG.

[0113] In the example of FIG. 20, first, in step S21, the manufacturing equipment connects the pads 181 to 186 of the first integrated circuit device 4a to the electrodes 41 to 46 of the first container 3a, respectively.

[0114] Next, in step S22, the manufacturing equipment connects the terminals 55 and 56 of the first vibrator 5a to the electrodes 75 and 76 of the first container 3a, respectively.

[0115] Next, in step S23, the manufacturing equipment joins the first lid 6a to the first container 3a.

[0116] Next, if the first oscillator 2a to be manufactured in step S24 has a temperature compensation function, the manufacturing equipment creates temperature compensation data cmpDT in step S25. If the first oscillator 2a to be manufactured in step S24 does not have a temperature compensation function, the manufacturing equipment does not perform step S25.

[0117] Next, in step S26, the manufacturing equipment sets whether or not to operate the temperature compensation circuit 130. Specifically, if the first oscillator 2a to be manufactured is one that has a temperature compensation function, the manufacturing equipment writes a temperature compensation function setting bit cmpEN into the nonvolatile memory 160 to operate the temperature compensation circuit 130, and if the first oscillator 2a to be manufactured is one that does not have a temperature compensation function, the manufacturing equipment writes a temperature compensation function setting bit cmpEN into the nonvolatile memory 160 to prevent the temperature compensation circuit 130 from operating.

[0118] Finally, in step S27, the manufacturing equipment sets the output type, output capacity, and frequency division ratio of the output circuit 140. Specifically, the manufacturing equipment writes the output setting data outDT, in which the output type, output capacity, and frequency division ratio are set, into the nonvolatile memory 160.

[0119] FIG. 21 is a flowchart showing an example of the detailed procedure of step S4 in FIG.

[0120] In the example of FIG. 21, first, in step S41, the manufacturing equipment connects the pads 281 to 286 of the second integrated circuit device 4b to the electrodes 41 to 46 of the second container 3b, respectively.

[0121] Next, in step S42, the manufacturing equipment connects terminals 55 and 56 of second vibrator 5b to electrodes 75 and 76 of second container 3b, respectively.

[0122] Next, in step S43, the manufacturing equipment joins the second lid 6b to the second container 3b.

[0123] Next, if the second oscillator 2b to be manufactured in step S44 has a temperature compensation function, the manufacturing equipment creates temperature compensation data cmpDT in step S45. If the second oscillator 2b to be manufactured in step S24 does not have a temperature compensation function, the manufacturing equipment does not perform step S45.

[0124] Next, in step S46, the manufacturing equipment sets whether or not to operate the temperature compensation circuit 230. Specifically, if the second oscillator 2b to be manufactured is one that has a temperature compensation function, the manufacturing equipment writes a temperature compensation function setting bit cmpEN into the nonvolatile memory 270 to operate the temperature compensation circuit 230, and if the second oscillator 2b to be manufactured is one that does not have a temperature compensation function, the manufacturing equipment writes a temperature compensation function setting bit cmpEN into the nonvolatile memory 270 to prevent the temperature compensation circuit 230 from operating.

[0125] Next, in step S47, the manufacturing equipment controls the operation of the PLL circuit 240 as an integer PL The manufacturing equipment sets the PLL method to the L method or the fractional PLL method, and in step S48, sets the division ratio of the PLL circuit 240. Specifically, in steps S47 and S48, the manufacturing equipment writes PLL setting data pllDT, in which the PLL method and the division ratio are set, into the nonvolatile memory 270.

[0126] Finally, in step S49, the manufacturing equipment sets the output type, output capacity, and frequency division ratio of the output circuit 250. Specifically, the manufacturing equipment writes the output setting data outDT, in which the output type, output capacity, and frequency division ratio are set, into the nonvolatile memory 270.

[0127] The first oscillator 2a and the second oscillator 2b may be manufactured in the same factory or in different factories, and may be manufactured in the same country or in different countries.

[0128] 1-7.Effects As described above, according to the first embodiment, the first oscillator 2a is manufactured by housing the first resonator 5a and the first integrated circuit device 4a without a PLL circuit in the first container 3a, and the second oscillator 2b is manufactured by housing the second resonator 5b and the second integrated circuit device 4b with the PLL circuit 240 in the second container 3b, so it is possible to manufacture a plurality of types of oscillators having different functions related to output frequency. Furthermore, according to the first embodiment, since the first container 3a and the second container 3b are the same type of container, man-hours for setting mounting conditions and man-hours for container design are not required in the development of the first oscillator 2a or the second oscillator 2b, and a plurality of types of oscillators can be manufactured efficiently at low cost.

[0129] Furthermore, in the first embodiment, the positions of the pads 181-186 on the first integrated circuit device 4a are the same as the positions of the pads 281-286 on the second integrated circuit device 4b. Therefore, according to the first embodiment, the six positions where the pads 181-186 are connected to the electrodes 41-46 of the first container 3a, respectively, are the same as the six positions where the pads 281-286 are connected to the electrodes 41-46 of the second container 3b, respectively, and therefore the degree of freedom in the size and shape of the electrodes 41-46 is improved.

[0130] Furthermore, in the first embodiment, the first vibrator 5a and the second vibrator 5b have the same size and shape, and the first integrated circuit device 4a and the second integrated circuit device 4b have the same size and shape, so that the first container 3a and the second container 3b can be made to an optimal size.

[0131] Furthermore, according to the first embodiment, it is possible to standardize the layout of each circuit except for the temperature compensation circuit 130 of the first integrated circuit device 4a and the layout of each circuit except for the temperature compensation circuit 230 and the PLL circuit 240 of the second integrated circuit device 4b, thereby reducing the development man-hours for the first integrated circuit device 4a or the second integrated circuit device 4b, and thereby reducing the manufacturing cost of the first oscillator 2a or the second oscillator 2b.

[0132] Furthermore, according to the first embodiment, the second integrated circuit device 4b includes the PLL circuit 240 and the temperature compensation circuit 230, thereby enabling the manufacture of a second oscillator 2b that can set a target frequency over a wide frequency range and has excellent frequency-temperature characteristics. The PLL circuit 240 and the temperature compensation circuit 230 are disposed in the second area A2 of the second integrated circuit device 4b, which corresponds to the first area A1 of the first integrated circuit device 4a in which the temperature compensation circuit 130 is disposed. Therefore, a wide area is secured for the temperature compensation circuit 130 in the first integrated circuit device 4a, thereby realizing a temperature compensation circuit 130 that can generate compensation signals corresponding to terms of each order of the temperature compensation function with high resolution and generate compensation signals corresponding to terms of higher orders. Therefore, according to the first embodiment, a first oscillator 2a with excellent frequency-temperature characteristics can be manufactured.

[0133] Furthermore, according to the first embodiment, by setting the temperature compensation circuit 130 to operate, it is possible to manufacture a first oscillator 2a having a high frequency-temperature characteristic, and by setting the temperature compensation circuit 130 to not operate, it is possible to manufacture a first oscillator 2a with low current consumption.

[0134] Furthermore, according to the first embodiment, by setting the operation of the PLL circuit 240 to the integer PLL method, it is possible to manufacture a second oscillator 2b that has low current consumption and can set a target frequency over a wide frequency range, and by setting the operation of the PLL circuit 240 to the fractional PLL method, it is possible to manufacture a second oscillator 2b that can set a target frequency over a wide frequency range with high resolution.

[0135] 2. Second embodiment In the following, in the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and explanations of the same components as those in the first embodiment are omitted or simplified, and differences from the first embodiment will be mainly described.

[0136] The structures of the first oscillator 2a and the second oscillator 2b in the second embodiment are the same as those in FIGS. 16 to 18, and therefore illustration and description thereof will be omitted. Also, the functional block diagram of the first integrated circuit device 4a is the same as that in FIG. 2, and the functional block diagram of the second integrated circuit device 4b is the same as that in FIG. 8, and therefore illustration and description thereof will be omitted. Also, the layout arrangement of the second integrated circuit device 4b is the same as that in FIG. 13, and therefore illustration and description thereof will be omitted. Also, an example of the procedure for the manufacturing method of the oscillator in the second embodiment is the same as that in FIGS. 19 to 21, and therefore illustration and description thereof will be omitted.

[0137] In the second embodiment, the configuration of the temperature compensation circuit 130 included in the first integrated circuit device 4a is different from that in the first embodiment. Fig. 22 is a diagram showing an example configuration of the temperature compensation circuit 130 in the second embodiment. In the example of Fig. 22, the temperature compensation circuit 130 includes a temperature sensor 131, a zeroth-order component generating circuit 132, a first-order component generating circuit 133, a high-order component generating circuit 134, an I / V conversion circuit 135, and an RC low-pass filter 136.

[0138] The functions of the temperature sensor 131, the zeroth-order component generating circuit 132, the first-order component generating circuit 133, the high-order component generating circuit 134, and the I / V converting circuit 135 are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0139] RC low-pass filter 136 is a low-pass filter including a resistive element 137 and a capacitive element 138, which receives the signal output from I / V conversion circuit 135 and outputs temperature compensation signal Vcmp. In other words, RC low-pass filter 136 reduces noise contained in temperature compensation signal Vcmp.

[0140] The first oscillator 2a in the second embodiment has a lower phase noise than the first embodiment because the first integrated circuit device 4a includes an RC low-pass filter 136. FIG. 23 shows an example of the phase noise of the oscillation signal Vout output from the first oscillator 2a in the second embodiment, indicated by a solid line. In FIG. 23, the dashed line indicates the phase noise of the oscillation signal Vout output from the second oscillator 2b, indicated by a dashed line in FIG. 15, and the dashed-dotted line indicates the phase noise of the oscillation signal Vout output from the first oscillator 2a in the first embodiment, indicated by a solid line in FIG. 15. In FIG. 23, the horizontal axis represents the offset frequency, with the target frequency set to 0, and the vertical axis represents the phase noise. In the example of FIG. 23, the first oscillator 2a in the second embodiment has a lower phase noise in the frequency band with an offset frequency of 1 MHz or less than the first oscillator 2a in the first embodiment.

[0141] The layout of the first integrated circuit device 4a may be the same as that shown in FIG. 12. In this case, to ensure the area required for arranging the RC low-pass filter 136 in the first region A1 where the temperature compensation circuit 130 is arranged, for example, the high-order component generating circuit 134 may output current signals corresponding to the second-order to fifth-order terms of the temperature compensation function. By preventing the high-order component generating circuit 134 from generating current signals corresponding to the sixth-order or seventh-order terms of the temperature compensation function, the area required for arranging the high-order component generating circuit 134 becomes smaller than that of the first embodiment, and the RC low-pass filter 136 can be arranged in the resulting area. In particular, increasing the capacitance of the capacitive element 138 is more effective at reducing phase noise than increasing the resistance of the resistive element 137. Therefore, it is preferable to increase the capacitance of the capacitive element 138 and arrange it in the first region A1.

[0142] According to the second embodiment described above, it is possible to obtain the same effects as those of the first embodiment. Furthermore, according to the second embodiment, the temperature compensation circuit 130 includes the RC low-pass filter 136 that reduces noise contained in the temperature compensation signal Vcmp, so it is possible to manufacture a first oscillator 2a with reduced phase noise.

[0143] 3. Third embodiment Hereinafter, for the third embodiment, the same symbols will be used for configurations that are similar to those of the first or second embodiment, and explanations that are similar to those of the first or second embodiment will be omitted or simplified, and the following will mainly describe the differences from the first and second embodiments.

[0144] The structures of the first oscillator 2a and the second oscillator 2b in the third embodiment are the same as those in FIGS. 16 to 18, and therefore illustration and description thereof will be omitted. Also, the functional block diagram of the first integrated circuit device 4a is the same as that in FIG. 2, and the functional block diagram of the second integrated circuit device 4b is the same as that in FIG. 8, and therefore illustration and description thereof will be omitted. Also, the layout arrangement of the second integrated circuit device 4b is the same as that in FIG. 13, and therefore illustration and description thereof will be omitted. Also, an example of the procedure for the manufacturing method of the oscillator in the second embodiment is the same as that in FIGS. 19 to 21, and therefore illustration and description thereof will be omitted.

[0145] In the first or second embodiment, the oscillator circuit 120 included in the first integrated circuit device 4a and the oscillator circuit 220 included in the second integrated circuit device 4b have the same circuit configuration and layout.

[0146] In contrast, in the third embodiment, the size of the MOS transistor 121 included in the oscillation circuit 120 is larger than the size of the MOS transistor 221 included in the oscillation circuit 220. Similarly, the size of the MOS transistor 122 included in the MOS transistor 121 included in the oscillation circuit 120 is larger than the size of the MOS transistor 222 included in the oscillation circuit 220. Here, the size is the product of the gate width W and the gate length L. For example, if the gate width W of the MOS transistors 121 and 122 is twice the gate width W of the MOS transistors 221 and 222, respectively, and the gate length L of the MOS transistors 121 and 122 is twice the gate length L of the MOS transistors 221 and 222, respectively, then the sizes of the MOS transistors 121 and 122 are four times the sizes of the MOS transistors 221 and 222, respectively.

[0147] As described above, in the first oscillator 2a of the third embodiment, the sizes of the MOS transistors 121 and 122 included in the oscillation circuit 120 are large, so the 1 / f noise generated in the MOS transistors 121 and 122 is small, and similar to the second embodiment, the phase noise is reduced more than in the first embodiment. However, in the third embodiment, the sizes of the MOS transistors 221 and 222 are larger than in the first or second embodiment, so the size of the oscillation circuit 120 is The placement area also becomes larger.

[0148] FIG. 24 is a diagram illustrating an example of the layout of the first integrated circuit device 4a according to the third embodiment. Comparing FIG. 24 with FIG. 12, the layout area of ​​the oscillator circuit 120 is larger. Specifically, as shown in FIG. 24, the third region A3 of the first integrated circuit device 4a, which corresponds to the second region A2 in which the PLL circuit 240 of the second integrated circuit device 4b shown in FIG. 13 is arranged, contains a temperature compensation circuit 130 and a portion of the oscillator circuit 120, i.e., some or all of the MOS transistors 121 and 122. The third region A3 has the same size, shape, and position as the second region A2. Thus, to arrange a portion of the oscillator circuit 120 in the third region A3, the layout area of ​​the temperature compensation circuit 130 must be smaller than in the first or second embodiment. For example, in the configuration shown in FIG. 5, the high-order component generating circuit 134 may output current signals corresponding to the second- to fifth-order terms of the temperature compensation function. By preventing the high-order component generating circuit 134 from generating current signals corresponding to the sixth-order or seventh-order terms of the temperature compensation function, the layout area of ​​the high-order component generating circuit 134 can be made smaller than in the first embodiment. Alternatively, the RC low-pass filter 136 may be omitted from the configuration shown in FIG.

[0149] According to the third embodiment described above, the same effects as those of the first embodiment can be obtained. Furthermore, according to the third embodiment, the 1 / f noise generated in the MOS transistors 121 and 122 included in the oscillation circuit 120 is reduced, so that the first oscillator 2a with reduced phase noise can be manufactured.

[0150] 4. Variations The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0151] In the above embodiments, the pads 181-186 of the first integrated circuit device 4a and the pads 281-286 of the second integrated circuit device 4b are the same in size, shape, and position, but as long as the pads 181-186 are connectable to the electrodes 41-46 of the first container 3a, respectively, and the pads 281-286 are connectable to the electrodes 41-46 of the second container 3b, respectively, the pads 181-186 and the pads 281-286 may differ in at least one of size, shape, and position. Furthermore, the arrangement and functions of the pads 181-186 and the pads 281-286 are not limited to the examples given in the above embodiments.

[0152] Furthermore, in each of the above embodiments, the first integrated circuit device 4a has six pads 181-186, and the first container 3a is provided with six electrodes 41-46 connected to the pads 181-186, respectively, but the number of pads in the first integrated circuit device 4a and the number of electrodes provided in the first container 3a are not limited to 6. Similarly, the second integrated circuit device 4b has six pads 281-286, and the second container 3b is provided with six electrodes 41-46 connected to the pads 281-286, respectively, but the number of pads in the second integrated circuit device 4b and the number of electrodes provided in the second container 3b are not limited to 6. For example, when the first oscillator 2a and the second oscillator 2b are oscillators that output differential oscillation signals, or when the frequency of the oscillation signal changes based on an external control signal, the number of pads that the first integrated circuit device 4a and the second integrated circuit device 4b each have and the number of electrodes that are provided in the first container 3a and the second container 3b may be more than 6. That is, for any integer N greater than or equal to 2, the first integrated circuit device 4a may have 1st to Nth pads, and the first container 3a may be provided with 1st to Nth electrodes connected to the 1st to Nth pads, respectively, and the second integrated circuit device 4b may have N+1th to 2Nth pads, and the second container 3b may be provided with N+1th to 2Nth electrodes connected to the N+1th to 2Nth pads, respectively.

[0153] 17, the first oscillator 2a is an oscillator with a single seal structure in which the first integrated circuit device 4a and the first vibrator 5a are housed in the same space, and similarly, the second oscillator 2b is an oscillator with a single seal structure in which the second integrated circuit device 4b and the second vibrator 5b are housed in the same space, but the first oscillator 2a and the second oscillator 2b are not limited to oscillators with a single seal structure. For example, the first oscillator 2a may be an oscillator with a structure in which the first integrated circuit device 4a is disposed outside the housing space for the first vibrator 5a, and similarly, the second oscillator 2b may be an oscillator with a structure in which the second integrated circuit device 4b is disposed outside the housing space for the second vibrator 5b.

[0154] In the above embodiments, tuning-fork vibrators using quartz crystal as a base material have been exemplified as the first vibrator 5a and the second vibrator 5b. However, the base material of the first vibrator 5a and the second vibrator 5b may be, in addition to quartz crystal, piezoelectric materials such as piezoelectric single crystals (e.g., lithium tantalate and lithium niobate), piezoelectric ceramics (e.g., lead zirconate titanate), or silicon semiconductor materials. The first vibrator 5a and the second vibrator 5b may be, for example, AT-cut quartz crystal vibrators, SAW resonators, or MEMS vibrators. SAW stands for Surface Acoustic Wave, and MEMS stands for Micro Electro Mechanical Systems. The excitation means for the first vibrator 5a and the second vibrator 5b may be based on the piezoelectric effect or electrostatic driving using Coulomb force.

[0155] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0156] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0157] The following can be derived from the above-described embodiment and modifications.

[0158] One aspect of the method for manufacturing an oscillator includes: A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, but does not include a PLL circuit; the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal; The first container and the second container are the same type of container.

[0159] According to this method for manufacturing an oscillator, a first oscillator is manufactured by housing a first resonator and a first integrated circuit device that does not have a PLL circuit in a first container, and a second oscillator is manufactured by housing a second resonator and a second integrated circuit device that has a PLL circuit in a second container, so that it is possible to manufacture a plurality of types of oscillators that have different functions related to output frequency. In the development of the first or second oscillator, the man-hours for setting mounting conditions and the man-hours for designing the container are not required, and multiple types of oscillators can be manufactured efficiently at low cost.

[0160] In one aspect of the method for manufacturing the oscillator, N is an integer equal to or greater than 2, The first container is provided with first to Nth electrodes, The second container is provided with N+1 to 2N electrodes, the first integrated circuit device has first to Nth pads, the second integrated circuit device has pads (N+1) to (2N), For each integer i greater than or equal to 1 and less than or equal to N, the shape of the i-th electrode and the shape of the N+i-th electrode are the same, and the position of the i-th electrode in the first container and the position of the N+i-th electrode in the second container are the same; manufacturing the first oscillator includes connecting the first to Nth pads to the first to Nth electrodes, respectively; Manufacturing the second oscillator may include connecting the (N+1)th to 2Nth pads to the (N+1)th to 2Nth electrodes, respectively.

[0161] In one aspect of the method for manufacturing the oscillator, For each integer i, the position of the i-th pad on the first integrated circuit device may be the same as the position of the N+i-th pad on the second integrated circuit device.

[0162] According to this method of manufacturing an oscillator, the N positions where the first to Nth pads are connected to the first to Nth electrodes, respectively, can be the same as the N positions where the N+1th to 2Nth pads are connected to the N+1th to 2Nth electrodes, respectively, thereby improving the degree of freedom in the size and shape of the first to Nth electrodes and the N+1th to 2Nth electrodes.

[0163] In one aspect of the method for manufacturing the oscillator, The first integrated circuit device and the second integrated circuit device may be the same size.

[0164] In one aspect of the method for manufacturing the oscillator, the first integrated circuit device includes a first temperature compensation circuit that outputs a first temperature compensation signal that compensates for the frequency temperature characteristic of the first oscillation signal; The PLL circuit may be arranged in at least a part of a second area of ​​the second integrated circuit device corresponding to a first area of ​​the first integrated circuit device in which the first temperature compensation circuit is arranged.

[0165] According to this oscillator manufacturing method, a large layout area for the first temperature compensation circuit is secured in the first integrated circuit device, so that it is possible to realize a temperature compensation circuit that can generate compensation signals corresponding to terms of each order of the temperature compensation function with high resolution and that can generate compensation signals corresponding to terms of higher orders. Therefore, according to this oscillator manufacturing method, it is possible to manufacture a first oscillator having excellent frequency-temperature characteristics.

[0166] In one aspect of the method for manufacturing the oscillator, The first temperature compensation circuit may include an RC low-pass filter that reduces noise contained in the first temperature compensation signal.

[0167] According to this method for manufacturing an oscillator, it is possible to manufacture a first oscillator with reduced phase noise.

[0168] In one aspect of the method for manufacturing the oscillator, the second integrated circuit device includes a second temperature compensation circuit that outputs a second temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal; the size of the second temperature compensation circuit is smaller than the size of the first temperature compensation circuit; The PLL circuit and the second temperature compensation circuit may be disposed in at least a part of the second region.

[0169] According to this method for manufacturing an oscillator, it is possible to manufacture a second oscillator that can set a target frequency over a wide frequency range and has good frequency temperature characteristics.

[0170] In one aspect of the method for manufacturing the oscillator, the first integrated circuit device is capable of setting whether or not to operate the first temperature compensation circuit; Manufacturing the first oscillator may include setting whether or not to operate the first temperature compensation circuit.

[0171] According to this method for manufacturing an oscillator, a first oscillator having a high frequency-temperature characteristic can be manufactured by setting the first temperature compensation circuit to operate, and a first oscillator with low current consumption can be manufactured by setting the first temperature compensation circuit to not operate.

[0172] In one aspect of the method for manufacturing the oscillator, the first oscillation circuit includes a first amplifier circuit that amplifies a signal from the first vibrator and outputs the first oscillation signal, and a first current source that has a first transistor that supplies a first current to the first amplifier circuit; the second oscillation circuit includes a second amplifier circuit that amplifies a signal from the second vibrator and outputs the second oscillation signal, and a second current source that has a second transistor that supplies a second current to the second amplifier circuit; The size of the first transistor may be greater than the size of the second transistor.

[0173] According to this method for manufacturing an oscillator, the 1 / f noise generated in the first transistor is reduced, so that a first oscillator with reduced phase noise can be manufactured.

[0174] In one aspect of the method for manufacturing the oscillator, the second integrated circuit device is capable of setting the operation of the PLL circuit to an integer PLL system or a fractional PLL system; Manufacturing the second oscillator may include setting the operation of the PLL circuit to the integer PLL method or the fractional PLL method.

[0175] According to this method for manufacturing an oscillator, a second oscillator with low current consumption and capable of setting a target frequency over a wide frequency range can be manufactured by setting the operation of the PLL circuit to an integer PLL system, and a second oscillator with high resolution and capable of setting a target frequency over a wide frequency range can be manufactured by setting the operation of the PLL circuit to a fractional PLL system.

[0176] One aspect of the oscillator is An oscillator included in an oscillator group consisting of multiple types of oscillators, a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, but does not include a PLL circuit; another oscillator included in the oscillator group includes a second vibrator, a second integrated circuit device that causes the second vibrator to oscillate, and a second container that houses the second vibrator and the second integrated circuit device; the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal; The first container and the second container are the same type of container.

[0177] This oscillator houses a first resonator and a first integrated circuit device that does not have a PLL circuit in a first container, and other oscillators in the oscillator group house a second resonator and a second integrated circuit device that has a PLL circuit in a second container, so the two oscillators have different functions related to output frequency. Furthermore, because the first container and the second container are the same type of container, the development of this oscillator or other oscillators does not require labor hours for setting mounting conditions or labor hours for container design, and multiple types of oscillators can be manufactured efficiently at low cost.

[0178] Another aspect of the oscillator is An oscillator included in an oscillator group consisting of multiple types of oscillators, a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal; Another oscillator included in the oscillator group includes a first vibrator, a first integrated circuit device that causes the first vibrator to oscillate, and a first container that accommodates the first vibrator and the first integrated circuit device; the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, but does not include a PLL circuit; The first container and the second container are the same type of container.

[0179] This oscillator houses a second resonator and a second integrated circuit device having a PLL circuit in a second container, while other oscillators in the oscillator group house a first resonator and a first integrated circuit device not having a PLL circuit in a first container, so the two oscillators have different functions related to output frequency. Furthermore, because the first container and the second container are the same type of container, the development of this oscillator or other oscillators does not require labor hours for setting mounting conditions or labor hours for container design, and multiple types of oscillators can be manufactured efficiently at low cost. [Explanation of symbols]

[0180] 1...oscillator group, 2a...first oscillator, 2b...second oscillator, 3a...first container, 3b...second container, 4a...first integrated circuit device, 4b...second integrated circuit device, 5a...first vibrator, 5b...second vibrator, 6a...first lid, 6b...second lid, 7...accommodation space, 8...external terminal, 31...substrate, 31a...first surface of substrate, 31b...second surface of substrate, 32...first frame substrate Plate, 32a...first surface of first frame substrate, 32b...second surface of first frame substrate, 33...second frame substrate, 41, 42, 43, 44, 45, 46...electrodes, 55, 56...terminals, 75, 76...electrodes, 61, 62, 63...bonding members, 100...semiconductor substrate, 100a, 100b, 100c, 100d...edges of semiconductor substrate, 110...bias circuit, 111...bandgap reference circuit , 112... operational amplifier, 113... resistance element, 114... capacitance element, 115... MOS transistor, 116... resistance element, 117... resistance element, 120... oscillation circuit, 121... MOS transistor, 122... MOS transistor, 123... MOS transistor, 124... bipolar transistor, 125... variable capacitance element, 126... variable capacitance element, 127... current source, 128... amplifier circuit, 130... temperature compensation circuit, 131... temperature sensor , 132...0th-order component generating circuit, 133...1st-order component generating circuit, 134...higher-order component generating circuit, 135...I / V conversion circuit, 136...RC low-pass filter, 137...resistive element, 138...capacitive element, 140...output circuit, 141...waveform shaping buffer, 142...frequency divider circuit, 143...pre-buffer, 144...output buffer, 150...logic circuit, 160...non-volatile memory, 181, 182, 183, 184, 185, 186...pad , 200... semiconductor substrate, 200a, 200b, 200c, 200d... edges of semiconductor substrate, 210... bias circuit, 220... oscillation circuit, 221... MOS transistor, 222... MOS transistor, 223... MOS transistor, 224... bipolar transistor, 225... variable capacitance element, 226... variable capacitance element, 227... current source, 228... amplifier circuit, 230... temperature compensation circuit, 231... temperature sensor, 232... zeroth-order component generating circuit circuit, 233...first-order component generating circuit, 234...third-order component generating circuit, 235...I / V conversion circuit, 240...PLL circuit, 241...phase comparator, 242...charge pump, 243...low-pass filter, 244...voltage-controlled oscillator circuit, 245...waveform shaping circuit, 246...frequency divider circuit, 247...delta-sigma modulation circuit, 250...output circuit, 260...logic circuit, 270...non-volatile memory, 281, 282, 283, 284, 285, 286...pads

Claims

1. A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, comprising: manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, and a first temperature compensation circuit that outputs a first temperature compensation signal that compensates for the frequency temperature characteristic of the first oscillation signal, but does not include a PLL circuit; the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal, the first container and the second container are the same type of container, the first integrated circuit device and the second integrated circuit device are the same size; A method for manufacturing an oscillator, wherein the PLL circuit is arranged in at least a portion of a second area of ​​the second integrated circuit device corresponding to a first area of ​​the first integrated circuit device in which the first temperature compensation circuit is arranged.

2. In claim 1, The method for manufacturing an oscillator, wherein the first temperature compensation circuit includes an RC low-pass filter that reduces noise included in the first temperature compensation signal.

3. In claim 1 or 2, the second integrated circuit device includes a second temperature compensation circuit that outputs a second temperature compensation signal that compensates for the frequency temperature characteristic of the second oscillation signal; the size of the second temperature compensation circuit is smaller than the size of the first temperature compensation circuit; The method for manufacturing an oscillator, wherein the PLL circuit and the second temperature compensation circuit are disposed in at least a portion of the second region.

4. In any one of claims 1 to 3, the first integrated circuit device is capable of setting whether or not to operate the first temperature compensation circuit; A method for manufacturing an oscillator, wherein manufacturing the first oscillator includes setting whether or not the first temperature compensation circuit is to be operated.

5. In any one of claims 1 to 4, the first oscillation circuit includes a first amplifier circuit that amplifies a signal from the first vibrator and outputs the first oscillation signal, and a first current source that has a first transistor and supplies a first current to the first amplifier circuit; the second oscillation circuit includes a second amplifier circuit that amplifies a signal from the second vibrator and outputs the second oscillation signal, and a second current source that has a second transistor that supplies a second current to the second amplifier circuit; A method for manufacturing an oscillator, wherein the size of the first transistor is larger than the size of the second transistor.

6. A method for manufacturing a plurality of types of oscillators including a first oscillator and a second oscillator, comprising: manufacturing the first oscillator by housing a first resonator and a first integrated circuit device that causes the first resonator to oscillate in a first container; and manufacturing the second oscillator by housing a second vibrator and a second integrated circuit device that causes the second vibrator to oscillate in a second container; the first integrated circuit device includes a first oscillation circuit that causes the first oscillator to oscillate and outputs a first oscillation signal, but does not include a PLL circuit; the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal, the first container and the second container are the same type of container, the first oscillation circuit includes a first amplifier circuit that amplifies a signal from the first vibrator and outputs the first oscillation signal, and a first current source that has a first transistor and supplies a first current to the first amplifier circuit; the second oscillation circuit includes a second amplifier circuit that amplifies a signal from the second vibrator and outputs the second oscillation signal, and a second current source that has a second transistor that supplies a second current to the second amplifier circuit; A method for manufacturing an oscillator, wherein the size of the first transistor is larger than the size of the second transistor.

7. In any one of claims 1 to 6, N is an integer equal to or greater than 2, The first container is provided with first to N-th electrodes, The second container is provided with N+1 to 2N electrodes, the first integrated circuit device has first to Nth pads; the second integrated circuit device has pads (N+1) to (2N); For each integer i greater than or equal to 1 and less than or equal to N, the shape of the i-th electrode and the shape of the N+i-th electrode are the same, and the position of the i-th electrode in the first container and the position of the N+i-th electrode in the second container are the same; manufacturing the first oscillator includes connecting the first to Nth pads to the first to Nth electrodes, respectively; The method for manufacturing an oscillator, wherein manufacturing the second oscillator includes connecting the (N+1)th to 2Nth pads to the (N+1)th to 2Nth electrodes, respectively.

8. In claim 7, A method for manufacturing an oscillator, wherein for each integer i, the position of the i-th pad on the first integrated circuit device is the same as the position of the N+i-th pad on the second integrated circuit device.

9. In any one of claims 1 to 8, the second integrated circuit device is capable of setting the operation of the PLL circuit to an integer PLL system or a fractional PLL system; A method for manufacturing an oscillator, wherein manufacturing the second oscillator includes setting the operation of the PLL circuit to the integer PLL method or the fractional PLL method.

10. An oscillator group consisting of multiple types of oscillators including a first oscillator and a second oscillator, The first oscillator comprises: a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with the first integrated circuit device includes a first oscillation circuit that oscillates the first oscillator to output a first oscillation signal, and a first temperature compensation circuit that outputs a first temperature compensation signal that compensates for the frequency temperature characteristic of the first oscillation signal, but does not include a PLL circuit; The second oscillator comprises: a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal, the first container and the second container are the same type of container, the first integrated circuit device and the second integrated circuit device are the same size; An oscillator group, wherein the PLL circuit is arranged in at least a part of a second region of the second integrated circuit device corresponding to a first region of the first integrated circuit device in which the first temperature compensation circuit is arranged.

11. An oscillator group consisting of multiple types of oscillators including a first oscillator and a second oscillator, The first oscillator comprises: a first oscillator; a first integrated circuit device that causes the first vibrator to oscillate; a first container that houses the first vibrator and the first integrated circuit device; Equipped with the first integrated circuit device includes a first oscillation circuit that causes the first oscillator to oscillate and outputs a first oscillation signal, but does not include a PLL circuit; The second oscillator comprises: a second oscillator; and a second integrated circuit device that causes the second vibrator to oscillate; a second container that houses the second vibrator and the second integrated circuit device; Equipped with the second integrated circuit device includes a second oscillation circuit that oscillates the second oscillator to output a second oscillation signal, and a PLL circuit that receives the second oscillation signal and outputs a third oscillation signal, the first container and the second container are the same type of container, the first oscillation circuit includes a first amplifier circuit that amplifies a signal from the first vibrator and outputs the first oscillation signal, and a first current source that has a first transistor and supplies a first current to the first amplifier circuit; the second oscillation circuit includes a second amplifier circuit that amplifies a signal from the second vibrator and outputs the second oscillation signal, and a second current source that has a second transistor that supplies a second current to the second amplifier circuit; The oscillator group, wherein the size of the first transistor is greater than the size of the second transistor.

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