Power transistor controller and control method

Abstract

This controller 200 controls a plurality of power transistors M1 to MN provided on a plurality of parallel paths. A correction amount calculation unit 230 generates reference values on the basis of a plurality of detection values Sdet1 to SdetN correlated to the switching losses of the respective plurality of power transistors M1 to MN and generates a plurality of correction amounts Scomp1 to ScompN so that the plurality of detection values Sdet1 to SdetN approach the reference values. A gate signal generation unit 240 generates a plurality of gate signals Vg1 to VgN on the basis of a control command Sctrl and the plurality of correction amounts Scomp1 to ScompN.

Description

[Technical Field]

[0001] The present disclosure relates to a technology for driving a power transistor. [Background technology]

[0002] Hybrid cars, electric vehicles, and industrial machinery use power conversion devices such as DC / DC converters, AC / DC converters, and DC / AC converters (inverters). A power conversion device has, as its basic components, power transistors such as IGBTs (Insulated Gate Bipolar Transistors) and FETs, and their drive circuits.

[0003] Figures 1(a) and (b) are diagrams explaining the loss of a power transistor. The first row of Figure 1(b) shows the gate-source voltage Vgs, and the second row shows the drain-source voltage Vds and the drain current Ids. The third row shows the loss equivalent to the product of the drain voltage Vds and the drain current Ids. The drain current during the on-period is Ids (ON) , drain voltage Vds (ON) During the off period, the drain current is zero and the drain voltage is Vds (OFF) Let's say.

[0004] Power transistors have large losses, which can be divided into conduction loss Pon and switching loss Psw. Conduction loss Pon is the loss during the on-time of the power transistor. Note that the switching loss here does not include the charge / discharge loss that occurs when the power transistor gate is driven.

[0005] The switching loss Psw is calculated during the turn-on period T R , turn-off period T F The switching loss is expressed by equation (1). Psw={(Vds (OFF) ×Ids (ON)} / (T R +T F )×fSW …(1) f SW is the switching frequency.

[0006] In high-power applications, multiple power transistors are connected in parallel and used. When multiple power transistors are paralleled, due to the variation in the characteristics (threshold values) of individual devices, a bias occurs in the switching loss. Figures 2(a) and (b) are diagrams for explaining the loss in a parallel connection circuit of two power transistors.

[0007] As shown in Fig. 2(a), the gates, drains, and sources of the two transistors M1 and M2 are commonly connected, the gate voltages Vgs1 and Vgs2 are equal, and the drain voltages Vds1 and Vds2 are equal.

[0008] Fig. 2(b) shows the switching losses of two power transistors M1 and M2. Assume that there is a variation in the threshold values Vth1 and Vth2, and Vth1 < Vth2. In this case, relatively more current flows through the power transistor M1, and the switching loss of the transistor M1 becomes larger than the switching loss of the transistor M2.

[0009] The power transistor with a large switching loss has a relatively higher temperature compared to the small power transistor. This is called a hot spot. Since the threshold value Vth of the power transistor has a negative temperature characteristic, the threshold value Vth1 of the power transistor M1 located at the hot spot becomes even lower, and more drain current Ids1 flows, causing further heat generation.

[0010] Hot spots cause thermal runaway or are the cause of aging deterioration and reliability degradation. Also, the increase in switching loss reduces the efficiency of the system. As a countermeasure, attaching a large heat sink has the problem of increasing the size of the device.

Prior Art Documents

Non-Patent Documents

[0011] [Non-Patent Document 1] J. A. Butron Ccoa, B. Strauss, G. Mitic and A. Lindemann, "Investigation of Temperature Sensitive Electrical Parameters for Power Semiconductors (IGBT) in Real-Time Applications", PCIM Europe 2014; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2014, pp. 1-9. [Non-Patent Document 2] M. A. Eleffendi and C. M. Johnson, "Evaluation of on-state voltage VCE(ON) and threshold voltage Vth for real-time health monitoring of IGBT power modules", 2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe), Geneva, 2015, pp. 1-10 [Non-Patent Document 3] H. Chen, B. Ji, V. Pickert and W. Cao, "Real-Time Temperature Estimation for Power MOSFETs Considering Thermal Aging Effects", IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, pp. 220-228, March 2014 [Non-patent document 4] K. Miyazaki, Y. Lo, AKM Mahfuzul Islam, K. Hata, M. Takamiya and T. Sakurai, "CNN-based Approach for Estimating Degradation of Power Devices by Gate Waveform Monitoring", 2019 International Conference on IC Design and Technology (ICICDT), SUZHOU, China, 2019, pp. 1-4 Summary of the Invention [Problem to be solved by the invention]

[0012] The present disclosure has been made in light of such a situation, and one of its exemplary purposes is to provide a drive circuit that uniformly operates a plurality of power transistors provided on a plurality of parallel paths. [Means for solving the problem]

[0013] An aspect of the present disclosure relates to a controller for controlling multiple power transistors provided on multiple parallel paths, the controller including: a correction amount calculation unit that generates a reference value based on multiple detection values ​​correlated with the switching losses of the multiple power transistors, and generates multiple correction amounts so that the multiple detection values ​​approach the reference value; and a gate signal generation unit that generates multiple gate signals corresponding to the multiple power transistors based on a control command and the multiple correction amounts.

[0014] One aspect of the present disclosure is a controller for use in a power conversion device including multiple power transistors arranged on multiple parallel paths, the controller including: a main controller that calculates a duty cycle command value of a control pulse so that a state of the power conversion device approaches a target state; an A / D converter that converts multiple electrical signals correlated with the switching losses of the multiple power transistors into multiple digital detection values; a correction amount calculation unit that generates a reference value based on the multiple detection values ​​and generates multiple correction amounts so that the multiple detection values ​​approach the reference value; a duty cycle correction unit that corrects the duty cycle command value based on the multiple correction amounts to generate multiple corrected duty cycle command values; and a pulse converter that receives the multiple corrected duty cycle command values ​​and generates multiple gate signals corresponding to the multiple power transistors.

[0015] One aspect of the present disclosure is a controller for use in a power conversion device including multiple power transistors arranged on multiple parallel paths, the controller including: a main controller that calculates a duty cycle command value for a control pulse so that a state of the power conversion device approaches a target state; an A / D converter that converts multiple electrical signals correlated with the switching losses of each of the multiple power transistors into multiple digital detection values; a correction amount calculation unit that generates a reference value based on the multiple detection values ​​and generates multiple correction amounts so that the multiple detection values ​​approach the reference value; a pulse converter that generates a control pulse having a duty cycle corresponding to the duty cycle command value; and a gate signal generation unit that receives the control pulse and the multiple correction amounts and generates multiple gate signals each having a slew rate corresponding to a corresponding one of the multiple correction amounts.

[0016] Any combination of the above components or mutual substitution of the components or expressions of the present disclosure between methods, devices, systems, etc. are also valid aspects of the present disclosure. [Effects of the Invention]

[0017] According to an aspect of the present disclosure, a plurality of power transistors can be operated uniformly. [Brief explanation of the drawings]

[0018] [Figure 1] 1(a) and 1(b) are diagrams illustrating losses in a power transistor. [Figure 2] 2(a) and 2(b) are diagrams for explaining losses in a parallel-connected circuit of two power transistors. [Figure 3] FIG. 2 is a block diagram of a switching circuit according to an embodiment. [Figure 4] 4(a) and 4(b) are waveform diagrams illustrating pulse width correction. [Figure 5] 5(a) and 5(b) are waveform diagrams illustrating slew rate correction. [Figure 6] FIG. 6 is a block diagram of a switching circuit according to one embodiment. [Figure 7] FIG. 7 is a block diagram illustrating an example of the configuration of the loss calculating unit. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of the correction amount calculation unit. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of a filter. [Figure 10] FIG. 10 is a circuit diagram of a gate driver with a slew rate correction function. [Figure 11] FIG. 11 is a diagram illustrating the operation of the gate driver with a slew rate correction function shown in FIG. [Figure 12] FIG. 12 is a circuit diagram of a DC / DC converter. [Figure 13] FIG. 13 is a circuit diagram of a DC / DC converter. [Figure 14] FIG. 14 is a circuit diagram of a DC / DC converter. DETAILED DESCRIPTION OF THE INVENTION

[0019] (Outline of the embodiment) A controller according to one embodiment controls a plurality of power transistors provided on a plurality of parallel paths, and includes: a correction amount calculation unit that generates a reference value based on a plurality of detection values ​​correlated with the switching losses of the plurality of power transistors, and generates a plurality of correction amounts so that the plurality of detection values ​​approach the reference value; and a gate signal generation unit that generates a plurality of gate signals corresponding to the plurality of power transistors based on a control command and the plurality of correction amounts.

[0020] With this configuration, feedback is applied so that the switching loss of each of the multiple power transistors approaches a common target value, resulting in the temperature of the multiple power transistors being equalized. This suppresses hot spots and is expected to improve reliability and efficiency. In addition, since a large heat sink is no longer necessary, the device can be made more compact.

[0021] In one embodiment, the gate signal generator may correct the pulse width of the gate signal for each of the plurality of power transistors based on one of a plurality of corresponding correction amounts. Widening the pulse width of the gate signal for a power transistor increases the switching loss, while narrowing the pulse width decreases the switching loss. Therefore, by using the pulse width as the feedback control amount, the switching loss can be equalized.

[0022] In one embodiment, the gate signal generator may correct the slew rate of each of the gate signals of the plurality of power transistors based on one of the corresponding correction amounts. If the slew rate (slope) of the edge corresponding to the turn-on of a gate signal of a power transistor is relatively increased (i.e., if the transition time is shortened), or if the slew rate (slope) of the edge corresponding to the turn-off is relatively decreased (i.e., if the transition time is lengthened), the switching loss increases. Conversely, if the slew rate (slope) of the edge corresponding to the turn-on is relatively decreased, or if the slew rate (slope) of the edge corresponding to the turn-off is relatively increased, the switching loss decreases. Therefore, by using the slew rate as a feedback control amount, the switching loss can be equalized.

[0023] In one embodiment, slew rate (transition time) correction and pulse width correction may be used in combination.

[0024] In one embodiment, the detected value for calculating the correction amount may be a detected temperature value indicating the temperature of the power transistor. Since the temperature of the power transistor has a positive correlation with the switching loss, the switching loss can be estimated by monitoring the temperature. For example, a temperature sensor such as a thermistor or diode may be disposed near the power transistor to detect the temperature.

[0025] In one embodiment, the threshold voltage at which the power transistor switches on and off may be used as the detection value for calculating the correction amount.

[0026] In one embodiment, the controller may further include a waveform acquisition unit that measures a waveform of a gate voltage of each of the plurality of power transistors, and a temperature estimator that generates one of a plurality of detection values ​​corresponding to the waveform of the gate voltage of each of the plurality of power transistors. With this configuration, it is possible to estimate the temperature from the waveform of the gate voltage.

[0027] In one embodiment, the temperature estimator may include an estimator based on a trained model obtained by machine learning.

[0028] In one embodiment, the detection value may be based on the product of a measured drain current and a measured drain-source voltage of the power transistor.

[0029] In one embodiment, the correction amount calculation unit may include a plurality of PID (proportional-integral-derivative) compensators.

[0030] In one embodiment, the correction amount calculation unit may include a plurality of first multipliers that multiply outputs of the plurality of PID compensators by first coefficients to generate a plurality of first correction amounts, and a plurality of second multipliers that multiply outputs of the plurality of PID compensators by second coefficients to generate a plurality of second correction amounts. The correction processing unit may correct a slew rate of a gate signal of each of the plurality of power transistors based on a corresponding one of the plurality of first correction amounts, and may correct a pulse width of a gate signal of each of the plurality of power transistors based on a corresponding one of the plurality of second correction amounts.

[0031] In one embodiment, the gate signal generating unit may include a plurality of gate drivers corresponding to the plurality of power transistors, each of the plurality of gate drivers including an output node connected to a gate of the corresponding power transistor, a multi-stage delay circuit that delays a control pulse, a plurality of first transistors, each having one end connected to a first voltage line and the other end connected to the output node, a plurality of second transistors, each having one end connected to a second voltage line and the other end connected to the output node, a plurality of first logic gates corresponding to the plurality of first transistors, each supplying a corresponding output of the multi-stage delay circuit to a gate of the corresponding first transistor when a corresponding bit of a first control code has a predetermined value, and a plurality of second logic gates corresponding to the plurality of second transistors, each supplying a corresponding output of the multi-stage delay circuit to a gate of the corresponding second transistor when a corresponding bit of a second control code has a predetermined value.

[0032] In one embodiment, the controller may further include a monitoring circuit that generates a warning flag based on the plurality of correction amounts, thereby increasing the reliability of the system.

[0033] In one embodiment, the controller may further include an A / D converter that converts a plurality of detection signals correlated with the switching losses of each of the plurality of power transistors into a plurality of detection values.

[0034] In one embodiment, the power transistors may be switching transistors or synchronous rectifier transistors of a switching converter.

[0035] In one embodiment, the switching converter is a multi-phase type, and the controller may output gate signals to the plurality of power transistors with a phase difference of 360° / N (N≧2).

[0036] In one embodiment, the multiple power transistors may form an upper arm or a lower arm of an inverter.

[0037] (Embodiment) The present disclosure will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the disclosure, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure.

[0038] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0039] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0040] Furthermore, "signal A (voltage, current) corresponds to signal B (voltage, current)" means that signal A has a correlation with signal B, and specifically means (i) when signal A is signal B, (ii) when signal A is proportional to signal B, (iii) when signal A is obtained by level-shifting signal B, (iv) when signal A is obtained by amplifying signal B, (v) when signal A is obtained by inverting signal B, (vi) or any combination thereof. Those skilled in the art will understand that the scope of "corresponding to" is determined depending on the type and application of signals A and B.

[0041] In this specification, the symbols attached to electrical signals such as voltage signals and current signals, or to circuit elements such as resistors and capacitors, represent the respective voltage values, current values, resistance values, or capacitance values ​​as necessary. Furthermore, the symbols attached to terminals represent the voltage or signal level generated thereat.

[0042] 3 is a block diagram of a switching circuit 100 according to an embodiment. The switching circuit 100 is a part of a power conversion device such as an inverter or a converter, and includes a power stage 110 and a controller 200.

[0043] The power stage 110 includes a plurality of N (N≧2) power transistors M1 to M2, each having an independent control terminal (gate). N A plurality of power transistors M1 to M N are provided on a plurality of parallel paths, and it is expected that an equal current flows through the plurality of paths.

[0044] Power transistors M1 to M N The transistors may be FETs (Field-Effect Transistors) such as Si, SiC, or GaN, or may be IGBTs (Insulated Gate Bipolar Transistors).

[0045] The controller 200 uses the electrical state of the switching circuit 100 or a load (not shown) as a control variable and drives the power stage 110 so that the control variable approaches a target state. The electrical state of the switching circuit 100 may include the output power, output voltage, output current, input current of the switching circuit 100 itself, or the current flowing through the load, the voltage of a node in the load, the power consumption of the load, etc.

[0046] The controller 200 includes a main controller 210, a loss acquisition unit 220, a correction amount calculation unit 230, and a gate signal generation unit 240. The controller 200 can be configured as an analog circuit, a digital circuit, or an analog-digital mixed circuit.

[0047] The main controller 210 generates a control command Sctrl so that the controlled variable approaches the target variable. For example, the control command Sctrl is N This signal indicates the length of the on-time, in other words, the duty cycle.

[0048] When the main controller 210 is configured as a digital circuit, it includes an error detector (adder / subtractor) that detects the error between the controlled variable and the target variable, and a filter that generates a control command Sctrl according to the error. The type of filter is designed according to the characteristics of the power stage 110 and the load, and a P (proportional compensator), PI (proportional-integral) compensator, PID (proportional-integral-derivative) compensator, etc. is used.

[0049] When the main controller 210 is configured with an analog circuit, it includes an error amplifier that amplifies the error between the controlled variable and the target variable.

[0050] The loss calculation unit 220 calculates the loss of the power transistors M1 to M N Multiple detection values ​​Sdet1 to Sdet that are correlated with each switching loss N The configuration of the loss acquisition unit 220 is not particularly limited, and it is sufficient if it can directly or indirectly measure or estimate the temperature or power loss of the power transistor.

[0051] For example, the detected value Sdet i (i=1,2,…N) is the corresponding power transistor M i The loss acquisition unit 220 is the temperature of the power transistor M i The temperature sensor may be disposed near the temperature sensor and generate a temperature detection signal.

[0052] Or the detected value Sdet i is the power transistor M i In this case, the loss acquisition unit 220 may acquire the switching loss of the power transistor M i The voltage detection signal indicating the voltage between both ends (drain-source voltage) of the power transistor M iThe loss acquisition unit 220 is configured to be able to generate a current detection signal indicating the drain current of the power supply. Examples of current detection methods include those using a Hall sensor, a Rogowski coil, a current transformer, and a current detection resistor (shunt resistor). The loss acquisition unit 220 calculates a detection value Sdet indicating the switching loss based on equation (1). i may be generated.

[0053] When the correction amount calculation unit 230 and the gate signal generation unit 240 are configured with digital circuits, the loss calculation unit 220 further includes an A / D converter that converts the electrical signal into a digital value.

[0054] The correction amount calculation unit 230 calculates the correction amount for the plurality of power transistors M1 to M N Multiple detection values ​​Sdet1 to Sdet indicating switching loss N A reference value Sref is generated based on the detected values ​​Sdet1 to Sdet N Multiple correction amounts Scomp1 to Scomp are calculated so that each approaches the reference value Sref. N Here, the reference value Sref is generated by dividing the detected values ​​Sdet1 to Sdet N The absolute value of the required correction amount can be minimized by using the detected value that is the center value as the reference value Sref, which is calculated from the relative error of the above.

[0055] The gate signal generator 240 generates a control command Sctrl and a plurality of correction amounts Scomp1 to Scomp N Based on this, multiple gate signals Vg1 to Vg N A plurality of gate signals Vg1 to Vg N have common characteristics (pulse width, slew rate), but each gate signal Vg i The characteristics of the multiple correction amounts Scomp1 to Scomp N One of the corresponding Scomp i It has been corrected based on

[0056] Specifically, the gate signal generating unit 240 generates a plurality of gate signals Vg1 to Vg NAt least one of the pulse width and the slew rate (transition time) is corrected.

[0057] 1. Pulse width correction When only the pulse width is corrected, each correction amount Scomp i includes the pulse width correction amount ΔTon i The pulse width Ton i of each gate signal Vg i is Ton i = Tonref + ΔTon i where Tonref is the pulse width before correction determined according to the control command Sctrl.

[0058] 2. Slew rate correction When only the slew rate is corrected, the correction amount Scomp includes the slew rate correction amounts ΔTr and ΔTf. ΔTr is the correction amount of the transition time of the rising edge (positive edge, leading edge) of the gate signal, and ΔTf is the correction amount of the transition time of the falling edge (negative edge, trailing edge) of the gate signal. The slew rate correction amounts ΔTr and ΔTf are collectively referred to as ΔTsr.

[0059] 3. Pulse width correction and slew rate correction When both the pulse width and the slew rate are corrected, the correction amount Scomp i includes the pulse width correction amount ΔTon i and the slew rate correction amount ΔTsr.

[0060] The above is the basic configuration of the switching circuit 100. Subsequently, its operation will be described.

[0061] (Pulse width correction) Figs. 4(a) and (b) are waveform diagrams for explaining pulse width correction. Here, two power transistors M1 and M2 are considered, and the case where Vth1 < Vth2 is explained. Fig. 4(a) shows the operation without correction, and as shown in Fig. 2(b), Psw1 > Psw2.

[0062] Figure 4(b) shows the gate signals Vg1 and Vg2 of the power transistors M1 and M2 when pulse width correction is performed. The pulse width Ton2 of the gate signal Vg2 is corrected to be longer than the pulse width Ton1 of the gate signal Vg1.

[0063] By this pulse width correction, the switching losses Psw1 and Psw2 of the two power transistors M1 and M2 approach each other, and the heat generation amounts become equal.

[0064] (Through - rate correction) Figures 5(a) and (b) are waveform diagrams for explaining through - rate correction. Here, two power transistors M1 and M2 are considered, and the case where Vth1 < Vth2 is explained. Figure 5(a) shows the operation without correction, and as shown in Figure 2(b), Psw1 > Psw2.

[0065] Figure 5(b) shows the gate signals Vg1 and Vg2 of the power transistors M1 and M2 when through - rate correction is performed. When the power transistors M1 and M2 are N - channel, the positive edge corresponds to turn - on and the negative edge corresponds to turn - off. The through - rate of the positive edge of the gate signal Vg2 is corrected to be relatively higher than the through - rate of the gate signal Vg1. In other words, the transition time Tr2 of the gate signal Vg2 is corrected to be shorter than the transition time Tr1 of the gate signal Vg1. Tr2 > Tr1

[0066] Also, the through - rate of the negative edge of the gate signal Vg2 is corrected to be relatively lower than the through - rate of the gate signal Vg1. In other words, the transition time Tf2 of the gate signal Vg2 is corrected to be longer than the transition time Tf1 of the gate signal Vg1. Tf2 > Tf1

[0067] By this through - rate correction, the switching losses Psw1 and Psw2 of the two power transistors M1 and M2 approach each other, and the heat generation amounts become equal.

[0068] The above is the operation of the switching circuit 100. With this switching circuit 100, the heat generation amounts of multiple power transistors can be made similar. This prevents current from concentrating on a specific power transistor, protecting the circuit. Furthermore, because multiple power transistors operate evenly, the capabilities of the multiple power transistors can be utilized, improving efficiency.

[0069] Furthermore, when current is concentrated in a power transistor, the deterioration of that transistor progresses rapidly over time. However, according to this embodiment, the deterioration of multiple power transistors over time can be slowed down, and the life of the switching circuit 100 can be extended.

[0070] 3, the main controller 210 and the gate signal generating unit 240 are integrated into the same IC, but this is not limited thereto, and the main controller 210 and the gate signal generating unit 240 may be separate ICs. In this case, the loss calculating unit 220 and the correction amount calculating unit 230 may be integrated into the same IC (gate drive circuit) as the gate signal generating unit 240.

[0071] The pulse width correction or slew rate correction described above targets both the positive and negative edges of the gate signal, but may target only one edge.

[0072] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 3 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the disclosure.

[0073] A specific configuration of the switching circuit 100 will be described below.

[0074] 6 is a block diagram of a switching circuit 100A according to one embodiment. In this switching circuit 100A, a controller 200A is configured as a digital circuit and is configured to be able to correct both the pulse width and the slew rate.

[0075] The loss acquisition unit 220 includes a sensor group 222 and an A / D converter 224. The sensor group 222 is a N The A / D converter 224 converts the electrical signals into digital detection values ​​Sdet1 to Sdet N Convert to.

[0076] The correction amount calculation unit 230 calculates the plurality of detection values ​​Sdet1 to Sdet N The correction values ​​Scomp1 to Scomp are set so that each approaches the common target value Sref. N In this embodiment, the correction value Scomp i is the pulse width correction value ΔTon i and the slew rate correction value ΔTsr i Includes.

[0077] The gate signal generating unit 240 includes an adder 242, a digital PWM circuit 244, and a gate driving circuit 246. The adder 242 adds a pulse width command value Tonref indicated by a control command Sctrl generated by the main controller 210 to a pulse width correction value ΔTon i The corrected pulse width command value Ton is added to i Generate. Ton i =Tonref+ΔTon i

[0078] The digital PWM circuit 244 outputs digital pulse width command values ​​Ton1 to Ton N and outputs PWM signals Spwm1 to Spwm2 having a predetermined period and a pulse width (duty cycle) according to the pulse width command value. NThe digital PWM circuit 244 may have any configuration and may use any known technology. Examples of the digital PWM circuit 244 include a system using a counter that counts the on-time, a system using a variable delay circuit, and a system using a phase interpolator.

[0079] The gate drive circuit 246 includes a plurality of gate drivers GD1 to GD N Includes multiple gate drivers GD1 to GD N The i-th (i=1, 2...N) gate driver GD i The gate signal Vg i is the slew rate correction amount ΔTsr i The slope changes according to the

[0080] FIG. 7 is a block diagram showing an example of the configuration of the loss acquisition unit 220. Here, a configuration where N=5 is shown, but N is not limited to this. The channels corresponding to the power transistors M1 to M5 are denoted as Ch0 to Ch4. The loss acquisition unit 220 includes a waveform acquisition unit 226 and a temperature estimator 228. The waveform acquisition unit 226 includes an analog multiplexer 223 and an A / D converter 224. The analog multiplexer 223 outputs the waveforms corresponding to the plurality of power transistors M1 to M5. N Gate signals Vg1 to Vg N The A / D converter 224 selects each of the k-th (k=1, 2...N) gate signals Vg k Converts digital waveform data to WAV format k It is also possible to omit the analog multiplexer 223 and provide an A / D converter 224 for each power transistor.

[0081] The temperature estimator 228 receives waveform data WAV k Based on this, the corresponding power transistor M k The temperature of the detected value Sdet kThe temperature estimator 228 can be configured by machine learning. Specifically, the relationship between the gate voltage waveform of the power transistor and the temperature is measured offline, and a trained model is formed by machine learning, with the waveform as input and the temperature as output. The temperature estimator 228 is implemented based on the trained model. This method eliminates the need for a temperature sensor or a current sensor, thereby simplifying the configuration.

[0082] The threshold voltage of a power transistor can also be used as a detection value indicating the switching loss of the power transistor. For example, when a power transistor switches, its gate voltage is at a constant level near the threshold voltage due to the Miller effect. Therefore, the threshold voltage can be detected by detecting the gate voltage at a constant level. Other specific methods include similar methods such as those shown in Non-Patent Documents 1 to 3, and known techniques such as Non-Patent Document 4, which uses machine learning.

[0083] 8 is a block diagram showing an example of the configuration of the correction amount calculation unit 230. The correction amount calculation unit 230 includes a reference value generation unit 232, a plurality of adder-subtractors 234_1 to 234_N, and a plurality of filters 236_1 to 236_N. The reference value generation unit 232 calculates a plurality of detection values ​​Sdet1 to Sdet N For example, the reference value generating unit 232 generates a reference value Sref based on a plurality of detection values ​​Sdet1 to Sdet N The maximum value of the detected values ​​Sdet1 to Sdet2 may be used as the reference value Sref. N The center value of the detection values ​​Sdet1 to Sdet2 may be used as the reference value Sref. N The average value of the detected values ​​Sdet1 to Sdet2 may be used as the reference value Sref. N The minimum value of may be set as the reference value Sref.

[0084] Each adder / subtractor 234_i calculates the corresponding detection value Sdet i and the error e of the reference value Sref i The filter 236_i outputs the error e i Based on this, the correction amount ΔToni and ΔTsr i Generate.

[0085] FIG. 9 is a block diagram showing an example of the configuration of the filter 236_i. The filter 236_i includes a PID (proportional-integral-derivative) compensator 250. Considering the response speed and stability of the temperature control feedback loop, PID control is optimal. Specifically, the PID compensator 250 includes a proportional term calculation unit 252, an integral term calculation unit 254, a derivative term calculation unit 256, an adder 258, and multipliers 260 and 262. The proportional term calculation unit 252 calculates Kp·e i (t), where Kp is the proportional gain. The integral term calculation unit 254 calculates the proportional term Ki / Ti·∫e i (t)dt, where Ki is the integral gain and Ti is the integral time. The differential term calculation unit 256 calculates Kd / Td·de i The differential term, which is (t) / dt, is calculated, where Kd is the differential gain and Td is the differential time. An adder 258 adds the proportional term, integral term, and differential term.

[0086] The first multiplier 260 multiplies the output of the PID compensator 250 by a first coefficient Ksr to obtain a slew rate correction amount ΔTsr i The second multiplier 262 multiplies the output of the PID compensator 250 by a second coefficient Kpw to generate a second correction amount ΔTon i Generate.

[0087] In this example, the PID compensator 250 is shared between the pulse width correction and the slew rate correction, but this is not limited to this, and a compensator for pulse width correction and a compensator for slew rate correction may be provided separately. In this case, the coefficients Kp, Ki, and Kd can be set separately for the pulse width correction and the slew rate correction.

[0088] Next, a specific example of slew rate correction and pulse width correction will be described.

[0089] Figure 10 shows a gate driver GD # (#=1,2...N) Gate driver GD #The input node IN of the # is input, and the output node OUT is connected to the corresponding power transistor M # This gate driver GD # A first control code corresponding to the slew rate correction amount ΔTr and a second control code corresponding to the slew rate correction amount ΔTf are input to the slew rate correction amount ΔTr. Each of the first control code ΔTr and the second control code ΔTf is m bits long.

[0090] The multi-stage delay circuit 270 generates the control pulse Spwm # The multi-stage delay circuit 270 outputs a plurality of control pulses before or after delay.

[0091] A plurality of first transistors MP1 to MP m are P-channel MOS transistors, each having one end (source) connected to the first voltage line and the other end (drain) connected to the output node OUT. m are N-channel MOS transistors, one end (source) of each of which is connected to the second voltage line, and the other end (drain) of each of which is connected to the output node OUT.

[0092] A plurality of first logic gates GP1 to GP m is a NAND gate. The jth (j=1, 2, ...M) first logic gate GP j When the corresponding bit of the first control code ΔTr is a predetermined value (true, for example, 1), the corresponding output of the multi-stage delay circuit 270 is transmitted to the corresponding first transistor MP j The j-th first logic gate GP j When the corresponding bit of the first control code ΔTr is not a predetermined value (false, for example, 0), it outputs high, and the corresponding first transistor MP j Fixed off.

[0093] A plurality of second logic gates GN1 to GN m is a NOR gate. The j-th second logic gate GNj When the corresponding bit of the first control code ΔTr is a predetermined value (for example, 1), the corresponding output of the multi-stage delay circuit 270 is transmitted to the corresponding second transistor MN j The j-th second logic gate GN j When the corresponding bit of the second control code ΔTf is not a predetermined value (false, for example, 0), the corresponding second transistor MN j Fixed off.

[0094] Figure 11 shows the gate driver GD10 with slew rate compensation function. # The first control code ΔTr and the second control code ΔTf are shown as relative values ​​corresponding to a reference value. # Gate signal Vg # The slew rate (slope) of the positive edge can be made steeper or gentler by increasing or decreasing the first control code ΔTr from a reference value.

[0095] Similarly, the gate driver GD # Gate signal Vg # The slew rate of the negative edge can be made steeper or slower by increasing or decreasing the second control code ΔTf from the reference value.

[0096] (Application) Next, the use of the switching circuit 100 will be described.

[0097] 12 is a circuit diagram of the DC / DC converter 300 A. The DC / DC converter 300 A is a synchronous rectification type step-down (Buck) converter that steps down the input voltage Vin on the input line 302 and generates an output voltage Vout on the output line 304.

[0098] The DC / DC converter 300A includes a controller 200A and its peripheral circuit 310A. The peripheral circuit 310A includes a high-side transistor MH, a low-side transistor ML, an inductor L1, and an output capacitor C1.

[0099] The high-side transistor MH and the low-side transistor ML are connected in series between an input line 302 and ground. An inductor L1 is connected between a connection node (switching node) LX between the high-side transistor MH and the low-side transistor ML and an output line 304. An output capacitor C1 is connected to the output line 304.

[0100] The high-side transistor MH includes a plurality of (N=3 in this example) power transistors MH1 to MH3 connected in parallel, and the low-side transistor ML includes a plurality of (N=3 in this example) power transistors ML1 to ML3 connected in parallel.

[0101] A feedback signal Vfb corresponding to the output of the DC / DC converter 300A is input to a feedback pin FB of the controller 200A. In this embodiment, the voltage obtained by dividing the output voltage Vout using resistors R1 and R2 is used as the feedback signal Vfb, but this is not limited to this; the output voltage Vout may also be used as the feedback signal Vfb. In the case of a converter that outputs a constant current, the output current of the DC / DC converter 300A may also be used as the feedback signal Vfb. Alternatively, the voltage of an internal node of a load connected to the output line 304 of the DC / DC converter 300A may be used as the feedback signal Vfb, or the current flowing through the internal node of the load may be used as the feedback signal Vfb.

[0102] The controller 200A integrates a drive circuit for the high-side transistor MH and a drive circuit for the low-side transistor ML, and the respective components are distinguished by adding the subscripts H and L to them.

[0103] The A / D converter 212 converts the feedback signal Vfb into a digital signal. The main controller 210 generates a control command Sctrl so that the feedback signal Vfb approaches a predetermined target value. The control command Sctrl is a duty cycle command value and includes a high-side pulse width command value TonrefH and a low-side pulse width command value TonrefL.

[0104] An analog multiplexer 223L and an A / D converter 224L detect gate signals VgL1 to VgL3 of low-side power transistors ML1 to ML3. A correction amount calculation unit 230L estimates the temperatures of the power transistors ML1 to ML3 based on the gate signals VgL1 to VgL3, respectively, and generates correction amounts ScompL1 to ScompL3 so that the temperatures of the power transistors ML1 to ML3 are equal.

[0105] Similarly, the analog multiplexer 223H, the A / D converter 224H, and the correction amount calculation unit 230H generate correction amounts ScompH1 to ScompL3 for the high-side power transistors MH1 to MH3.

[0106] The correction amounts ScompL and ScompH can include at least one of a duty cycle correction amount and a slew rate correction amount, but in this example, they include duty cycle correction amounts ΔTonL1 to ΔTonL3 and ΔTonH1 to ΔTonH3.

[0107] The adder 242L adds the correction amounts ΔTonL1 to ΔTonL3 to the pulse width command value TonrefL to generate the pulse width command values ​​TonL1 to TonL3 for the power transistors ML1 to ML3, respectively. Similarly, the adder 242H adds the correction amounts ΔTonH1 to ΔTonH3 to the pulse width command value TonrefH to generate the pulse width command values ​​TonH1 to TonH3 for the power transistors MH1 to MH3, respectively.

[0108] The digital PWM circuit 244 generates PWM pulses SH1-SH3 and SL1-SL3 based on the corrected pulse width command values ​​TonL1-TonL3 and TonH1-TonH3. The gate drivers GDH1-GDH3 drive the power transistors MH1-MH3 in response to the PWM pulses SH1-SH3. The gate drivers GDL1-GDL3 drive the power transistors ML1-ML3 in response to the PWM pulses SL1-SL3.

[0109] The above is the configuration of the DC / DC converter 300A. With this DC / DC converter 300A, the amounts of heat generated by the multiple power transistors MH1 to MH3 can be made uniform, and similarly, the amounts of heat generated by the multiple power transistors ML1 to ML3 can be made uniform.

[0110] The DC / DC converter 300A may be a step-up type or a step-up / step-down type. Furthermore, it is not limited to a synchronous rectification type, and may be a diode rectification type.

[0111] 13 is a circuit diagram of a DC / DC converter 300B. The DC / DC converter 300B is an N-phase multiphase converter, and is a synchronous rectification buck converter, similar to that in FIG.

[0112] In this example, a converter with N=3 phases is shown, and the peripheral circuit 310B includes three power transistors MH1 to MH3, three power transistors ML1 to ML3, three inductors L1 to L3, an output capacitor C1, and resistors R1 and R2.

[0113] The basic configuration of the controller 200B is the same as that of Fig. 12. In the multiphase converter, the operation of the digital PWM circuit 244 is different from that of the digital PWM circuit 244 of Fig. 12, and the N PWM pulses SH1 to SH N are phase shifted by 360° / N, and similarly, N PWM pulses SL1 to SL N is phase shifted by 360° / N.

[0114] 14 is a circuit diagram of a DC / DC converter 300C. Similar to the DC / DC converter 300A in FIG.

[0115] The controller 200C includes monitoring circuits 280L and 280H in addition to the controller 200A of FIG. 12. The monitoring circuit 280L generates a warning flag based on a plurality of correction amounts ScompL1 to ScompL3. When the deterioration of the power transistors over time progresses to the point where temperature smoothing is difficult, the correction amounts ScompL1 to ScompL3 overflow or underflow. Therefore, the monitoring circuit 280L asserts a warning flag when the correction amounts ScompL1 to ScompL3 overflow or underflow. When the warning flag is asserted, it becomes possible to take action such as stopping the system or prompting the user to perform maintenance, thereby improving the reliability of the system.

[0116] Alternatively, when the correction amounts ScompL1 to ScompL3 deviate from a predetermined appropriate range, the monitoring circuit 280L may determine that deterioration over time has progressed and assert a warning flag. Alternatively, the monitoring circuit 280L may generate an index indicating the degree of deterioration over time of the power transistors ML1 to ML3 based on the correction amounts ScompL1 to ScompL3. The same applies to the monitoring circuit 280H, which can monitor the deterioration over time of the power transistors MH1 to MH3 based on the correction amounts ScompH1 to ScompH3.

[0117] 12 to 14, an embodiment in which pulse width correction is performed has been described, but instead of or in addition to this, a function of slew rate correction may be incorporated.

[0118] The application of the switching circuit 100 is not limited to DC / DC converters, but can also be applied to inverters, rectifier circuits, motor drive circuits, and battery charging circuits. For example, multiple power transistors can form the upper arm or lower arm of an inverter.

[0119] The present disclosure has been described using specific terms based on the embodiments, but the embodiments merely illustrate the principles and applications of the present disclosure, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present disclosure as defined in the claims. [Industrial Applicability]

[0120] The present disclosure can be used to drive power transistors. [Explanation of symbols]

[0121] 100 Switching Circuit 110 Power Stage 200 Controller 210 Main Controller 212 A / D converter 220 Loss Acquisition Department 222 Sensor Group 224 A / D converter 226 Waveform acquisition section 228 Temperature Estimator 230 Correction amount calculation section 232 Reference value generation unit 234 Adder / Subtractor 236 filters 240 Gate signal generator 242 Adder 244 Digital PWM Circuit 246 Gate drive circuit 250 PID compensator 252 Proportional term calculation section 254 Integral term calculation section 256 Differential term calculation section 258 adder 260,262 multiplier 280 Monitoring circuit 300 DC / DC Converter 302 input line 304 Output Line 310 Peripheral Circuits

Claims

1. A controller for controlling a plurality of power transistors provided on a plurality of parallel paths, a correction amount calculation unit that generates a reference value based on a plurality of detection values ​​that are correlated with the switching losses of the plurality of power transistors, and generates a plurality of correction amounts so that the plurality of detection values ​​approach the reference value; a gate signal generating unit that generates a plurality of gate signals corresponding to the plurality of power transistors based on a control command and the plurality of correction amounts; Equipped with The gate signal generation unit corrects a pulse width of the gate signal for each of the plurality of power transistors based on a corresponding one of the plurality of correction amounts.

2. The controller according to claim 1 , wherein the gate signal generating unit corrects a slew rate of the gate signal of each of the plurality of power transistors based on a corresponding one of the plurality of correction amounts.

3. A controller for controlling a plurality of power transistors provided on a plurality of paths in parallel, comprising: a correction amount calculation unit that generates a reference value based on a plurality of detection values ​​that are correlated with the switching losses of the plurality of power transistors, and generates a plurality of correction amounts so that the plurality of detection values ​​approach the reference value; a gate signal generating unit that generates a plurality of gate signals corresponding to the plurality of power transistors based on a control command and the plurality of correction amounts; Equipped with The gate signal generation unit corrects the slew rate of the gate signal of each of the plurality of power transistors based on a corresponding one of the plurality of correction amounts.

4. 4. The controller according to claim 1, wherein the detected value is based on a temperature detected value indicating a temperature of the power transistor.

5. 4. The controller according to claim 1, wherein the detected value is based on a threshold voltage of the power transistor.

6. a waveform acquisition unit for measuring a waveform of a gate voltage of each of the plurality of power transistors; a temperature estimator that generates a corresponding one of the plurality of detection values ​​based on a waveform of a gate voltage of each of the plurality of power transistors; The controller of claim 1 , further comprising:

7. The controller of claim 6 , wherein the temperature estimator includes an estimator based on a trained model obtained by machine learning.

8. 4. The controller of claim 1, wherein the detected value is based on a product of a measured value of a drain current and a measured value of a drain-source voltage of the power transistor.

9. The controller according to claim 1 , wherein the correction amount calculation unit includes a plurality of PID (proportional-integral-derivative) compensators.

10. The correction amount calculation unit a plurality of first multipliers that multiply outputs of the plurality of PID compensators by first coefficients to generate a plurality of first correction amounts; a plurality of second multipliers that multiply outputs of the plurality of PID compensators by second coefficients to generate a plurality of second correction amounts; Including, The gate signal generation unit correcting a slew rate of a gate signal of each of the plurality of power transistors based on a corresponding one of the plurality of first correction amounts; The controller according to claim 9 , wherein the pulse width of the gate signal for each of the plurality of power transistors is corrected based on a corresponding one of the plurality of second correction amounts.

11. the gate signal generation unit includes a plurality of gate drivers corresponding to the plurality of power transistors, Each of the plurality of gate drivers an output node connected to the gate of a corresponding power transistor; a multi-stage delay circuit that delays the control pulse; a plurality of first transistors, each having one end connected to a first voltage line and the other end connected to the output node; a plurality of second transistors, each having one end connected to a second voltage line and the other end connected to the output node; a plurality of first logic gates corresponding to the plurality of first transistors, each of which supplies a corresponding output of the multi-stage delay circuit to a gate of the corresponding first transistor when a corresponding bit of a first control code has a predetermined value; a plurality of second logic gates corresponding to the plurality of second transistors, each of which supplies a corresponding output of the multi-stage delay circuit to a gate of the corresponding second transistor when a corresponding bit of a second control code has a predetermined value; The controller of claim 3 , comprising:

12. The controller of claim 1 , further comprising a monitoring circuit that generates a warning flag based on the plurality of correction amounts.

13. 13. The controller according to claim 1, further comprising an A / D converter that converts a plurality of detection signals correlated with the switching losses of the plurality of power transistors into the plurality of detection values.

14. The controller according to claim 1 , wherein the plurality of power transistors are switching transistors of a switching converter or synchronous rectifier transistors.

15. the switching converter is a multi-phase type; The controller according to claim 14 , wherein the controller outputs gate signals for the plurality of power transistors with a phase difference of 360° / N.

16. The controller according to claim 1 , wherein the plurality of power transistors constitute an upper arm or a lower arm of an inverter.

17. A method for controlling a plurality of power transistors provided on a plurality of parallel paths, comprising: generating a plurality of detected values ​​correlated with the switching loss of each of the plurality of power transistors; generating a reference value based on the plurality of detected values; generating a plurality of correction amounts corresponding to the plurality of power transistors, each correction amount being generated so that an error between a corresponding one of the plurality of detection values ​​and the reference value approaches zero; correcting at least one of a pulse width and a slew rate of a gate signal for each of the plurality of power transistors based on a corresponding one of the plurality of correction amounts; A control method comprising:

Images