Package with substrate having peripheral interconnects

Abstract

The package includes a substrate, a first integrated device, and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of peripheral interconnects overlying the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and benefit of non-provisional application Ser. No. 17 / 164,723, filed with the United States Patent Office on February 1, 2021, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002] Various features relate to packages that include integrated devices, and more particularly to packages that include integrated devices and substrates. [Background technology]

[0003] 1 shows a package 100 including a substrate 102, an integrated device 104, and an integrated device 106. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. Electrically coupling the integrated device 104 and the integrated device 106 can adversely affect the overall performance of the package 100. There is a continuing need to provide better performing packages. Summary of the Invention

[0004] Various features relate to packages that include integrated devices, and more particularly to packages that include integrated devices and substrates.

[0005] One example provides a package including a substrate, a first integrated device, and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of peripheral interconnects overlying the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects.

[0006] Another example provides an apparatus including a substrate, a first integrated device, and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a means for peripheral interconnection located above the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the means for peripheral interconnection.

[0007] Another example provides a method for fabricating a package. The method includes providing a substrate comprising at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of peripheral interconnects overlying the solder resist layer. The method includes bonding a first integrated device to the substrate. The method includes bonding a second integrated device to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects.

[0008] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters refer to like elements throughout. [Brief explanation of the drawings]

[0009] [Figure 1]

[0009] FIG. 1 is a side view of a package including an integrated device and a substrate. [Figure 2]

[0010] FIG. 1 is a plan view of a package including a substrate with peripheral interconnects. [Figure 3]

[0011] 1 is a plan view of a close-up view of an integrated device bonded to a substrate with peripheral interconnects. [Figure 4]

[0012] FIG. 1 is a side view of a substrate with peripheral interconnects. [Figure 5]

[0013] FIG. 1 is a side view of a substrate with peripheral interconnects. [Figure 6]

[0014] FIG. 1 is a side view of a package including a substrate with peripheral interconnects. [Figure 7]

[0015] FIG. 1 is a side view of a package including a substrate with peripheral interconnects. [Figure 8]

[0016] 1A-1C illustrate an exemplary sequence for fabricating a substrate with peripheral interconnects. [Figure 9]

[0017] 1 is an exemplary flow diagram of a method for fabricating a substrate with peripheral interconnects. [Figure 10A]

[0018] 1A and 1B illustrate an exemplary sequence for fabricating a substrate. [Figure 10B] 1A and 1B illustrate an exemplary sequence for fabricating a substrate. [Figure 10C] 1A and 1B illustrate an exemplary sequence for fabricating a substrate. [Figure 11]

[0019] 1 is an exemplary flow diagram of a method for fabricating a substrate. [Figure 12A]

[0020] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with peripheral interconnects. [Figure 12B] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with peripheral interconnects. [Figure 13]

[0021] 1 is an exemplary flow diagram of a method for making a package including a substrate with peripheral interconnects. [Figure 14]

[0022] 1A-1C illustrate various electronic devices that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0023] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0011]

[0024] The present disclosure describes a package including a substrate, a first integrated device, and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of peripheral interconnects overlying the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects. The substrate includes a routing region and a keep-out region. The plurality of peripheral interconnects are located, at least in part, along a boundary between the routing region and the keep-out region. The plurality of peripheral interconnects are configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device.

[0012] Exemplary Package with Substrate with Peripheral Interconnects

[0025] 2 shows a plan view of a package 200 including a substrate with peripheral interconnects. Package 200 includes substrate 202, integrated device 201, integrated device 203, and integrated device 205. Substrate 202 includes routing region 204 and keepout region 206. Integrated device 201, integrated device 203, and integrated device 205 are bonded to a first surface of substrate 202. Integrated device 201, integrated device 203, and integrated device 205 are bonded to routing region 204 of substrate 202. Routing region 204 may include a region of substrate 202 that includes interconnects within substrate 202. Keepout region 206 may be free of interconnects within substrate 202. Routing region 204 and keepout region 206 share a boundary.

[0013]

[0026] Substrate 202 includes a first plurality of peripheral interconnects 213, a second plurality of peripheral interconnects 215, and a third plurality of peripheral interconnects 235. First plurality of peripheral interconnects 213, second plurality of peripheral interconnects 215, and / or third plurality of peripheral interconnects 235 may be located on a solder resist layer of substrate 202. First plurality of peripheral interconnects 213 is configured to electrically couple integrated device 201 and integrated device 203. Second plurality of peripheral interconnects 215 is configured to electrically couple integrated device 201 and integrated device 205. Third plurality of peripheral interconnects 235 is configured to electrically couple integrated device 203 and integrated device 205.

[0014]

[0027] The first plurality of peripheral interconnects 213, the second plurality of peripheral interconnects 215, and / or the third plurality of peripheral interconnects 235 may be interconnects located at least in part along the boundary between the routing region 204 and the keep-out region 206. The first plurality of peripheral interconnects 213, the second plurality of peripheral interconnects 215, and / or the third plurality of peripheral interconnects 235 may be interconnects located at least in part along the periphery of the routing region 204. The first plurality of peripheral interconnects 213, the second plurality of peripheral interconnects 215, and / or the third plurality of peripheral interconnects 235 may be interconnects located at least in part along the inner periphery of the keep-out region 206. A peripheral interconnect located along the boundary between the routing region 204 and the keep-out region 206 may mean that the periphery is located at least in part on the boundary, on a portion of the routing region 204 adjacent to the boundary, and / or on a portion of the keep-out region 206 adjacent to the boundary. The first plurality of peripheral interconnects 213, the second plurality of peripheral interconnects 215 and / or the third plurality of peripheral interconnects 235 may be means for peripheral interconnection.

[0015]

[0028] The peripheral interconnects may be configured as channels (e.g., signal channels) between two integrated devices (e.g., two power management integrated circuits (PIMCs)). The use of the first plurality of peripheral interconnects 213, the second plurality of peripheral interconnects 215, and / or the third plurality of peripheral interconnects 235 along the periphery of the routing region 204 helps to improve the performance of the power distribution network (PDN) of the package 200. For example, the first plurality of peripheral interconnects 213, the second plurality of peripheral interconnects 215, and / or the third plurality of peripheral interconnects 235 may be located as far as possible from power rails and / or power planes of the package 200 (which may be located in the routing region 204 of the substrate 202), which helps to improve the performance of the power rails and / or power planes. The power rails and / or power planes are examples of interconnects that may be coupled to one or more integrated devices. The power rails and / or power planes may be located in metal layers of the substrate 202. Furthermore, placing the peripheral interconnects along the boundary and / or periphery of the routing region 204 may help reduce the total area of ​​the metal layers including the peripheral interconnects and / or reduce the number of metal layers of the substrate 202.

[0016]

[0029] The first, second, and / or third peripheral interconnects 213, 215, and / or third peripheral interconnects 235 may have a minimum line width (L) of 25 micrometers and a minimum spacing (S) between peripheral interconnects of 25 micrometers. The first, second, and / or third peripheral interconnects 213, 215, and / or third peripheral interconnects 235 may have a minimum thickness of 18 micrometers.

[0017]

[0030] The integrated devices (e.g., 201, 203, 205) may include a die (e.g., a semiconductor bare die). The integrated devices may include a power management integrated circuit (PMIC). The integrated devices may include an application processor. The integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. The integrated devices (e.g., 201, 203, 205) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0018]

[0031] The integrated devices (e.g., 201, 203, 205) are located above the routing region 204 of the substrate 202. Note that different packages may have different numbers of integrated devices. The locations of the integrated devices are exemplary. The integrated devices may be bonded to different portions of the substrate.

[0019]

[0032] 3 shows a close-up view of a plan view of integrated device 201 and substrate 202. As shown in FIG. 3, first plurality of peripheral interconnects 213 and second plurality of peripheral interconnects 215 are configured to be coupled (e.g., electrically coupled) to integrated device 201. First plurality of peripheral interconnects 213 includes peripheral interconnects 311 and peripheral interconnects 312. Peripheral interconnects 311 and peripheral interconnects 312 are configured to be coupled to integrated device 201 and integrated device 203. Peripheral interconnects 311 and peripheral interconnects 312 are configured to provide electrical paths for signals between integrated device 201 and integrated device 203. As described further below, first plurality of peripheral interconnects 213 is coupled to integrated device 201 through multiple interconnects, multiple solder interconnects, and / or multiple pillar interconnects.

[0020]

[0033] Peripheral interconnects 311 are located within and along the periphery of routing region 204. Peripheral interconnects 312 are located within and along the inner periphery of keepout region 206. First plurality of peripheral interconnects 213 may extend along the boundary between routing region 204 and keepout region 206. The boundary between routing region 204 and keepout region 206 may include an adjacent portion of routing region 204 and / or an adjacent portion of keepout region 206 of substrate 202.

[0021]

[0034] The second plurality of peripheral interconnects 215 includes peripheral interconnects 331, peripheral interconnects 332, and peripheral interconnects 333. Peripheral interconnects 331, peripheral interconnects 332, and peripheral interconnects 333 are configured to be coupled to integrated device 201 and integrated device 205. Peripheral interconnects 331, peripheral interconnects 332, and peripheral interconnects 333 are configured to provide electrical paths for signals between integrated device 201 and integrated device 205. As described further below, the second plurality of peripheral interconnects 215 is coupled to integrated device 201 through multiple interconnects, multiple solder interconnects, and / or multiple pillar interconnects.

[0022]

[0035] Peripheral interconnect 331 is located within and along the periphery of routing region 204. Peripheral interconnects 332 and 333 are located within and along the inner periphery of keepout region 206. Second plurality of peripheral interconnects 215 may extend along the boundary between routing region 204 and keepout region 206. The boundary between routing region 204 and keepout region 206 may include an adjacent portion of routing region 204 and / or an adjacent portion of keepout region 206 of substrate 202.

[0023]

[0036] Other integrated devices (e.g., 203, 205) may be coupled to their respective peripheral interconnects in a manner similar to that described for integrated device 201. Note that different implementations may have a different number of peripheral interconnects coupled to an integrated device. Different implementations may arrange the peripheral interconnects in different portions of routing region 204 and / or keepout region 206. Different implementations may define the contiguous portion of routing region 204 differently. For example, the contiguous portion of routing region 204 may include a portion of routing region 204 that is within (e.g., 100 micrometers or less) of a boundary shared between routing region 204 and keepout region 206. Different implementations may use a value less than 100 micrometers to define the contiguous portion of routing region 204 relative to the boundary.

[0024]

[0037] 4 shows a side view of substrate 202 across cross section AA of FIG. 3. Substrate 202 includes at least one dielectric layer 402, a plurality of interconnects 322, a solder resist layer 401, a first plurality of peripheral interconnects 213, a second plurality of peripheral interconnects 215, and a peripheral dielectric layer 403. Some of the interconnects (e.g., pads) from the plurality of interconnects 322 are located on a surface of at least one dielectric layer 402. Solder resist layer 401 is located on at least one dielectric layer 402 and the plurality of interconnects 322. Peripheral interconnects 311, 312, 331, 332, and 333 are coupled to the interconnects from the plurality of interconnects 322. Peripheral dielectric layer 403 is located on solder resist layer 401 and the peripheral interconnects (e.g., 311, 312, 331, 332, 333). The plurality of interconnects 322 may be configured to be coupled to the integrated device (e.g., 201) through solder interconnects and / or pillar interconnects. The at least one dielectric layer 402 may include at least one dielectric layer 620, as further described below.

[0025]

[0038] FIG. 5 shows a side view of a substrate 502 across cross section AA of FIG. 3 . The substrate 502 of FIG. 5 may be similar to the substrate 202. Thus, the substrate 502 may include the same or similar components as the substrate 202. The substrate 502 includes at least one dielectric layer 402, a plurality of interconnects 522, a solder resist layer 401, a first plurality of peripheral interconnects 213, a second plurality of peripheral interconnects 215, and a peripheral dielectric layer 403. Some of the interconnects (e.g., pads) from the plurality of interconnects 522 are located in (e.g., embedded within) the at least one dielectric layer 402. The solder resist layer 401 is located over the at least one dielectric layer 402 and the plurality of interconnects 522. The peripheral interconnects 311, 312, 331, 332, and 333 are coupled to the interconnects from the plurality of interconnects 522. A peripheral dielectric layer 403 overlies the solder resist layer 401 and the peripheral interconnects (e.g., 311, 312, 331, 332, 333). The plurality of interconnects 522 may be configured to be coupled to the integrated device (e.g., 201) through solder interconnects and / or pillar interconnects. It should be noted that the configurations shown in Figures 4 and 5 may be applicable to the other integrated devices (e.g., 203, 205) described in this disclosure.

[0026]

[0039] 6 shows a side view of package 200 including substrate 202 with peripheral interconnects. Package 200 is coupled to a board 690 (e.g., a printed circuit board (PCB)) through a plurality of solder interconnects 680. Package 200 provides a compact, small form factor package while also having optimized and improved PDN performance.

[0027]

[0040] Package 200 includes substrate 202, integrated device 203, integrated device 205, and component 607 (e.g., a capacitor). Substrate 202 includes at least one dielectric layer 620, a plurality of interconnects 622, solder resist layer 401, solder resist layer 601, a plurality of peripheral interconnects 635, and peripheral dielectric layer 403. The plurality of interconnects 622 may represent the plurality of interconnects 322 and / or the plurality of interconnects 522. Although not shown, package 200 may include other integrated devices (e.g., 201) and other peripheral interconnects (e.g., 213, 215). The plurality of interconnects 622 may include the plurality of interconnects 322.

[0028]

[0041] The plurality of interconnects 622 may have a first minimum pitch and a first minimum line width (L) and spacing (S) (e.g., L / S). In some implementations, the first minimum line width and spacing (L / S) for the plurality of interconnects 622 is in a range of approximately 9 / 9 to 12 / 12 micrometers (μm) (e.g., a minimum line width of approximately 9 to 12 micrometers (μm), a minimum spacing of approximately 9 to 12 micrometers (μm)).

[0029]

[0042] The peripheral interconnects 635 may have a minimum line width (L) of 25 micrometers and a minimum spacing (S) between the peripheral interconnects of 25 micrometers. The peripheral interconnects 635 may have a minimum thickness of 18 micrometers.

[0030]

[0043] Different implementations may use different substrates. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer (e.g., a core substrate). In some implementations, the at least one dielectric layer 620 may include a core layer and / or a prepreg layer. The at least one dielectric layer 620 may have a dielectric constant in the range of approximately 3.5 to 3.7. The at least one dielectric layer 620 may include a glass fabric to reinforce the substrate 202. An example of fabricating the substrate is further described below in FIGS. 10A-10C. As further described below, in some implementations, the substrate 202 may be fabricated using a modified semi-additive process (mSAP) or a semi-additive process (SAP). FIG. 8 shows and describes a sequence for fabricating a substrate with peripheral interconnects.

[0031]

[0044] The integrated device 203 is coupled to a first surface (e.g., a top surface) of the substrate 202. The integrated device 203 is coupled to the substrate through a plurality of solder interconnects 630. The plurality of solder interconnects 630 may include pillar interconnects (e.g., copper pillars) and / or solder interconnects. An underfill 633 is located between the substrate 202 and the integrated device 203 (e.g., a first integrated device). The underfill 633 may surround the plurality of solder interconnects 630. The integrated device 205 is coupled to a first surface (e.g., a top surface) of the substrate 202. The integrated device 205 (e.g., a second integrated device) is coupled to the substrate through a plurality of solder interconnects 650. The plurality of solder interconnects 650 may include pillar interconnects (e.g., copper pillars) and / or solder interconnects. An underfill 653 is located between the substrate 202 and the integrated device 205. Underfill 653 may surround the plurality of solder interconnects 650. Integrated device 203 and integrated device 205 may be located over routing region 204 of substrate 202.

[0032]

[0045] An encapsulation layer 610 may be formed over the substrate 202, the integrated device(s) (e.g., 203, 205), and the component 607. The encapsulation layer 610 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 610. The encapsulation layer 610 may be photo-etchable. The encapsulation layer 610 may be a means for encapsulation.

[0033]

[0046] A plurality of peripheral interconnects 635 are located on the solder resist layer 401. The plurality of peripheral interconnects 635 may represent any of the peripheral interconnects described in this disclosure (e.g., 213, 215, 235, 311, 312, 331, 332, 333). The plurality of peripheral interconnects 635 may be located around the inner periphery of the keepout region 206, around the periphery of the routing region 204, and / or along the boundary between the routing region 204 and the keepout region 206. The keepout region 206 may be free of interconnects in the substrate 202. For example, the keepout region 206 of the substrate 202 may be free of interconnects located in at least one dielectric layer 620. In another example, there may be no interconnects located vertically between the solder resist layer 401 (e.g., a lower surface of the solder resist layer 401 bonded to the at least one dielectric layer 620) and the solder resist layer 601 (e.g., an upper surface of the solder resist layer 601 bonded to the at least one dielectric layer 620) within the keepout region 206 of the substrate 202. The peripheral dielectric layer 403 is located above the solder resist layer 401 and the plurality of peripheral interconnects 635. The plurality of peripheral interconnects 635 may be configured to electrically couple two or more integrated devices. The plurality of peripheral interconnects 625 may be configured as an electrical path(s) for signals between the two or more integrated devices.

[0034]

[0047] Integrated device 203 is coupled to a plurality of peripheral interconnects 635 through a plurality of solder interconnects 630 and interconnects (e.g., surface interconnects) from a plurality of interconnects 622. Integrated device 205 is coupled to a plurality of peripheral interconnects 635 through a plurality of solder interconnects 650 and interconnects (e.g., surface interconnects) from a plurality of interconnects 622.

[0035]

[0048] 7 shows a side view of package 700 including a substrate 702 with peripheral interconnects. Package 700 is similar to package 200. Thus, package 700 includes the same or similar components as package 200. Substrate 702 is similar to substrate 202. Thus, substrate 702 includes the same or similar components as substrate 202. Package 700 may represent package 200 of FIGS. 1-5.

[0036]

[0049] Substrate 702 includes at least one dielectric layer, a plurality of interconnects 722, solder resist layer 401, solder resist layer 601, a plurality of peripheral interconnects 635, and peripheral dielectric layer 403. As shown in Figure 7, integrated device 203 and integrated device 205 are coupled to the embedded interconnects of substrate 702.

[0037]

[0050] Integrated device 203 is coupled to a plurality of peripheral interconnects 635 through a plurality of solder interconnects 630 and interconnects (e.g., buried interconnects) from a plurality of interconnects 722. Integrated device 205 is coupled to a plurality of peripheral interconnects 635 through a plurality of solder interconnects 650 and interconnects (e.g., buried interconnects) from a plurality of interconnects 722. Integrated device 203 and integrated device 205 may be located above routing region 204 of substrate 702. As shown in FIGS. 6-7 , the plurality of peripheral interconnects 635 are located on a different metal layer than other interconnects of the substrate (e.g., 202, 702). For example, the plurality of peripheral interconnects 635 are located on a different metal layer than interconnects located between solder resist layer 401 and solder resist layer 601.

[0038] Exemplary Sequence for Fabricating a Substrate with Peripheral Interconnects

[0051] 8 shows an example sequence for providing or fabricating a substrate with peripheral interconnects. In some implementations, the sequence of FIG. 8 can be used to provide or fabricate the substrate 202 including peripheral interconnects of FIG. 6 or any of the substrates described in this disclosure.

[0039]

[0052] It should be noted that the sequence of Figure 8 may combine one or more stages to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure. The sequence of Figure 8 may be used to fabricate one substrate or several substrates at a time (as part of a wafer).

[0040]

[0053] Stage 1, as shown in FIG. 8, illustrates the state after the substrate 202 is provided. The substrate 202 can be provided or fabricated by a supplier. A process similar to that illustrated in FIGS. 10A-10C can be used to fabricate the substrate 202. However, different implementations may use different processes to fabricate the substrate 202. Examples of processes that can be used to fabricate the substrate 202 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 202 includes at least one dielectric layer 620 and a plurality of interconnects 622. The substrate 202 can be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer (e.g., a core substrate). In some implementations, the at least one dielectric layer 620 can include a core layer and / or a prepreg layer. The substrate 202 includes at least one dielectric layer 620, a plurality of interconnects 622, a solder resist layer 401, and a solder resist layer 601.

[0041]

[0054] Stage 2 shows the state after a plurality of peripheral interconnects 635 are formed on solder resist layer 401. The plurality of peripheral interconnects 635 may be coupled to the plurality of interconnects 622. The plurality of peripheral interconnects 635 may be formed in cavities in solder resist layer 401. The plurality of peripheral interconnects 635 may represent one or more peripheral interconnects from the plurality of peripheral interconnects (e.g., 213, 215, 235, 311, 312, 331, 332, 333). Different implementations may form the plurality of peripheral interconnects 635 differently. An inkjet and / or aerosol jet process may be used to form a conductive paste on solder resist layer 401 and some portions of the interconnects from the plurality of interconnects 622. The inkjet and / or aerosol jet process may form a conductive paste between two pads (e.g., a surface pad, a buried pad).

[0042]

[0055] Stage 3 shows the state after the peripheral dielectric layer 403 has been formed over the solder resist layer 401 and the plurality of peripheral interconnects 635. The peripheral dielectric layer 403 may also be formed in at least some of the cavities in the solder resist layer 401. Portions of the peripheral dielectric layer 403 may be located laterally between the solder resist layer 401 and the plurality of peripheral interconnects 635. Different implementations may form the peripheral dielectric layer 403 differently. An inkjet and / or an aerosol jet process may be used to form the dielectric paste over the solder resist layer 401 and the plurality of peripheral interconnects 635. Once the conductive paste and dielectric paste are provided and / or formed, a curing process may be performed, which transforms the conductive paste into the plurality of peripheral interconnects 635 and the dielectric paste into the peripheral dielectric layer 403. The curing process may include oven baking and / or ultraviolet (UV) curing.

[0043] 1 is an exemplary flow diagram of a method for fabricating a substrate with peripheral interconnects;

[0056] In some implementations, fabricating a substrate including peripheral interconnects involves several processes. Figure 9 shows an example flow diagram of a method 900 for providing or fabricating a substrate with peripheral interconnects. In some implementations, the method 900 of Figure 9 can be used to provide or fabricate the substrate (e.g., 202) of Figure 6 described in this disclosure. However, the method 900 can be used to provide or fabricate any of the substrates described in this disclosure.

[0044]

[0057] 9 may combine one or more processes to simplify and / or clarify the method for providing or making an interconnect device. In some implementations, the order of the processes may be changed or modified.

[0045]

[0058] The method provides (at 905) a substrate (e.g., 202). The substrate 202 can be provided or fabricated by a supplier. A process similar to that shown in FIGS. 10A-10C can be used to fabricate the substrate 202. However, different implementations may use different processes to fabricate the substrate 202. Examples of processes that can be used to fabricate the substrate 202 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 202 includes at least one dielectric layer 620 and a plurality of interconnects 622. The substrate 202 can be a laminate substrate, a coreless substrate, an organic substrate, or a substrate including a core layer (e.g., a core substrate). In some implementations, the at least one dielectric layer 620 can include a core layer and / or a prepreg layer. The substrate 202 includes at least one dielectric layer 620, a plurality of interconnects 622, a solder resist layer 401, and a solder resist layer 601.

[0046]

[0059] The method provides (at 910) a conductive paste on the solder resist layer 401. The conductive paste may be bonded to the plurality of interconnects 622. The conductive paste may be formed in the cavities of the solder resist layer 401. When cured, the conductive paste may form the plurality of peripheral interconnects 635. The plurality of peripheral interconnects 635 may represent one or more peripheral interconnects from the plurality of peripheral interconnects (e.g., 213, 215, 235, 311, 312, 331, 332, 333). Different implementations may form the conductive paste differently. An inkjet and / or aerosol jet process may be used to form the conductive paste on the solder resist layer 401 and some portions of the interconnects from the plurality of interconnects 622. The inkjet and / or aerosol jet process may form the conductive paste between two pads (e.g., surface pads, buried pads). Stage 2 of FIG. 8 shows and describes one example of a conductive paste (that will become the peripheral interconnects) formed on the solder resist layer.

[0047]

[0060] The method provides (at 915) a dielectric paste over the solder resist layer 401 and the conductive paste. The dielectric paste may be formed in at least some of the cavities of the solder resist layer 401. Portions of the dielectric paste may be located laterally between the solder resist layer 401 and the conductive paste. When cured, the dielectric paste may form the peripheral dielectric layer 403. Different implementations may form the dielectric paste differently. Inkjet and / or aerosol jet processes may be used to form the dielectric paste over the solder resist layer 401 and the conductive paste. Stage 3 of FIG. 8 shows and describes one example of a dielectric paste (that will become the peripheral dielectric layer) being formed over the solder resist layer.

[0048]

[0061] The method then (at 920) cures the conductive paste and / or the dielectric paste. The curing process may include oven baking and / or ultraviolet (UV) curing. Curing the conductive paste may form the plurality of peripheral interconnects 635. Curing the dielectric paste may form the peripheral dielectric layer 403. The curing of the conductive paste and the curing of the dielectric paste may be performed simultaneously or sequentially.

[0049] Exemplary Sequence for Fabricating a Substrate

[0062] In some implementations, fabricating a substrate includes several processes. Figures 10A-10C show an example sequence for providing or fabricating a substrate. In some implementations, the sequence of Figures 10A-10C may be used to provide or fabricate substrate 202 of Figure 6. However, the process of Figures 10A-10C may be used to fabricate any of the substrates described in this disclosure.

[0050]

[0063] 10A-10C may combine one or more stages to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the present disclosure.

[0051]

[0064] Stage 1, as shown in Figure 10A, depicts the state after a carrier 1000 is provided and a metal layer is formed on the carrier 1000. The metal layer may be patterned to form interconnects 1002. Plating and etching processes may be used to form the metal layer and interconnects.

[0052]

[0065] Stage 2 shows the state after a dielectric layer 1020 is formed over the carrier 1000 and the interconnects 1002. The dielectric layer 1020 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0053]

[0066] Stage 3 shows the state after the plurality of cavities 1010 have been formed in the dielectric layer 1020. The plurality of cavities 1010 may be formed using an etching process (e.g., a photoetching process) or a laser process.

[0054]

[0067] Stage 4 shows the state after interconnects 1012 have been formed in and on the dielectric layer 1020. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0055]

[0068] Stage 5 shows the state after another dielectric layer 1022 is formed over dielectric layer 1020. Dielectric layer 1022 can be the same material as dielectric layer 1020. However, different implementations can use different materials for the dielectric layer.

[0056]

[0069] Stage 6, as shown in Figure 10B, shows the state after a plurality of cavities 1030 have been formed in the dielectric layer 1022. An etching process or a laser process can be used to form the cavities 1030.

[0057]

[0070] Stage 7 shows the state after interconnects 1014 have been formed in and on the dielectric layer 1022. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnects.

[0058]

[0071] Stage 8 shows the state after another dielectric layer 1024 is formed over dielectric layer 1022. Dielectric layer 1024 can be the same material as dielectric layer 1020. However, different implementations can use different materials for the dielectric layer.

[0059]

[0072] Stage 9 shows the state after a plurality of cavities 1040 have been formed in the dielectric layer 1024. An etching process or a laser process can be used to form the cavities 1040.

[0060]

[0073] Stage 10, as shown in Figure 10C, depicts the state after interconnects 1016 have been formed in and on dielectric layer 1024. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0061]

[0074] Some or all of the interconnects 1002, 1012, 1014 and / or 1016 may define the plurality of interconnects 622 of the substrate 202. The dielectric layers 1020, 1022, 1024 may be represented by at least one dielectric layer 620.

[0062]

[0075] Stage 11 shows the state after carrier 1000 has been separated (eg, removed and ground) from dielectric layer 620 , leaving substrate 202 .

[0063]

[0076] Stage 12 shows the state after solder resist layer 401 and solder resist layer 601 have been formed on substrate 202. Solder resist layer 401 and solder resist layer 601 may be part of substrate 202.

[0064]

[0077] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0065] 1 is an exemplary flow diagram of a method for fabricating a substrate;

[0078] In some implementations, fabricating a substrate includes several processes. Figure 11 shows an example flow diagram of a method 1100 for providing or fabricating a substrate. In some implementations, the method 1100 of Figure 11 can be used to provide or fabricate the substrate of Figure 6. For example, the method of Figure 11 can be used to fabricate substrate 202. The method of Figure 11 can be used to fabricate an interconnect device when the interconnect device is implemented as a substrate and / or an interposer.

[0066]

[0079] 11 may combine one or more processes to simplify and / or clarify the method for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

[0067]

[0080] The method provides (at 1105) a carrier 1000. Different implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or carrier tape. Stage 1 of Figure 10A shows and describes an example of the state after the carrier is provided.

[0068]

[0081] The method forms (at 1110) a metal layer on the carrier 1000. The metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and interconnects. Stage 1 of Figure 10A shows and describes an example of the state after the metal layer and interconnects 1002 have been formed.

[0069]

[0082] The method forms (at 1115) a dielectric layer 1020 over the carrier 1000 and the interconnects 1002. The dielectric layer 1020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Steps 2-3 of FIG. 10A show and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0070]

[0083] The method forms (at 1120) interconnects in and on the dielectric layer. For example, interconnects 1012 may be formed in and on dielectric layer 1020. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or within the dielectric layer. Step 4 of Figure 10A shows and describes one example of forming interconnects in and on the dielectric layer.

[0071]

[0084] The method forms (at 1125) a dielectric layer 1022 over the dielectric layer 1020 and the interconnects. The dielectric layer 1022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Steps 5-6 of Figures 10A-10B illustrate forming the dielectric layer and the cavities in the dielectric layer.

[0072]

[0085] The method forms (at 1130) interconnects in and / or on the dielectric layer. For example, interconnect 1014 may be formed. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and within the dielectric layer. Step 7 of Figure 10B shows and describes one example of forming interconnects in and on the dielectric layer.

[0073]

[0086] The method may form additional dielectric layer(s) and additional interconnects as described at 1125 and 1130. Steps 8-10 of Figures 10B-10C show and describe one example of forming additional interconnects in and on a dielectric layer.

[0074]

[0087] Once all the dielectric layer(s) and additional interconnects are formed, the method may separate (e.g., remove, grind) the carrier (e.g., 1000) from the dielectric layer 1020, leaving the substrate. In some implementations, the method may form a solder resist layer (e.g., 401, 601) on the substrate.

[0075]

[0088] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process to form the metal layer(s). For example, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0076] Exemplary Sequence for Making a Package Including a Substrate with Peripheral Interconnects

[0089] Figures 12A-12B illustrate an exemplary sequence for providing or fabricating a package that includes a substrate with peripheral interconnects. In some implementations, the sequence of Figures 12A-12B can be used to provide or fabricate Package 200 that includes a substrate with peripheral interconnects of Figure 6, or any of the packages described in this disclosure.

[0077]

[0090] Note that the sequence of Figures 12A-12B can combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the process can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure. The sequence of Figures 12A-12B can be used to fabricate one package or several packages at a time (as part of a wafer).

[0078]

[0091] Step 1 shows the state after substrate 202 is provided, as shown in Figure 12A. Substrate 202 can be provided by a supplier or fabricated. A process similar to the processes shown in Figures 8 and 10A-10C can be used to fabricate substrate 202. However, different implementations can use different processes to fabricate substrate 202. Examples of processes that can be used to fabricate substrate 202 include semi-additive process (SAP) and modified semi-additive process (mSAP). Substrate 202 includes at least one dielectric layer 620 and a plurality of interconnects 622. Substrate 202 can be a laminated substrate, a coreless substrate, an organic substrate, a substrate that includes a core layer (e.g., a core substrate). In some implementations, at least one dielectric layer 620 can include a core layer and / or a prepreg layer. Substrate 202 includes at least one dielectric layer 620, a plurality of interconnects 622, a solder resist layer 401, a solder resist layer 601, a plurality of peripheral interconnects 635, and a peripheral dielectric layer 403.

[0079]

[0092] Stage 2 shows the state after integrated device 203, integrated device 205, and component 607 are coupled to a first surface (e.g., top surface) of substrate 202. Integrated device 203 may be coupled to substrate 202 through a plurality of solder interconnects 630. Integrated device 205 may be coupled to substrate 202 through a plurality of solder interconnects 650. Component 607 may be coupled to substrate 202 through a plurality of solder interconnects 670. Other integrated devices (e.g., 201) may be coupled to substrate 202. Integrated device 203 and integrated device 205 may be coupled to substrate 202 such that integrated device 203 and integrated device 205 are configured to be electrically coupled to each other through a plurality of peripheral interconnects 635. The plurality of peripheral interconnects 635 may be located, at least in part, along the boundary between routing region 204 and keepout region 206 of substrate 202. The integrated device 203 , the integrated device 205 and the component 607 may be coupled to the substrate 202 such that the integrated device 203 , the integrated device 205 and the component 607 are located above the routing region 204 of the substrate 202 .

[0080]

[0093] Stage 3, as shown in FIG. 12B, depicts the state after an encapsulation layer is provided over the substrate 202 and the integrated device. The encapsulation layer may encapsulate the integrated device(s) and / or components. For example, an encapsulation layer 610 may be formed over the substrate 202 and the integrated device(s) (e.g., 203, 205). The encapsulation layer 610 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 610. The encapsulation layer 610 may be photo-etchable. The encapsulation layer 610 may be a means for encapsulation.

[0081]

[0094] Stage 4 shows the state after a plurality of solder interconnects 680 have been bonded to a second surface (e.g., bottom surface) of substrate 202. The plurality of solder interconnects 680 may be bonded to interconnects from the plurality of interconnects 622 of substrate 202. A solder reflow process may be used to bond the plurality of solder interconnects 680 to substrate 202. Stage 4 may show package 600. The packages (e.g., 600) described in this disclosure may be fabricated one by one or together as part of one or more wafers and then singulated into individual packages.

[0082] 1 is an exemplary flow diagram of a method for fabricating a package including a substrate with peripheral interconnects;

[0095] In some implementations, fabricating a package including a substrate with peripheral interconnects involves several processes. Figure 13 shows an example flow diagram of a method 1300 for providing or fabricating a package including a substrate with peripheral interconnects. In some implementations, the method 1300 of Figure 13 can be used to provide or fabricate the package 600 of Figure 6 described in this disclosure. However, the method 1300 can be used to provide or fabricate any of the packages described in this disclosure.

[0083]

[0096] 13 may combine one or more processes to simplify and / or clarify a method for providing or making a package that includes a substrate with peripheral interconnects. In some implementations, the order of the processes may be changed or modified.

[0084]

[0097] The method provides (at 1305) a substrate (e.g., 202) with peripheral interconnects. The substrate 202 can be provided or fabricated by a supplier. The substrate 202 includes a first surface and a second surface. The substrate 202 includes at least one dielectric layer 620, a plurality of interconnects 622, a solder resist layer 401, a plurality of peripheral interconnects 635, and a peripheral dielectric layer 403. Different implementations may provide different substrates. Processes similar to those shown in FIGS. 8 and 10A-10C may be used to fabricate the substrate 202. However, different implementations may use different processes to fabricate the substrate 202. Stage 1 of FIG. 12A shows and describes an example of providing a substrate with peripheral interconnects.

[0085]

[0098] The method includes (at 1310) coupling a plurality of integrated devices (e.g., 201, 203, 205) and / or component(s) (e.g., 607) to a first surface of a substrate (e.g., 202). For example, integrated device 203 may be coupled to substrate 202 through a plurality of solder interconnects 630. The plurality of solder interconnects 630 may be coupled to interconnects from a plurality of interconnects 622 of substrate 202. In another example, integrated device 205 may be coupled to substrate 202 through a plurality of solder interconnects 650. The plurality of solder interconnects 650 may be coupled to interconnects from a plurality of interconnects 622 of substrate 202. Integrated device 203 and integrated device 205 may be coupled to the substrate such that integrated device 203 and integrated device 205 are configured to be electrically coupled to each other through a plurality of peripheral interconnects 635. The plurality of peripheral interconnects 635 may be located, at least in part, along the boundary between the routing region 204 and the keepout region 206 of the substrate 202. Stage 2 of Figure 12A shows and describes one example of integrated devices and components coupled to the substrate. Coupling the integrated devices to the substrate may also include providing an underfill (e.g., 613, 633, 653) between each integrated device (e.g., 203, 205) and the substrate 202. Stage 2 of Figure 12A shows and describes one example in which the underfill is provided.

[0086]

[0099] The method forms (at 1315) an encapsulation layer (e.g., 610) over the substrate (e.g., 202). The encapsulation layer 610 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the encapsulation layer 610. The encapsulation layer 610 may be photoetchable. The encapsulation layer 610 may be a means for encapsulation. The encapsulation layer may encapsulate the integrated device(s) and / or component(s). Step 3 of FIG. 12B shows and describes an example of forming an encapsulation layer over a substrate.

[0087]

[0100] The method includes (at 1320) bonding a plurality of solder interconnects (e.g., 680) to a second surface of the substrate (e.g., 202). Step 4 of Figure 12B shows and describes an example of bonding the solder interconnects to the substrate.

[0088] Exemplary Electronic Devices

[0101] 14 illustrates various electronic devices that may be integrated with any of the above-described devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed location terminal device 1406, a wearable device 1408, or an automotive vehicle 1410 may include a device 1400 described herein. The device 1400 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1402, 1404, 1406, and 1408 and the vehicle 1410 illustrated in FIG. 14 are merely illustrative. Other electronic devices may also characterize device 1400, including a group of devices (e.g., electronic devices), including, but not limited to, mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, eyeglasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0089]

[0102] One or more of the components, processes, features, and / or functions shown in Figures 2-9, 10A-10C, 11, 12A-12B, and / or 13-14 may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additionally, additional elements, components, processes, and / or functions may be added without departing from the present disclosure. It should also be noted that Figures 2-9, 10A-10C, 11, 12A-12B, and / or 13-14 in this disclosure, and their corresponding descriptions, are not limited to dies and / or ICs. 2-9, 10A-10C, 11, 12A-12B, and / or 13-14, and corresponding descriptions thereof, may be used to manufacture, create, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0090]

[0103] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the figures may not be to scale. In some instances, for clarity, not all components and / or parts may be shown. In some instances, the position, location, size, and / or shape of various parts and / or parts in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0091]

[0104] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects of the present disclosure. Likewise, the term “aspect” does not require that all aspects of the present disclosure include the described feature, advantage, or mode of operation. The term “coupled” is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C may still be considered to be coupled to each other even though they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled to each other such that an electric current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electric current traveling between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything beyond fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component, or a fourth component. The term "encapsulate" means that an object may partially or completely encapsulate another object. The terms "upper" and "lower" are arbitrary. A component located on the upper side may be located above a component located on the lower side. An upper component may be considered a lower component, and vice versa. As described in this disclosure, a first component located "on" a second component may mean that the first component is located above or below the second component, depending on how lower or upper is arbitrarily defined.In another example, a first component may be located on (e.g., above) a first surface of a second component, and a third component may be located on (e.g., below) a second surface of the second component, with the second surface facing the first surface. It is further noted that the term "over," as used herein in the context of one component being located on another component, may be used to mean a component that is on and / or in (e.g., on the surface of or embedded within) another component. Thus, for example, a first component that is over a second component may mean (1) that the first component is over the second component but is not in direct contact with the second component, (2) that the first component is on (e.g., on the surface of) the second component, and / or (3) that the first component is in (e.g., embedded within) the second component. A first component located "in" a second component can be partially located within the second component or completely located within the second component. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within 10 percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0092]

[0105] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form the interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or a plating process may be used to form the interconnect.

[0093]

[0106] Also, it should be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Further, the order of operations may be rearranged. A process ends when its operations are completed.

[0094]

[0107] In the following, further examples are described to facilitate understanding of the present invention.

[0095]

[0108] Aspect 1: A package comprising a substrate, a first integrated device, and a second integrated device. The substrate comprises at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of peripheral interconnects overlying the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate, wherein the second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects.

[0096]

[0109] Aspect 2: The package of aspect 1, wherein the substrate includes a routing region and a keepout region, and wherein the plurality of peripheral interconnects are located, at least in part, along a boundary between the routing region and the keepout region.

[0097]

[0110] Aspect 3: The package of aspect 2, wherein the keep-out region is an area of ​​the substrate that is free of interconnects.

[0098]

[0111] Aspect 4: The package of aspects 1 to 3, wherein the plurality of peripheral interconnects are configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device.

[0099]

[0112] Aspect 5: The package of aspects 1 to 4, wherein the first integrated device includes a first power management integrated device and / or a first application processor.

[0100]

[0113] Embodiment 6: The package of embodiment 5, wherein the second integrated device includes a second power management integrated device and / or a second application processor.

[0101]

[0114] Embodiment 7: The package of embodiments 1-6, further comprising a peripheral dielectric layer overlying the solder resist layer and the plurality of peripheral interconnects.

[0102]

[0115] Aspect 8: The package of Aspects 1 to 7, further comprising a third integrated device coupled to the substrate, wherein the substrate further includes a second plurality of peripheral interconnects located on the solder resist layer, wherein the substrate further includes a third plurality of peripheral interconnects located on the solder resist layer, wherein the first integrated device is configured to be electrically coupled to the third integrated device through the second plurality of peripheral interconnects, and wherein the second integrated device is configured to be electrically coupled to the third integrated device through the third plurality of peripheral interconnects.

[0103]

[0116] Embodiment 9: The package of embodiments 1 to 8, wherein the plurality of peripheral interconnects, the second plurality of peripheral interconnects, and the third plurality of peripheral interconnects are located along the periphery of the substrate.

[0104]

[0117] Aspect 10: The package of aspects 1 to 9, wherein the package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

[0105]

[0118] Aspect 11: An apparatus comprising a substrate, a first integrated device, and a second integrated device. The substrate comprises at least one dielectric layer, a plurality of interconnects, a solder resist layer, and means for peripheral interconnection located on the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate, wherein the second integrated device is configured to be electrically coupled to the first integrated device through the means for peripheral interconnection.

[0106]

[0119] Embodiment 12: The device of embodiment 11, wherein the substrate includes a routing region and a keepout region, and wherein the means for peripheral interconnection is located, at least in part, along the boundary between the routing region and the keepout region.

[0107]

[0120] Embodiment 13: The device of embodiment 12, wherein the keep-out region is a region of the substrate that is free of interconnects.

[0108]

[0121] Embodiment 14: The apparatus of embodiments 11 to 13, wherein the means for peripheral interconnection is configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device.

[0109]

[0122] Aspect 15: The apparatus of Aspects 11 to 14, wherein the first integrated device includes a first power management integrated device and / or a first application processor.

[0110]

[0123] Example 16: The apparatus of example 15, wherein the second integrated device includes a second power management integrated device and / or a second application processor.

[0111]

[0124] Embodiment 17: The apparatus of embodiments 11 to 16, further comprising a peripheral dielectric layer overlying the solder resist layer and the means for peripheral interconnection.

[0112]

[0125] Aspect 18: A method for fabricating a package. The method provides a substrate comprising at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of peripheral interconnects overlying the solder resist layer. The method bonds a first integrated device to the substrate. The method bonds a second integrated device to the substrate, wherein the second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects.

[0113]

[0126] Embodiment 19: The method of embodiment 18, wherein the substrate includes a routing region and a keep-out region, wherein the plurality of peripheral interconnects are located, at least in part, along a boundary between the routing region and the keep-out region.

[0114]

[0127] Embodiment 20: The method of embodiment 19, wherein the keep-out region is a region of the substrate that is free of interconnects.

[0115]

[0128] Embodiment 21: The method of embodiments 18 to 20, wherein the plurality of peripheral interconnects are configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device.

[0116]

[0129] Aspect 22: The method of aspects 18 to 21, wherein the first integrated device includes a first power management integrated device and / or a first application processor.

[0117]

[0130] Embodiment 23: The method of embodiments 18 to 22, further comprising a peripheral dielectric layer overlying the solder resist layer and the plurality of peripheral interconnects.

[0118]

[0131] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above-described aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is illustrative and does not limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art. The inventions described in the claims of the present application as originally filed are set forth below. [C1] A package, at least one dielectric layer; Multiple interconnections; a solder resist layer; a plurality of peripheral interconnects overlying said solder resist layer; a substrate comprising: a first integrated device coupled to the substrate; a second integrated device coupled to the substrate, wherein the second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects. package. [C2] the substrate includes a routing region and a keepout region; wherein the plurality of peripheral interconnects are located at least in part along a boundary between the routing region and the keepout region. Package as described in C1. [C3] The package of C2, wherein the keep-out area is an area of ​​the substrate that is free of interconnects. [C4] The package of C1, wherein the plurality of peripheral interconnects are configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device. [C5] The package of C1, wherein the first integrated device includes a first power management integrated device and / or a first application processor. [C6] The package of C5, wherein the second integrated device includes a second power management integrated device and / or a second application processor. [C7] The package of C1, further comprising a peripheral dielectric layer overlying the solder resist layer and the plurality of peripheral interconnects. [C8] further comprising a third integrated device coupled to the substrate; wherein the substrate further includes a second plurality of peripheral interconnects located on the solder resist layer; wherein the substrate further includes a third plurality of peripheral interconnects located on the solder resist layer; wherein the first integrated device is configured to be electrically coupled to the third integrated device through the second plurality of peripheral interconnects; wherein the second integrated device is configured to be electrically coupled to the third integrated device through the third plurality of peripheral interconnects. Package as described in C1. [C9] The package of C8, wherein the plurality of peripheral interconnects, the second plurality of peripheral interconnects, and the third plurality of peripheral interconnects are located along a periphery of the substrate. [C10] The package of C1, wherein the package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle. [C11] 1. An apparatus comprising: at least one dielectric layer; Multiple interconnections; a solder resist layer; means for peripheral interconnections located over said solder resist layer; a substrate comprising: a first integrated device coupled to the substrate; a second integrated device coupled to the substrate, wherein the second integrated device is configured to be electrically coupled to the first integrated device through the means for peripheral interconnection. Device. [C12] the substrate includes a routing region and a keepout region; wherein said means for peripheral interconnection is located at least in part along a boundary between said routing region and said keep-out region. The device described in C11. [C13] The apparatus of C12, wherein the keep-out region is an area of ​​the substrate that is free of interconnects. [C14] The apparatus of C11, wherein the means for peripheral interconnection is configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device. [C15] The apparatus of C11, wherein the first integrated device includes a first power management integrated device and / or a first application processor. [C16] The apparatus of C15, wherein the second integrated device includes a second power management integrated device and / or a second application processor. [C17] The apparatus of C11, further comprising a peripheral dielectric layer overlying the solder resist layer and the means for peripheral interconnection. [C18] 1. A method for fabricating a package, comprising: at least one dielectric layer; Multiple interconnections; a solder resist layer; a plurality of peripheral interconnects overlying said solder resist layer; providing a substrate comprising: coupling a first integrated device to the substrate; and coupling a second integrated device to the substrate, wherein the second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects. method. [C19] the substrate includes a routing region and a keepout region; wherein the plurality of peripheral interconnects are located at least in part along a boundary between the routing region and the keepout region. Method according to C18. [C20] The method of C19, wherein the keep-out regions are areas of the substrate that are free of interconnects. [C21] The method of C18, wherein the plurality of peripheral interconnects are configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device. [C22] The method of C18, wherein the first integrated device includes a first power management integrated device and / or a first application processor. [C23] The method of C18, further comprising a peripheral dielectric layer overlying the solder resist layer and the plurality of peripheral interconnects.

Claims

1. A package, at least one dielectric layer; Multiple interconnections; a solder resist layer; a plurality of peripheral interconnects overlying the solder resist layer; power rails and / or power planes located within the routing region; a substrate comprising: a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; wherein: the second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects; the plurality of peripheral interconnects are configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device; the plurality of peripheral interconnects are arranged along the periphery of the routing region; package.

2. the substrate includes a routing region and a keepout region; wherein the plurality of peripheral interconnects are located at least in part along a boundary between the routing region and the keepout region. The package of claim 1.

3. The package of claim 1 , wherein the first integrated device includes a first power management integrated device and / or a first application processor.

4. The package of claim 3 , wherein the second integrated device includes a second power management integrated device and / or a second application processor.

5. The package of claim 1 , further comprising a peripheral dielectric layer overlying said solder resist layer and said plurality of peripheral interconnects.

6. further comprising a third integrated device coupled to the substrate; wherein the substrate further includes a second plurality of peripheral interconnects located over the solder resist layer; wherein the substrate further includes a third plurality of peripheral interconnects located on the solder resist layer; wherein the first integrated device is configured to be electrically coupled to the third integrated device through the second plurality of peripheral interconnects; wherein the second integrated device is configured to be electrically coupled to the third integrated device through the third plurality of peripheral interconnects. The package of claim 1.

7. 10. The package of claim 1, wherein the package is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an automotive vehicle.

8. 1. A method for fabricating a package, comprising: at least one dielectric layer; Multiple interconnections; a solder resist layer; a plurality of peripheral interconnects overlying the solder resist layer; power rails and / or power planes located within the routing region; providing a substrate comprising: coupling a first integrated device to the substrate; coupling a second integrated device to the substrate, wherein the second integrated device is configured to be electrically coupled to the first integrated device through the plurality of peripheral interconnects; the plurality of peripheral interconnects are configured to provide at least one electrical path for at least one signal between the first integrated device and the second integrated device; the plurality of peripheral interconnects are arranged along the periphery of the routing region; method.

9. the substrate includes a routing region and a keepout region; wherein the plurality of peripheral interconnects are located at least in part along a boundary between the routing region and the keepout region. The method of claim 8.

10. The method of claim 8 , wherein the first integrated device includes a first power management integrated device and / or a first application processor.

11. The method of claim 8 , further comprising a peripheral dielectric layer overlying the solder resist layer and the plurality of peripheral interconnects.

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