memory device

Abstract

To provide a novel memory device.SOLUTION: A memory device includes: a transistor; and a capacitance device. The transistor includes: a first oxidation semiconductor body; a first conductor and a second conductor that are provided onto an upper surface of the first oxidation semiconductor body; a second oxidation semiconductor body that is formed onto the first oxidation semiconductor body, and is provided between the first and second conductors; a first insulation body that is provided so as to be in contact with the second oxidation semiconductor body; and a third conductor body that is provided so as to be in contact with the first insulation body. The capacitance device includes: the second conductor; a second insulation body on the second conductor; and a fourth conductor on the second insulation body. The first oxidation semiconductor body includes a groove part having a thickness deeper than those of the first and second conductors.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the configuration of a memory device, and more particularly to the configuration of a dynamic random access memory (DRAM).

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to an element, circuit, device, or the like that can function by utilizing semiconductor characteristics. As one example, a semiconductor element such as a transistor or a diode is a semiconductor device. As another example, a circuit having a semiconductor element is a semiconductor device. As yet another example, a device including a circuit having a semiconductor element is a semiconductor device. [Background technology]

[0004] The cost of DRAM memory devices has been decreasing, and research and development into increasing capacity is being actively pursued to further reduce costs. While increasing capacity can be achieved by, for example, changing the layout of memory cells and miniaturizing elements, there are limits to how much memory cell dimensions can be reduced and how miniaturized elements can be.

[0005] As memory cell layouts, there have been disclosed a configuration in which the size of a memory cell is reduced by three-dimensionally stacking transistors using silicon (Si) in a semiconductor layer, and a configuration in which the size of a memory cell is reduced by stacking transistors using an oxide semiconductor (OS) in a semiconductor layer (hereinafter referred to as OS transistors) (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 11-40772 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-145875 Summary of the Invention [Problem to be solved by the invention]

[0007] As shown in Patent Documents 1 and 2, extensive research has been conducted into structures for reducing the dimensions of memory cells, but there is still room for improvement.

[0008] Therefore, an object of one embodiment of the present invention is to provide a novel memory device.Another object of one embodiment of the present invention is to provide a memory device with a novel structure that has an improved storage capacity and excellent data reliability.Another object of one embodiment of the present invention is to provide a memory device with a novel structure that can reduce the circuit area of ​​a memory cell and achieve miniaturization.Another object of one embodiment of the present invention is to provide a semiconductor device including the novel memory device.

[0009] It should be noted that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted as appropriate from these descriptions. It should be noted that one embodiment of the present invention solves at least one of the problems listed above and / or other problems. [Means for solving the problem]

[0010] One embodiment of the present invention includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor, a first conductor and a second conductor provided on a top surface of the first oxide semiconductor, a second oxide semiconductor formed over the first oxide semiconductor and provided between the first conductor and the second conductor, a first insulator provided in contact with the second oxide semiconductor, and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor, a second insulator on the second conductor, and a fourth conductor on the second insulator. The first oxide semiconductor has grooves that are deeper than the thicknesses of the first conductor and the second conductor.

[0011] In the above aspect, it is preferable that the second oxide semiconductor, the first insulator, and the third conductor are embedded in the groove, and the second oxide semiconductor has a curvature.

[0012] In each of the above aspects, it is preferable that the first oxide semiconductor and the second oxide semiconductor each contain indium, an element M (M is gallium, yttrium, or tin), and zinc.

[0013] In each of the above embodiments, the first oxide semiconductor preferably has a region having a higher atomic ratio of indium than the second oxide semiconductor.

[0014] In each of the above embodiments, the first oxide semiconductor and the second oxide semiconductor preferably have crystallinity.

[0015] Another aspect of the present invention is a semiconductor device having a memory device of any of the above aspects, where when the memory device is a first memory device, the semiconductor device has the first memory device, an nth (n is a natural number greater than or equal to 2) memory device on the first memory device, and a device containing silicon electrically connected to the first memory device and the nth memory device, and the device containing silicon, the first memory device, and the nth memory device are stacked in order.

[0016] In the above aspect, the nth memory device preferably includes an oxide semiconductor. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a novel memory device can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a novel structure that has improved storage capacity and excellent data reliability can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a novel structure that can reduce the circuit area of ​​a memory cell and achieve miniaturization can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including the novel memory device can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0019] [Figure 1]1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] 2A and 2B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 3] 3A and 3B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] 4A and 4B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 5 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13]13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 25B to 25D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 26B to 26D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A and 27B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 29] 29A and 29B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 30 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 31] FIG. 31 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 32] 32A and 32B are cross-sectional views illustrating the configuration of a memory device according to one embodiment of the present invention. [Figure 33] FIG. 33 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 34] 34A and 34B are block diagrams illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 35] 35A to 35H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 36]36A and 36B are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 37] 37A and 37B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 38] 38A to 38E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 39] 39A to 39C are block diagrams illustrating configuration examples of a semiconductor device according to one embodiment of the present invention. [Figure 40] Fig. 40A is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, Fig. 40B is a circuit diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and Fig. 40C is a timing chart illustrating an operation example of a semiconductor device according to one embodiment of the present invention. [Figure 41] FIG. 41 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. [Figure 42] 42A is a circuit diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and FIG 42B is a timing chart illustrating an operation example of a semiconductor device according to one embodiment of the present invention. [Figure 43] FIG. 43 is a block diagram showing a semiconductor device according to one embodiment of the present invention. [Figure 44] FIG. 44 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 45] 45A and 45B are schematic diagrams illustrating an example of an electronic component according to one embodiment of the present invention. [Figure 46] 46A to 46F are diagrams showing electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] (Embodiment 1) In this embodiment, a memory device according to one embodiment of the present invention and a semiconductor device including the memory device will be described.

[0022] A memory device of one embodiment of the present invention includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor, a first conductor and a second conductor provided on a top surface of the first oxide semiconductor, a second oxide semiconductor formed over the first oxide semiconductor and provided between the first conductor and the second conductor, a first insulator provided in contact with the second oxide semiconductor, and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor, a second insulator on the second conductor, and a fourth conductor on the second insulator. The first oxide semiconductor has grooves that are deeper than the thicknesses of the first conductor and the second conductor.

[0023] By forming a groove deeper than the thickness of the first conductor and the second conductor in the first oxide semiconductor, the second oxide semiconductor, the first insulator, and the third conductor are embedded in the groove, and the second oxide semiconductor can have a structure having curvature. Note that since a channel formation region of a transistor is provided at or near the interface between the first oxide semiconductor and the second oxide semiconductor, the second oxide semiconductor having curvature can have an effective L length longer than the L length in a plan view.

[0024] In manufacturing a transistor including an oxide semiconductor, the upper portion of the first oxide semiconductor may be slightly removed when the first conductor and the second conductor are processed, specifically, when they are etched. However, in one embodiment of the present invention, in order to increase the effective L length, the first oxide semiconductor is processed using an insulator provided on the upper portion of the first conductor and the second conductor as a mask to form the groove. The depth (length) of the groove may be larger than the thickness (film thickness) of the first conductor and the second conductor. Typically, the depth of the groove is 10 nm to 50 nm, preferably 15 nm to 30 nm. However, the depth of the groove is not limited to the above value because it depends on the thickness of the first conductor and the second conductor.

[0025] The first oxide semiconductor and the second oxide semiconductor each preferably contain indium, an element M (M is gallium, yttrium, or tin), and zinc. The first oxide semiconductor preferably has a region in which the atomic ratio of indium is higher than that of the second oxide semiconductor. By making the atomic ratio of indium higher in the first oxide semiconductor than in the second oxide semiconductor, a channel formation region can be formed on the first oxide semiconductor side.

[0026] Furthermore, when the first oxide semiconductor and the second oxide semiconductor each have crystallinity, the memory device can have high reliability. A crystalline oxide semiconductor can reduce the concentration of impurities (typically, hydrogen, water, and the like), thereby improving reliability.

[0027] The above configuration will be described in detail with reference to FIGS.

[0028] <Memory device configuration example> 1A, 1B, 2A, and 2B are diagrams illustrating a memory device 290. Fig. 1A is a top view of the memory device 290, and Fig. 1B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 1A. The cross-sectional view shown in Fig. 1B corresponds to a cross-sectional view in the channel length direction of a transistor.

[0029] 2A is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 1A, and FIG. 2B is a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 1A. The cross-sectional view in FIG. 2A corresponds to a cross-sectional view in the channel width direction of the transistor.

[0030] The memory device 290 shown in FIGS. 1A, 1B, 2A, and 2B includes a transistor, a capacitance device 292, and wiring connected to the transistor. More specifically, memory device 290 has insulator 211, insulator 212 on insulator 211, insulator 214 on insulator 212, conductor 205 (conductor 205a and conductor 205b), insulator 216 on insulator 214, insulator 222, insulator 224, oxide 230 (oxide 230a, oxide 230b, and oxide 230c), conductor 242 (conductor 242a and conductor 242b), oxide 243 (oxide 243a and oxide 243b), insulator 272, insulator 273, insulator 250, and conductor 260 (conductor 260a and conductor 260b).

[0031] An insulator 280 and an insulator 282 on the insulator 280 are provided above the oxide 230. An insulator 287 is provided in contact with the side surfaces of the insulators 212, 214, 216, 222, 224, 272, 273, 280, and 282. An insulator 283 and an insulator 284 on the insulator 283 are provided to cover the insulator 282.

[0032] The memory device 290 also includes a conductor 240a that is electrically connected to the conductor 242a and functions as a plug. An insulator 241a is provided in contact with the side surface of the conductor 240a. A conductor 246a that is electrically connected to the conductor 240a and functions as a wiring is provided on the insulator 284 and the conductor 240a. An insulator 286 is provided on the conductor 246a and the insulator 274.

[0033] The memory device 290 also includes a capacitor 292. The capacitor 292 includes a conductor 242b, an insulator 272 and an insulator 273 provided over the conductor 242b, and a conductor 294 provided over the insulator 273. That is, the capacitor 292 constitutes a metal-insulator-metal (MIM) capacitor. Note that one of a pair of electrodes included in the capacitor 292, i.e., the conductor 242b, can also serve as a source electrode or a drain electrode of a transistor. Furthermore, a dielectric layer included in the capacitor 292 can also serve as a protective layer provided in the transistor, i.e., the insulator 272 and the insulator 273. Therefore, part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitor 292, thereby providing a highly productive semiconductor device. Furthermore, one of the pair of electrodes of the capacitor 292, i.e., the conductor 242b, also serves as the source electrode or drain electrode of the transistor, which makes it possible to reduce the area in which the transistor and the capacitor are arranged.

[0034] 2B, in a cross section in the channel width direction of the transistor, the capacitive device 292 also has a region on the side surface of the conductor 242b that overlaps with the conductor 294. Since capacitance can be formed in this region as well, it is possible to increase the capacitance value even in a small area.

[0035] The conductor 294 may be made of a material that can be used for the conductor 242 described later.

[0036] In the memory device 290, the conductor 260 functions as a first gate of a transistor, the conductor 205 functions as a second gate of the transistor, and the conductor 242a and the conductor 242b function as source and drain electrodes of the transistor.

[0037] The oxide 230 functions as a semiconductor having a channel formation region of the transistor. The insulator 250 functions as a first gate insulator, and the insulators 222 and 224 function as second gate insulators.

[0038] The insulators 214, 272, and 273 function as interlayer films. The insulators 214, 272, and 273 are preferably formed using a material that has barrier properties against oxygen or a material that can absorb hydrogen. By using a material that can absorb hydrogen for the insulators 214, 272, and 273, the amount of hydrogen can be kept constant within the memory device 290. Materials that can be used for the insulators 214, 272, and 273 include Al compounds, or compounds containing Al and the element Ma (the element Ma represents an element with low electronegativity (a highly reactive element), such as Mg, Zr, Si, or B).

[0039] 1B, 2A, and 2B, the transistor included in the memory device 290 has a structure in which the insulator 282 and the oxide 230c are in contact with each other. This structure can prevent oxygen contained in the insulator 280 from diffusing toward the conductor 260. Furthermore, the oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b via the oxide 230c, thereby reducing oxygen vacancies in the oxide 230a and the oxide 230b and improving the electrical characteristics and reliability of the transistor.

[0040] 1, the conductor 260 is formed in a self-aligned manner in an opening provided in an interlayer film such as the insulator 280, via the insulator 250. That is, the conductor 260 is formed so as to fill the opening provided in the interlayer film including the insulator 280, via the insulator 250. Therefore, when arranging the conductor 260 in the region between the conductor 242a and the conductor 242b, alignment of the conductor 260 is not required.

[0041] Furthermore, it is preferable to provide the oxide 230c in an opening provided in an interlayer film including the insulator 280. Therefore, the insulator 250 and the conductor 260 have a region overlapping with the stacked structure of the oxide 230b and the oxide 230a via the oxide 230c. This structure allows the oxide 230c and the insulator 250 to be formed by successive film formation, thereby keeping the interface between the oxide 230 and the insulator 250 clean. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor in the memory device 290 can achieve high on-state current and high frequency characteristics.

[0042] 1 has a channel formation region mainly at or near the interface between the oxide 230c and the oxide 230b. The oxide 230c is formed in a U-shape so as to fit along openings formed in the insulator 280, the insulator 272, the insulator 273, the conductor 242 (the conductor 242a and the conductor 242b), the oxide 243 (the oxide 243a and the oxide 243b), and the oxide 230b.

[0043] For example, when the channel length of a transistor is miniaturized (typically 5 nm or more and less than 60 nm, preferably 10 nm or more and 30 nm or less), the effective L length can be increased by using the transistor structure of the memory device 290 shown in FIG. 1. As an example, when the distance between the conductor 242a and the conductor 242b is 20 nm, the effective L length can be increased to 40 nm or more and 60 nm or less, which is approximately two to three times longer than the distance between the conductor 242a and the conductor 242b, i.e., the minimum processing dimension. Therefore, the memory device 290 shown in FIG. 1 is one of the structures of a transistor and a capacitor device that are excellent for miniaturization.

[0044] 1, the insulator 211 is in contact with the insulator 283, and the insulators 212, 214, 287, and 282 are provided inside the insulator 283. The insulator 284 is provided outside the insulator 283. For example, it is preferable that the insulators 214, 287, and 282 are formed using a material capable of capturing and fixing hydrogen, and the insulators 211, 212, 283, and 284 are formed using a material capable of suppressing the diffusion of hydrogen and oxygen. Typically, the insulators 214, 287, and 282 can be made of aluminum oxide. Typically, the insulators 211, 212, 283, and 284 can be made of silicon nitride.

[0045] In other words, the above structure can be referred to as a double sealing structure including a first sealing structure using an aluminum oxide film and a second sealing structure using a silicon nitride film disposed outside the first sealing structure. The second sealing structure may be configured as a triple sealing structure by adding another silicon nitride film. The above structure enables control of either or both of the hydrogen concentration and the oxygen concentration in the memory device 290, thereby providing a highly reliable memory device. The memory device 290 of one embodiment of the present invention is not limited to the above structure. For example, the memory device 290 may have a structure without a sealing structure. Examples of a structure without a sealing structure are shown in FIGS. 3A, 3B, 4A, and 4B. Here, FIG. 3A corresponds to FIG. 1A, FIG. 3B corresponds to FIG. 1B, FIG. 4A corresponds to FIG. 2A, and FIG. 4B corresponds to FIG. 2B, respectively. The memory device 290 shown in FIGS. 3A, 3B, 4A, and 4B is similar to the memory device 290 shown in FIGS. 1A, 1B, 2A, and 2B, except that no sealing structure is provided.

[0046] <Application examples of memory devices> Next, application examples of the memory device 290 shown in FIGS. 1A, 1B, 2A, and 2B will be described with reference to FIGS. 5 and 6. FIG.

[0047] 5 and 6 are cross-sectional views of an example of a memory device having a structure in which a plurality of memory devices 290 are stacked in the vertical direction.

[0048] FIG. 5 illustrates a configuration in which a memory device 290_1, a memory device 290_2, and a memory device 290_n (n is a natural number equal to or greater than 3) are stacked. As illustrated in FIG. 5, the memory device 290_2 is configured such that the position of the conductor 240a functioning as a plug is arranged at a different position from that of the memory device 290_1. This configuration reduces parasitic capacitance with adjacent memory devices and increases the degree of freedom in circuit design. While the configuration illustrated in FIG. 5 illustrates a configuration in which the positions of the conductors 240a functioning as plugs are staggered between the upper and lower memory devices, the present invention is not limited to this. For example, the conductors 240a functioning as plugs and the capacitive devices 292 may be arranged by rotating them by 90° around the conductor 260 in a top view.

[0049] Alternatively, the conductors 240a functioning as plugs may be arranged at the same position in a cross-sectional view in the channel width direction. An example of such a configuration is shown in FIG. 6. The configuration shown in FIG. 6 allows, for example, adjacent memory devices to share a write bit line. That is, the bit line and the like can be shared among multiple memory devices 290, resulting in a structure advantageous for miniaturization. Note that FIG. 6 illustrates a configuration in which the conductors 240a functioning as plugs electrically connected to the bit line are shared by adjacent memory devices, but this is not limiting. For example, a structure in which the back gate electrodes of transistors and the like are shared between adjacent memory devices may be used.

[0050] 5 and 6, the memory device 290_1, the memory device 290_2, and the memory device 290_n are covered with an insulator 287, an insulator 283, and an insulator 284. The insulator 283 and the insulator 211 are in contact with each other on the outer periphery of the memory device 290_1. Above the insulator 284, the insulator 284 and the insulator 286 are in contact with each other.

[0051] Furthermore, an insulator 282, an insulator 296, an insulator 298, and an insulator 214 are provided between the memory device 290_1 and the memory device 290_2.

[0052] The insulator 296 and the insulator 298 can be made of, for example, a material similar to that of the insulator 211. For example, the insulators 282 and 214 can be made of aluminum oxide, and the insulators 296 and 298 can be made of silicon nitride.

[0053] 1 has a three-layer stack structure of insulators 211, 212, and 214 below the conductor 205, but in the transistors included in the memory devices 290_2 to 290_n shown in FIGS. 5 and 6, some of the layers formed above the transistors included in the memory devices in the lower layer can be shared, so that one or two layers can be reduced from the three-layer stack structure. In other words, by sharing some of the insulators between the upper and lower memory devices, a semiconductor device with high productivity can be obtained.

[0054] (Embodiment 2) An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described below.

[0055] In the previous embodiment, the memory device 290 was described, but in this embodiment, a transistor that can be used in the memory device 290 or components related to the transistor will be described.

[0056] <Configuration Example 1 of Semiconductor Device> 7A, 7B, 7C, and 7D are a top view and a cross-sectional view of a transistor 200 and the periphery of the transistor 200 according to one embodiment of the present invention.

[0057] FIG. 7A is a top view of a semiconductor device having a transistor 200. FIGS. 7B, 7C, and 7D are cross-sectional views of the semiconductor device. FIG. 7B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 7A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 7C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 7A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 7D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 7A. Note that some elements are omitted from the top view of FIG. 7A for clarity.

[0058] Here, in the transistor 200, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for a semiconductor including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0059] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, In-Ga oxide or In-Zn oxide may be used as the oxide semiconductor.

[0060] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely low leakage current in an off-state, and therefore can provide a semiconductor device with low power consumption. Furthermore, an oxide semiconductor can be deposited by a sputtering method or the like, and therefore can be used for the transistor 200 that constitutes a highly integrated semiconductor device.

[0061] On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to fluctuate due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0062] Therefore, it is preferable to use an oxide semiconductor having a low impurity concentration and a low density of defect states. Note that in this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic.

[0063] Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor as much as possible. Note that examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0064] In particular, hydrogen as an impurity contained in oxide semiconductors creates oxygen vacancies (V O In addition, defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) may generate carrier electrons. In addition, some of the hydrogen may react with oxygen, which bonds with metal atoms, generating carrier electrons.

[0065] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field, the reliability of the transistor may be reduced if the oxide semiconductor contains a large amount of hydrogen.

[0066] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen and oxygen vacancies are reduced as the oxide semiconductor used for the transistor.

[0067] Therefore, in order to prevent the intrusion of impurities from the outside, the transistor 200 may be sealed with a material that prevents the diffusion of impurities (hereinafter also referred to as a barrier material against impurities).

[0068] In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability), or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0069] For example, materials that have the function of suppressing the diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, etc. In particular, silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, and is therefore preferably used as a sealing material.

[0070] Furthermore, for example, materials having the function of capturing and fixing hydrogen include metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

[0071] Here, the structure for sealing the transistor 200 can be provided as a single layer or a stacked structure of two or more layers. In particular, the structure for sealing the transistor 200 is preferably provided as a stacked structure, more preferably as a nested structure.

[0072] Specifically, a description will be given of a case where the structure encapsulating the transistor 200 has a two-layer structure. The structure encapsulating the transistor 200 has a first structure adjacent to the transistor 200 and a second structure provided outside the first structure. In other words, the transistor 200 and the second structure are provided via the first structure.

[0073] In the above structure, the first structure may be made of a material that has the function of capturing and fixing hydrogen, and the second structure may be made of a material that has the function of suppressing the diffusion of hydrogen and oxygen.

[0074] By using a material that has the function of capturing and adhering hydrogen on the side close to the transistor 200, hydrogen in the transistor 200 or in the interlayer film provided between the first structure and the transistor 200 is captured and adhering to the first structure, thereby reducing the hydrogen concentration in the transistor 200.

[0075] On the other hand, the second structure seals the transistor 200 via the first structure. Therefore, the second structure prevents hydrogen diffusing from the outside of the transistor 200 from diffusing into the interior of the second structure (toward the transistor 200). In other words, the first structure can efficiently capture and fix hydrogen present in the internal structure of the second structure.

[0076] Specifically, in the above structure, a metal oxide such as aluminum oxide can be used for the first structure, and a nitride such as silicon nitride can be used for the second structure. More specifically, an aluminum oxide film can be disposed between the transistor 200 and the silicon nitride film.

[0077] Furthermore, the hydrogen concentration in the film can be reduced by appropriately setting the film formation conditions for the material used for the structure.

[0078] Generally, films formed by CVD have higher coverage than films formed by sputtering. However, the compound gas used in CVD often contains hydrogen, and films formed by CVD have a higher hydrogen content than films formed by sputtering.

[0079] Therefore, for example, a film with a reduced hydrogen concentration (specifically, a film formed by sputtering) may be used as a film close to the transistor 200. On the other hand, when a film with high coverage but a relatively high hydrogen concentration (specifically, a film formed by CVD) is used as a film for suppressing impurity diffusion, a film with a reduced hydrogen concentration and capable of capturing and fixing hydrogen may be disposed between the transistor 200 and the film with a relatively high hydrogen concentration but high coverage.

[0080] That is, a film with a relatively low hydrogen concentration is preferably used for a film disposed close to the transistor 200. On the other hand, a film with a relatively high hydrogen concentration is preferably disposed away from the transistor 200.

[0081] Specifically, in the above structure, when the transistor 200 is sealed with a silicon nitride film formed by a CVD method, an aluminum oxide film formed by a sputtering method may be disposed between the transistor 200 and the silicon nitride film formed by a CVD method. More preferably, a silicon nitride film formed by a sputtering method may be disposed between the silicon nitride film formed by a CVD method and the aluminum oxide film formed by a sputtering method.

[0082] When forming a film using a CVD method, the hydrogen concentration in the formed film may be reduced by forming the film using a compound gas that does not contain hydrogen atoms or has a low content of hydrogen atoms.

[0083] A specific configuration for sealing the transistor 200 will be described below with reference to FIG.

[0084] A semiconductor device of one embodiment of the present invention includes an insulator 211 on a substrate (not shown), an insulator 212 on the insulator 211, an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 287 covering a side surface of the insulator 280, an insulator 283 covering the insulator 282 and the insulator 287, an insulator 284 on the insulator 283, and an insulator 274 provided in contact with the insulator 284.

[0085] Note that the insulators 211, 212, 216, 214, 280, 282, 287, 283, 284, and 274 function as interlayer films.

[0086] Here, when a structure having an excess oxygen region is provided near an oxide semiconductor, excess oxygen from the structure having the excess oxygen region can be diffused into oxygen vacancies occurring in the oxide semiconductor, thereby compensating for the oxygen vacancies.

[0087] Therefore, it is preferable that the insulator 280 in contact with the oxide 230c desorbs oxygen upon heating. In this specification, oxygen desorbed upon heating may be referred to as excess oxygen. Oxygen present in excess of the stoichiometric composition may also be referred to as excess oxygen. A region where oxygen exists in excess of the stoichiometric composition may also be referred to as an excess oxygen region.

[0088] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. An oxide from which oxygen is released by heating (hereinafter also referred to as an insulator material having an excess oxygen region) is an oxide in which the amount of released oxygen molecules is 1.0 × 10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0089] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies can be used as the insulator 280. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0090] In particular, silicon oxide and silicon oxynitride are preferred for use as the insulator 280 because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are also preferred because they can easily form regions containing oxygen that is released by heating. The insulator 280 may also have a laminated structure of the above materials, such as a laminated structure of silicon oxide formed by sputtering and a silicon oxynitride film formed by CVD on top of it. Silicon nitride may also be laminated on top of this.

[0091] To provide an excess oxygen region in the insulator 280, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator 280 to form a region containing excess oxygen.

[0092] Specifically, one example of the oxygen introduction treatment is a method of stacking a metal oxide using a sputtering apparatus on the insulator 280. For example, by using a sputtering apparatus to form the insulator 282 under an oxygen gas atmosphere, oxygen can be introduced into the insulator 280 while the insulator 282 is being formed.

[0093] In particular, it is preferable to use silicon oxynitride as the insulator 280 and aluminum oxide as the insulator 282. By forming an aluminum oxide film over a silicon oxynitride film by a sputtering method, an excess oxygen region can be formed in the silicon oxide film that is the film formation target.

[0094] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 be reduced.

[0095] Furthermore, by using a material that has barrier properties against impurities for the insulators 211, 212, 214, 282, 287, 283, and 284, the oxide semiconductor included in the transistor 200 can be kept highly pure and intrinsic.

[0096] Specifically, the insulator 214, the insulator 287, and the insulator 282 form a structure that seals the transistor 200 and the insulator 280 (hereinafter also referred to as a sealing structure). For example, as shown in FIG. 7, the insulator 214 is provided below the transistor 200, and the insulator 282 is provided above the transistor 200. The insulator 287 is provided in a sidewall shape on the side surface of the transistor 200. Furthermore, the bottom end of the sidewall-shaped insulator 287 contacts the end of the insulator 214, and the top end of the insulator 287 contacts the end of the insulator 282.

[0097] Here, it is preferable that the insulator 287 and the insulator 214 are in secure contact with each other. Therefore, in order to provide a region where the insulators 214 and 287 are in secure contact with each other, it is preferable to provide the insulator 287 so as to be in contact with the side surface of the insulator 212 provided below the insulator 214.

[0098] Therefore, the insulator 214, the insulator 287, and the insulator 282 form a structure surrounding the transistor 200.

[0099] Here, the same material is used for the insulator 214, the insulator 287, and the insulator 282. Preferably, the insulator 214, the insulator 287, and the insulator 282 are formed under the same conditions. When the insulator 214, the insulator 287, and the insulator 282, which have the same film quality, are in contact with each other, a highly airtight sealing structure can be formed.

[0100] Furthermore, a material capable of capturing and fixing hydrogen is preferably used for the insulators 214, 287, and 282. Specifically, a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used.

[0101] The insulator 214, the insulator 287, and the insulator 282 that form the sealing structure are provided in contact with the transistor 200 or the insulator 280. Therefore, hydrogen mixed in the transistor 200 or the insulator 280 can be captured and fixed, thereby reducing the hydrogen concentration in the oxide semiconductor included in the transistor 200.

[0102] Furthermore, the insulators 214 , 287 , and 282 that are the structure that seals the transistor 200 are surrounded by a sealing structure provided by the insulators 211 , 212 , and 283 .

[0103] 7, for example, insulators 211 and 212 are arranged below insulator 214, and insulator 283 is provided to cover insulators 287 and 282. Furthermore, outside the structure that seals transistor 200, which is provided by insulators 214, 287, and 282, insulator 211 and insulator 283 come into contact with each other, thereby forming a second sealing structure.

[0104] Here, it is preferable to use a material that has a function of suppressing the diffusion of hydrogen and oxygen for the insulators 211, 212, and 283. In particular, silicon nitride or silicon nitride oxide has a high barrier property against hydrogen, and is therefore preferably used as an insulator that forms a sealing structure.

[0105] Furthermore, an insulator 284 with high coverage is preferably provided above the insulator 283 that covers the upper side of the transistor 200. Note that the insulator 284 is preferably made of the same material as the insulators 211, 212, and 283.

[0106] For example, the insulators 212 and 283 can be formed by sputtering, whereby a sealing structure can be provided using a film with a relatively low hydrogen concentration.

[0107] On the other hand, films formed by sputtering have relatively low coverage. Therefore, by forming the insulators 211 and 284 by a method such as CVD, which has high coverage, the sealing performance can be further improved.

[0108] Therefore, it is preferable that the insulators 212 and 283 have a lower hydrogen concentration than the insulators 211 and 284.

[0109] Note that a material having a barrier property against oxygen may be used for the insulators 211, 212, 214, 282, 287, 283, and 284. When the sealing structure has a barrier property against oxygen, it can suppress outward diffusion of excess oxygen contained in the insulator 280 and efficiently supply oxygen to the transistor 200.

[0110] The semiconductor device of one embodiment of the present invention also includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 200 and functioning as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. Over the insulator 284 and the conductor 240, a conductor 246 (conductor 246a and conductor 246b) electrically connected to the conductor 240 and functioning as a wiring is provided. Over the conductor 246 and the insulator 274, an insulator 286 is provided.

[0111] Here, insulator 241 (insulator 241a or insulator 241b) is provided in contact with the inner walls of the openings provided in insulator 272, insulator 273, insulator 280, insulator 282, insulator 283, and insulator 284, and a first conductor of conductor 240 (conductor 240a or conductor 240b) is provided in contact with the side surface of insulator 241, and a second conductor of conductor 240 is provided further inside.

[0112] The height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 284 can be approximately the same. Also, while Fig. 7 shows a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured as a single layer or a stacked structure of three or more layers.

[0113] Furthermore, it is preferable that the conductors 240a and 240b be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure. While the conductors 240a and 240b are shown as being circular in top view in FIG. 7A, this is not limiting. For example, the conductors 240a and 240b may be substantially circular, such as an ellipse, polygonal, such as a rectangle, or polygonal, such as a rectangle, with rounded corners, in top view.

[0114] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen, may be used in a single layer or a layered structure. By using such a conductive material, it is possible to further reduce the intrusion of impurities such as water or hydrogen that diffuse from the insulator 280 into the oxide 230 through the conductors 240a and 240b. It is also possible to prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a and 240b.

[0115] The insulators 241a and 241b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulators 284, 283, 282, 273, and 272, and therefore can prevent impurities such as water or hydrogen from the insulator 274 and the like from mixing into the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0116] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surfaces of the conductors 240a and 240b, functioning as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0117] [Transistor 200] As shown in FIG. 7, the transistor 200 includes an insulator 216, a conductor 205 (conductor 205a and conductor 205b), an insulator 222, an insulator 224, an oxide 230 (oxide 230a, oxide 230b, and oxide 230c), a conductor 242 (conductor 242a and conductor 242b), an oxide 243 (oxide 243a and oxide 243b), an insulator 272, an insulator 273, an insulator 250, and a conductor 260 (conductor 260a and conductor 260b).

[0118] In the transistor 200, the conductor 260 functions as a first gate of the transistor, the conductor 205 functions as a second gate of the transistor, and the conductor 242a and the conductor 242b function as a source electrode and a drain electrode.

[0119] The oxide 230 functions as a semiconductor having a channel formation region.

[0120] Insulator 250 serves as a first gate insulator, and insulators 222 and 224 serve as second gate insulators.

[0121] In the transistor 200 shown in FIG. 7, a conductor 260 is formed in a self-aligned manner in an opening provided in an interlayer film such as an insulator 280 with an insulator 250 interposed therebetween.

[0122] That is, the conductor 260 is formed so as to fill the opening provided in the interlayer film including the insulator 280 via the insulator 250. Therefore, when placing the conductor 260 in the region between the conductor 242a and the conductor 242b, alignment of the conductor 260 is not required.

[0123] Furthermore, it is preferable to provide the oxide 230c in an opening provided in the interlayer film including the insulator 280. Therefore, the insulator 250 and the conductor 260 have a region overlapping with the stacked structure of the oxide 230b and the oxide 230a via the oxide 230c. This structure enables the oxide 230c and the insulator 250 to be formed by successive film formation, thereby keeping the interface between the oxide 230 and the insulator 250 clean. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can achieve high on-state current and high frequency characteristics.

[0124] 7, the bottom and side surfaces of the conductor 260 are in contact with the insulator 250. The bottom and side surfaces of the insulator 250 are in contact with the oxide 230c.

[0125] 7B and 7C, the transistor 200 has a structure in which the insulator 282 and the oxide 230c are in direct contact with each other. This structure can suppress the diffusion of oxygen contained in the insulator 280 into the conductor 260.

[0126] Therefore, the oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b via the oxide 230c, thereby reducing oxygen vacancies in the oxide 230a and the oxide 230b and improving the electrical characteristics and reliability of the transistor 200.

[0127] A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0128] In the transistor 200, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

[0129] For example, a metal oxide that functions as an oxide semiconductor preferably has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large energy gap, the leakage current (off-state current) of the transistor 200 in a non-conducting state can be made extremely small. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0130] Specifically, it is preferable to use a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) as oxide 230. In particular, it is preferable to use aluminum, gallium, yttrium, or tin as element M. It is also possible to use In-M oxide, In-Zn oxide, or M-Zn oxide as oxide 230.

[0131] 7, the oxide 230 preferably includes an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230c disposed on the oxide 230b and at least a portion of which is in contact with the top surface of the oxide 230b. Here, the side surfaces of the oxide 230c are preferably in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272, the insulator 273, and the insulator 280.

[0132] That is, the oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Furthermore, by providing the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230c to the oxide 230b.

[0133] Although the transistor 200 has a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c stacked in the channel formation region and its vicinity, the present invention is not limited to this structure. For example, the present invention may have a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers. For example, the oxide 230c may have a two-layer structure, and a four-layer stacked structure may be formed.

[0134] Furthermore, the oxide 230 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 230a is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 230b. Furthermore, the atomic ratio of element M to In in the metal oxide used for the oxide 230a is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. Furthermore, the atomic ratio of In to element M in the metal oxide used for the oxide 230b is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230a. Furthermore, the oxide 230c can be the same metal oxide that can be used for the oxide 230a or the oxide 230b.

[0135] Specifically, the oxide 230a may be a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The oxide 230b may be a metal oxide with an atomic ratio of In:Ga:Zn=4:2:3 or 1:1:1. The oxide 230c may be a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a layered structure of Ga:Zn=2:1 [atomic ratio] and In:Ga:Zn=4:2:3 [atomic ratio], a layered structure of Ga:Zn=2:5 [atomic ratio] and In:Ga:Zn=4:2:3 [atomic ratio], and a layered structure of gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio].

[0136] The oxide 230b may be crystalline. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. Furthermore, even when heat treatment is performed, the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process because the extraction of oxygen from the oxide 230b can be reduced.

[0137] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216.

[0138] Here, the conductor 260 may function as a first gate (also referred to as a top gate), and the conductor 205 may function as a second gate (also referred to as a bottom gate).

[0139] When the conductor 205 functions as a gate electrode, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0140] As shown in FIG. 7A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 7C, the conductor 205 preferably extends to an area outside the end of the oxide 230 that intersects with the channel width direction. That is, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other through an insulator. Alternatively, providing a large conductor 205 may alleviate local charging (referred to as charge-up) in plasma treatment in manufacturing processes after the formation of the conductor 205. However, one embodiment of the present invention is not limited thereto. The conductor 205 may overlap at least the oxide 230 located between the conductors 242a and 242b.

[0141] Furthermore, it is preferable that, with respect to the bottom surface of insulator 224, the height of the bottom surface of conductor 260 in the region where oxide 230a and oxide 230b do not overlap with conductor 260 is positioned at a lower position than the height of the bottom surface of oxide 230b.

[0142] As shown in Figure 7C, the conductor 260 functioning as a gate has a structure in which the side and top surfaces of the oxide 230b in the channel formation region are covered via the oxide 230c and the insulator 250. This makes it easier for the electric field generated by the conductor 260 to affect the entire channel formation region generated in the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. In this specification, a transistor structure in which the electric fields of the first and second gates electrically surround the channel formation region is referred to as a surrounded channel (S-channel) structure.

[0143] Conductor 205a is preferably a conductor that inhibits the permeation of impurities such as water or hydrogen, and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Conductor 205b is preferably a conductive material containing tungsten, copper, or aluminum as a main component. While conductor 205 is illustrated as having two layers, it may also have a multi-layer structure of three or more layers.

[0144] Here, it is preferable to successively form different types of films, that is, an oxide semiconductor, an insulator or conductor located under the oxide semiconductor, and an insulator or conductor located over the oxide semiconductor, without exposure to the atmosphere, because this allows the formation of a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (particularly, hydrogen and water) is reduced.

[0145] At least one of the insulators 272 and 273 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, at least one of the insulators 222, 272, and 273 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0146] For example, it is preferable to use silicon nitride or silicon nitride oxide as the insulator 273, and aluminum oxide or hafnium oxide as the insulator 272.

[0147] This can prevent impurities such as water or hydrogen from diffusing from the substrate side to the transistor 200 side through the insulator 222. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side through the insulator 222.

[0148] Furthermore, it is possible to prevent impurities such as water or hydrogen from diffusing from the insulator 280 or the like disposed between the insulators 272 and 273 toward the transistor 200. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 272 and 273, which have the function of preventing the diffusion of impurities such as water or hydrogen and oxygen.

[0149] The insulator 222 and the insulator 224 function as gate insulators.

[0150] Here, the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0151] Specifically, it is preferable to use an oxide material from which a portion of oxygen is desorbed by heating as the insulator 224. The oxide material from which oxygen is desorbed by heating is an oxide material from which the amount of desorbed oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0152] The insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224 and the oxide 230 with the insulator 222 and the insulator 283, impurities such as water or hydrogen can be prevented from entering the transistor 200 from the outside.

[0153] Furthermore, it is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. The insulator 222 is preferable because it has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the oxide 230 below the insulator 222. Furthermore, it can suppress the reaction of the conductor 205 with the insulator 224 and the oxygen contained in the oxide 230.

[0154] The insulator 222 may be an insulator containing oxide of one or both of insulating materials, aluminum and hafnium. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing oxide of one or both of aluminum and hafnium. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 and the intrusion of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200.

[0155] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0156] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0157] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0158] Alternatively, the oxide 243 (oxide 243a and oxide 243b) may be disposed between the oxide 230b and the conductor 242 (conductor 242a and conductor 242b) that functions as a source electrode or a drain electrode. This prevents the conductor 242 from contacting the oxide 230, thereby preventing the conductor 242 from absorbing oxygen from the oxide 230. In other words, preventing the conductor 242 from being oxidized can prevent a decrease in the conductivity of the conductor 242. Therefore, it is preferable that the oxide 243 has a function of suppressing the oxidation of the conductor 242.

[0159] Therefore, the oxide 243 preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or a drain electrode, and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b can be reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0160] A metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, oxide 243 may be gallium oxide. Alternatively, oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0161] It should be noted that the oxide 243 does not necessarily have to be provided. In that case, when the conductor 242 (conductor 242a and conductor 242b) comes into contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 242, causing the conductor 242 to oxidize. When the conductor 242 oxidizes, the conductivity of the conductor 242 is likely to decrease. The diffusion of oxygen in the oxide 230 into the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230.

[0162] Furthermore, oxygen in the oxide 230 diffuses into the conductor 242 (conductor 242a and conductor 242b), which may result in the formation of a heterogeneous layer between the conductor 242a and the oxide 230b, and between the conductor 242b and the oxide 230b. Since the heterogeneous layer contains more oxygen than the conductor 242, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 242, the heterogeneous layer, and the oxide 230b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0163] It should be noted that the above-mentioned different layer is not limited to being formed between the conductor 242 and the oxide 230b, but may also be formed, for example, between the conductor 242 and the oxide 230c, between the conductor 242 and the oxide 230b, and between the conductor 242 and the oxide 230c.

[0164] The conductors 242 (conductors 242a and 242b) functioning as a source electrode and a drain electrode are provided over the oxide 243. The thickness of the conductors 242 is, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.

[0165] The conductor 242 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing the above metal elements or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel are preferred. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are also preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0166] The insulator 272 is preferably provided in contact with the top surface of the conductor 242 and functions as a barrier layer. This structure can prevent the conductor 242 from absorbing excess oxygen contained in the insulator 280. Furthermore, by preventing oxidation of the conductor 242, an increase in contact resistance between the transistor 200 and wiring can be suppressed. Therefore, the transistor 200 can have good electrical characteristics and reliability.

[0167] Therefore, the insulator 272 preferably has a function of suppressing oxygen diffusion. For example, the insulator 272 preferably suppresses oxygen diffusion more easily than the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Alternatively, as the insulator 272, for example, an insulator containing aluminum nitride may be used.

[0168] 7D, insulator 272 contacts a portion of the upper surface of conductor 242b and the side surface of conductor 242b. Although not shown, insulator 272 contacts a portion of the upper surface of conductor 242a and the side surface of conductor 242a. Insulator 273 is disposed on insulator 272. By doing so, for example, oxygen added to insulator 280 can be prevented from being absorbed by conductor 242.

[0169] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0170] Like the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen when heated. By providing the insulator 250, which releases oxygen when heated, in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b. Also, like the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0171] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0172] Furthermore, the metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 250 and the metal oxide, it is possible to achieve a stacked structure that is thermally stable and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0173] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0174] Alternatively, the metal oxide may function as a part of the gate. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0175] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as a gate. Alternatively, the conductive material containing the metal element and nitrogen described above may be used. Also, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0176] Although the conductor 260 is shown as having a two-layer structure in FIG. 7, it may have a single-layer structure or a laminated structure of three or more layers.

[0177] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0178] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0179] Furthermore, it is preferable that the conductor 260b be made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 260 also functions as wiring, it is preferable that a conductor with high conductivity be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 260b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0180] <<Semiconductor Device Variation 1>> An example of a semiconductor device including the transistor 200 of one embodiment of the present invention will be described below with reference to FIG.

[0181] Here, A in Fig. 8 shows a top view. Fig. 8B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 8A. Fig. 8C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 8A. Fig. 8D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 8A. In the top view of Fig. 8A, some elements are omitted for clarity.

[0182] 8 differs from the semiconductor device illustrated in FIG. 7 in that the top surface of the insulator 212 is in contact with the insulator 283. Specifically, the insulator 212 is preferably provided to extend below the insulator 283. In addition, the thickness of the insulator 212 in a region overlapping with the transistor 200 might be thicker than the thickness of the region in contact with the insulator 283.

[0183] <<Semiconductor Device Modification Example 2>> An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below with reference to FIG.

[0184] Here, A in Fig. 9 shows a top view. Fig. 9B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 9A. Fig. 9C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 9A. Fig. 9D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 9A. In the top view of Fig. 9A, some elements are omitted for clarity.

[0185] For example, when the insulators 211 and 284 are formed by a CVD method using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content, the insulators 212 and 283 do not necessarily need to be provided, as shown in FIG. 9.

[0186] Alternatively, for example, the insulators 211, 212, 283, and 284 can be formed by a CVD method using a compound gas that does not contain hydrogen atoms or that contains a small amount of hydrogen atoms. That is, the hydrogen concentrations in the insulators 211, 212, 283, and 284 may be reduced to reduce hydrogen entering the channel formation region of the oxide semiconductor.

[0187] For example, in the formation of a film containing silicon atoms such as silicon nitride, a gas containing molecules containing silicon atoms is mainly used as the film formation gas. In order to reduce the hydrogen contained in the film to be formed, it is preferable that the molecules containing silicon atoms contain fewer hydrogen atoms, and it is more preferable that the molecules containing silicon atoms do not contain hydrogen atoms. Of course, it is also preferable that film formation gases other than the gas containing molecules containing silicon atoms contain fewer hydrogen atoms, and it is more preferable that they do not contain hydrogen atoms.

[0188] The molecules containing silicon atoms as shown above are called Si x -R yIn this example, the functional group R can be at least one of an isocyanate group (-N=C=O), a cyanate group (-OC≡N), a cyano group (-C≡N), a diazo group (=N2), an azide group (-N3), a nitroso group (-NO), and a nitro group (-NO2). For example, 1≦x≦3 and 1≦y≦8 may be satisfied. Examples of such molecules containing silicon atoms include tetraisocyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate silane, and octaisocyanate silane. While molecules in which the same type of functional group is bonded to the silicon atom have been exemplified here, the present embodiment is not limited to this. Different types of functional groups may also be bonded to the silicon atom.

[0189] Furthermore, for example, a halogen (Cl, Br, I, or F) may be used as the functional group R. For example, 1≦x≦2 and 1≦y≦6 may be satisfied. Examples of molecules containing silicon atoms include tetrachlorosilane (SiCl4) and hexachlorodisilane (Si2Cl6). Although an example in which chlorine is used as the functional group has been shown, halogens other than chlorine, such as bromine, iodine, and fluorine, may also be used as the functional group. Also, a different type of halogen may be bonded to the silicon atom.

[0190] The insulators 211, 212, 283, and 284 may be formed by chemical vapor deposition (CVD) using a gas having molecules containing silicon atoms as described above. The CVD method has a relatively fast film formation rate and is therefore suitable for forming thick insulator films.

[0191] As the CVD method, it is preferable to use a plasma-enhanced CVD (PECVD) method that uses plasma, or a thermal CVD (TCVD) method that uses heat. When using a thermal CVD method, an atmospheric pressure CVD (APCVD) method that forms a film under atmospheric pressure may be used, or a low pressure CVD (LPCVD) method that forms a film under a reduced pressure lower than atmospheric pressure may be used.

[0192] When forming the insulators 211, 212, 283, and 284 using a CVD method, it is preferable to use an oxidizer. As the oxidizer, it is preferable to use a gas that does not contain hydrogen atoms, such as O2, O3, NO, NO2, N2O, N2O3, N2O4, N2O5, CO, or CO2.

[0193] Alternatively, the insulators 211, 212, 283, and 284 may be deposited by atomic layer deposition (ALD). In the ALD method, a first source gas (hereinafter referred to as a precursor, which may also be referred to as a precursor or a metal precursor) and a second source gas (hereinafter referred to as a reactant, which may also be referred to as a reactant or a non-metal precursor) for the reaction are alternately introduced into a chamber, and the introduction of these source gases is repeated to deposit the film.

[0194] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer by switching between source gases. Therefore, the ALD method can form ultrathin films, films on structures with high aspect ratios, films with few defects such as pinholes, and films with excellent coverage. Therefore, the ALD method is suitable for forming the insulators 250 and 224 of the transistor 200, in addition to the insulators 211, 212, 283, and 284.

[0195] The ALD method may be a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, or a plasma enhanced ALD (PEALD) method in which a plasma excited reactant is used.

[0196] When the ALD method is used, a gas having molecules containing silicon atoms may be used as a precursor and the oxidizing agent may be used as a reactant, which can significantly reduce the amount of hydrogen absorbed into insulators 216, 274, 280, 224, and 250.

[0197] Although the above describes an example in which the silicon-containing molecule does not contain hydrogen atoms, the present embodiment is not limited to this. The silicon-containing molecule may have a configuration in which some of the functional groups bonded to the silicon atoms are substituted with hydrogen atoms. However, it is preferable that the silicon-containing molecule contains fewer hydrogen atoms than silane (SiH4). That is, it is preferable that the silicon-containing molecule has three or fewer hydrogen atoms per silicon atom. Furthermore, it is more preferable that the gas containing the silicon-containing molecule has three or fewer hydrogen atoms per silicon atom.

[0198] As described above, by forming at least one of insulator 211, insulator 212, insulator 283, and insulator 284 using a film formation method using a gas in which hydrogen atoms have been reduced or removed, the amount of hydrogen contained in these insulators can be reduced.

[0199] Therefore, by doubly sealing the transistor 200 and the insulator 280 with a first sealing structure using a material that captures or fixes impurities such as hydrogen, and a second sealing structure using a material that suppresses the diffusion of impurities such as hydrogen, the hydrogen concentration within the sealed area can be reduced and the amount of hydrogen that enters from the outside can be further reduced.

[0200] <<Metal oxides>> It is preferable to use a metal oxide that functions as an oxide semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0201] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0202] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0203] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0204] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0205] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0206] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they can also have non-regular hexagonal shapes. Furthermore, the lattice arrangement of CAAC-OS can be pentagonal, heptagonal, or other shapes due to distortion. It is difficult to identify clear grain boundaries in CAAC-OS, even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0207] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0208] CAAC-OS is a metal oxide with high crystallinity. Because it is difficult to identify clear grain boundaries in CAAC-OS, it is unlikely that the electron mobility will decrease due to grain boundaries. Furthermore, because the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0209] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0210] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable to make it into smaller crystals (for example, the above-mentioned nanocrystals) than larger crystals (here, crystals of a few millimeters or a few centimeters).

[0211] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0212] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0213] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0214] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor is likely to have normally-on characteristics.

[0215] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear and may behave like fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0216] Furthermore, the presence of impurities in the channel formation region of the oxide semiconductor may reduce the crystallinity of the channel formation region or the crystallinity of an oxide provided in contact with the channel formation region. The low crystallinity of the channel formation region tends to reduce the stability or reliability of the transistor. Furthermore, the low crystallinity of the oxide provided in contact with the channel formation region may form an interface state, which may reduce the stability or reliability of the transistor.

[0217] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in and around a channel formation region of an oxide semiconductor, such as hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0218] Specifically, the concentration of the impurities measured by SIMS in the channel formation region of the oxide semiconductor and its vicinity is set to 1×10 18 atoms / cm 3Less than or equal to 2 x 10 16 atoms / cm 3 or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, as determined by elemental analysis using EDX, is set to 1.0 atomic % or less. When an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0219] Furthermore, metal oxides with reduced impurity concentrations have a low defect state density, and therefore may also have a low trap state density.

[0220] In addition, when hydrogen enters an oxygen vacancy in a metal oxide, the oxygen vacancy and hydrogen bond to form V O May form H. V O H acts as a donor and can generate carrier electrons. Also, some of the hydrogen can bond with oxygen that bonds with metal atoms, generating carrier electrons.

[0221] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field, the reliability of the transistor may be reduced if the oxide semiconductor contains a large amount of hydrogen.

[0222] That is, V in metal oxides O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with a sufficiently reduced amount of H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygen addition treatment).O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0223] In addition, it is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. To reduce the carrier concentration of an oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as being highly pure intrinsic or substantially highly pure intrinsic. Examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0224] In particular, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons, which serve as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0225] A defect where hydrogen enters an oxygen vacancy (V O H) may function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation may be performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0226] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0227] The carrier concentration of the oxide semiconductor in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0228] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0229] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0230] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0231] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0232] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0233] <Method for manufacturing semiconductor device> Next, a manufacturing method of a semiconductor device including the transistor 200 according to the present invention shown in FIG. 7 will be described with reference to FIGS. 10 to 26. In FIGS. 10 to 26, A in each figure is a top view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in A, which is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in A, which is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in A. Note that some elements are omitted from the top view A in each figure for clarity.

[0234] First, a substrate (not shown) is prepared, and then an insulator 211 is formed on the substrate. The insulator 211 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0235] CVD methods can be classified into plasma CVD (PECVD), which uses plasma; thermal CVD, which uses heat; and photo-CVD, which uses light. They can also be divided into metal CVD and metal organic CVD, depending on the source gas used. Furthermore, they can be divided into atmospheric pressure CVD, which deposits films under atmospheric pressure, and low-pressure CVD, which deposits films under reduced pressure below atmospheric pressure, depending on the pressure during film formation.

[0236] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0237] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0238] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD method utilizes plasma, which can be preferable because it allows film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0239] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0240] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0241] In this embodiment, a silicon nitride film is formed as the insulator 211 by a CVD method. Next, an insulator 212 is formed on the insulator 211. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed as the insulator 212 by a sputtering method.

[0242] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0243] By using an insulator that is impermeable to copper, such as silicon nitride, as the insulators 211 and 212 and further disposing the insulator 214 on the insulator 212, even if a metal that easily diffuses, such as copper, is used in a conductor in a layer (not shown) below the insulator 211, the metal can be prevented from diffusing into the upper layer via the insulators 211 and 212. Furthermore, by using an insulator that is impermeable to impurities such as water or hydrogen, such as silicon nitride, the diffusion of impurities such as water or hydrogen from the layer below the insulator 211 can be prevented.

[0244] It is preferable that the hydrogen concentration of the insulator 212 is lower than that of the insulator 211, and that the hydrogen concentration of the insulator 214 is lower than that of the insulator 212. By forming the insulator 212 using silicon nitride by a sputtering method, it is possible to form silicon nitride having a lower hydrogen concentration than the insulator 211, which is formed using a CVD method. Furthermore, by using aluminum oxide for the insulator 214, it is possible to form the insulator 214 with a lower hydrogen concentration than the insulator 212.

[0245] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration be placed farther from the transistor 200.

[0246] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. The insulator 216 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration in the insulator 216 to be reduced.

[0247] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may also refer to a region in which an opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if a silicon oxide film or a silicon oxynitride film is used for the insulator 216 that forms the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0248] After the openings are formed, a conductive film that will become the conductor 205a is formed. It is desirable that the conductive film contain a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, it can be a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that will become the conductor 205a can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0249] In this embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, a tantalum nitride film is formed by sputtering, and then titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used in the conductive film that becomes the conductor 205b (described later), the metal can be prevented from diffusing out of the conductor 205a.

[0250] Next, a conductive film that will become the conductor 205b is formed. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a low-resistance conductive material such as copper is deposited as the conductive film that will become the conductor 205b.

[0251] Next, a chemical mechanical polishing (CMP) process is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductors 205a and 205b remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface. Note that the CMP process may remove a portion of the insulator 216 (see FIG. 10).

[0252] In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but this embodiment is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and a part of the insulator 216 may be removed by performing CMP processing on the insulator 216, thereby exposing the surface of the conductor 205.

[0253] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0254] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0255] Next, the insulator 224 is deposited on the insulator 222. The insulator 224 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 224. The insulator 224 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 will be the insulator 224 in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0256] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by another heat treatment in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0257] In this embodiment, treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour, and then treatment is continuously performed in an oxygen atmosphere at 400° C. for 1 hour. By this heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.

[0258] Alternatively, the heat treatment may be performed after the formation of the insulator 222. The heat treatment can be performed under the above-described heat treatment conditions.

[0259] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies high-frequency waves such as RF to the substrate side may be used. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not necessary.

[0260] Here, an aluminum oxide film may be formed on the insulator 224 by, for example, a sputtering method, and then CMP may be performed on the aluminum oxide until it reaches the insulator 224. This CMP can flatten and smooth the surface of the insulator 224. Placing the aluminum oxide on the insulator 224 and then performing CMP facilitates detection of the CMP endpoint. Furthermore, CMP may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later, potentially preventing a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0261] Next, oxide film 230A and oxide film 230B are sequentially formed on insulator 224 (see FIG. 10). Preferably, the oxide films are formed successively without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide film 230A and oxide film 230B, and to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0262] The oxide film 230A and the oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0263] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the In-M-Zn oxide target can be used.

[0264] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A should be 70% or more, preferably 80% or more, and more preferably 100%.

[0265] When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can achieve relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can achieve relatively high reliability.

[0266] In this embodiment, oxide film 230A is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:1:0.5 (2:2:1) or 1:3:4. Oxide film 230B is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=4:2:4.1 or 1:1:1. Each oxide film can be formed according to the desired characteristics of oxide 230 by appropriately selecting the film formation conditions and atomic ratio.

[0267] Next, a heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as water and hydrogen from the oxide film 230A and the oxide film 230B. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour.

[0268] Next, an oxide film 243A is formed on the oxide film 230B (see FIG. 10). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:3:4.

[0269] Next, a conductive film 242A is formed on the oxide film 243A (see FIG. 10). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0270] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into island shapes using lithography to form the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B (see FIG. 11). Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B are formed so that at least a portion of each overlaps the conductor 205. This processing can be performed using a dry etching method or a wet etching method. Processing using the dry etching method is suitable for fine processing. Note that during this process, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may become thin.

[0271] In the lithography method, first, a resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique can also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Instead of the light described above, an electron beam or an ion beam can also be used. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0272] Alternatively, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0273] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high density plasma source.

[0274] Furthermore, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B are approximately perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B are approximately perpendicular to the top surface of the insulator 222, it becomes possible to reduce the area and increase the density when providing multiple transistors 200. However, this is not limited thereto, and a configuration in which the angles formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B and the top surface of the insulator 222 are low may also be used.

[0275] Next, the insulator 272 is formed over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B (see FIG. 12). The insulator 272 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is formed as the insulator 272 by a sputtering method. By forming aluminum oxide by a sputtering method, oxygen can be injected into the insulator 224.

[0276] Next, the insulator 273 is deposited on the insulator 272 (see FIG. 12). The insulator 273 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In the embodiment, a silicon nitride film is deposited as the insulator 273 by sputtering.

[0277] Next, the insulator 280 is formed. The insulator 280 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed as the insulator 280 using a sputtering method, and a silicon oxide film can be formed thereon using a PEALD method or a thermal ALD method. Furthermore, the insulator 280 is preferably formed using a film formation method using a gas in which hydrogen atoms have been reduced or removed as described above. This allows the hydrogen concentration in the insulator 280 to be reduced.

[0278] Next, the insulator 280 is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIG. 13). Note that, similar to the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed on the aluminum oxide until it reaches the insulator 280.

[0279] Next, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the conductor layer 242B, and a portion of the oxide layer 243B are processed to form an opening that reaches the oxide 230b (see FIG. 14). The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed.

[0280] A portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the oxide layer 243B, and a portion of the conductor layer 242B can be processed by dry etching or wet etching. Dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 273 may be processed by wet etching, the insulator 272 may be processed by dry etching, and the oxide layer 243B and a portion of the conductor layer 242B may be processed by dry etching.

[0281] By performing processes such as dry etching, impurities originating from etching gases may adhere to or diffuse into the surface or interior of oxide 230a, oxide 230b, etc. Examples of impurities include fluorine and chlorine.

[0282] Cleaning is performed to remove the above-mentioned impurities, etc. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate.

[0283] For wet cleaning, a cleaning treatment may be performed using an aqueous solution of oxalic acid, phosphoric acid, ammonia water, or hydrofluoric acid diluted with carbonated water or pure water, or ultrasonic cleaning using pure water or carbonated water.

[0284] Previous processes such as dry etching or the cleaning process described above may result in the film thickness of the regions of oxide 230b that do not overlap with oxide 243a and oxide 243b being thinner than the film thickness of the regions of oxide 230b that overlap with oxide 243a and oxide 243b (see Figure 14).

[0285] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed, for example, at a temperature of 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0286] Next, the oxide film 230C is formed (see FIG. 15). A heat treatment may be performed before the formation of the oxide film 230C. The heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed immediately after the heat treatment without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b can be further reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower, more preferably 150°C or higher and 350°C or lower. In this embodiment, the heat treatment is performed at a temperature of 200°C under reduced pressure.

[0287] Here, it is preferable that oxide film 230C is provided so as to be in contact with at least a portion of the upper surface of oxide 230b, a portion of the side surface of oxide 243, a portion of the side surface of conductor 242, a portion of the side surface of insulator 272, a portion of the side surface of insulator 273, and a portion of the side surface of insulator 280. By being surrounded by oxide 243, insulator 272, insulator 273, and oxide film 230C, conductor 242 can be prevented from decreasing in conductivity due to oxidation of conductor 242 in subsequent steps.

[0288] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 230C is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 230C is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:3:4.

[0289] The oxide film 230C may be a laminated film. For example, a film may be formed by sputtering using a target with an atomic ratio of In:Ga:Zn=4:2:4.1, followed by a film formed by using a target with an atomic ratio of In:Ga:Zn=1:3:4.

[0290] During the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, during the formation of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%.

[0291] Next, a heat treatment may be performed. Alternatively, the heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. By performing the heat treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is set to 200°C.

[0292] Next, an insulating film 250A is formed on the oxide film 230C (see FIG. 15). The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A will become the insulator 250 that will be in contact with the oxide 230c in a later process, it is preferable that the hydrogen concentration be reduced in this way.

[0293] Next, high frequency waves such as microwaves or RF may be applied. The applied high frequency waves such as microwaves or RF penetrate into the insulator 280, the oxide 230b, and the oxide 230a, and remove hydrogen therein. In particular, in the oxide 230a and the oxide 230b, V O A reaction occurs in which the bonds of H are broken, resulting in dehydrogenation. Some of the hydrogen generated at this time may be removed from the oxide 230 and the insulator 280. Some of the hydrogen may also be gettered by the conductor 242. In this way, the hydrogen concentrations in the insulator 280, the oxide 230b, and the oxide 230a can be reduced by irradiating with microwaves or high-frequency waves such as RF.

[0294] Alternatively, oxygen gas may be converted into plasma using microwaves or high-frequency waves such as RF to form oxygen radicals. That is, plasma treatment may be performed in an atmosphere containing oxygen in the insulator 280, the oxide 230b, and the oxide 230a. Hereinafter, such treatment may be referred to as oxygen plasma treatment. Furthermore, the formed oxygen radicals can supply oxygen to the insulator 280, the oxide 230b, and the oxide 230a. Furthermore, when plasma treatment is performed in an atmosphere containing oxygen in the insulator 280, the oxide 230b, and the oxide 230a, the oxide 230 may be configured to be less susceptible to irradiation of microwaves or high-frequency waves such as RF.

[0295] The oxygen plasma treatment is preferably performed using a microwave processing device having a power supply for generating high-density plasma using microwaves. The microwave processing device may also have a power supply for applying RF to the substrate side. High-density plasma can generate high-density oxygen radicals. Applying RF to the substrate side can efficiently guide oxygen ions generated by the high-density plasma into the insulator 280 and the oxide 230. The oxygen plasma treatment is preferably performed under reduced pressure, with a pressure of 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, and even more preferably 400 Pa or higher. The oxygen flow ratio (O2 / O2+Ar) is preferably 50% or lower, preferably 10% to 30%. The treatment temperature may be, for example, about 400°C. After the oxygen plasma treatment, a heat treatment may be performed without exposure to the outside air.

[0296] Next, the conductive film 260A (conductive film 260Aa and conductive film 260Ab) is formed (see FIG. 16). The conductive film 260Aa and the conductive film 260Ab can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use a CVD method. In this embodiment, the conductive film 260Aa is formed using an ALD method, and the conductive film 260Ab is formed using a CVD method.

[0297] Next, the oxide film 230C, the insulating film 250A, the conductive film 260Aa and the conductive film 260Ab are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 17).

[0298] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0299] Next, the insulator 282 is formed over the conductor 260, the oxide 230c, the insulator 250, and the insulator 280 (see FIG. 18). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, it is preferable to form a film of aluminum oxide by a sputtering method, for example. By forming the insulator 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 during film formation. At this time, it is preferable to form the insulator 282 while heating the substrate. Furthermore, it is preferable to form the insulator 282 in contact with the top surface of the conductor 260, because this can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 260 during subsequent heat treatment.

[0300] Next, portions of the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 are processed to form openings that reach the insulator 211 (see FIG. 19 ). The openings may be formed to surround the transistor 200. Alternatively, the openings may be formed to surround multiple transistors 200. Thus, portions of the side surfaces of the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 are exposed in the openings.

[0301] A dry etching method or a wet etching method can be used to process a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 273, a portion of the insulator 272, a portion of the insulator 224, a portion of the insulator 222, a portion of the insulator 216, a portion of the insulator 214, and a portion of the insulator 212. Processing by the dry etching method is suitable for fine processing. Furthermore, the processing may be performed under different conditions.

[0302] At this time, high frequency waves such as microwaves or RF may be irradiated onto the insulator 280. The irradiated high frequency waves such as microwaves or RF may penetrate the insulator 280, the oxide 230b, and the oxide 230a, and may remove hydrogen therein. For example, in the oxide 230a and the oxide 230b, V O A reaction occurs in which the bonds of H are broken, resulting in dehydrogenation. Some of the hydrogen generated at this time may be removed from the oxide 230 and the insulator 280. Some of the hydrogen may also be gettered into the conductor 242.

[0303] Next, an insulating film 287A is formed to cover the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 (see FIG. 20). The insulating film 287A is preferably formed under the same conditions as those for the insulator 282. For example, the insulating film 287A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0304] Specifically, the insulating film 287A is preferably formed of aluminum oxide by, for example, a sputtering method. By forming the insulating film 287A in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 during film formation. At this time, it is preferable to form the insulating film 287A while heating the substrate. Furthermore, since the insulator 282 is formed in contact with the upper surface of the conductor 260, absorption of oxygen contained in the insulator 280 into the conductor 260 can be suppressed during the film formation process of the insulating film 287A.

[0305] Next, an anisotropic etching process is performed on the insulating film 287A to form an insulator 287 on the side surfaces of the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 (see Figure 21).

[0306] Here, the side edge of insulator 282 contacts the upper end of insulator 287, and the side edge of insulator 214 contacts the lower end of insulator 287, thereby forming a structure that seals transistor 200 and insulator 280.

[0307] The anisotropic etching is preferably performed by dry etching, which removes the insulating film formed on a surface approximately parallel to the substrate surface, thereby forming the insulator 272 in a self-aligned manner.

[0308] Next, the insulator 283 is formed to cover the insulators 282, 287, and 211 (see FIG. 22). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 may also be a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and another silicon nitride film may be formed on the silicon nitride film by a CVD method. As shown in FIG. 22, the insulator 283 contacts the insulator 211 at the bottom of the opening. That is, the upper and side surfaces of the transistor 200 are surrounded by the insulator 283, and the lower surface is surrounded by the insulator 211. In this way, by surrounding the transistor 200 with the insulator 283 and the insulator 211, which have high barrier properties, moisture and hydrogen can be prevented from entering from the outside.

[0309] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400°C for 1 hour. This heat treatment allows the oxygen added by the formation of the insulator 282 to diffuse into the insulator 280 and further to be supplied to the oxide 230a and the oxide 230b via the oxide 230c. In this way, by performing the oxygen-adding treatment on the oxide 230, oxygen vacancies in the oxide 230 (oxide 230b) are repaired by oxygen.

[0310] Furthermore, the hydrogen remaining in the oxide 230 diffuses through the insulator 280 to the insulator 282 and the insulator 287, and is captured or fixed to the insulator 287. In other words, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O It is possible to suppress the formation of H. Note that the heat treatment may be performed after the insulator 282 is formed, not only after the insulator 283 is formed.

[0311] Alternatively, the insulator 284 may be formed on the insulator 283 (see FIG. 23). Note that the insulator 284 is preferably formed using a film formation method with high coverage. For example, the insulator 284 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulator 284 is preferably formed using the same material as the insulators 211, 212, and 283.

[0312] Specifically, it is preferable to form a silicon nitride film by a CVD method, and in particular, it is preferable to form the insulator 284 by a CVD method using a compound gas that does not contain hydrogen atoms or that contains a small amount of hydrogen atoms.

[0313] The amount of hydrogen contained in the insulator 284 can be reduced by forming the insulator 284 by a deposition method using a gas in which hydrogen atoms are reduced or removed. That is, the concentration of hydrogen contained in the insulator 284 can be reduced, and hydrogen entering the channel formation region of the oxide semiconductor can be reduced.

[0314] Next, an insulating film that will become the insulator 274 is formed on the insulator 284. The insulating film that will become the insulator 274 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In addition, the insulating film that will become the insulator 274 is preferably formed by a film formation method that uses a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration of the insulating film that will become the insulator 274 to be reduced.

[0315] Next, the insulating film that will become the insulator 274 is subjected to CMP processing to form the insulator 274 with a flat upper surface (see FIG. 24).

[0316] Next, openings are formed in the insulators 272, 273, 280, 282, 283, and 284, reaching the conductor 242 (see FIG. 25). The openings may be formed using lithography. Note that although the shape of the openings is circular in top view in FIG. 25A, the shape is not limited to this. For example, the openings may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view.

[0317] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see Figure 25). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that will become the insulator 241, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form a film of aluminum oxide using a PEALD method. Alternatively, it is preferable to form a film of silicon nitride using a PEALD method, similar to the formation of the insulator 283. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0318] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0319] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that will become the conductor 240a and the conductor 240b is preferably a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0320] Next, CMP processing is performed to remove portions of the conductive film that will become conductors 240a and 240b, exposing the upper surfaces of insulators 284 and 274. As a result, the conductive film remains only in the openings, thereby forming conductors 240a and 240b with flat upper surfaces (see FIG. 25). Note that the CMP processing may remove portions of the upper surfaces of insulators 284 and 274.

[0321] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0322] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246a that contacts the upper surface of the conductor 240a and the conductor 246b that contacts the upper surface of the conductor 240b (see FIG. 26). At this time, part of the insulator 284 may be removed in a region where the conductors 246a and 246b do not overlap with the insulator 284.

[0323] Next, the insulator 286 is formed on the conductor 246 and the insulator 284 (see FIG. 7). The insulator 286 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be multilayered. For example, a silicon nitride film may be formed using a sputtering method, and a silicon nitride film may be formed on the silicon nitride using a CVD method. By forming the insulator 286 on the conductor 246 and the insulator 284, the upper surface and side surfaces of the conductor 246 are in contact with the insulator 286, and the lower surface of the conductor 246 is in contact with the insulator 284. In other words, the conductor 246 can be configured to be surrounded by the insulators 284 and 286. This configuration can suppress the penetration of oxygen from the outside and prevent oxidation of the conductor 246. It is also preferable because it can prevent impurities such as water and hydrogen from conductor 246 from diffusing to the outside.

[0324] Through the above steps, a semiconductor device including the transistor 200 illustrated in FIG 7 can be manufactured. As illustrated in FIGS. 10 to 26, the transistor 200 can be manufactured by the method for manufacturing a semiconductor device described in this embodiment.

[0325] <Application examples of semiconductor devices> 27 and 28 , an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from the semiconductor device described above in <Structural Example of Semiconductor Device>, will be described. In the semiconductor device shown in FIGS. 27 and 28 , the same reference numerals are used to designate structures having the same functions as those of the semiconductor device described in <Structural Example 1 of Semiconductor Device> (see FIG. 7 ). In this section, the materials described in detail in <Structural Example 1 of Semiconductor Device> can be used to construct the transistor 200.

[0326] <<Semiconductor Device Application Example 1>> 27A and 27B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 211. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 27A and 27B, this is not a limitation. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, they may be arranged without any regularity depending on the design.

[0327] 27A, a portion where the insulator 283 and the insulator 211 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 211. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0328] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate is divided along the dicing lines, so that a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0329] 27A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in Fig. 27B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 27B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0330] In this manner, by using a structure in which the plurality of transistors 200_1 to 200_n are surrounded by a plurality of sealing portions, the area in which the insulator 283 and the insulator 211 are in contact with each other increases, thereby further improving the adhesion between the insulator 283 and the insulator 211. This makes it possible to more reliably seal the plurality of transistors 200_1 to 200_n.

[0331] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0332] <<Semiconductor Device Application Example 2>> 28 is a cross-sectional view of a transistor 200. The transistor 200 shown in FIG. 28 differs from the transistor 200 shown in FIG. 7 in that it does not have an oxide 230b. That is, in the transistor 200 shown in FIG. 28, the oxide 230 is composed of an oxide 230a, an oxide 230c1, and an oxide 230c2. The lower surfaces of the conductors 242a and 242b are in contact with the oxide 230a.

[0333] The oxide 230 has a stacked structure of the oxide 230a, the oxide 230c1, and the oxide 230c2, which provides the following excellent effects.

[0334] For example, by configuring oxide 230a with an atomic ratio of In:Ga:Zn=1:3:4, oxide 230c1 with an atomic ratio of In:Ga:Zn=4:2:3, and oxide 230c2 with an atomic ratio of In:Ga:Zn=1:3:4, a channel formation region can be formed in oxide 230c1. In this configuration, oxide 230c1 and oxide 230c2 are formed in a U-shape along openings formed in insulator 280, insulator 272, insulator 273, conductor 242 (conductor 242a, conductor 242b), and oxide 230a. Furthermore, the side surfaces of conductor 242a and conductor 242b can be in contact with the side surfaces of oxide 230c1. Furthermore, the oxide 230c2 is in contact with the upper surface of the oxide 230c1, which can prevent the insulator 250 from coming into contact with the oxide 230c1.

[0335] The above configuration can reduce the contact area between the conductor 242 (conductor 242a and conductor 242b) and the oxide 230c1. Reducing the contact area between the conductor 242 and the oxide 230c1 can reduce the junction leakage current (also called junction leakage current) that may occur between the conductor 242 and the oxide 230c1. Furthermore, adjusting the thickness of the conductor 242 makes it possible to arbitrarily adjust the contact area with the oxide 230c1.

[0336] For example, a semiconductor device having the transistor 200 shown in FIG. 28 can be suitably used in outer space, such as in a space shuttle or artificial satellite. In outer space, cosmic radiation or electrons and protons emitted from the sun may penetrate into the semiconductor device and affect its semiconductor characteristics. The transistor 200 shown in FIG. 28 has a reduced junction leakage current, and therefore has a highly reliable structure that is highly resistant to cosmic radiation and the like.

[0337] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having normally-off electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with small off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0338] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0339] (Embodiment 3) In this embodiment, one mode of a semiconductor device that can be applied to other embodiments of the present invention will be described. A configuration example of a semiconductor device will be described below.

[0340] <Configuration Example 2 of Semiconductor Device> FIG. 29A is a cross-sectional view of transistor 2100A in the channel length direction.

[0341] The transistor 2100A is provided over a substrate 2102 and includes an insulating layer 2121, an insulating layer 2122, an insulating layer 2123, a conductive layer 2106, an insulating layer 2103, a semiconductor layer 2108, an insulating layer 2110, a metal oxide layer 2114, a conductive layer 2112, an insulating layer 2124, an insulating layer 2125, an insulating layer 2126, and the like. The insulating layer 2121, the insulating layer 2122, and the insulating layer 2123 are provided in this order over the substrate 2102, the conductive layer 2106 is provided over the insulating layer 2123, and the insulating layer 2103 is provided over the insulating layer 2123 and the conductive layer 2106. The island-shaped semiconductor layer 2108 is provided over the insulating layer 2103 and has a region overlapping with part of the conductive layer 2106. The insulating layer 2110 is provided over the semiconductor layer 2108. The metal oxide layer 2114 and the conductive layer 2112 are stacked in this order over the insulating layer 2110 and have a region overlapping with part of the semiconductor layer 2108 and part of the conductive layer 2106 .

[0342] The insulating layer 2124 has a region in contact with part of the insulating layer 2123, and is provided over the conductive layer 2106, the insulating layer 2103, the semiconductor layer 2108, the insulating layer 2110, the metal oxide layer 2114, and the conductive layer 2112. The insulating layer 2125 has a region in contact with part of the insulating layer 2122 and the insulating layer 2121, and is provided over the insulating layer 2124. The insulating layer 2126 is provided over the insulating layer 2125.

[0343] In the transistor 2100A, at least the semiconductor layer 2108 is preferably provided between the insulating layer 2123 and the insulating layer 2124, and the insulating layer 2123 and the insulating layer 2124 are preferably in contact with each other on the outside of the semiconductor layer 2108. The insulating layer 2123 and the insulating layer 2124 are provided between the insulating layer 2121 and the insulating layer 2122 and the insulating layer 2125 and the insulating layer 2126. In this case, the insulating layer 2125 is preferably in contact with at least the insulating layer 2122, and more preferably in contact with the insulating layer 2121.

[0344] In other words, in the transistor 2100A, the semiconductor layer 2108 is surrounded by the insulating layer 2123 and the insulating layer 2124, and the semiconductor layer 2108, the insulating layer 2123, and the insulating layer 2124 are surrounded by the insulating layer 2122 and the insulating layer 2125. Furthermore, the semiconductor layer 2108, the insulating layer 2123, the insulating layer 2124, the insulating layer 2122, and the insulating layer 2125 are sandwiched between the insulating layer 2121 and the insulating layer 2126, and therefore can be said to be surrounded by the insulating layer 2121 and the insulating layer 2126.

[0345] That is, the sealing structure formed by the insulating layers 2123 and 2124 corresponds to the sealing structure formed by the insulators 214, 287, and 282 described in the previous embodiment. Therefore, the descriptions of the insulators 214, 287, and 282 can be referred to for the insulating layers 2123 and 2124.

[0346] The sealing structure formed by the insulating layers 2121, 2122, and 2125 corresponds to the sealing structure formed by the insulators 211, 212, and 283 described in the previous embodiment. Therefore, the descriptions of the insulators 211, 212, and 283 can be referred to for the insulating layers 2122 and 2125.

[0347] Furthermore, the insulating layer 2126 corresponds to the insulator 284 described in the above embodiment. Therefore, the description of the insulator 284 can be referred to for the insulating layer 2126.

[0348] The ends of the conductive layer 2112 and the metal oxide layer 2114 are located inside the ends of the insulating layer 2110. In other words, the insulating layer 2110 has a portion that protrudes outward beyond the ends of the conductive layer 2112 and the metal oxide layer 2114 at least on the semiconductor layer 2108.

[0349] In addition, it is preferable that the end of the conductive layer 2112 is located inside the end of the metal oxide layer 2114. In addition, the insulating layer 2124 is provided in contact with part of the upper surface and the side surface of the metal oxide layer 2114.

[0350] In the transistor 2100A, the end of the conductive layer 2112 is located inside the end of the metal oxide layer 2114. In other words, the metal oxide layer 2114 has a portion that protrudes outside the end of the conductive layer 2112 at least on the insulating layer 2110.

[0351] By positioning the end of the conductive layer 2112 more inward than the end of the metal oxide layer 2114, the steps on the side surfaces of the conductive layer 2112 and the metal oxide layer 2114 are gentler, improving the step coverage of the layers (e.g., insulating layer 2124, insulating layer 2125, insulating layer 2126) formed on the conductive layer 2112 and the metal oxide layer 2114, and preventing defects such as breaks and voids in the layers.

[0352] A wet etching method can be suitably used to form the conductive layer 2112 and the metal oxide layer 2114. Furthermore, by using a material for the metal oxide layer 2114 that has an etching rate slower than that of the conductive layer 2112, the end of the conductive layer 2112 can be located more inward than the end of the metal oxide layer 2114. Furthermore, the metal oxide layer 2114 and the conductive layer 2112 can be formed in the same process, thereby improving productivity.

[0353] Note that this embodiment is not limited to the above. The edge of the conductive layer 2112 may coincide with the edge of the metal oxide layer 2114. Alternatively, the side surface of the conductive layer 2112 and the side surface of the metal oxide layer 2114 may be flush with each other.

[0354] The semiconductor layer 2108 has a pair of regions 2108L that sandwich a channel formation region and a pair of regions 2108N that are located outside the pair of regions 2108L. The regions 2108L are regions of the semiconductor layer 2108 that overlap with the insulating layer 2110 but do not overlap with the metal oxide layer 2114 or the conductive layer 2112.

[0355] The region 2108C functions as a channel formation region. Here, if the metal oxide layer 2114 is conductive, it functions as part of the gate electrode, and therefore an electric field is applied from the gate electrode to the region 2108C through the insulating layer 2110, which functions as a gate insulating layer, to form a channel. However, this embodiment is not limited to this. A channel may also be formed in a portion that does not overlap with the metal oxide layer 2114 but overlaps with the conductive layer 2106 (a portion including the region 2108L and the region 2108N).

[0356] The region 2108L functions as a buffer region for alleviating the drain electric field. The region 2108L does not overlap with the conductive layer 2112 or the metal oxide layer 2114, and therefore, is a region in which a channel is hardly formed even when a gate voltage is applied to the conductive layer 2112. The region 2108L preferably has a higher carrier concentration than the region 2108C. This allows the region 2108L to function as an LDD region.

[0357] Region 2108L can also be said to be a region with the same or lower resistance, the same or higher carrier concentration, the same or higher oxygen vacancy density, or the same or higher impurity concentration compared to region 2108C.

[0358] Region 2108L can also be said to be a region with the same or higher resistance, the same or lower carrier concentration, the same or lower oxygen vacancy density, or the same or lower impurity concentration compared to region 2108N.

[0359] In this way, by providing the region 2108L that functions as an LDD region between the region 2108C that is a channel formation region and the region 2108N that is a source or drain region, a highly reliable transistor can be realized that has both a high drain breakdown voltage and a high on-current.

[0360] The region 2108N functions as a source region or a drain region, and is the region with the lowest resistance compared to other regions of the semiconductor layer 2108. Alternatively, the region 2108N can also be said to be the region with the highest carrier concentration, the highest oxygen vacancy density, or the highest impurity concentration compared to other regions of the semiconductor layer 2108.

[0361] The lower the electrical resistance of the region 2108N, the more preferable. For example, the sheet resistance of the region 2108N is 1 Ω / □ or more and 1×10 3 Less than Ω / □, preferably 1Ω / □ or more 8×10 2 It is preferable to set it to Ω / □ or less.

[0362] Furthermore, the higher the electrical resistance of the region 2108C in a state where no channel is formed, the more preferable. For example, the sheet resistance of the region 2108C is 1×10 9 Ω / □ or more, preferably 5×10 9 Ω / □ or more, preferably 1×10 10 It is preferably Ω / □ or more.

[0363] The higher the electrical resistance of the region 2108C in a state where a channel is not formed, the better, so no upper limit is set. However, if an upper limit is set, the sheet resistance of the region 2108C, for example, should be 1×10 9 Ω / □ or more 1×10 12 Ω / □ or less, preferably 5×10 9 Ω / □ or more 1×10 12 Ω / □ or less, more preferably 1×10 10 Ω / □ or more 1×10 12 It is preferably Ω / □ or less.

[0364] The sheet resistance value of the region 2108L is, for example, 1×10 3 Ω / □ or more 1×10 9 Ω / □ or less, preferably 1×10 3 Ω / □ or more 1×10 8 Ω / □ or less, more preferably 1×10 3 Ω / □ or more 1×10 7Ω / □ or less. By setting the resistance in this range, a transistor with good electrical characteristics and high reliability can be obtained. The sheet resistance can be calculated from the resistance value. By providing such region 2108L between region 2108N and region 2108C, the source-drain breakdown voltage of transistor 2100A can be increased.

[0365] Furthermore, the electrical resistance of the region 2108C in a state where no channel is formed is 1×10 6 more than 1x10 12 times or less, preferably 1 x 10 6 more than 1x10 11 times or less, more preferably 1×10 6 more than 1x10 10 It can be twice or less.

[0366] The electrical resistance of region 2108C in a state where no channel is formed is 1×10 of the electrical resistance of region 2108L. 0 more than 1x10 9 times or less, preferably 1 x 10 1 more than 1x10 8 times or less, more preferably 1×10 2 more than 1x10 7 It can be twice or less.

[0367] The electrical resistance of region 2108L is 1×10 of the electrical resistance of region 2108N. 0 more than 1x10 9 times or less, preferably 1 x 10 1 more than 1x10 8 times or less, more preferably 1×10 1 more than 1x10 7 It can be twice or less.

[0368] By providing the region 2108L having the above-described resistance between the region 2108N and the channel formation region, the source-drain breakdown voltage of the transistor 2100A can be increased.

[0369] Furthermore, it is preferable that the carrier concentration in the semiconductor layer 2108 has a distribution in which the region 2108C is lowest and the carrier concentration increases in the order of the region 2108L and the region 2108N. By providing the region 2108L between the regions 2108C and 2108N, the carrier concentration in the region 2108C can be kept extremely low even if impurities such as hydrogen diffuse from the region 2108N during the manufacturing process, for example.

[0370] The lower the carrier concentration in the region 2108C that functions as a channel forming region, the better. 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 More preferably, it is 1×10 or less. 13 cm -3 More preferably, it is 1×10 or less. 12 cm -3 The lower limit of the carrier concentration of the region 2108C is not particularly limited, but is preferably 1×10 -9 cm -3 It can be said that:

[0371] On the other hand, the carrier concentration in the region 2108N is, for example, 5×10 18 cm -3 or more, preferably 1 × 10 19 cm -3 More preferably, 5 × 10 19 cm -3 The upper limit of the carrier concentration in the region 2108N is not particularly limited, but may be, for example, 5×10 21 cm -3 , or 1 × 10 22 cm -3 etc.

[0372] The carrier concentration in region 2108L can be a value between regions 2108C and 2108N. For example, 1×10 14 cm-3 More than 1×10 20 cm -3 It is sufficient to set the value in the range below.

[0373] The carrier concentration in the region 2108L may not be uniform, and may have a gradient such that the carrier concentration decreases from the region 2108N side to the channel formation region side. For example, either the hydrogen concentration or the oxygen vacancy concentration in the region 2108L, or both, may have a gradient such that the concentration decreases from the region 2108N side to the channel formation region side.

[0374] The semiconductor layer 2108 preferably contains a metal oxide. The oxide 230 or the like shown in other embodiments or other structure examples can be referred to as the metal oxide that can be used for the semiconductor layer 2108. Furthermore, it is preferable to use an oxide film for the insulating layer 2103 and the insulating layer 2110, which are in contact with the channel formation region of the semiconductor layer 2108. For example, an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. In this way, oxygen desorbed from the insulating layer 2103 or the insulating layer 2110 can be supplied to the channel formation region of the semiconductor layer 2108, thereby reducing oxygen vacancies in the semiconductor layer 2108.

[0375] A portion of an end of the insulating layer 2110 is located on the semiconductor layer 2108. The insulating layer 2110 has a portion that overlaps with the conductive layer 2112 and functions as a gate insulating layer, and a portion that does not overlap with the conductive layer 2112 or the metal oxide layer 2114 (i.e., a portion that overlaps with the region 2108L).

[0376] The insulating layer 2110 may have a stacked structure of two or more layers. FIG. 29A shows an example in which the insulating layer 2110 has a three-layer structure consisting of an insulating layer 2110a, an insulating layer 2110b on the insulating layer 2110a, and an insulating layer 2110c on the insulating layer 2110b. Note that, because insulating layers 2110a, 2110b, and 2110c can be made of insulating films made of the same material, the interfaces between the insulating layers 2110a, 2110b, and 2110c may not be clearly visible. Therefore, in this embodiment, the interfaces between the insulating layers 2110a, 2110b, and 2110c are shown with dashed lines.

[0377] The insulating layer 2110a has a region in contact with the channel formation region of the semiconductor layer 2108. The insulating layer 2110c has a region in contact with the metal oxide layer 2114. The insulating layer 2110b is located between the insulating layer 2110a and the insulating layer 2110c.

[0378] The insulating layers 2110a, 2110b, and 2110c are preferably insulating films containing oxide, and are preferably formed successively using the same film formation apparatus.

[0379] For example, insulating layer 2110a, insulating layer 2110b, and insulating layer 2110c can be formed using an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.

[0380] The insulating layer 2110 in contact with the semiconductor layer 2108 preferably has a stacked-layer structure of oxide insulating films and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 2110 has an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 2110 by forming the insulating layer 2110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the formed insulating layer 2110 in an oxygen atmosphere, or forming an oxide film on the insulating layer 2110 in an oxygen atmosphere. In particular, the insulating layer 2110a in contact with the semiconductor layer 2108 preferably contains oxygen in excess, similar to the insulator 280 described in the above embodiment.

[0381] For example, the insulating layer 2110a, the insulating layer 2110b, and the insulating layer 2110c can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. Also, examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method.

[0382] In particular, it is preferable that the insulating layers 2110a, 2110b, and 2110c are formed by plasma CVD.

[0383] Similar to insulator 250, insulating layer 2110c is preferably an extremely dense film with reduced surface defects compared to insulating layer 2110b, which is less likely to adsorb impurities contained in the air, such as water.

[0384] The insulating layer 2110b is preferably formed thicker than the insulating layers 2110a and 2110c. For example, the insulating layer 2110b may be formed thicker by using conditions that result in a faster deposition rate than the insulating layers 2110a and 2110c. This can shorten the time required for the deposition process of the insulating layer 2110.

[0385] Here, the boundary between insulating layer 2110a and insulating layer 2110b, and the boundary between insulating layer 2110b and insulating layer 2110c may be unclear, so these boundaries are shown by dashed lines in Figure 29A. If insulating layer 2110a and insulating layer 2110b have different film densities, these boundaries may be observable as differences in contrast in a transmission electron microscope (TEM) image of a cross section of insulating layer 2110. Similarly, the boundary between insulating layer 2110b and insulating layer 2110c may also be observable.

[0386] When forming the conductive layer 2112 and the metal oxide layer 2114, the thickness of the insulating layer 2110 may be reduced in regions that do not overlap with the conductive layer 2112. Fig. 29A shows a configuration in which the insulating layer 2110c is removed from regions that do not overlap with the metal oxide layer 2114, leaving the insulating layers 2110a and 2110b. Furthermore, the thickness of the insulating layer 2110b in regions that do not overlap with the metal oxide layer 2114 may be reduced compared to the insulating layer 2110b in regions that overlap with the metal oxide layer 2114.

[0387] By reducing the thickness of the insulating layer 2110 in the area that does not overlap with the metal oxide layer 2114, the step at the end of the insulating layer 2110 is reduced, the step coverage of the layers formed on the insulating layer 2110 (e.g., insulating layer 2124, insulating layer 2125, insulating layer 2126) is improved, and defects such as breaks and voids in the layers can be suppressed.

[0388] 29A , the insulating layer 2110 may have a configuration in which the insulating layers 2110a, 2110b, and 2110c remain in regions that do not overlap with the metal oxide layer 2114. The insulating layer 2110c may have a configuration in which the thickness of the insulating layer 2110c in regions that do not overlap with the metal oxide layer 2114 is thinner than the thickness of the insulating layer 2110c in regions that do not overlap with the metal oxide layer 2114. By leaving the insulating layer 2110c in regions that do not overlap with the metal oxide layer 2114, it is possible to prevent water from being adsorbed to the insulating layer 2110. The thickness of the insulating layer 2110c in regions that overlap with the metal oxide layer 2114 is set to 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less.

[0389] The insulating layer 2110 may have a two-layer structure of an insulating layer 2110a and an insulating layer 2110c on the insulating layer 2110a. Alternatively, the insulating layer 2110 may have a single-layer structure. As the insulating layer 2110, any of the insulating layer 2110a, the insulating layer 2110b, and the insulating layer 2110c described above can be appropriately selected depending on the purpose.

[0390] 29A shows an example in which the insulating layer 2103 has a structure in which an insulating layer 2103a, an insulating layer 2103b, an insulating layer 2103c, and an insulating layer 2103d are stacked in this order from the conductive layer 2106 side. The insulating layer 2103a is in contact with the conductive layer 2106. The insulating layer 2103d is in contact with the semiconductor layer 2108.

[0391] It is preferable that the insulating layer 2103 satisfy one or more of the following requirements: high breakdown voltage, low film stress, low hydrogen and water release, few defects in the film, and suppression of diffusion of metal elements contained in the conductive layer 2106; and it is most preferable that the insulating layer 2103 satisfy all of these requirements.

[0392] Of the four insulating layers included in the insulating layer 2103, the insulating layer 2103a, the insulating layer 2103b, and the insulating layer 2103c located on the conductive layer 2106 side are preferably formed using an insulating film containing nitrogen. On the other hand, the insulating layer 2103d in contact with the semiconductor layer 2108 is preferably formed using an insulating film containing oxygen. Furthermore, the four insulating layers included in the insulating layer 2103 are preferably formed successively without exposure to air using a plasma CVD apparatus.

[0393] The insulating layers 2103a, 2103b, and 2103c can be preferably formed using an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film. The insulating layer 2103d can be formed using an insulating film that can be used for the insulating layer 2110.

[0394] The insulating layers 2103a and 2103c are preferably dense films that can prevent diffusion of impurities from below. The insulating layer 2103a is preferably a film that can block metal elements contained in the conductive layer 2106, and the insulating layer 2103c is preferably a film that can block hydrogen and water contained in the insulating layer 2103b. Therefore, the insulating layer 2103a and the insulating layer 2103c can be formed using insulating films that are formed at a lower deposition rate than the insulating layer 2103b.

[0395] On the other hand, the insulating layer 2103b is preferably an insulating film formed under conditions of low stress and high deposition rate. The insulating layer 2103b is preferably formed thicker than the insulating layers 2103a and 2103c.

[0396] For example, even if insulating layer 2103a, insulating layer 2103b, and insulating layer 2103c each use a silicon nitride film formed by plasma CVD, insulating layer 2103b will have a lower film density than the other two insulating layers. Therefore, this may be observed as a difference in contrast in a transmission electron microscope image of the cross section of insulating layer 2103. Note that the boundaries between insulating layer 2103a and insulating layer 2103b, and between insulating layer 2103b and insulating layer 2103c may be unclear, and therefore these boundaries are indicated by dashed lines in FIG. 29A.

[0397] The insulating layer 2103d in contact with the semiconductor layer 2108 is preferably a dense insulating film that is less likely to adsorb impurities such as water on its surface. It is also preferable to use an insulating film with as few defects as possible and in which impurities such as water and hydrogen are reduced. For example, the insulating layer 2103d can be an insulating film similar to the insulating layer 2110c of the insulating layer 2110.

[0398] In addition, when a metal film or an alloy film whose constituent elements are unlikely to diffuse into the insulating layer 2103 is used as the conductive layer 2106, the insulating layer 2103a may not be provided, and a structure in which three insulating layers, namely, the insulating layer 2103b, the insulating layer 2103c, and the insulating layer 2103d, are stacked may be used.

[0399] The insulating layer 2103 having such a stacked structure makes it possible to realize a highly reliable transistor.

[0400] The insulating layer 2123 and the insulating layer 2124 are preferably made of a material that absorbs impurities such as hydrogen contained in the semiconductor layer 2108, the insulating layer 2103, the insulating layer 2110, and the like. For example, a material containing aluminum oxide can be used for the insulating layer 2123 and the insulating layer 2124. In this case, the insulating layer 2123 and the insulating layer 2124 function as gettering layers for impurities such as hydrogen. Note that the term "hydrogen" as used here includes hydrogen atoms, hydrogen molecules, hydrogen bonded to oxygen, and ionized forms of these.

[0401] It is more preferable that the materials used for the insulating layers 2123 and 2124 have the effect of suppressing oxygen permeation.

[0402] 29A , in the channel length direction, the insulating layer 2124 is provided to cover the top and side surfaces of the conductive layer 2112, the top and side surfaces of the metal oxide layer 2114, the top and side surfaces of the insulating layer 2110, the top and side surfaces of the semiconductor layer 2108, and the side surfaces of the insulating layer 2103. The insulating layer 2124 is in contact with the insulating layer 2123 on the outside of the insulating layer 2103. Here, the edge of the insulating layer 2103 roughly coincides with the edge of the semiconductor layer 2108. Alternatively, the side surfaces of the insulating layer 2103 and the side surfaces of the semiconductor layer 2108 have the same plane.

[0403] Although not shown, the insulating layer 2123 in a region that does not overlap with the insulating layer 2110 in the channel width direction is preferably provided in contact with the insulating layer 2124.

[0404] With the above structure, impurities such as hydrogen contained in the semiconductor layer 2108, the insulating layer 2103, the insulating layer 2110, and the like can be efficiently absorbed by the insulating layer 2123 and the insulating layer 2124, thereby enabling gettering of the impurities such as hydrogen. In addition, oxygen contained in the semiconductor layer 2108, the insulating layer 2103, the insulating layer 2110, and the like can be prevented from diffusing to the outside of the insulating layer 2123 and the insulating layer 2124.

[0405] It is preferable to use a material that suppresses hydrogen permeation for insulating layers 2121, 2122, 2125, and 2126. For example, a material containing silicon nitride or silicon oxide containing nitrogen can be used for insulating layers 2121, 2122, 2125, and 2126. Silicon nitride is preferably used as such a material. In this case, insulating layers 2121, 2122, 2125, and 2126 function as protective layers against impurities such as hydrogen. Note that hydrogen here includes hydrogen atoms, hydrogen molecules, hydrogen bonded to oxygen, and ionized forms of these.

[0406] The insulating layer 2125 is provided to cover the insulating layer 2124. The insulating layer 2125 is preferably in contact with the insulating layer 2122 so as to surround the insulating layer 2123 and the insulating layer 2124. The insulating layer 2125 is further preferably in contact with the insulating layer 2121 on the outside of the insulating layer 2123 and the insulating layer 2124. The insulating layer 2126 is provided over the insulating layer 2125.

[0407] The above structure can prevent impurities such as hydrogen from entering the semiconductor layer 2108 from outside the insulating layers 2121, 2122, 2125, and 2126. In other words, in the transistor 2100A, at least the semiconductor layer 2108 is surrounded by the insulating layers 2121, 2122, 2125, and 2126, which can prevent impurity elements such as hydrogen from entering from the outside.

[0408] Note that although the protective layer has a stacked structure of insulating layers 2125 and 2126, one of the insulating layers 2125 and 2126 may not be provided if it is not necessary. The insulating layer 2125 may have a stacked structure of two or more layers. Similarly, the protective layer has a stacked structure of insulating layers 2121 and 2122, but one of the insulating layers 2121 and 2122 may not be provided if it is not necessary. The insulating layer 2122 may have a stacked structure of two or more layers.

[0409] Preferably, the end of the insulating layer 2110, the end of the metal oxide layer 2114, and the end of the conductive layer 2112 each have a tapered shape. Furthermore, the taper angle of the end of the metal oxide layer 2114 is preferably smaller than the taper angle of the end of the insulating layer 2110, and the taper angle of the end of the conductive layer 2112 is preferably smaller than the taper angle of the end of the metal oxide layer 2114. With this configuration, the coverage of the layers (e.g., insulating layer 2124, insulating layer 2125, and insulating layer 2126) formed on the insulating layer 2110, the metal oxide layer 2114, and the conductive layer 2112 is improved, and defects such as discontinuities and voids in the layers can be suppressed.

[0410] In addition, in this specification, the taper angle refers to the inclination angle between the side and bottom surfaces of a target layer when the layer is observed from a direction perpendicular to the cross section (e.g., a surface perpendicular to the surface of the substrate).

[0411] Part of the conductive layer 2106 functions as a first gate electrode (also referred to as a bottom gate electrode), and part of the conductive layer 2112 functions as a second gate electrode (also referred to as a top gate electrode). Part of the insulating layer 2103 functions as a first gate insulating layer, and part of the insulating layer 2110 functions as a second gate insulating layer.

[0412] The conductive layer 2106 may be electrically connected to the conductive layer 2112. This allows the conductive layer 2106 and the conductive layer 2112 to be applied with the same potential.

[0413] Although not shown, it is preferable that the conductive layer 2112 and the conductive layer 2106 protrude outward in the channel width direction beyond the end portions of the semiconductor layer 2108. In this case, the entire semiconductor layer 2108 in the channel width direction is covered with the conductive layer 2112 and the conductive layer 2106 with the insulating layer 2110 and the insulating layer 2103 interposed therebetween.

[0414] With this structure, the semiconductor layer 2108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In this case, it is particularly preferable to apply the same potential to the conductive layer 2106 and the conductive layer 2112. This allows an electric field for inducing a channel in the semiconductor layer 2108 to be effectively applied, thereby increasing the on-state current of the transistor 2100A. This also enables miniaturization of the transistor 2100A.

[0415] Note that the conductive layer 2112 and the conductive layer 2106 may not be connected to each other. In this case, a constant potential may be applied to one of a pair of gate electrodes, and a signal for driving the transistor 2100A may be applied to the other. In this case, the threshold voltage when the transistor 2100A is driven by the other electrode can also be controlled by the potential applied to one electrode.

[0416] 29A , the transistor 2100A may include a conductive layer 2120a and a conductive layer 2120b over an insulating layer 2126. The conductive layer 2120a and the conductive layer 2120b function as a source electrode and a drain electrode. The conductive layer 2120a and the conductive layer 2120b are electrically connected to a region 2108N (described later) through an opening 2119a or an opening 2119b provided in the insulating layer 2124, the insulating layer 2125, and the insulating layer 2126, respectively.

[0417] The semiconductor layer 2108 can be made of an oxide such as a metal oxide that can be used for the oxide 230 shown in other embodiments or other configuration examples. For example, the semiconductor layer 2108 preferably contains indium, M (M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0418] In particular, it is preferable to use an oxide containing indium, gallium, and zinc for the semiconductor layer 2108.

[0419] The semiconductor layer 2108 may have a stacked structure in which layers with different compositions, layers with different crystallinity, or layers with different impurity concentrations are stacked.

[0420] A low-resistance material is preferably used for the conductive layer 2112. By using a low-resistance material for the conductive layer 2112, parasitic resistance can be reduced, resulting in a transistor with high on-state current, and a semiconductor device with high on-state current can be obtained. Furthermore, by reducing the wiring resistance in a large display device or a high-resolution display device, signal delay can be suppressed, enabling high-speed driving. Since the conductive layer 2112 functions as a gate electrode, a conductive material that can be used for a gate electrode, such as the conductor 260 or the conductor 205, described in other embodiments or other configuration examples can be used. For example, copper, silver, gold, aluminum, or the like can be used for the conductive layer 2112. Copper is particularly preferable because of its low resistance and excellent mass productivity.

[0421] The conductive layer 2112 may have a stacked structure. When the conductive layer 2112 has a stacked structure, a second conductive layer is provided on top of or under, or both of, a first conductive layer with low resistance. The second conductive layer is preferably made of a conductive material that is less susceptible to oxidation (has oxidation resistance) than the first conductive layer. Furthermore, the second conductive layer is preferably made of a material that suppresses the diffusion of components of the first conductive layer. For example, the second conductive layer can be made of a metal oxide such as indium oxide, indium zinc oxide, indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO), or zinc oxide, or a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, or tungsten nitride.

[0422] The metal oxide layer 2114 located between the insulating layer 2110 and the conductive layer 2112 functions as a barrier film that prevents oxygen contained in the insulating layer 2110 from diffusing toward the conductive layer 2112. The metal oxide layer 2114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 2112 from diffusing toward the insulating layer 2110. The metal oxide layer 2114 can be made of a material that is less permeable to oxygen and hydrogen than the insulating layer 2110, for example.

[0423] The metal oxide layer 2114 can prevent oxygen from diffusing from the insulating layer 2110 to the conductive layer 2112, even when the conductive layer 2112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Furthermore, even when the conductive layer 2112 contains hydrogen, the metal oxide layer 2114 can prevent hydrogen from diffusing from the conductive layer 2112 to the semiconductor layer 2108 through the insulating layer 2110. As a result, the carrier concentration in the channel formation region of the semiconductor layer 2108 can be made extremely low.

[0424] An insulating material or a conductive material can be used for the metal oxide layer 2114. When the metal oxide layer 2114 has insulating properties, it functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 2114 has conductivity, it functions as a part of the gate electrode.

[0425] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 2114. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like, because the driving voltage can be reduced.

[0426] A metal oxide can be used for the metal oxide layer 2114. For example, an oxide containing indium, such as indium oxide, indium zinc oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO), can be used. Conductive oxides containing indium are preferable because of their high conductivity. Furthermore, ITSO is less likely to crystallize due to the silicon it contains, and has high flatness, which increases the adhesion to a film formed on the ITSO. A metal oxide, such as zinc oxide or zinc oxide containing gallium, can be used for the metal oxide layer 2114. Alternatively, a stacked structure of these oxides may be used for the metal oxide layer 2114.

[0427] It is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 2108 for the metal oxide layer 2114. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 2108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that for the semiconductor layer 2108 for the metal oxide layer 2114, because this allows the use of common equipment.

[0428] Alternatively, when a metal oxide material containing indium and gallium is used for both the semiconductor layer 2108 and the metal oxide layer 2114, it is preferable to use a material with a higher gallium content (content rate) than the semiconductor layer 2108, because this can further improve the blocking property against oxygen. In this case, by using a material with a higher indium content than the metal oxide layer 2114 for the semiconductor layer 2108, the field-effect mobility of the transistor 2100A can be increased.

[0429] The metal oxide layer 2114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 2110 and the semiconductor layer 2108 by forming the oxide film in an atmosphere containing oxygen gas.

[0430] The conductive layer 2106 can be formed using a material similar to that of the conductive layer 2112, the conductive layer 2120a, or the conductive layer 2120b. In particular, it is preferable to use a material containing copper for the conductive layer 2106 because it can reduce wiring resistance. Furthermore, if the conductive layer 2106 is formed using a material containing a high-melting-point metal such as tungsten or molybdenum, it can be processed at a high temperature in a later step.

[0431] Region 2108N is a region containing an impurity element (first element). Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable for the region 2108N to contain boron, phosphorus, magnesium, or aluminum. It may also contain two or more of these elements.

[0432] The impurity element can be added by ion implantation, ion doping, etc. Alternatively, the impurity element may be added to the region 2108N by forming an insulating layer 2124 in contact with the region 2108N.

[0433] The process of adding an impurity element to the region 2108N can be performed using the insulating layer 2110 as a mask, thereby allowing the region 2108N to be formed in a self-aligned manner.

[0434] The region 2108N has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than 1×10, more preferably 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0435] The concentration of impurities contained in region 2108N can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side with XPS analysis.

[0436] Furthermore, in the region 2108N, the impurity element is preferably present in an oxidized state. For example, it is preferable to use an easily oxidized element such as boron, phosphorus, magnesium, aluminum, or silicon as the impurity element. Such easily oxidized elements can be bonded to oxygen in the semiconductor layer 2108 and exist stably in an oxidized state, and therefore are prevented from being desorbed even when high temperatures (e.g., 400°C or higher, 600°C or higher, or 800°C or higher) are applied in later processes. Furthermore, the impurity element removes oxygen from the semiconductor layer 2108, generating many oxygen vacancies in the region 2108N. These oxygen vacancies combine with hydrogen in the film to serve as a carrier supply source, resulting in the region 2108N having an extremely low resistance.

[0437] When a high-temperature treatment is performed, if a large amount of oxygen is supplied to the region 2108N from the outside or from a film in the vicinity of the region 2108N, the resistance may increase. Therefore, when a high-temperature treatment is performed, it is preferable to perform the treatment in a state where the semiconductor layer 2108 is covered with the insulating layer 2124, which has a high barrier property against oxygen.

[0438] The insulating layer 2124 is provided in contact with the region 2108N of the semiconductor layer 2108.

[0439] The insulating layer 2124 can be, for example, an insulating film containing aluminum oxide.

[0440] The region 2108N contains many oxygen vacancies due to the addition of impurity elements as described above.

[0441] With this configuration, a transistor 2100A with excellent electrical characteristics and high reliability can be realized.

[0442] <Configuration Example 3 of Semiconductor Device> FIG. 29B is a cross-sectional view of transistor 2100B in the channel length direction.

[0443] The transistor 2100B is provided over a substrate 2102 and includes an insulating layer 2121, an insulating layer 2122, an insulating layer 2123, a conductive layer 2134, an insulating layer 2136, a semiconductor layer 2138, a conductive layer 2142a, a conductive layer 2142b, an insulating layer 2144, an insulating layer 2146, an insulating layer 2124, an insulating layer 2125, an insulating layer 2126, and the like. The insulating layer 2121, the insulating layer 2122, and the insulating layer 2123 are provided in this order over the substrate 2102, and the conductive layer 2134 is provided over the insulating layer 2123. The insulating layer 2136 is provided to cover the conductive layer 2134. The semiconductor layer 2138 has an island shape and is provided over the insulating layer 2136. The conductive layer 2142a and the conductive layer 2142b are each in contact with the top surface of the semiconductor layer 2138 and are provided separately from each other over the semiconductor layer 2138. An insulating layer 2144 is provided to cover the insulating layer 2136, the conductive layer 2142a, the conductive layer 2142b, and the semiconductor layer 2138, and an insulating layer 2146 is provided over the insulating layer 2144. The insulating layer 2124 is provided over the insulating layer 2146 and has a region in contact with part of the insulating layer 2123. The insulating layer 2125 has a region in contact with part of the insulating layer 2122 and the insulating layer 2121 and is provided over the insulating layer 2124. The insulating layer 2126 is provided over the insulating layer 2125.

[0444] In the transistor 2100B, at least the semiconductor layer 2138 is preferably provided between the insulating layer 2123 and the insulating layer 2124, and the insulating layer 2123 and the insulating layer 2124 are preferably in contact with each other on the outside of the semiconductor layer 2108. The insulating layer 2123 and the insulating layer 2124 are provided between the insulating layer 2121 and the insulating layer 2122 and the insulating layer 2125 and the insulating layer 2126. In this case, the insulating layer 2125 is preferably in contact with at least the insulating layer 2122, and more preferably in contact with the insulating layer 2121. In other words, in the transistor 2100B, the semiconductor layer 2138 is surrounded by the insulating layer 2123 and the insulating layer 2124, and the semiconductor layer 2108, the insulating layer 2123, and the insulating layer 2124 are surrounded by the insulating layer 2122 and the insulating layer 2125. Furthermore, the semiconductor layer 2138, the insulating layer 2123, the insulating layer 2124, the insulating layer 2122, and the insulating layer 2125 are sandwiched between the insulating layer 2121 and the insulating layer 2126, and therefore can be said to be surrounded by the insulating layer 2121 and the insulating layer 2126.

[0445] The conductive layer 2134 functions as a gate electrode. Part of the insulating layer 2136 functions as a gate insulating layer. The conductive layer 2142a functions as one of a source electrode and a drain electrode, and the conductive layer 2142b functions as the other. A region of the semiconductor layer 2138 overlapping with the conductive layer 2134 functions as a channel formation region. The transistor 2100B is a so-called bottom-gate transistor in which a gate electrode is provided on the formation surface side (the substrate 2102 side) of the semiconductor layer 2138. Here, the surface of the semiconductor layer 2138 opposite to the conductive layer 2134 side may be referred to as the back channel side surface. The transistor 2100B is a transistor with a so-called channel-etched structure in which no protective layer is provided between the back channel side of the semiconductor layer 2138 and the source electrode and the drain electrode.

[0446] The semiconductor layer 2138 has a layered structure in which a semiconductor layer 2138a and a semiconductor layer 2138b are stacked in this order from the formation surface side. Both the semiconductor layer 2138a and the semiconductor layer 2138b preferably contain metal oxide. The semiconductor layer 2138b located on the back channel side is preferably a film with higher crystallinity than the semiconductor layer 2138a located on the conductive layer 2134 side. This can prevent a part of the semiconductor layer 2138 from being etched and lost when the conductive layers 2142a and 2142b are processed.

[0447] The semiconductor layer 2138 can be made of an oxide such as a metal oxide that can be used for the oxide 230 shown in other embodiments or other configuration examples. For example, the semiconductor layer 2138 preferably contains indium, M (M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0448] In particular, it is preferable to use an oxide containing indium, gallium, and zinc for the semiconductor layer 2138.

[0449] The semiconductor layer 2138a and the semiconductor layer 2138b may be layers having different compositions, different crystallinity, or different impurity concentrations. Alternatively, they may have a stacked structure of three or more layers.

[0450] The conductive layer 2142a and the conductive layer 2142b each have a layered structure in which a conductive layer 2143a, a conductive layer 2143b, and a conductive layer 2143c are stacked in this order from the formation surface side.

[0451] The conductive layer 2143b is preferably made of a low-resistance conductive material containing copper, silver, gold, aluminum, or the like. In particular, the conductive layer 2143b preferably contains copper or aluminum. The conductive layer 2143b is preferably made of a conductive material having lower resistance than the conductive layers 2143a and 2143c. This allows the conductive layers 2142a and 2142b to have extremely low resistance.

[0452] The conductive layer 2143a and the conductive layer 2143c can each independently be formed using a conductive material different from that of the conductive layer 2143b. For example, the conductive layer 2143a and the conductive layer 2143c can each independently be formed using a conductive material containing titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, ruthenium, or the like.

[0453] In this manner, by sandwiching the conductive layer 2143b containing copper, aluminum, or the like between the conductive layer 2143a and the conductive layer 2143c, it is possible to suppress oxidation of the surface of the conductive layer 2143b and to suppress diffusion of elements of the conductive layer 2143b into surrounding layers. In particular, by providing the conductive layer 2143a between the semiconductor layer 2138 and the conductive layer 2143b, it is possible to prevent the metal elements contained in the conductive layer 2143b from diffusing into the semiconductor layer 2138, thereby realizing a highly reliable transistor 2100B.

[0454] Here, an insulating layer 2144 is provided in contact with the end of the conductive layer 2143b.

[0455] The conductive layers 2142a and 2142b are not limited to a three-layer structure, and may be a two-layer structure including a conductive layer containing copper, silver, gold, or aluminum, or a four-layer structure. For example, the conductive layers 2142a and 2142b may be a two-layer structure in which the conductive layers 2143a and 2143b are stacked, or a two-layer structure in which the conductive layers 2143b and 2143c are stacked.

[0456] The conductive layer 2134 can be formed using any of the above-mentioned conductive materials that can be used for the conductive layers 2143a, 2143b, and 2143c. In particular, it is preferable to use a conductive material containing copper.

[0457] An insulating material containing oxide is preferably used for the insulating layer 2136 and the insulating layer 2144 in contact with the semiconductor layer 2138. When the insulating layer 2136 and the insulating layer 2144 have a stacked structure, an insulating material containing oxide is used for the layer in contact with the semiconductor layer 2138.

[0458] Alternatively, a nitride insulating film such as silicon nitride or aluminum nitride may be used for the insulating layer 2136. When an insulating material not containing oxide is used, it is preferable to form a region containing oxygen by performing treatment to add oxygen to the upper part of the insulating layer 2136. Examples of treatment to add oxygen include heat treatment or plasma treatment in an atmosphere containing oxygen, and ion doping treatment.

[0459] The insulating layer 2146 functions as a protective layer that protects the transistor 2100B. The insulating layer 2146 can be formed using an inorganic insulating material such as silicon nitride, silicon nitride oxide, silicon oxide, silicon oxynitride, aluminum oxide, or aluminum nitride. In particular, using a material that does not easily diffuse oxygen, such as silicon nitride or aluminum oxide, for the insulating layer 2146 is preferable because oxygen can be prevented from being released from the semiconductor layer 2138 or the insulating layer 2144 to the outside through the insulating layer 2146 due to heat or the like applied during the manufacturing process.

[0460] Alternatively, an organic insulating material that functions as a planarizing film may be used as the insulating layer 2146. Alternatively, the insulating layer 2146 may be a stacked film of a film containing an inorganic insulating material and a film containing an organic insulating material.

[0461] The semiconductor layer 2138 may have a pair of low-resistance regions that function as a source region and a drain region and are located in contact with and near the conductive layer 2142a and the conductive layer 2142b. These regions are part of the semiconductor layer 2138 and have lower resistance than the channel formation region. The low-resistance region can also be referred to as a region with high carrier density or an n-type region. In addition, a region of the semiconductor layer 2138 that is sandwiched between the pair of low-resistance regions and overlaps with the conductive layer 2134 functions as a channel formation region.

[0462] The insulating layer 2123 and the insulating layer 2124 can be formed using the materials shown in the previous structural example.

[0463] 29B , insulating layer 2136, insulating layer 2144, and insulating layer 2146 are partially removed outside conductive layer 2134, semiconductor layer 2138, conductive layer 2142a, and conductive layer 2142b in the channel length direction. In this case, the end of insulating layer 2136, the end of insulating layer 2144, and the end of insulating layer 2146 may be approximately aligned. Furthermore, the side surfaces of insulating layer 2136, the side surfaces of insulating layer 2144, and the side surfaces of insulating layer 2146 may be coplanar. Therefore, insulating layer 2123 has regions that do not overlap with insulating layer 2136, insulating layer 2144, and insulating layer 2146.

[0464] The insulating layer 2124 is provided to cover the top and side surfaces of the insulating layer 2146 , the side surfaces of the insulating layer 2144 , and the side surfaces of the insulating layer 2136 , and has a region in contact with part of the insulating layer 2123 .

[0465] Although not shown, the insulating layer 2123 in a region that does not overlap with the insulating layer 2136, the insulating layer 2144, or the insulating layer 2146 is preferably provided in contact with the insulating layer 2124 in the channel width direction as well.

[0466] With the above structure, impurities such as hydrogen contained in the semiconductor layer 2138, the insulating layer 2136, the insulating layer 2144, the insulating layer 2146, and the like can be efficiently absorbed by the insulating layer 2123 and the insulating layer 2124, thereby enabling gettering of the impurities such as hydrogen. In addition, oxygen contained in the semiconductor layer 2138, the insulating layer 2136, the insulating layer 2144, the insulating layer 2146, and the like can be prevented from diffusing outside the insulating layer 2123 and the insulating layer 2124.

[0467] The insulating layer 2121, the insulating layer 2122, the insulating layer 2125, and the insulating layer 2126 can be formed using the materials shown in the previous structural example.

[0468] The insulating layer 2125 is provided to cover the insulating layer 2124. The insulating layer 2125 is preferably in contact with the insulating layer 2122 so as to surround the insulating layer 2123 and the insulating layer 2124. The insulating layer 2125 is further preferably in contact with the insulating layer 2121 on the outside of the insulating layer 2123 and the insulating layer 2124. The insulating layer 2126 is provided over the insulating layer 2125.

[0469] The above structure can prevent impurities such as hydrogen from entering the semiconductor layer 2138 from outside the insulating layers 2121, 2122, 2125, and 2126. In other words, in the transistor 2100B, at least the semiconductor layer 2138 is surrounded by the insulating layers 2121, 2122, 2125, and 2126, which can prevent impurity elements such as hydrogen from entering from the outside.

[0470] Note that although the protective layer has a stacked structure of insulating layers 2125 and 2126, one of the insulating layers 2125 and 2126 may not be provided if it is not necessary. The insulating layer 2125 may have a stacked structure of two or more layers. Similarly, the protective layer has a stacked structure of insulating layers 2121 and 2122, but one of the insulating layers 2121 and 2122 may not be provided if it is not necessary. The insulating layer 2122 may have a stacked structure of two or more layers.

[0471] With this configuration, a transistor 2100B with excellent electrical characteristics and high reliability can be realized.

[0472] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0473] (Fourth embodiment) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0474] [Storage device 1] 30 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be the transistor 200. Alternatively, the transistor 2100A or the transistor 2100B described in the above embodiment can be used as the transistor 200. Alternatively, as illustrated in FIGS. 1 and 2 in the above embodiment, a transistor of the memory device 290 may be used as the transistor 200, and a capacitor 292 may be provided as the capacitor 100.

[0475] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0476] 30 , a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0477] Moreover, the memory device shown in FIG. 30 can be arranged in a matrix to form a memory cell array.

[0478] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0479] Here, in the transistor 300 shown in FIG. 30, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0480] Note that the transistor 300 shown in FIG. 30 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0481] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric. Here, the insulator 130 is preferably the same as the insulator 286 described in the above embodiment.

[0482] For example, the conductor 112 over the conductor 246 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0483] 30, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0484] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0485] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0486] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0487] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0488] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0489] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0490] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0491] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 30, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0492] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 211, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0493] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 211, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 211, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0494] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 211, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0495] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0496] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0497] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0498] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0499] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulators 214, 211, 212, and 350 can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0500] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0501] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0502] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. Using a low-resistance conductive material can reduce wiring resistance.

[0503] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0504] 30, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 272, the insulator 273, the insulator 282, the insulator 283, and the insulator 284, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0505] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0506] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high blocking property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0507] As in the above embodiment, the transistor 200 is preferably sealed with the insulators 211, 212, 214, 287, 282, 283, and 284. This structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0508] Here, the conductor 240 penetrates the insulators 284, 283, and 282, and the conductor 218 penetrates the insulators 214, 212, and 211. However, as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 211, 212, 214, 287, 282, 283, and 284 via the conductors 240 and 218. In this way, the transistor 200 can be more reliably sealed with the insulators 211, 212, 214, 287, 282, 283, 284, 241, and 217, and it is possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 274 from the outside.

[0509] Furthermore, as described in the previous embodiment, the insulators 216, 224, 280, 250, and 274 are preferably formed by a deposition method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 274.

[0510] In this way, the hydrogen concentration in the silicon-based insulating film near the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0511] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0512] 30, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 273, the insulator 272, the insulator 224, the insulator 222, the insulator 216, the insulator 214, and the insulator 212 so that the area where the insulator 283 and the insulator 211 contact each other overlaps with the dicing line. That is, in the vicinity of the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200, openings are provided in the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212.

[0513] That is, the insulator 211 and the insulator 283 contact each other through openings formed in the insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212. Alternatively, openings may be formed in the insulators 282, 280, 273, 272, 224, 222, 216, and 214, and the insulators 212 and 283 may contact each other through the openings. For example, the insulators 212 and 283 may be formed using the same material and the same method. Providing the insulators 212 and 283 using the same material and the same method can improve adhesion. For example, silicon nitride is preferably used.

[0514] With this structure, the transistor 200 can be surrounded by the insulators 211, 212, 214, 287, 282, 283, and 284. At least one of the insulators 211, 212, 214, 287, 282, 283, and 284 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0515] Furthermore, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0516] 30, the shape of the capacitor 100 is a planar type, but the shape of the capacitor 100 in the memory device shown in this embodiment is not limited to this. For example, as shown in FIG. 31, the shape of the capacitor 100 may be a cylindrical type. Note that the memory device shown in FIG. 31 has the same configuration below the insulator 150 as the semiconductor device shown in FIG.

[0517] 31 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the openings formed in the insulator 150 and the insulator 142.

[0518] The conductor 115 functions as the lower electrode of the capacitor 100, the conductor 125 functions as the upper electrode of the capacitor 100, and the insulator 145 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 150 and 142, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0519] The insulator 152 may be an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be an insulator that can be used for the insulator 214.

[0520] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be rectangular, a polygonal shape other than a rectangular, a polygonal shape with curved corners, or a circular shape including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0521] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0522] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0523] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0524] Examples of high-dielectric-constant (high-k) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials ensures sufficient capacitance of the capacitor 100 even when the insulator 145 is thick. By thickening the insulator 145, leakage current between the conductor 115 and the conductor 125 can be suppressed.

[0525] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x), silicon nitride (SiN x ) can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0526] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0527] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0528] 30 and 31 show a configuration in which one layer of transistor 200 is stacked on transistor 300, but the present embodiment is not limited to this. For example, a memory device 290 as shown in FIGS. 1 and 2, or multiple memory devices 290 stacked vertically as shown in FIGS. 5 and 6, may be provided on transistor 300.

[0529] FIG. 32 shows memory devices 290_1 to 290_n (n is a natural number of 2 or more). Note that in this embodiment, a configuration in which the memory device 290_n is provided has been exemplified, but the present invention is not limited to this. For example, a configuration in which the memory device 290_n is not provided may also be used. Note that the value of n is not particularly limited, but can be 2 to 200, preferably 2 to 100, and more preferably 2 to 10. FIG. 32B shows a cross-sectional view of a transistor included in the memory device 290 in the channel length direction. FIG. 32A shows a cross-sectional view of the transistor in the channel width direction at a portion indicated by the dashed dotted line AB in FIG. 32B. The memory device shown in FIG. 32 has the same structure below the insulator 354 as the memory device shown in FIG. 30.

[0530] 32, memory devices 290_1 to 290_n are stacked on an insulator 354. Each layer including the memory device 290 is provided with a capacitance device 292 and a conductor 240. The memory device 290 in each layer is electrically connected to the conductor 240 in the adjacent layer via the conductor 240 in each layer, and is also electrically connected to the transistor 300. Note that in FIG. 32B, hidden portions of the conductors 240_1 to 240_n in the channel width direction are represented by dotted lines.

[0531] The memory device 290 shown in FIG. 32 has a different structure from the memory device 290 shown in FIG. 1. In the memory device 290 shown in FIG. 32, the conductor 240 is formed so as to straddle the oxide 230b and the like, and the insulator 241 is formed on the side of the conductor 240. Here, the insulator 241 is not formed on the lower surface of the conductor 240, so the lower surface of the conductor 240 in each layer contacts the conductor 242a in that layer and the conductor 246a in the layer immediately below. This allows the memory device 290 in each layer to be electrically connected to the conductor 246a in the layer immediately below.

[0532] However, the memory device described in this embodiment is not limited to the structure shown in Fig. 32. For example, a structure may be adopted in which a conductor 240 is provided between an upper conductor 246a and a lower conductor 246a by penetrating an oxide 230b or the like. Furthermore, for example, a structure may be adopted in which the conductors 240_1 to 240_n are formed by one through electrode.

[0533] Furthermore, since the capacitor device 292 is formed as a planar type in each layer, it is possible to prevent the height of each layer from becoming excessively large. This makes it relatively easy to increase the number of layers of the memory device 290. For example, the number of layers of the memory device 290 may be about 100.

[0534] The above is a description of the configuration example. By using this configuration, in a semiconductor device using a transistor including an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

[0535] [Storage device 2] An example of a memory device using a semiconductor device according to one embodiment of the present invention is illustrated in Fig. 33. The memory device illustrated in Fig. 33 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in Fig. 30.

[0536] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 are 0 V. Because the drain current of the transistor 400 is very small when the second gate voltage and the first gate voltage are 0 V, the negative potential of the second gate of the transistor 200 can be maintained for a long time without supplying power to the transistors 200 and 400. This allows a memory device including the transistor 200 and 400 to retain stored content for a long time.

[0537] 33, a wiring 1001 is electrically connected to the source of the transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of the transistor 200, a wiring 1004 is electrically connected to the gate of the transistor 200, and a wiring 1006 is electrically connected to the backgate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100. A wiring 1007 is electrically connected to the source of the transistor 400, a wiring 1008 is electrically connected to the gate of the transistor 400, a wiring 1009 is electrically connected to the backgate of the transistor 400, and a wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

[0538] 30, the memory device illustrated in FIG. 33 can be arranged in a matrix to form a memory cell array. Note that one transistor 400 can control the second gate voltages of multiple transistors 200. Therefore, it is preferable to provide fewer transistors 400 than transistors 200. Furthermore, in the memory device illustrated in FIG. 33, like the memory device illustrated in FIG. 30, the transistors 200 and 400 can be sealed with insulators 211, 212, 214, 287, 282, 283, and 284.

[0539] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and can be fabricated in parallel. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) functioning as a first gate, a conductor 405 functioning as a second gate, insulators 222, 224, and 450 functioning as gate insulating layers, an oxide 430c having a channel formation region, conductor 442a, oxide 443a, oxide 431a, and oxide 431b functioning as a source, and conductor 442b, oxide 443b, oxide 432a, and oxide 432b functioning as a drain. Similar to the transistor 200, conductors functioning as plugs are provided in contact with the conductor 442a and the conductor 442b.

[0540] In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b. The conductor 442 is in the same layer as the conductor 242. The oxide 443 is in the same layer as the oxide 243. The oxide 430c is in the same layer as the oxide 230c. The insulator 450 is in the same layer as the insulator 250. The conductor 460 is in the same layer as the conductor 260.

[0541] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing the oxide film that will become oxide 230c.

[0542] The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water, similar to the oxide 230. As a result, the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0543] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0544] (Embodiment 5) In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 34 and 35 . The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0545] <Storage device configuration example> 34A shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0546] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to the memory cell of the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to access.

[0547] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.

[0548] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0549] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0550] 34A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 34B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0551] FIG. 35 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0552] [DOSRAM] 35A to 35C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 35A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a front gate) and a back gate.

[0553] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0554] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0555] Furthermore, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 35B. Furthermore, for example, the memory cell MC may be configured as a memory cell including a single-gate transistor, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 35C.

[0556] When the semiconductor device described in the above embodiment is used in the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. Alternatively, as shown in FIGS. 1 and 2 in the above embodiment, a transistor of the memory device 290 can be used as the transistor M1, and the capacitor 292 can be provided as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0557] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0558] FIG. 36A shows an example of a memory device 1400 in which a memory cell array 1470 is provided on a peripheral circuit 1411 and a plurality of memory cells 1471 are provided in the memory cell array 1470.

[0559] In the memory cell array 1470, a plurality of memory cells 1471 are arranged in a matrix, and wirings WOL, wirings BGL, etc. are also extended in the row direction or column direction in the memory cell array 1470. The wirings BIL are connected to the column circuits 1430 provided in the peripheral circuit 1411, and the memory cell array 1470 is electrically connected to a sense amplifier, etc. via the wirings BIL.

[0560] The memory cell array 1470 includes OS transistors, and as described in the previous embodiment, is preferably sealed with the insulators 211, 212, 214, 287, 282, 283, and 284. For example, as shown in FIG. 27 , the top, side, and bottom surfaces of the memory cell array 1470 are preferably sealed with the insulators 211, 212, 214, 287, 282, 283, and 284.

[0561] 36B, a structure in which multiple memory cell arrays 1470_1 to 1470_n (n is a natural number equal to or greater than 2) are stacked may be used. The structure of each memory cell array 1470 is almost the same as the structure shown in FIG. 36A, but the column circuit 1430 and the memory cells 1471 of each memory cell array 1470 are connected by wiring BIL. The wiring BIL may be formed by a single or multiple conductors 240 penetrating the memory cell arrays 1470_1 to 1470_n, as shown in FIG.

[0562] The plurality of memory cell arrays 1470 each include an OS transistor, and as shown in the above embodiment, the plurality of memory cell arrays 1470 are preferably collectively sealed with the insulators 211, 212, 214, 287, 282, 283, and 284. For example, as shown in FIG. 5, FIG. 6, or FIG. 32, the top, side, and bottom surfaces of the plurality of memory cell arrays 1470 are preferably sealed with the insulators 211, 212, 214, 287, 282, 283, and 284. As shown in FIG. 5 and FIG. 6, the insulators 282, 296, 298, and 214 are preferably stacked at the boundary of each memory cell array 1470.

[0563] [NOSRAM] 35D to 35H show circuit configuration examples of a gain cell type memory cell with two transistors and one capacitor. Memory cell 1474 shown in FIG. 35D includes transistor M2, transistor M3, and capacitor CB. Transistor M2 has a front gate (sometimes simply referred to as a gate) and a back gate. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor as transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0564] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0565] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0566] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 35E. Furthermore, for example, the memory cell MC may be configured as a memory cell having a single gate structure, that is, a memory cell including a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 35F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 35G.

[0567] When the semiconductor device described in the above embodiment is used in the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. Alternatively, as shown in FIGS. 1 and 2 in the above embodiment, a transistor of the memory device 290 can be used as the transistor M2, and the capacitor 292 can be provided as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be retained by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, the extremely low leakage current allows the memory cell 1474 to retain multilevel data or analog data. The same applies to the memory cells 1475 to 1477.

[0568] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0569] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0570] FIG. 35H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 35H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0571] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0572] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0573] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors 300, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be significantly reduced. Alternatively, as shown in FIGS. 1 and 2 in the above embodiment, a transistor of the memory device 290 can be used as the transistor M4, and a capacitor 292 can be provided as the capacitor CC.

[0574] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0575] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0576] (Sixth embodiment) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown with reference to Fig. 37. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0577] As shown in FIG. 37A, chip 1200 has a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0578] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201, as shown in Fig. 37B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of PCB 1201, which is connected to a motherboard 1203.

[0579] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0580] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0581] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0582] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0583] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0584] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0585] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0586] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0587] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0588] The GPU module 1204 includes the chip 1200 using SoC technology, allowing its size to be reduced. Furthermore, because it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute operations such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0589] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0590] (Embodiment 7) In this embodiment, application examples of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" here refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIG. 38 schematically shows several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0591] 38A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 of the board 1104.

[0592] FIG. 38B is a schematic diagram of the appearance of an SD card, and FIG. 38C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113, etc.

[0593] FIG. 38D is a schematic diagram of the appearance of an SSD, and FIG. 38E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 of board 1153, etc.

[0594] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiments.

[0595] (Embodiment 8) In this embodiment, a field-programmable gate array (FPGA) will be described as an example of a semiconductor device to which an OS transistor and a capacitor according to one embodiment of the present invention are applied, with reference to FIGS. 39 to 42. In the FPGA of this embodiment, an OS memory is applied to a configuration memory and a register. Here, such an FPGA is referred to as an "OS-FPGA."

[0596] < <os-fpga>> Figure 39A shows an example of the configuration of an OS-FPGA. The OS-FPGA 3110 shown in Figure 39A is capable of normally-off (NOFF) computing, which performs context switching using a multi-context structure and fine-grained power gating for each PLE. The OS-FPGA 3110 has a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

[0597] The programmable area 3115 has two input / output blocks (IOBs) 3117 and a core 3119. The IOB 3117 has multiple programmable input / output circuits. The core 3119 has multiple logic array blocks (LABs) 3120 and multiple switch array blocks (SABs) 3130. The LAB 3120 has multiple PLEs 3121. Figure 39B shows an example in which the LAB 3120 is configured with five PLEs 3121. As shown in Figure 39C, the SAB 3130 has multiple switch blocks (SBs) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and to the LABs 3120 in the four directions (top, bottom, left, and right) via the SAB 3130.

[0598] SB3131 will be described with reference to FIGS. 40A to 40C. SB3131 shown in FIG. 40A receives inputs of data, datab, signals context[1:0], and word[1:0]. data and datab are configuration data, and data and datab have complementary logic. The number of contexts in the OS-FPGA3110 is two, and signal context[1:0] is a context selection signal. Signal word[1:0] is a word line selection signal, and the wiring to which signal word[1:0] is input is each a word line. Note that input shown in FIG. 40A corresponds to the input terminal of SB3131, and output corresponds to the output terminal of SB3131.

[0599] The SB3131 has PRS (programmable routing switches) 3133[0] and 3133[1]. PRS3133[0] and 3133[1] have configuration memories (CMs) that can store complementary data. When there is no need to distinguish between PRS3133[0] and PRS3133[1], they are referred to as PRS3133. The same applies to other elements.

[0600] Figure 40B shows an example of the circuit configuration of PRS3133[0]. PRS3133[0] and PRS3133[1] have the same circuit configuration. PRS3133[0] and PRS3133[1] have different input context selection signals and word line selection signals. Signals context[0] and word[0] are input to PRS3133[0], and signals context[1] and word[1] are input to PRS3133[1]. For example, in SB3131, when signal context[0] becomes "H", PRS3133[0] becomes active.

[0601] PRS3133[0] includes CM3135 and Si transistor M31. Si transistor M31 is a pass transistor controlled by CM3135. CM3135 includes memory circuits 3137 and 3137B. Memory circuits 3137 and 3137B have the same circuit configuration. Memory circuit 3137 includes a capacitance element C31 and OS transistors MO31 and MO32. Memory circuit 3137B includes a capacitance element CB31 and OS transistors MOB31 and MOB32.

[0602] When the semiconductor device described in the above embodiment is used for the SAB3130, the transistors described in the above embodiment can be used as the OS transistors MO31 and MOB31. This reduces the off-state current of the OS transistors MO31 and MOB31, allowing configuration data to be retained for a long period of time. Furthermore, the area occupied by each pair of a transistor and a capacitor in a top view can be reduced, enabling high integration of the semiconductor device according to this embodiment.

[0603] The OS transistors MO31, MO32, MOB31, and MOB32 each have a back gate, and these back gates are electrically connected to a power supply line that supplies a fixed voltage.

[0604] The gate of Si transistor M31 is node N31, the gate of OS transistor MO32 is node N32, and the gate of OS transistor MOB32 is node NB32. Nodes N32 and NB32 are charge retention nodes of CM3135. OS transistor MO32 controls the conduction state between node N31 and the signal line for signal context[0]. OS transistor MOB32 controls the conduction state between node N31 and the low-potential power supply line VSS.

[0605] The data held in memory circuits 3137 and 3137B are complementary to each other, so either OS transistor MO32 or MOB32 is turned on.

[0606] An example of the operation of PRS3133[0] will be described with reference to Fig. 40C. Configuration data has already been written to PRS3133[0], and node N32 of PRS3133[0] is "H" and node NB32 is "L".

[0607] While the signal context[0] is "L", PRS3133[0] is inactive. During this period, even if the input terminal of PRS3133[0] transitions to "H", the gate of Si transistor M31 remains "L", and the output terminal of PRS3133[0] also remains "L".

[0608] PRS3133[0] is active while the signal context[0] is "H". When the signal context[0] transitions to "H", the gate of the Si transistor M31 transitions to "H" according to the configuration data stored in CM3135.

[0609] When the input terminal transitions to "H" while PRS3133[0] is active, the gate voltage of the Si transistor M31 rises due to boosting because the OS transistor MO32 of the memory circuit 3137 is a source follower. As a result, the OS transistor MO32 of the memory circuit 3137 loses its driving capability, and the gate of the Si transistor M31 becomes floating.

[0610] In the PRS3133, which has a multi-context function, the CM3135 also has the function of a multiplexer.

[0611] 41 shows an example configuration of the PLE 3121. The PLE 3121 has an LUT (look-up table) block 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to select and output internal data according to inputs inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.

[0612] The PLE 3121 is electrically connected to the power supply line for voltage VDD via a power switch 3127. The on / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grained power gating is possible. The fine-grained power gating function makes it possible to power gate PLE 3121 that is not used after a context switch, thereby effectively reducing standby power consumption.

[0613] To realize NOFF computing, the register block 3124 is configured with a nonvolatile register. The nonvolatile register in the PLE 3121 is a flip-flop with OS memory (hereinafter referred to as [OS-FF]).

[0614] The register block 3124 has OS-FFs 3140[1] and 3140[2]. The signals user_res, load, and store are input to the OS-FFs 3140[1] and 3140[2]. The clock signal CLK1 is input to the OS-FF 3140[1], and the clock signal CLK2 is input to the OS-FF 3140[2]. An example configuration of the OS-FF 3140 is shown in Figure 42A.

[0615] The OS-FF3140 has an FF3141 and a shadow register 3142. The FF3141 has nodes CK, R, D, Q, and QB. A clock signal is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. The node D is a data input node, and the node Q is a data output node. The nodes Q and QB have complementary logic.

[0616] The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB in accordance with the signal store, and writes the backed up data back to the nodes Q and QB in accordance with the signal load.

[0617] The shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B. The memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitance element C36 and OS transistors MO35 and MO36. The memory circuit 3143B includes a capacitance element CB36 and OS transistors MOB35 and MOB36. Nodes N36 and NB36 are the gates of the OS transistors MO36 and MOB36, and are charge retention nodes, respectively. Nodes N37 and NB37 are the gates of the Si transistors M37 and MB37.

[0618] When the semiconductor device described in the above embodiment is used for LAB3120, the transistors described in the above embodiment can be used as the OS transistors MO35 and MOB35. This reduces the off-state current of the OS transistors MO35 and MOB35, allowing backed-up data to be retained for a long period of time in the OS-FF. Furthermore, the area occupied by each pair of a transistor and a capacitor in a top view can be reduced, enabling the semiconductor device according to this embodiment to be highly integrated.

[0619] The OS transistors MO35, MO36, MOB35, and MOB36 each have a back gate, and these back gates are electrically connected to a power supply line that supplies a fixed voltage.

[0620] An example of the operation method of OS-FF 3140 will be described with reference to FIG. 42B.

[0621] (Backup) When a "H" signal store is input to OS-FF3140, the shadow register 3142 backs up the data of FF3141. Node N36 becomes "L" when data of node Q is written thereto, and node NB36 becomes "H" when data of node QB is written thereto. After that, power gating is executed and the power switch 3127 is turned off. The data of nodes Q and QB of FF3141 is lost, but the shadow register 3142 retains the backed up data even when the power is off.

[0622] (Recovery) Turn on the power switch 3127 to supply power to PLE3121. After that, when the signal load of "H" is input to OS-FF3140, the shadow register 3142 writes back the backed-up data to FF3141. Since node N36 is "L", node N37 maintains "L", and since node NB36 is "H", node NB37 becomes "H". Therefore, node Q becomes "H" and node QB becomes "L". That is, OS-FF3140 returns to the state during the backup operation.

[0623] By combining fine-grained power gating and the backup / recovery operation of OS-FF3140, the power consumption of OS-FPGA3110 can be effectively reduced.

[0624] An example of an error that can occur in a memory circuit is a soft error caused by the incidence of radiation. A soft error occurs when an alpha ray emitted from materials such as those constituting a memory or package, or a secondary cosmic ray neutron generated by a nuclear reaction between a primary cosmic ray incident from space to the atmosphere and the nucleus of an atom existing in the atmosphere irradiates a transistor, generating electron-hole pairs, resulting in malfunctions such as the inversion of data held in the memory. An OS memory using OS transistors has high soft error tolerance. Therefore, by mounting an OS memory, a highly reliable OS-FPGA3110 can be provided.

[0625] The configuration shown in this embodiment can be appropriately combined with the configuration shown in other embodiments and used.

[0626] (Embodiment 9) In this embodiment, an example of a CPU including a semiconductor device according to an aspect of the present invention, such as the above-described storage device, will be described.

[0627] <Configuration of CPU> 43 includes a CPU core 6401, a power management unit 6421, and a peripheral circuit 6422. The power management unit 6421 includes a power controller 6402 and a power switch 6403. The peripheral circuit 6422 includes a cache 6404 having a cache memory, a bus interface (BUS I / F) 6405, and a debug interface (Debug I / F) 6406. The CPU core 6401 includes a data bus 6423, a control unit 6407, a PC (program counter) 6408, a pipeline register 6409, a pipeline register 6410, an ALU (arithmetic logic unit) 6411, and a register file 6412. Data is exchanged between the CPU core 6401 and peripheral circuits 6422 such as a cache 6404 via a data bus 6423 .

[0628] The semiconductor device described in the above embodiment can be applied to many logic circuits, including the power controller 6402 and the control device 6407. As a result, a semiconductor device 6400 capable of reducing power consumption can be provided. Further, a semiconductor device 6400 capable of improving operation speed can be provided. Further, a semiconductor device 6400 capable of reducing fluctuations in power supply voltage can be provided.

[0629] Furthermore, it is preferable to apply a p-channel Si transistor and the transistor including an oxide semiconductor in a channel formation region described in the above embodiment to the semiconductor device 6400. This makes it possible to provide a small-sized semiconductor device 6400. Furthermore, it is possible to provide a semiconductor device 6400 that can reduce power consumption. Furthermore, it is possible to provide a semiconductor device 6400 that can improve operation speed. In particular, by using only p-channel Si transistors, it is possible to reduce the manufacturing cost of the semiconductor device.

[0630] The control device 6407 has the function of comprehensively controlling the operations of the PC 6408, pipeline register 6409, pipeline register 6410, ALU 6411, register file 6412, cache 6404, bus interface 6405, debug interface 6406, and power controller 6402, thereby decoding and executing instructions contained in programs such as input applications.

[0631] The ALU 6411 has the function of performing various arithmetic operations such as arithmetic operations and logical operations.

[0632] The cache 6404 has the function of temporarily storing frequently used data. The PC 6408 is a register that has the function of storing the address of the next instruction to be executed. Although not shown in FIG. 43, the cache 6404 is provided with a cache controller that controls the operation of the cache memory.

[0633] The pipeline register 6409 is a register that has the function of temporarily storing instruction data.

[0634] The register file 6412 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of the arithmetic processing of the ALU 6411, and the like.

[0635] The pipeline register 6410 is a register that has the function of temporarily storing data used in the arithmetic processing of the ALU 6411, or data obtained as a result of the arithmetic processing of the ALU 6411, and the like.

[0636] The bus interface 6405 functions as a data path between the semiconductor device 6400 and various devices external to the semiconductor device 6400. The debug interface 6406 functions as a signal path for inputting commands for controlling debugging into the semiconductor device 6400.

[0637] The power switch 6403 has a function of controlling the supply of power supply voltage to various circuits other than the power controller 6402 included in the semiconductor device 6400. The various circuits described above belong to several power domains, and the supply of power supply voltage to various circuits belonging to the same power domain is controlled by the power switch 6403. In addition, the power controller 6402 has a function of controlling the operation of the power switch 6403.

[0638] The semiconductor device 6400 having the above configuration can perform power gating. An example of the flow of power gating operations will be described.

[0639] First, the CPU core 6401 sets the timing for stopping the supply of power supply voltage in a register of the power controller 6402. Next, the CPU core 6401 sends a command to start power gating to the power controller 6402. Next, the various registers and cache 6404 included in the semiconductor device 6400 start saving data. Next, the power switch 6403 stops the supply of power supply voltage to various circuits other than the power controller 6402 included in the semiconductor device 6400. Next, an interrupt signal is input to the power controller 6402, which starts the supply of power supply voltage to various circuits included in the semiconductor device 6400. Note that a counter may be provided in the power controller 6402, and the timing for starting the supply of power supply voltage may be determined using the counter, regardless of the input of the interrupt signal. Next, the various registers and cache 6404 start restoring data. Next, instruction execution in the control device 6407 is resumed.

[0640] This type of power gating can be applied to the entire ...

Claims

1. a transistor and a capacitance device, The transistor is a first oxide semiconductor having a groove; a first conductor and a second conductor having a region disposed above the first oxide semiconductor and disposed to face each other with the trench portion interposed therebetween in a plan view; a second oxide semiconductor having a region disposed in the groove of the first oxide semiconductor and a region disposed between the first conductor and the second conductor; a first insulator having a region in contact with the second oxide semiconductor and a region facing a side surface and a bottom surface of the first oxide semiconductor in the trench with the second oxide semiconductor interposed therebetween; a third conductor having a region in contact with the first insulator and a region facing a side surface and a bottom surface of the first oxide semiconductor in the trench with the second oxide semiconductor and the first insulator interposed therebetween; The capacitive device is the second conductor; a second insulator having a region disposed above the second conductor; a fourth conductor having a region disposed above the second insulator; a side surface of the first oxide semiconductor, a first side surface of the first conductor, and a first side surface of the second conductor each have a region in contact with the second insulator; a second side surface of the first conductor and a second side surface of the second conductor have a region in contact with the second oxide semiconductor; a side surface of the first oxide semiconductor has a region facing the fourth conductor with the second insulator interposed therebetween; Memory device.

2. In claim 1, the first oxide semiconductor and the second oxide semiconductor each contain indium, an element M (M is gallium, yttrium, or tin), and zinc; Memory device.

3. In claim 2, the first oxide semiconductor has a region in which the atomic ratio of indium is higher than that of the second oxide semiconductor; Memory device.

4. In any one of claims 1 to 3, each of the first oxide semiconductor and the second oxide semiconductor has crystallinity; Memory device.

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