Temperature sensor for nonvolatile memory

Abstract

Embodiments of the present disclosure provide a temperature sensor that may be integrated into a memory device along with a 1T1C reference voltage generator, enabling the 1T1C reference voltage generator to provide a temperature-dependent 1T1C reference voltage to a memory core (e.g., an F-RAM memory core) of the memory device. The temperature sensor may detect the temperature of the memory core and output this information (e.g., as a trim) for the 1T1C reference voltage generator to use in providing the temperature-dependent 1T1C reference voltage. In this manner, the P-term and U-term margins of the memory core may be maintained even as the temperature of the memory core increases.

Description

[Technical Field]

[0001] Related Applications This application is an international application of U.S. Non-provisional Patent Application No. 17 / 219,160, filed March 31, 2021, which claims priority to U.S. Provisional Patent Application No. 63 / 153,412, filed February 25, 2021, all of which are incorporated herein by reference.

[0002] The present disclosure relates generally to non-volatile (NV) memory devices, and more particularly to temperature sensors for enabling single-ended sensing of temperature dependence, such as one-transistor-one-capacitor (hereinafter "1T1C") reference voltage generation for ferroelectric random access memory (F-RAM) devices. [Background technology]

[0003] Memory that retains its data even when operating power is unavailable is classified as NV memory. Examples of NV memory are non-volatile SRAM (nvSRAM), F-RAM, electrically erasable PROM (EEPROM), and flash memory. This class of memory can be used in applications where important data must be stored after power is removed or when power is interrupted during operation.

[0004] In some embodiments, for example in F-RAM devices, 1T1C refers to a memory cell architecture that utilizes single-ended sensing, as opposed to differential sensing used by 2T2C. More specifically, the sensing operation of a sense amplifier in a 1T1C architecture compares the amplitude of a memory signal output from a first memory cell to a reference signal. 1T1C F-RAM architectures are advantageous due to their smaller cell size compared to two-transistor, two-capacitor (2T2C) F-RAM architectures. The unswitching term (U-term) is the charge generated in an F-RAM ferroelectric capacitor when there is no polarity switching involved after a voltage or field is applied. The switching term (P-term) is the charge generated when there is polarity switching. In a 1T1C configuration, the U-term may represent a data "0" and the P-term may represent a data "1," or vice versa in some embodiments.

[0005] For 1T1C F-RAM, a reference voltage is required to distinguish between switching (P) and non-switching (U) terms and to distinguish a data "0" from a data "1." A temperature-independent 1T1C reference voltage may be generated, for example, from a programmable metal-oxide-semiconductor (MOS) capacitance array. The 1T1C reference voltage must be programmed such that the reference is higher than the maximum U term and lower than the minimum P term to properly distinguish a data "0" from a data "1."

[0006] Embodiments of the present invention are illustrated by way of example and not limitation in the accompanying drawings, in which: [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 illustrates a temperature sensor according to some embodiments of the present disclosure. [Figure 2] FIG. 10 illustrates a graph of comparator outputs representing different temperature zones, according to some embodiments of the present disclosure. [Figure 3]1 is a graph of P-term and U-term margins in a memory core when using a temperature independent 1T1C reference voltage and when using a temperature dependent 1T1C reference voltage generated using an embodiment of the present disclosure. [Figure 4] FIG. 1 illustrates a temperature sensor according to some embodiments of the present disclosure. [Figure 5] FIG. 5 is a block diagram illustrating the temperature sensor of FIG. 4 according to some embodiments of the present disclosure. [Figure 6A] 6 illustrates the performance of the temperature sensor of FIG. 5 in accordance with some embodiments of the present disclosure. [Figure 6B] 6 is a graph illustrating the relationship between temperature and counter digital output VCount of the sensor of FIG. 5 in accordance with some embodiments of the present disclosure. [Figure 7A] 1 illustrates a memory device in which embodiments of the present disclosure may be implemented. [Figure 7B] 1 illustrates a memory device in which embodiments of the present disclosure may be implemented. [Figure 8] 1 is a flow diagram of a method for providing a temperature-dependent 1T1C reference voltage in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present embodiments. However, it will be apparent to those skilled in the art that the present embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail, but rather in block diagram form, to avoid unnecessarily obscuring the understanding of this description.

[0009] References in the description to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in this description do not necessarily refer to the same embodiment.

[0010] The temperature-independent sensing or read reference voltage is fixed and determined based on the P-term and / or U-term at a specific temperature or temperature range and does not change with temperature. For example, the 1T1C reference voltage may be set to 21 mV above the U-term at room temperature. However, as the temperature of the F-RAM memory core increases, the P-term memory margin may gradually decrease, and as a result, both the P-term and U-term margins are inconsistent across temperature shifts (see Figure 3). In other NVM devices, the sensing reference voltage may be fixed according to other characteristics of the NVM cell, such as the drain current or threshold voltage of the flash memory.

[0011] While existing 2T2C solutions employing differential sensing may not require a sensing reference voltage, other alternative solutions require restricting the use of 1T1C cells until industrial temperatures (e.g., 85 degrees Celsius (°C)) are reached and adjusting the 1T1C voltage reference for all 1T1C macros. However, 2T2C solutions are area inefficient and therefore often reduce memory density by half. Other previous implementations have proposed utilizing conventional silicon-based temperature sensor designs based on bandgap-type circuits for the temperature sensor. However, these methods involve high levels of design complexity, slow startup times, high standby currents, and require large layout areas.

[0012] Embodiments of the present disclosure provide systems and devices (temperature sensors) in which a 1T1C reference voltage can be adjusted to configure the temperature behavior of an F-RAM memory. For convenience of explanation, described with respect to an F-RAM memory and a 1T1C architecture, embodiments of the present disclosure are not so limited and may be applied to memory devices having any suitable type of NV memory and a memory core based on any suitable architecture.

[0013] In one embodiment, a temperature sensor is provided that includes a resistor circuit including an n-well and a silicide-block polysilicon resistor. The n-well resistor has a large positive temperature coefficient. The polysilicon resistor, in comparison, has a small temperature coefficient close to zero. As the temperature of the memory core increases, the reference voltage of the temperature sensor may increase, while the input voltage of the temperature sensor decreases with increasing memory core temperature. The temperature sensor further includes a resistor stack with eight tap points, so that when current flows through the stack, the voltage at each tap point is lower than the voltage at the tap point above. Each tap point is connected to a respective comparator. Given the appropriate ratio between the resistors in the resistor circuit, the comparator outputs shift to define nine different temperature zones at a particular temperature. These outputs are used to adjust the 1T1C reference voltage provided to the memory core to compensate for increasing memory core temperature based on the designated temperature zone.

[0014] FIG. 1 illustrates a temperature sensor 100 (hereinafter referred to as “sensor 100”) for sensing the temperature of a memory core (e.g., F-RAM memory core 705 shown in FIG. 7 ). Sensor 100 may be integrated into a 1T1C reference voltage generator (e.g., F-RAM 1T1C reference voltage generator 715 shown in FIG. 7 ) to provide a temperature-dependent 1T1C reference voltage (hereinafter referred to as 1T1C Vref) to the memory core according to the sensed temperature of the memory core. In one embodiment, sensor 100 may be located physically adjacent to the memory core, such that sensor 100 and the memory core are exposed to approximately the same range of temperatures. Sensor 100 may include resistors 105 and 110 and resistors 115 and 120 (resistors 105 through 120 may together form a resistor circuit such as a resistor ladder). Resistors 105 and 110 may be Nwell resistors or other resistive devices known in the art that have a large positive temperature coefficient (i.e., the resistance of resistors 105 and 110 may change significantly as the temperature of the memory core changes). In contrast, resistors 115 and 120 may be silicide-blocked polysilicon resistors or other resistive devices that have a small temperature coefficient close to zero relative to the temperature coefficient of resistors 105 and 110. In other words, the resistance of resistors 115 and 120 does not change significantly as the temperature of the memory core changes. Because resistors 105 through 120 may be coupled together as shown in FIG. 1 , when the temperature of the memory core increases, the resistance of resistor 105 may increase, thereby resulting in an increase in the reference voltage (Vref) of sensor 100. At the same time, an increase in the temperature of the memory core may cause the resistance of resistor 110 to increase, while the resistance of resistor 120 remains unchanged, thereby resulting in a decrease in the voltage at node 150. With this configuration of resistors with different temperature coefficients, e.g., between resistors 105 to 120, Vref may increase as the temperature of the memory core increases. Note that Vref refers to the reference voltage of sensor 100 and is distinguishable from the 1T1C Vref generated, e.g., by the sense / read or F-RAM 1T1C reference voltage generator 715 shown in FIG. 7.

[0015] The sensor 100 may further include a resistor stack 125 located between or coupled to resistor 110 and resistor 120. The resistor stack 125 may also be an N-well resistor and may include multiple tap points T1 through T8. When current flows through the resistor stack 125 toward ground 160, the voltage at each tap point T1 through T8 (VT1 through VT8) may be lower than the voltage at the tap point above it (e.g., VT2 is lower than VT1). While eight tap points are shown, the resistor stack 125 may include any suitable number of tap points, as described in more detail herein. Each tap point T1 through T8 (also referred to herein as a resistor divider point) is connected to a corresponding comparator 130A through 130H, which may compare the voltage at the corresponding tap point with Vref. As described above, when the temperature of the memory core increases, Vref may increase and the voltage at node 150 may decrease based on the ratio of the resistance values ​​between resistors 105 through 115. As a result, as the temperature of the memory core increases, the V at each tap point T1 through T8 may decrease so that over time, as the V of each successive comparator 130A through 130H decreases below Vref, the output of that comparator transitions (e.g., from "0" to "1" or "low" to "high") at a particular temperature, as shown in Figure 3. In this manner, the outputs of comparators 130A through 130H may define nine different temperature zones, as detailed herein.

[0016] FIG. 2 illustrates the output of each comparator 130 as the temperature of the memory core increases. Because tap point T1 is the first tap point of resistor ladder 125, the voltage at tap point T1 is the highest among all tap points T1 through T8. Therefore, the corresponding input voltage to comparator 130A is the highest among all comparators 130A through 130H. As illustrated, when the temperature of the memory core reaches 9 degrees, VT1 may drop below Vref, and comparator 130A may change its output from one binary state to another, for example, from "0" to "1." Similarly, when the temperature of the memory core reaches 25 degrees, VT2 may drop below Vref, and comparator 130B may change its output from "0" to "1." As the temperature of the memory core continues to increase, the number of comparators 130A through 130H having a "1" output may increase. In this manner, the outputs of multiple comparators 130A through 130H may define multiple temperature zones. For example, if the outputs of comparators 130A and 130B are "1" (while the outputs of the remaining comparators 130 are "0"), this may correspond to a temperature zone of 25 to 39 degrees, while if the outputs of comparators 130A, 130B, 130C, and 130D are "1", this may correspond to a temperature zone of 54 to 67 degrees. Note that the resolution of the temperature zones can be increased by increasing the number of tap points T in resistor ladder 125 and the number of comparators 130A through 130H.

[0017] As described in more detail herein, sensor 100 may be integrated into a 1T1C reference voltage generator (e.g., F-RAM 1T1C reference voltage generator 715) as part of a memory device (e.g., memory device 700 shown in FIG. 7 ), so that the outputs of comparators 130A through 130H may be used as trims to adjust 1T1C Vref (i.e., the reference voltage generated by the 1T1C reference voltage generator) to compensate for effects due to changes in the temperature of the memory core based on the designated temperature zone. As described above, the outputs of sensor 100 (i.e., the outputs of multiple comparators 130) may define multiple temperature zones. In one embodiment, the 1T1C reference voltage generator may adjust the 1T1C reference voltage based on output signals received from multiple comparators 130A through 130H. For example, if the outputs of comparators 130A and 130B are "1" (while the outputs of the remaining comparators 130 are "0"), this may correspond to a temperature zone of 25 to 39 degrees, and the 1T1C reference voltage generator may adjust the 1T1C reference voltage accordingly. If the outputs of comparators 130A, 130B, 130C, and 130D are "1" (while the outputs of the remaining comparators 130 are "0"), this may correspond to a temperature zone of 54 to 67 degrees. Note that the temperature zones described herein are for example purposes only, and that the temperature zones may be defined with any appropriate desired resolution.

[0018] With regard to adjusting the 1T1C Vref, the 1T1C reference voltage generator may achieve this using any suitable means. In one example, the 1T1C reference voltage generator may include a set of capacitor units that control the 1T1C Vref. The output of sensor 100 may control the removal or addition of capacitor units from the 1T1C reference voltage generator to increase or decrease the 1T1C Vref as needed. In other embodiments, the output of sensor 100 may be used to trim or adjust other single-ended sense reference signal strengths for other types of memory technologies, such as flash memory, R-RAM, M-RAM, floating gate memory, etc., to compensate for temperature.

[0019] FIG. 3 illustrates a graph 300 (mV) of P-term (shown as curve 315 with squares) and U-term (shown as curve 320 with circles) versus temperature for an F-RAM memory core. Graph 300 illustrates a temperature-independent (i.e., constant) 1T1C Vref 305 produced with or without an embodiment of the present disclosure, and a temperature-dependent 1T1C Vref 310 produced in accordance with an embodiment of the present disclosure. As illustrated, the P-term 315 of an F-RAM cell within the memory core decreases incrementally as the temperature of the memory core increases. Thus, with the temperature-independent 1T1C Vref 305, as the temperature of the memory core increases, the sensing margin between P-term 315 and 1T1C Vref 305 also decreases incrementally. As a result, the ability to distinguish data "1" decreases as the temperature of the memory core increases. However, 1T1C Vref 310 is temperature dependent and is controlled by the output of sensor 100 (or sensor 400 in some embodiments, as described further herein) and decreases as the temperature of the memory core increases. In this way, the margin between P term 315 and 1T1C Vref 310 is maintained. In the example of Figure 3, when using 1T1C Vref 310, the P term margin at 125°C can be twice the P term margin when using 1T1C Vref 305 at the same temperature.

[0020] While sensor 100 may be utilized to achieve a varying and temperature-dependent 1T1C Vref, the process of trimming resistor ladder 125 to achieve an output with a desired temperature interval can be challenging, particularly in scenarios where each comparator 130 has a different voltage offset and / or the desired resolution is higher (e.g., more comparators 130 are required). Figure 4 illustrates a temperature sensor 400 (hereinafter "sensor 400") for sensing the temperature of a memory core (e.g., F-RAM memory core 705 shown in Figure 7) that addresses the above-mentioned issues with sensor 100 of Figure 1. When integrated into a 1T1C reference voltage generator (e.g., F-RAM 1T1C reference voltage generator 715) as part of a memory device (e.g., memory device 700 shown in Figure 7), the output of sensor 400 may be used by the 1T1C reference voltage generator to provide a temperature-varying 1T1C Vref according to some embodiments of the present disclosure.

[0021] Sensor 400 may include resistors 405 and 410 and resistors 415 and 420. Resistors 405 through 420 may form a resistive circuit 407 (e.g., a resistive ladder). Resistors 405 and 410 may be Nwell resistors or other resistive devices with large positive temperature coefficients (i.e., the resistance values ​​of resistors 405 and 410 may change significantly as the temperature changes). In contrast, resistors 415 and 420 may be silicide-blocked polysilicon resistors or other resistive devices with small temperature coefficients close to zero relative to the temperature coefficients of resistors 405 and 410. In other words, the resistance values ​​of resistors 415 and 420 do not change significantly as the temperature of the memory core changes. Resistors 405 through 420 may be coupled together, similar to resistors 105 through 120 shown in FIG. 1, so that as the temperature of the memory core increases, the resistance of resistor 405 may increase, thereby resulting in an increase in the voltage (VCount) at node 450. Node 450 may represent the division point between resistor 405 and resistor 415. At the same time, an increase in the temperature of the memory core may increase the resistance of resistor 410, while the resistance of resistor 420 remains unchanged, thereby resulting in a decrease in the reference voltage (Vref) of sensor 400. As the temperature increases, the voltage at the bottom of resistor 415 may increase, increasing the resistance of resistor 405. As the temperature of the memory core increases, the voltage at the top of resistor 420 may decrease, increasing the resistance of resistor 410. However, as described in more detail herein, resistor 405 may be a variable resistor that is trimmed or configured to equalize the input voltages to comparator 425 (i.e., Vref and VCount shown in FIG. 4 ) to indicate a state from which the current temperature of the memory core may be determined. Note that Vref refers to the reference voltage of sensor 400 and is distinguishable from, for example, the 1T1C Vref generated by F-RAM 1T1C reference voltage generator 715 shown in FIG. 7 .

[0022] As described above, when the temperature of the memory core increases, Vref may decrease stepwise, while VCount increases stepwise. Therefore, when the temperature of the memory core increases, the resistance of resistor 405 must decrease in order to make Vref and VCount equal. Therefore, sensor 400 may further include a comparator 425 that may receive as an input the output voltage (Vref and VCount) of resistor circuit 407. Sensor 400 may further include an up / down counter logic block 430 (hereinafter referred to as counter 430), which may be coupled to comparator 425 to form a feedback loop and enable control of resistor 405, as described in detail herein. Counter 430 may maintain a count value based on the output of comparator 425 and may output a current value of the count value. More specifically, when the temperature of the memory core increases, Vref may decrease stepwise, while VCount increases stepwise; therefore, when VCount now exceeds Vref, the output of comparator 425 may be “1” (“high”). In response to receiving a 1 input from comparator 425, counter 430 may count up (increment the current count value). If VCount is below Vref, the output of comparator 425 may be "0" ("low"), and counter 430 may count down (decrement the current count value) based on receiving a 0 input. Counter 430 may operate based on a clock signal provided by oscillator 440. The count value of counter 430 may vary, for example, from 100 to 200, and when the count value increases, this may correspond to an increase in the temperature of the memory core. In some embodiments, the count value may have a minimum value of 0 and a maximum value of 2 (for an X-bit up / down counter). X It may have -1.

[0023] Counter 430 may output the current value of the count value (shown in FIGS. 4 and 5 as “Counter Digital Output [7:0]”) as an “x”-bit (8 in the example of FIG. 4 ) digital input word, and use the current value of the count value to control (trim) the resistance of resistor 405 to incrementally equalize VCount and Vref. As the current value increases incrementally, the resistance of resistor 405 may decrease incrementally. For example, every time the current value increases by 10, counter 430 may change one or more bits of the “x”-bit input word to reflect the current temperature (e.g., a current value changing from 6 to 16 may correspond to a digital output word changing from 00110 to 010000). Thus, at 50 degrees, the input word may be 00000, and as the temperature of the memory core increases, one or more bits of the input word may change (e.g., from low to high (“0” to “1”) or from high to low), which may correspond to an increase in temperature. Continuing with the example above, a temperature change from 50 degrees to 60 degrees may result in an input word of 00001. Thus, when the temperature of the memory core increases (causing an increase in VCount and a decrease in Vref), the current value may increase, resulting in the counter digital output gradually decreasing the resistance value of resistor 405. Similarly, if the temperature of the memory core decreases, VCount will fall below Vref and the output of comparator 425 will be 0. This may cause counter 430 to generate a counter digital output that decrements the count value and increases the resistance value of resistor 405 until VCount and Vref are equal. This operation of comparator 425 and counter 430 may continually adjust the value of resistor 405 until Vref and VCount are equal (the input voltages of comparator 425 are equal), causing the output of comparator 425 to alternately shift between "1" and "0." This, in turn, may cause counter 430 to toggle (stabilize) between two count values. For example, when Vref and VCount are equal, the current value of the count value may shift alternately between 99 and 100.Once this state is achieved, the output of counter 430 (99 or 100 in the example above) may indicate the current temperature of the memory core.

[0024] Counter 430 may be coupled to a count converter logic block 435 (hereinafter count converter 435), which receives as an input the counter digital output from counter 430 and may convert the counter digital output to an 'x' bit of trim (shown as therm_sense_trim[11:0] in FIGS. 4 and 5) for use by the 1T1C reference voltage generator in generating the 1T1C Vref. More specifically, count converter 435 may normalize the digital counter output value over process corners and convert the normalized counter output value to a trim for the 1T1C reference voltage generator. These trims may be provided to the 1T1C reference voltage generator over time (e.g., as the temperature of the memory core increases), and the 1T1C reference voltage generator may utilize the trim to provide a temperature-dependent 1T1C Vref based on the temperature profile of the memory core.

[0025] The embodiment described in FIG. 4 provides a temperature sensor that is easier to calibrate because it includes a single comparator and there are no input offset differences to consider. While oscillator 440 is required to output a clock signal to counter 430, temperature sensor 400 may provide higher resolution (e.g., more output bits) compared to sensor 100, which is also advantageous. In addition, the detected temperature is configurable by changing the number of count values ​​between adjacent temperature detections. For example, when the count value is 100 (at 25° C.), therm_sense_trim[0] may be 1, and when the count value is 110 (at 35° C.), therm_sense_trim[1] may be 1. This can be changed so that when the count value is 100 (at 25° C.), therm_sense_trim[0] may be 1, and when the count value is 114 (at 40° C.), therm_sense_trim[1] may be 1.

[0026] FIG. 5 shows a block diagram of a sensor 400 according to some embodiments of the present disclosure. As shown, the sensor 400 may be coupled to a buzzer circuit 445 (hereinafter referred to as “buzzer 445”) that may turn the sensor 400 on and off to manage current consumption. This is possible because the temperature of the memory core does not change instantaneously, but rather at intervals (e.g., 10 degrees / second). Therefore, the buzzer 445 may generate on / off pulses (shown as “Tmpsen_on / off” in FIG. 5 ) that allow the sensor 400 to wake up for a period of time, sense the temperature of the memory core (not shown in FIG. 5 ), and then immediately return to sleep. In this way, the buzzer 445 may optimize the power consumption of the sensor 400. The buzzer 445 may utilize its own ring oscillator 445A, which may operate at a frequency of, for example, 1 to 2 MHz.

[0027] 6A is a graph 600 of the performance of one temperature sensor 400 over time, specifically, the inputs to comparator 425 (Vref and VCount), the counter digital output, and the buzzer 445 on / off pulse (Tmpsen_on / off) versus time. For graph 600, the decimal value of the counter digital output is converted to a voltage and shown as a waveform. As shown, buzzer 445 may provide an “on” signal to sensor 400 for the first 10 microseconds (μs), during which time sensor 400 may determine that the temperature of the memory core is −40° C. (also shown as 145.0 V), represented (in decimal) by the counter digital output as 100.0. 6A also shows how the inputs to comparator 425 (Vref and VCount) differ at the beginning of a 10 μs measurement cycle but match near the end as the operation of comparator 425 and counter 430 continuously adjusts the value of resistor 405 until Vref and VCount are equal, as described in more detail herein. At 10 μs, buzzer 445 may send an “off” signal to sensor 400. Then, at 47 μs, buzzer 445 may again send an “on” signal to sensor 400, and then again at 52 μs, sending an “off” signal to sensor 400. During this second measurement cycle, sensor 400 may determine that the temperature of the memory core is 50° C. (also shown as 192.0 V), represented by the counter digital output as 145.0 (decimal). Again, the Vref and VCount values ​​may differ until later in the measurement cycle when the operation of comparator 425 and counter 430 causes Vref and VCount to be equal.

[0028] 6B is a graph showing counter digital output[7:0] (decimal) from counter 430 and therm_sense_trim[11:0] generated from counter digital output[7:0] by count converter 435 as the temperature of the memory core increases. Figure 6B shows the relationship between counter digital output[7:0] and therm_sense_trim[11:0] as count converter 435 normalizes the counter's digital counter output value over process corners and converts the normalized counter digital output value to a trim for the 1T1C reference voltage generator.

[0029] FIG. 7A illustrates a memory device 700 in which embodiments of the present disclosure may be implemented. The memory device 700 includes an F-RAM memory core 705, a sensor 400, a timing control 710, and a 1T1C reference voltage generator 715. While the sensor 400 is shown here, the sensor 100 illustrated in FIG. 1 may also be used. As illustrated, the output of the sensor 400 (or sensor 100) is provided to the 1T1C reference voltage generator 715, which adjusts the 1T1C reference provided to the F-RAM memory core based on the output of the sensor 400. As described herein, the output of the sensor 400 may be trimmed appropriately for the 1T1C reference voltage generator to generate a temperature-dependent 1T1C Vref (best shown as 1T1C Vref 310 in FIG. 3 ), which is supplied to the F-RAM core 705 for a single, single-ended sensing / read operation. This 1T1C Vref allows memory device 700 to distinguish between P and U terms over the temperature ranges described herein. As shown in FIG. 3 , the 1T1C Vref generated using embodiments of the present disclosure is temperature dependent and has a temperature profile that allows it to distinguish between P or U terms over the temperature range. Because memory device 700 can adjust the 1T1C Vref, it can ensure that the margin of error between P and U terms remains constant throughout the temperature range. Timing control circuit 710 may provide timing and coordination between various components of memory device 700. While shown as an F-RAM memory core 705, the memory core may be a memory device based on any suitable memory technology, such as floating gate, flash, R-RAM, M-RAM, etc. 1T1C reference voltage generator 715 may be a device that provides a temperature-dependent sensed reference signal to the memory device and trims or adjusts the sensed reference signal strength at least in part in response to the output of temperature sensor 400 or 100.

[0030] FIG. 7B shows a block diagram of a semiconductor memory 750 including a memory portion 760. Within the memory portion 760 is a memory array 765 of nonvolatile (NV) memory cells 770 arranged in many rows, each sharing a common word line (WL), and many columns, each sharing a common bit line. In one embodiment, the NV memory cells 770 may be, for example, 1T1C F-RAM cells. In one embodiment, a 1T1C reference voltage generator 775 and the sensor 400 (or the sensor 100 in some embodiments) may also be located within the memory portion 760. The semiconductor memory 750 further includes a processing element 780, such as a microcontroller, microprocessor, or state machine. In one embodiment, the processing element 780 may issue command or control signals, such as WL and RWL signals, to each of the NV memory cells 770 and the reference generation array 775 to perform read, erase, and program operations as described above, and to other peripheral circuitry to read from or write to the memory array 765. The peripheral circuitry includes a row decoder 785 that converts and applies memory addresses to the word lines of the NV memory cells 770 in the memory array 765. When a data word is read from the semiconductor memory 750, the NV memory cells 770 coupled to selected word lines (WL) are read onto bit lines, and the states of those lines are detected by sense amplifiers / drivers 790. A column decoder 795 outputs data from the bit lines to the sense amplifiers / drivers 790. In one embodiment, the row decoder 785 and / or the column decoder 795 converts and applies addresses to the read word lines (RWL) and may control the output of a specific composite temperature-dependent 1T1C reference signal to the sense amplifiers / drivers 790 for the read operation.

[0031] 8 is a flow diagram of a method 800 for applying a temperature-dependent 1T1C reference voltage according to some embodiments of the present disclosure. Method 800 may be performed by processing logic, which may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, processor, processing device, central processing unit (CPU), system-on-chip (SoC), etc.), software (e.g., instructions operating / executing on a processing device), firmware (e.g., microcode), or a combination thereof. For example, method 800 may be performed by sensor 400 of FIGS. 4 and 5.

[0032] 4 and 5, in block 805, when the temperature of the memory core increases, Vref may decrease stepwise, while VCount increases stepwise. Therefore, when the temperature of the memory core increases, the resistance of resistor 405 must decrease in order to make Vref and VCount equal. Therefore, sensor 400 may further include a comparator 425, which may receive the output voltage (Vref and VCount) of resistor circuit 407 as an input in block 810. Sensor 400 may further include an up / down counter logic block 430 (hereinafter referred to as counter 430), which is coupled to comparator 425 and may form a feedback loop to enable control of resistor 405, as described in more detail herein. Counter 430 may maintain a count value based on the output of comparator 425 (which in turn depends on the temperature of the memory core) and may output a current value of the count value in block 815. More specifically, as the temperature of the memory core increases, Vref may decrease incrementally, while VCount may increase incrementally; thus, when VCount now exceeds Vref, the output of comparator 425 may be “1” (“high”). In response to receiving a 1 input from comparator 425, counter 430 may count up (increment the current count value). When VCount falls below Vref, the output of comparator 425 may be “0” (“low”), and counter 430 may count down (decrement the current count value) based on receiving a 0 input. Counter 430 may operate based on a clock signal provided by oscillator 440. The count value of counter 430 may vary, for example, from 50 to 150, and when the count value increases, this may correspond to an increase in the temperature of the memory core. In some embodiments, the count value may have a minimum value of 0 and a maximum value of 2 (for an X-bit up / down counter). X It may have -1.

[0033] In block 820, counter 430 may output the current value of the count value (shown in FIGS. 4 and 5 as “Counter Digital Output [7:0]”) as an “x”-bit (8 in the example of FIG. 4 ) digital input word, and use the current value of the count value to control (trim) the resistance value of resistor 405 to incrementally equalize VCount and Vref. As the current value increases incrementally, the resistance value of resistor 405 may decrease incrementally. For example, each time the current value increases by 10, counter 430 may change one or more bits of the “x”-bit input word to reflect the current temperature (e.g., a current value changing from 6 to 16 may correspond to a digital output word changing from 00110 to 010000). Thus, at 50 degrees, the input word may be 00000, and as the temperature of the memory core increases, one or more bits of the input word may change (e.g., from low to high (“0” to “1”) or from high to low), which may correspond to an increase in temperature. Continuing with the example above, a temperature change from 50 degrees to 60 degrees may result in an input word of 00001. Thus, when the temperature of the memory core increases (causing an increase in VCount and a decrease in Vref), the current value may increase, resulting in the counter digital output gradually decreasing the resistance value of resistor 405. Similarly, if the temperature of the memory core decreases, VCount will fall below Vref and the output of comparator 425 will be 0. This may cause counter 430 to generate a counter digital output that decrements the count value and increases the resistance value of resistor 405 until VCount and Vref are equal. This operation of comparator 425 and counter 430 may continually adjust the value of resistor 405 until Vref and VCount are equal (the input voltages of comparator 425 are equal), causing the output of comparator 425 to alternately shift between "1" and "0." This, in turn, may cause counter 430 to toggle (stabilize) between two count values. For example, when Vref and VCount are equal, the current value of the count value may shift alternately between 99 and 100.Once this state is achieved, the output of counter 430 (99 or 100 in the example above) may indicate the current temperature of the memory core.

[0034] The counter 430 may be coupled to a count converter logic block 435 (hereinafter, count converter 435), which may receive as an input the counter digital output from the counter 430 and convert the counter digital output into “x” bits of trim (shown as therm_sense_trim[11:0] in FIGS. 4 and 5 ) for use by the 1T1C reference voltage generator in generating the 1T1C Vref. More specifically, in block 825, the count converter 435 may normalize the digital counter output value over process corners and convert the normalized counter output value into a trim for the 1T1C reference voltage generator. These trims may be provided to the 1T1C reference voltage generator over time (e.g., as the temperature of the memory core increases), and the 1T1C reference voltage generator may utilize the trim in block 830 to provide a temperature-dependent 1T1C Vref based on the temperature profile of the memory core.

[0035] The embodiments described herein may be used in various designs of mutual capacitance sensing systems, self-capacitance sensing systems, or a combination of both. The embodiments described herein are not related to a particular capacitive sensing solution, and may be used with other sensing solutions as well, including optical sensing solutions, as will be appreciated by those skilled in the art having the benefit of this disclosure.

[0036] In the foregoing description, numerous details are set forth. However, it will be apparent to one skilled in the art having the benefit of this disclosure that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the description.

[0037] Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. These quantities, although not necessarily, usually take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0038] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise indicated, and as is apparent from the above description, it should be recognized that throughout the description, discussions utilizing terms such as "determining," "detecting," "comparing," "resetting," "adding," "calculating," and the like refer to the actions and processes of a computing system or similar electronic computing device that manipulate and convert data represented as physical (e.g., electronic) quantities in the computing system's registers and memory into other data that are similarly represented as physical quantities in the computing system's memory or registers or other such information storage, transmission, or display devices.

[0039] As used herein, the term "example" or "exemplary" is used to mean serving as an example, illustration, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the term "example" or "exemplary" is intended to present the concept in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, in any of the above examples, "X includes A or B" is satisfied if X includes A, if X includes B, or if X includes both A and B. Additionally, as used in this application and the appended claims, the singular indefinite article "a," "an," or "an" should generally be construed to mean "one or more" unless otherwise stated or clear from context. Furthermore, use of the terms "embodiment" or "one embodiment" or "implementation" or "one implementation" throughout is not intended to refer to the same embodiment or implementation unless so stated.

[0040] The embodiments described herein may also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored therein. Such a computer program may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be considered to include any medium that can store, encode, or transmit a set of instructions for execution by a machine, causing the machine to perform any one or more of the methods of the present embodiments. Accordingly, the term "computer-readable storage medium" is intended to include, but is not limited to, solid-state memory, optical media, magnetic media, and any medium capable of storing a set of instructions for execution by a machine, causing the machine to perform any one or more of the methods of the present embodiments.

[0041] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the embodiments described herein.

[0042] The foregoing description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to provide a good understanding of some embodiments of the present disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known components or methods have not been described in detail or have been presented in simple block diagram form to avoid unnecessarily obscuring the embodiments. Thus, the specific details set forth above are merely illustrative. Particular implementations may vary from these example details and still be considered within the scope of the embodiments.

[0043] It is to be understood that the foregoing description is intended to be illustrative, and not limiting. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the foregoing description. The scope of the embodiments should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. a resistor circuit comprising a set of resistors configured to control a reference voltage based on a temperature of the memory; a comparator configured to output a count-up signal and a count-down signal; A counter and An apparatus comprising: each resistor of the set of resistors having a first or second temperature coefficient, and a first resistor of the set of resistors modifies its resistance value based on the temperature of the memory until the reference voltage and the output voltage are equal; The counter incrementing and decrementing a current count value based on the count-up signal and the count-down signal output by the comparator; periodically outputting a word corresponding to the current count value; It is configured as follows: the word indicates the temperature of the memory in the first resistance; Device.

2. To output the count up and count down signals, the comparator comparing the reference voltage with the output voltage; If the output voltage is lower than the reference voltage, a count-up signal is output to the counter; If the output voltage is higher than the reference voltage, a countdown signal is output to the counter.

10. The apparatus of claim 1.

3. toggling the current count value between two different values ​​indicates that the reference voltage and the output voltage are equal; the word output after toggling the current count value indicates the current temperature of the memory; 3. The apparatus of claim 2.

4. The apparatus further comprises a count converter, the count converter comprising: converting the word output after toggling the current count value into a trim value; outputting the trim value to a reference signal generator of a memory device including the memory; It is configured as follows:

4. The apparatus of claim 3.

5. the reference signal generator is a one-transistor, one-capacitor (1T1C) reference signal generator; 5. The apparatus of claim 4.

6. the memory is a ferroelectric random access memory (F-RAM); 10. The apparatus of claim 1.

7. The resistor set includes: one or more resistors having the first temperature coefficient that is positive; one or more resistors having the second temperature coefficient; Equipped with the second temperature coefficient does not cause a change in resistance based on the temperature of the memory relative to the first temperature coefficient.

10. The apparatus of claim 1.

8. Memory and a reference signal generator configured to generate a reference signal based on a current temperature of the memory; A temperature sensor; A system comprising: The temperature sensor a resistor circuit comprising a set of resistors configured to control a reference voltage based on a temperature of the memory; a comparator configured to output a count-up signal and a count-down signal; A counter and Equipped with each resistor of the set of resistors having a first or second temperature coefficient, and a first resistor of the set of resistors modifies its resistance value based on the temperature of the memory until the reference voltage and the output voltage are equal; The counter incrementing and decrementing a current count value based on the count-up signal and the count-down signal output by the comparator; periodically outputting a word corresponding to the current count value; It is configured as follows: the word indicates the temperature of the memory in the first resistance; system.

9. To output the count up and count down signals, the comparator comparing the reference voltage with the output voltage; If the output voltage is lower than the reference voltage, a count-up signal is output to the counter; If the output voltage is higher than the reference voltage, a countdown signal is output to the counter. It is configured as follows: The system of claim 8.

10. toggling the current count value between two different values ​​indicates that the reference voltage and the output voltage are equal; the word output after toggling the current count value indicates the current temperature of the memory; The system of claim 9.

11. The temperature sensor further comprises a count converter, the count converter comprising: converting the word output after toggling the current count value into a trim value; outputting the trim value to the reference signal generator; It is configured as follows: The system of claim 10.

12. the reference signal is a one transistor one capacitor (1T1C) reference signal; The system of claim 11.

13. the system further comprising a buzzer circuit configured to operate the temperature sensor at periodic intervals and to maintain the temperature sensor in a low power state outside of the periodic intervals. The system of claim 8.

14. a resistor circuit comprising a set of resistors configured to control a reference voltage based on a temperature of the memory; a resistor stack coupled to the resistor circuit; a plurality of comparators; An apparatus comprising: each resistor of the set of resistors having a first or second temperature coefficient, the resistor stack comprising a plurality of tap points, the output voltage at each of the plurality of tap points being successively lower than the output voltage at the previous tap point; Each comparator of the plurality of comparators is coupled to a corresponding one of the plurality of tap points, and each of the plurality of comparators comprises: comparing the output voltage at the corresponding tap point to the reference voltage; outputting a high signal when the output voltage at the corresponding tap point is greater than the reference voltage; It is configured as follows: Device.

15. When the temperature increases based on a ratio of resistance values ​​between the resistor sets, the reference voltage decreases, so that when the temperature of the memory increases, each successive comparator of the plurality of comparators outputs a respective high signal.

15. The apparatus of claim 14.

16. each of the plurality of comparators outputs the respective high signal to a reference signal generator of a memory device including the memory; 16. The apparatus of claim 15.

17. Each successive high signal defines a temperature zone, such that multiple temperature zones are defined.

16. The apparatus of claim 15.

18. The resistor set includes: one or more resistors having the first temperature coefficient that is positive; one or more resistors having the second temperature coefficient; Equipped with the second temperature coefficient does not cause a change in resistance based on the temperature of the memory relative to the first temperature coefficient.

15. The apparatus of claim 14.

19. the memory is a ferroelectric random access memory (F-RAM); 15. The apparatus of claim 14.

20. the reference signal generator is a one-transistor, one-capacitor (1T1C) reference signal generator; 17. The apparatus of claim 16.

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