Semiconductor Devices

Abstract

To provide a highly reliable semiconductor display device consuming less power.SOLUTION: A decoder is provided for a scan line driving circuit. In accordance with the signals input to the scan line driving circuit, pulses are sequentially input only to the scan lines of the pixels that perform display but not input to the scan lines of the pixels that do not perform display. By supplying video signals from a signal line driving circuit to all the pixels in the line selected by the pulses or some pixels of the selected line, just the pixels disposed in the particular area in the pixel portion perform display.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an active matrix semiconductor display device using thin film transistors and Regarding the driving method. [Background technology]

[0002] Thin film transistors using semiconductor films formed on insulating surfaces are called active matrix transistors. It is an essential semiconductor element for a driver circuit or a pixel portion of the semiconductor display device. Since the manufacturing of thin film transistors is limited by the heat resistance temperature of the substrate, it is necessary to manufacture thin film transistors at a relatively low temperature. Amorphous silicon can be formed into a film, and can be obtained by crystallization using laser light or catalytic elements. Thin film transistors having polysilicon or the like in their active layers are used in semiconductor display devices. It has become the mainstream transistor.

[0003] In recent years, the high mobility achieved by polysilicon and the high mobility achieved by amorphous silicon have been As a new semiconductor material that combines these properties with uniform device characteristics, oxide semiconductors have been developed. Metal oxides that exhibit semiconducting properties are attracting attention. For example, indium oxide, a well-known metal oxide, is used in liquid crystal displays and other devices. Metal oxides that exhibit semiconducting properties include, for example, , tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides exhibiting these characteristics in the channel formation region are already known. (Patent Documents 1 to 4, Non-Patent Document 1).

[0004] Metal oxides are not only mono-component oxides but also multi-component oxides. For example, homologous InGaO3(ZnO) with phase m (m: natural number) is a polycrystalline silicon containing In, Ga, and Zn. It is known as a metal oxide semiconductor (Non-Patent Documents 2 to 4). Oxide semiconductors made of n-Ga-Zn oxides are used in the channel layer of thin-film transistors. It has been confirmed that this is applicable (Patent Document 5, Non-Patent Documents 5 and 6). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-150900 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-103957 [Non-patent literature]

[0006] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3652 [Non-patent document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-licensed Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System", J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-licensed Document 4] Masaki Nakamura, Noboru Kimizuka, Naohiko Mori, Mitsumasa Isobe, "The crystal structure of the ホモロガス phase, InFeO3(ZnO)m(m: natural number) and the same type of compound", Solid State Physics, 1993, Vol.28, No.5, p.317-327 [Non-licensed Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-licensed Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 Summary of the Invention [Problem to be solved by the invention]

[0007] By the way, active matrix semiconductor display devices can display higher definition and higher resolution images. Therefore, the number of pixels tends to increase. The circuit requires high-speed driving, and the high driving frequency leads to high power consumption. Furthermore, semiconductor display devices are being developed to withstand continuous use over long periods of time. High reliability is also required. For example, when fixing an image displayed on a semiconductor display device, In this case, deterioration of the semiconductor element or display element progresses in a specific pixel, resulting in a phenomenon known as burn-in. Burn-in is a phenomenon that is seen in all semiconductor display devices, but it is also seen in LCDs and organic light-emitting displays. Light-emitting devices using semiconductor elements, surface conduction electron emission device displays (SEDs), etc. This is particularly likely to occur in display devices.

[0008] To achieve the high reliability and low power consumption required for these semiconductor display devices, In addition to improving the characteristics of semiconductor elements or display elements, we have also devised innovative driving methods. When a semiconductor display device is used continuously for a long period of time, the semiconductor element or is a driving method to prevent deterioration of the display element and also to prevent power consumption from increasing. Partial drive is an example of this. Partial drive is a method in which the image displayed on the screen is When there is no change for a certain period of time, the image is displayed only in a limited area of ​​the pixel section, and This is a driving method in which image display is stopped in the other areas.

[0009] However, even when partial drive is used, the drive circuit continues to operate and consumes It could not be said that the power consumption was significantly reduced compared to normal operation.

[0010] In view of the above-described problems, it is an object of the present invention to provide a semiconductor display device having high reliability. An object of the present invention is to provide a semiconductor display device that can reduce power consumption.

[0011] Another object is to provide a method for driving a semiconductor display device that can improve reliability. Alternatively, one of the objects is to provide a method for driving a semiconductor display device that can reduce power consumption. do. [Means for solving the problem]

[0012] In order to solve the above problem, a scanning line driving circuit is provided which sequentially selects only the pixels of the line to be displayed. Specifically, a decoder is provided in the scanning line driving circuit, and the scanning lines In accordance with the signal input to the driving circuit, only the scanning lines of the pixels of the line to be displayed are sequentially A pulse is input to the scanning lines of the pixels of the lines that do not perform display, and no pulse is input to the scanning lines of the pixels of the lines that do not perform display. Then, all the pixels in the line selected by the pulse are or by supplying a video signal from a signal line driver circuit to some pixels of a selected line. An image is displayed only in pixels arranged in a specific area of ​​the pixel section.

[0013] Note that displaying an image in the entire pixel area and displaying an image in a partial area of ​​the pixel area are different. It can be controlled by the signal input to the imager. When displaying, a specific pixel among a plurality of pixels included in the pixel unit is selected by a signal input to the decoder. It is sufficient to input pulses in sequence only to the scanning lines of the pixels in the line. When an image is displayed, the signals input to the decoder are used to select the scanning lines of the pixels on all lines. All you have to do is input pulses in sequence.

[0014] The pixels are small pixels whose switching is controlled in accordance with the pulses of the signals input to the scanning lines. At least one thin film transistor, and when the thin film transistor is turned on, a signal line driving circuit and a display element whose operation is controlled in accordance with a video signal provided from The thin film transistor uses an oxide semiconductor for a channel formation region. A semiconductor device using an oxide semiconductor in a part or all of a driving circuit and a signal line driver circuit Conductor elements, such as thin film transistors, in which an oxide semiconductor is used in the channel formation region , may be provided.

[0015] The oxide semiconductor is an In-Sn-Ga-Zn-O-based oxide semiconductor, which is a quaternary metal oxide. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, In-O based oxide semiconductors, Sn-O based oxide semiconductors, Zn-O based oxide semiconductors, etc. In this specification, for example, an In—Sn—Ga—Zn—O system Oxide semiconductors are made of indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The stoichiometric composition ratio is not particularly important. The oxide semiconductor may contain silicon.

[0016] Alternatively, the oxide semiconductor may have the chemical formula InMO3(ZnO) m (m>0) Here, M is one or more metal elements selected from Ga, Al, Mn, and Co. Shows.

[0017] Note that after the oxide semiconductor film is formed, it is heated under a reduced pressure atmosphere or an inert gas atmosphere. By performing heat treatment, moisture and hydroxy groups adsorbed on the surface or inside of the oxide semiconductor film are removed. The temperature range of the heat treatment is 400°C or more and 700°C or less, preferably The heat treatment is preferably performed at a temperature higher than or equal to 450° C. and lower than or equal to 650° C. , water present in the gate insulating film, or at the interface between the oxide semiconductor film and other insulating films and in the vicinity thereof impurities such as amines, hydroxy groups, or hydrogen atoms are removed. This can prevent deterioration of the resistor characteristics.

[0018] The thin film transistor may be a bottom gate type or a top gate type. The bottom-gate type transistor may be a bottom-contact type. a gate electrode on the surface, a gate insulating film on the gate electrode, and a gate electrode on the gate insulating film. an oxide semiconductor film overlapping the electrode, a source electrode and a drain electrode on the oxide semiconductor film, and an oxide The oxide insulating film on the semiconductor film, the source electrode, and the drain electrode, and the oxide insulating film on the oxide insulating film A top-gate transistor has an oxide semiconductor film and a conductive film overlapping the oxide semiconductor film. a gate insulating film which is an oxide insulating film on the oxide semiconductor film; a gate electrode that overlaps with the oxide semiconductor film and functions as a conductive film; A bottom-contact transistor has a gate electrode on an insulating surface and a gate electrode on the gate electrode. a gate insulating film, a source electrode and a drain electrode on the gate insulating film, and a source electrode and a drain electrode on the gate insulating film. an oxide semiconductor film that is on the top and overlaps with the gate electrode on the gate insulating film; an oxide insulating film on the oxide semiconductor film, and a conductive film on the oxide insulating film that overlaps with the oxide semiconductor film The membrane. [Effects of the Invention]

[0019] The scanning line driver circuit is operated so that pulses are input only to the pixels on the specified line. , it is possible to prevent power consumption in scan lines other than the designated line, and The power consumption of a semiconductor display device using a semiconductor can be reduced. By operating the scanning line driver circuit so that pulses are input only to the in-pixels, and a semiconductor element or a display element using an oxide semiconductor, which prevents the display device from being used continuously for a long period of time. can be prevented from deteriorating. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are a block diagram of a semiconductor display device and a diagram showing a configuration of a pixel portion. [Figure 2] 3 is a timing chart of a pixel section. [Figure 3] 3 is a timing chart of a pixel section. [Figure 4] FIG. 2 is a diagram showing the arrangement of areas in a pixel portion where an image is displayed. [Figure 5] FIG. 2 is a diagram showing the configuration of a decoder. [Figure 6] 1A and 1B are a cross-sectional view and a top view of a transistor. [Figure 7] 1A and 1B are a cross-sectional view and a top view of a transistor. [Figure 8] 1A and 1B are a cross-sectional view and a top view of a transistor. [Figure 9] FIG. 1 is a circuit diagram showing the configuration of a NOR circuit. [Figure 10] FIG. 1 is a circuit diagram showing the configuration of a NOR circuit. [Figure 11] FIG. 1 is a block diagram of a semiconductor display device. [Figure 12] Circuit diagram of the pixel section. [Figure 13] Circuit diagram of the pixel section. [Figure 14] 1A and 1B are a top view and a cross-sectional view of an electronic paper. [Figure 15] FIG. 10 is a diagram showing an example of an image displayed in a partial area. [Figure 16] FIG. 10 is a schematic diagram showing the order of an initialization period, a writing period, and a retention period. [Figure 17] 4 is a timing chart showing voltages applied to pixel electrodes and voltages of selection signals input to each scanning line. [Figure 18] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 19] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 20] 4 is a timing chart illustrating the configuration of a pulse output circuit and the operation of a shift register. [Figure 21]1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 22] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 23] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 24] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 25] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 26] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 27] FIG. [Figure 28] FIG. [Figure 29] FIG. 1 is a diagram showing a configuration of a module of a liquid crystal display device. [Figure 30] 10A to 10C are diagrams illustrating electronic devices using semiconductor display devices. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0022] The semiconductor display device of the present invention includes a liquid crystal display device and an organic light emitting diode (OLED). Light-emitting devices with light-emitting elements in each pixel, electronic paper, DMD (Digital Microphone) romirror device), PDP (Plasma Display Pane) l), SED (Surface-conduction Electron-emitt) FED (Field Emission Display) ) and other semiconductor display devices having circuit elements using semiconductor films in their driving circuits, It falls into that category.

[0023] (Embodiment 1) FIG. 1A illustrates an example of a block diagram of a semiconductor display device according to one embodiment of the present invention.

[0024] The semiconductor display device shown in FIG. 1A has a plurality of pixels each including a display element and a thin film transistor. a pixel section 100 having a scanning line driver circuit 101 for selecting each pixel for each line; and a signal line driver circuit 102 for controlling the input of video signals to the pixels of the selected line. As shown in FIG. 1B, the pixel section 100 is provided with a scanning line driver circuit 101. a plurality of scanning lines G1 to Gy extending from the signal line driving circuit 102; Each pixel 105 has a small number of scanning lines S1 to Sx. At least one signal line is provided, and at least one of a plurality of signal lines is provided, and the signal is input to the scanning line. The display element and thin film transistor of each pixel 105 are driven by the signal and the signal input to the signal line. The operation of the controller is controlled.

[0025] The scanning line driving circuit 101 has a decoder 103. The operation is controlled by n-bit control signals D1 to Dn. Depending on the combination of the bit values ​​of the signals D1 to Dn, the decoder 103 outputs the scan line G1 Selection signals having pulses can be input to the control signals D1 to Gy in sequence. The combination of the values ​​of each bit of Dn determines the scan line of the pixel of the line to be displayed. The pulse is input in order only to the scanning lines of the pixels of the lines that do not perform display. The scanning line driving circuit 101 can be operated so as not to input pulses.

[0026] For example, in the pixel section 100 shown in FIG. 1B, only the area 104 displays an image. In this case, the scanning lines G1 to Gt-1 of the pixels in the area 104 are Pulses are input in the order of the scanning lines Gt to Gt of the pixels of the lines that do not perform display. The combination of the values ​​of each bit of the control signals D1 to Dn is used so that no pulse is input to y. The scanning line driving circuit 101 is operated by this.

[0027] The signal line driver circuit 102 receives a video signal and a signal for controlling the driving of the signal line driver circuit 102. A driving signal is input to drive all pixels in the line selected by the pulse, or the selected A video signal is supplied from the signal line driver circuit 102 to some pixels of the line. , the image is displayed only in the pixels arranged in a specific area 104 of the pixel unit 100. Specifically, in FIG. 1B, the signal line S1 is connected to the signal line driver circuit 102. ~A video signal that has image information only in Sq-1 (q is a natural number greater than 2 and less than x) and video signals that do not contribute to the display of images are input to the signal lines Sq to Sx. , an image is displayed only in the pixels arranged in area 104.

[0028] The video signal that does not contribute to the display of an image is a current or voltage to a display element of a pixel. A video signal that does not contribute to the display of an image is input to a pixel. If a current or voltage is interrupted from being applied to the display element in the pixel, or if a series of The gray scale displayed by the display element is maintained over the frame period. No image will be displayed.

[0029] Also, a video signal having image information is sent from the signal line driver circuit 102 to the selected line Specifically, when the video signal is input to only a part of the pixels in a specific area 104 The signal is supplied only to the signal lines S1 to Sq-1 of the pixels in the frame frequency. If so, a video signal having image information for all pixels of the selected line is input. In this case, a video signal having image information in some pixels of a selected line is input. In this case, the driving frequency of the signal line driving circuit 102 can be kept low, and therefore, the power consumption can be reduced. It can reduce power consumption.

[0030] In FIG. 1B, a part of the area 104 where an image is displayed is connected to the signal lines S1 to Sq-1. and a pixel group having scanning lines G1 to Gt-1, and located at the upper left of the pixel section 100. However, the present invention is not limited to this configuration. For example, as shown in FIG. As shown in FIG. 1, a part of the area 104 for displaying an image may be located at the upper right of the pixel section 100. Alternatively, it may be located in the center of the pixel section 100 as shown in FIG. 4(B), or in the center of the pixel section 100 as shown in FIG. 4(C). As shown in the figure, the pixel area 100 may be located at the bottom left of the pixel area 100. The position and range of the line 104 are determined by the scanning line driving circuit 101. The signal line driver circuit 102 inputs a video signal having image information to the signal line. So you can decide accordingly.

[0031] Next, an example of a specific configuration of the decoder 103 is shown in the circuit diagram of FIG. The data is stored in a plurality of NOR circuits 106-1 to 106-2. nEach NOR circuit has n bits. The number of NOR circuits shown in FIG. 5 is merely an example. , not necessarily 2 n The number of NOR circuits is not limited by the number of bits of the control signal. .

[0032] The n-bit control signal is the control signals D1 to Dn, or the polarity of the control signals D1 to Dn is inverted. The control signals Db1 to Dbn are selected from the control signals Db1 to Dbn obtained by 106-2 n The control signals input to the NOR circuits 106- The NOR circuit 106-1 receives control signals D1 to Dn. The NOR circuit 106-2 receives control signals D2 to Dn. The NOR circuit 106-3 receives the control signals D1, D3, and Dn, and the control signal Db1. In this way, the NOR circuits 106-1 to 106-Dn and the control signal Db2 are input. -2 n The control signals input to the NOR circuits 106-1 to 106-6 are different from each other. -2 n Only the signal output from one of the Specifically, the NOR circuits 106-1 to 106-2 n Either The signal output from only one of the two is at a high level (Hi) and the others are at a low level (L o) can be used as the voltage of the control signals D1 to Dn and the control signals Db1 to Dbn. By changing the value of at predetermined intervals, the NOR circuits 106-1 to 106-2 n From high It is possible to output a signal in which the voltage pulses of different levels are shifted.

[0033] NOR circuits 106-1 to 106-2 nThe signal output from the scan line G1 is used as a selection signal. A voltage corresponding to a selection signal pulse is input to the scanning lines G1 to Gy. The scanning line being displayed corresponds to the so-called selected scanning line.

[0034] The control signals Db1 to Dbn are generated by an inverter or the like inside the scanning line driving circuit 101. The polarity of the control signals D1 to Dn may be inverted, or the polarity may be generated by the scanning line driving circuit. The scanning line driving circuit 101 receives control signals D1 to Dn from an external device such as a controller. It may be input to the path 101.

[0035] When an image is to be displayed in all of the pixel sections 100, selection signals are sequentially applied to the scanning lines G1 to Gy. The values ​​of the control signals D1 to Dn and the control signals Db1 to Dbn are determined so that the pulses When an image is displayed only in the area 104, the scanning lines G1 to Gt-1 are selected in order. The control signal is set so that a pulse is input to the selection signal and no pulse is input to the scanning lines Gt to Gy. The values ​​of the signals D1 to Dn and the control signals Db1 to Dbn are determined.

[0036] The decoder shown in FIG. 5 receives an n-bit control signal and outputs at least one of the following: A selection signal with a pulse is output from one NOR circuit. If it is necessary to input a selection signal that does not have Or, for an n-bit control signal, the total number of NOR circuits is 2 n -a, and the total number of NOR circuits is 2 n - a is equal to or greater than the total number of scan lines y Or, in addition to the n-bit control signal, a high level (Hi) voltage is applied to all NO The output from all NOR circuits is forced to a low level. It may be set to a voltage of (Lo).

[0037] FIG. 2 shows the inputs to the scanning lines G1 to Gy when an image is displayed in all of the pixel units 100. 10 shows a timing chart of the selection signals input to the signal lines S1 to Sx and the video signals input to the signal lines S1 to Sx. As shown in FIG. 2, when an image is displayed in the entire pixel section 100, one frame During this period, a selection signal in which voltage pulses are shifted in order is input to the scanning lines G1 to Gy. Therefore, the pixels of all the lines become display lines for display. During one line period when a pulse appears in the selection signal input to the line, A video signal having image information is input to 1 to Sx.

[0038] 3 shows a case where an image is displayed only in a partial area 104 of the pixel section 100. , selection signals input to the scanning lines G1 to Gy, and video signals input to the signal lines S1 to Sx. As shown in FIG. 3, the image is displayed only in the area 104. When this is done, voltage pulses are sequentially applied to the scanning lines G1 to Gt-1 during one frame period. The selection signal is inputted, and the scanning lines Gt to Gy have no pulses, that is, A selection signal having a voltage of a flat height is input. The pixels of the line having the scanning lines Gt to Gy are the display lines for displaying. The pixel becomes a non-display line that does not display anything. During the line period, a video signal is input to the signal lines S1 to Sx, and the scanning line G1 A video signal is input only to the pixels of the display line having area 1. The video signals input to the signal lines S1 to Sq-1 of the pixels 04 have image information. The video signals input to the lines Sq to Sx do not contribute to the display of images. An image can be displayed only in the pixels in area 104 by the driving method.

[0039] After the scanning up to the scanning line Gt-1 is completed, the video signal input to the signal lines S1 to Sq-1 is The video signal is set to a constant voltage that does not contribute to the display of an image, or no video signal is input. The signal lines S1 to Sq-1 can also be set in a floating state. After scanning up to 1 is completed, the charge and discharge of the signal lines S1 to Sq-1 is stopped, so the signal line drive This allows for a reduction in the power consumption of the operating circuit.

[0040] The signal line driving circuit 10 is configured to input video signals only to the signal lines S1 to Sq-1. In this case, the image is displayed more efficiently than when the entire pixel unit 100 is used to display an image. Furthermore, the driving frequency of the signal line driving circuit 102 can be lowered, thereby reducing power consumption.

[0041] In addition, in FIG. 2 and FIG. 3, the video signals input to the signal lines S1 to Sx are displayed as pulses. However, there may be cases where no pulse appears depending on the image information contained in the video signal.

[0042] 2 and 3, the signal line driver circuit 102 sequentially inputs video signals to each signal line. The timing chart shows an example of a dot sequential drive. However, the present invention is not limited to this configuration. The signal line driver circuit 102 inputs video signals to all the signal lines in parallel. It may also be the next drive.

[0043] In addition, when an image is displayed only in a part of the area 104, the image is displayed in the entire pixel section 100. The frame frequency is deliberately set lower than when the scanning line driving circuit 101 performs the above operation. Therefore, by reducing the number of scans in which the scan lines are selected in order, the power consumption of the scan line driving circuit can be reduced. It is also possible to lower the value.

[0044] In addition, in the case of time gray scale driving, the number of scans is reduced by lowering the frame frequency. Alternatively, the number of scans can be reduced by lowering the number of gradations, and the number of scan lines can be reduced. The power consumption of the driving circuit may be reduced. This is a driving method for displaying gray scales by controlling the time during which the pixel displays white.

[0045] A semiconductor display device according to one aspect of the present invention is configured to input a pulse only to pixels on a specified line. Therefore, power is not supplied to the scan lines other than the designated line. This can prevent the power consumption of the semiconductor display device from increasing, thereby reducing the power consumption of the semiconductor display device. Also, the scanning line driving circuit is operated so that pulses are input only to the pixels on the specified line. By doing so, in the pixel section 100, in the region other than the part of the area 104, Prevents continuous use and deterioration of semiconductor elements such as thin-film transistors or display elements It is possible.

[0046] The semiconductor display device shown in FIG. 1A includes a pixel portion 100, a scanning line driver circuit 101, or a The signal line driver circuit 102 may be formed on one substrate in a system-on-panel configuration. By using a muon panel, the driving circuits such as the scanning line driving circuit 101 and the signal line driving circuit 102 can be easily The number of pins for connecting the driving circuit and the pixel section 100 is reduced, and the connection between the driving circuit and the pixel section is reduced. The problem of poor mechanical strength at the connection points using pins, etc. Furthermore, it is possible to not only reduce the size of the display device but also to shorten the assembly and inspection processes. The realization of a system-on-panel also makes it possible to reduce costs through reductions. For panels, connections such as FPC (Flexible Printed Circuit) Various signals such as control signals, video signals, and drive signals are transmitted from the controller via this section. A source voltage is supplied to the pixel section 100, the scanning line driving circuit 101 or the signal line driving circuit 102. can be.

[0047] The semiconductor display device of the present invention is not limited to a system-on-panel. For example, the output section of the scanning line driving circuit 101 or the signal line driving circuit 102 is used. The analog switches and other components are formed on the same substrate together with the pixel section 100, and the remaining drive frequency A relatively high number of circuits may be formed on a separate substrate. The pixel portion 100 and the driving frequency are formed by semiconductor elements using single crystal semiconductors. A low-temperature circuit can be formed using a semiconductor element using an oxide semiconductor. By partially adopting a system on panel, the yield decrease caused by the above-mentioned connection failure can be reduced. , to avoid low mechanical strength at the connection points using pins, or The benefits of a system on panel, such as cost reduction due to the elimination of inspection processes, Furthermore, the pixel section 100, the scanning line driving circuit 101, and the signal line driving circuit 102 Compared to a system-on-panel where all the components are formed on a single substrate, the performance of the circuitry with a high drive frequency is improved. This is difficult to achieve when using single-crystal semiconductors. A pixel portion with a large area can be formed.

[0048] (Embodiment 2) In this embodiment, an oxide semiconductor film used for a pixel or a driver circuit of a semiconductor display device is Regarding the structure of a thin film transistor having a channel forming region, We will explain this using the TomGate type as an example.

[0049] FIG. 6(A) is a cross-sectional view of the thin film transistor 201, and FIG. 6(B) is a cross-sectional view of the thin film transistor shown in FIG. 6(A). 6B. The broken line A1-A2 in FIG. 6B shows a top view of the transistor 201. The cross-sectional view in this case corresponds to FIG. 6(A).

[0050] The thin film transistor 201 includes a gate electrode 203 formed on a substrate 202 and a gate electrode A gate insulating film 204 is formed on the gate electrode 203, and a gate electrode 204 is formed on the gate insulating film 204 at a position where the gate electrode 203 overlaps the gate electrode 203. The island-shaped oxide semiconductor film 205 formed on the gate insulating film 204 and the island-shaped oxide semiconductor film The source electrode 206 and the drain electrode 207 are formed on the oxide semiconductor film 205. 5, an oxide insulating film 208 formed on the source electrode 206 and the drain electrode 207; is doing.

[0051] An insulating film serving as a base film may be provided between the gate electrode 203 and the substrate 202 . The base film is an insulating film that prevents the diffusion of impurity elements from the substrate 202, specifically, silicon nitride. A single layer of a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film is used. The gate electrode 203 can be made of a material such as molybdenum. Metallic materials such as buten, titanium, chromium, tantalum, tungsten, neodymium, and scandium Conductive films using alloy materials whose main components are these metal materials, or nitrides of these metals The film can be used in a single layer or a laminated layer. If it can withstand the temperature, aluminum and copper can also be used as the metal material. .

[0052] For example, the two-layered structure of the gate electrode 203 is a titanium nitride film and a molybdenum film. It is preferable to use a two-layer structure in which a tungsten film is laminated. The film is a tungsten nitride film and an alloy film of aluminum and silicon or an alloy film of aluminum and titanium. It is preferable to use a three-layer structure in which a gold film and a titanium nitride film or a titanium film are laminated.

[0053] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It refers to a substance.

[0054] The thickness of the gate electrode 203 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm film is formed by sputtering using a tungsten target. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. By patterning, the gate electrode 203 is formed.

[0055] The gate insulating film 204 is a silicon oxide film formed by using a plasma CVD method, a sputtering method, or the like. , a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film is formed in a single layer or in a laminated layer. For example, silane (e.g., monosilane), oxygen, and nitrogen are used as the deposition gas. In this embodiment, a silicon oxynitride film is formed by plasma CVD. An insulating film having a thickness of 200 nm formed by the micro-CVD method is used as the gate insulating film 204. The film formation conditions were a silane gas flow rate of 4 sccm and a dinitrogen monoxide (N2O) flow rate of 80 The flow rate is set to 0 sccm and the substrate temperature is set to 400°C.

[0056] The island-shaped oxide semiconductor film 205 is formed by sputtering using an oxide semiconductor as a target. After forming the oxide semiconductor film, the film is processed into a desired shape by etching or the like. The oxide semiconductor film is formed in a rare gas (for example, argon) atmosphere and an oxygen atmosphere. The film can be formed by a sputtering method under a mixed atmosphere of a rare gas and oxygen.

[0057] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating film 204 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. The treatment may be carried out in an atmosphere containing argon to which chlorine, carbon tetrafluoride, etc. have been added.

[0058] The oxide semiconductor film for forming the channel formation region has the above-described semiconductor characteristics. An oxide material that can achieve this may be used.

[0059] In this embodiment, the oxide semiconductor film is formed using indium (In), gallium (Ga), and Zn (zinc) containing oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1 :1) is used to obtain an In-Ga-Zn-O system non-single crystal film by sputtering. In this embodiment, a DC sputtering method is used, and the flow rate of argon is set to 30 sccm, and the flow rate of oxygen is set to 100 sccm. The flow rate is set to 15 sccm, and the substrate temperature is set to room temperature.

[0060] The gate insulating film 204 and the oxide semiconductor film can be formed successively without being exposed to the air. By continuously forming films without exposing them to the atmosphere, the interface is free from water and hydrocarbons. The interface between each layer is formed without being contaminated by atmospheric components or impurity elements floating in the air. Therefore, the variation in the thin film transistor characteristics can be reduced.

[0061] In addition, the oxide semiconductor film 205 is heated to a temperature of 1000° C. for 1 hour so that moisture, hydrogen, and a hydroxy group contained therein are eliminated. Under reduced pressure, inert gas atmosphere such as nitrogen or rare gas, oxygen gas atmosphere, or ultra-dry Dry air (measured using a CRDS (cavity ring-down laser spectroscopy) dew point meter) The moisture content when the air is cooled is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. Preferably, the temperature is 400°C or higher and 700°C or lower under an atmosphere of air (preferably 10 ppb or lower). Alternatively, the island-shaped oxide semiconductor film 205 is subjected to heat treatment at a temperature in the range of 450° C. or higher and 650° C. or lower. It is desirable to perform the heating and then gradually cool the material to a temperature in the range of room temperature or higher but lower than 100°C in an inert atmosphere. By performing heat treatment on the oxide semiconductor film 205 under the above atmosphere, the oxide semiconductor The moisture, hydrogen, and hydroxyl groups contained in the film 205 are released.

[0062] Heat treatment is carried out using an electric furnace, a GRTA (Gas Rapture Treatment) method using heated gas, etc. id Thermal Anneal (LRTA) method or lamp light Rapid Thermal Annealing (RTA) and other instantaneous heating methods can be used. For example, when heat treatment is performed using an electric furnace, the temperature rise rate can be set to 0.1°C / min or more. 20℃ / min or less, and the temperature drop characteristic can be 0.1℃ / min to 15℃ / min. preferable.

[0063] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0064] After the heat treatment, the island-shaped oxide semiconductor film 205 may be partially or entirely crystallized. stomach.

[0065] After the heat treatment on the oxide semiconductor film 205, the oxide semiconductor film 205 is The oxide semiconductor film 205 may be subjected to heat treatment. Impurities such as moisture can be removed by heat treatment in an oxygen atmosphere. The oxide semiconductor film 205 can have high resistance by being in an oxygen-excess state. The temperature of the heat treatment below is set so that metals with low melting points, such as Zn, which make up the oxide semiconductor, vaporize. For example, a temperature of 100°C or higher and lower than 350°C, preferably 150°C or higher and lower than 250°C The oxygen gas used in the heat treatment in the oxygen atmosphere contains moisture, hydrogen, etc. Alternatively, the purity of the oxygen gas introduced into the heat treatment device is preferably 6N (99 0.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities in oxygen It is preferable to keep the concentration of the substance at 1 ppm or less, preferably 0.1 ppm or less.

[0066] The source electrode 206 and the drain electrode 207 are formed on the island-shaped oxide semiconductor film 205. After forming the conductive film for the source and drain electrodes, patterning is performed by etching or the like. By the above patterning, a source electrode 206 and a drain electrode 207 are formed. During the formation of the oxide semiconductor film 205, the exposed portion of the island-shaped oxide semiconductor film 205 is partly etched.

[0067] Examples of conductive films for source and drain electrodes include aluminum, chromium, tantalum, Titanium, manganese, magnesium, molybdenum, tungsten, zirconium, beryllium An element selected from aluminum and yttrium, or a compound containing one or more of the above elements In addition, when a heat treatment is performed after the formation of the conductive film, the heat treatment It is preferable to give the conductive film heat resistance to the treatment. When heat treatment is performed after forming the conductive film, , in combination with heat-resistant conductive materials to form conductive films. The conductive materials include titanium, tantalum, tungsten, molybdenum, chromium, and neodymium. Elements selected from aluminum and scandium, or compounds containing one or more of the above elements Gold or nitrides containing the above elements as components are preferred.

[0068] The thickness of the source electrode 206 and the drain electrode 207 is 10 nm to 400 nm, preferably 1 In this embodiment, a molybdenum target is used for sputtering. After forming a conductive film for the source and drain electrodes by a photolithography method, the conductive film is etched. The source electrode 206 and the drain electrode 20 Form 7.

[0069] The oxide insulating film 208 covers the island-shaped oxide semiconductor film 205, the source electrode 206, and the drain electrode 207. The oxide semiconductor layer 204 is formed by sputtering so as to be in contact with the inner electrode 207. The oxide insulating film 208 formed in contact with the conductive film 205 is resistant to moisture, hydrogen, oxygen, hydroxyl, and the like. Silicon oxide is free of impurities such as bases, blocking their entry from the outside. An inorganic insulating film such as a silicon nitride oxide film is used.

[0070] In this embodiment, a silicon oxide film with a thickness of 300 nm is formed as the oxide insulating film 208. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower, and in this embodiment, it is set to 100° C. The silicon oxide film is formed by sputtering under a rare gas (e.g., argon) atmosphere and oxygen. It can be carried out under atmosphere or under a noble gas (eg argon) and oxygen atmosphere. As the target, either a silicon oxide target or a silicon target may be used. For example, silicon oxide is formed by sputtering in an oxygen atmosphere using a silicon target. This can be done.

[0071] In contact with the oxide semiconductor film 205 with reduced resistance, an oxidized layer is formed by sputtering or PCVD. When the oxide insulating film 208 is formed, at least the oxide semiconductor film 205 having a low resistance is formed. The region in contact with the oxide insulating film 208 has a carrier concentration of preferably 1×10 18 / cm 3 less than The resistance increases as the oxide insulating film 2 decreases to 2000 Ω / s. By forming the oxide insulating film 208, the oxide semiconductor film 205 has a high resistance near the interface with the oxide insulating film 208. The semiconductor layer has a crystalline oxide semiconductor region.

[0072] After the source electrode 206 and the drain electrode 207 are formed, an oxide insulating film 208 is formed. Before or after the formation, the mixture is heated under reduced pressure, in an inert gas atmosphere such as nitrogen or rare gas, or in an acid atmosphere. under nitrogen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. , preferably 1 ppm or less, preferably 10 ppb or less) in an atmosphere of air, The oxide semiconductor film 205 is again subjected to heat treatment to remove moisture, hydrogen, and The source electrode 206 and the drain electrode 207 may be formed by removing the hydroxyl group. The heat treatment after the formation is carried out in consideration of the heat resistance of the source electrode 206 and the drain electrode 207. The heat treatment is performed at a temperature lower than that performed before forming the source electrode 206 and the drain electrode 207. Specifically, it is desirable to heat the material at a temperature of 350°C or higher and 650°C or lower, preferably 400°C or higher and 60°C or lower. It is best to do this at temperatures below 0°C.

[0073] As shown in FIG. 6C, the thin film transistor 201 has a structure in which The conductive film 209 may further be provided. The conductive film 209 is The conductive film 209 can be made of the same material or have the same laminated structure as the inner electrode 207. The film thickness is set to 10 nm to 400 nm, preferably 100 nm to 200 nm. A resist mask is formed using photolithography and processed into the desired shape (patterning) The conductive film 209 is formed to overlap with a channel formation region of the oxide semiconductor film 205. The conductive film 209 may be in a floating state where it is electrically insulated, or In the latter case, the conductive film 209 may be in a state where a potential is applied. It can be given the same potential as 3, or a fixed potential such as ground. By controlling the level of the potential applied to the conductive film 209, the thin film transistor 20 The threshold voltage of 1 can be controlled.

[0074] When the conductive film 209 is formed, an insulating film 210 is formed to cover the conductive film 209. The insulating film 210 is preferably formed by removing impurities such as moisture, hydrogen, oxygen, and hydroxyl groups as much as possible. These do not contain silicon dioxide, silicon nitride oxide, etc., which block the intrusion of these substances from the outside. Any inorganic insulating film may be used.

[0075] Thin film transistors using oxide semiconductors are different from thin film transistors using amorphous silicon. Thin-film transistors that have higher mobility than amorphous silicon Therefore, not only the pixel area but also the driving frequency area is An oxide semiconductor can be used for the semiconductor element that constitutes the driving circuit with a high wave number, and the laser - A system-on-panel can be realized without using processes such as crystallization.

[0076] In addition, the gate electrode, source electrode, drain electrode, and Even if a metal material with high resistance is used as the conductive film on the oxide insulating film, the display Pulses are input in sequence only to the scan lines of the pixels in a specific area of ​​the pixel section. By displaying a single image, the power consumption of the entire semiconductor display device can be reduced, and reliability can be improved. can be increased.

[0077] This embodiment mode can be implemented in combination with the above embodiment modes.

[0078] (Embodiment 3) In this embodiment, a bottom thin film transistor having a different structure from the thin film transistor 201 described in Embodiment 2 is used. The structure of the thin film transistor of the contact type will be described. The parts or parts having similar functions and steps can be performed in the same manner as in the second embodiment. Therefore, repeated explanation will be omitted.

[0079] FIG. 7(A) is a cross-sectional view of the thin film transistor 211, and FIG. 7(B) is a cross-sectional view of the thin film transistor shown in FIG. 7B. The broken line B1-B2 in FIG. The cross-sectional view in this case corresponds to FIG. 7(A).

[0080] The thin film transistor 211 includes a gate electrode 213 formed on a substrate 212 and a gate electrode A gate insulating film 214 is formed on the gate insulating film 213, and a source The gate electrode 213 is connected to the gate insulating layer 216 and the drain electrode 217. The island-shaped insulating film 214 is formed on the source electrode 216 and the drain electrode 217. the oxide semiconductor film 215 and the oxide insulating film 218 formed over the oxide semiconductor film 215. It has the following characteristics.

[0081] An insulating film serving as a base film may be provided between the gate electrode 213 and the substrate 212 . The base film can be made of the same material and with the same laminated structure as in the second embodiment. The material and laminated structure of the second embodiment can be used for the outer electrode 213. .

[0082] The thickness of the gate electrode 213 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm film is formed by sputtering using a tungsten target. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. By patterning, the gate electrode 213 is formed.

[0083] The gate insulating film 214 employs the same material and laminated structure as in the second embodiment. In this embodiment, the plasma CVD method is used. The insulating film having a thickness of 200 nm formed by the above method is used as the gate insulating film 214. The conditions are a silane gas flow rate of 4 sccm and a nitrous oxide (N2O) flow rate of 800 sccm. The substrate temperature is set to 400°C.

[0084] The source electrode 216 and the drain electrode 217 are formed on the gate insulating film 214. After forming a conductive film for the drain electrode, it is patterned by etching or the like. The conductive film for the source and drain electrodes is made of the same material and laminated film as in the second embodiment. The structure can be adopted.

[0085] In the case of a bottom contact type, the film thickness of the source electrode 216 and the drain electrode 217 is In order to prevent the oxide semiconductor film 215 formed in the above-described embodiment from being cut off, It is desirable to make it thinner than the bottom gate type. In this embodiment, a molybdenum target is used. After forming a conductive film for the source and drain electrodes by a sputtering method using a The source electrode 216 and the drain electrode 217 are formed by processing (patterning) the semiconductor substrate into a desired shape using etching. The gate electrode 217 is formed.

[0086] The island-shaped oxide semiconductor film 215 is formed using the same material and stacked structure as those in Embodiment 2. The gate insulating film 213 is formed at a position overlapping the gate electrode 213 by the manufacturing method shown in the second embodiment. The film 214 can be formed on the source electrode 216 and the drain electrode 217 so as to be in contact with the film 214. Cut.

[0087] In this embodiment, the oxide semiconductor film is formed using indium (In), gallium (Ga), and Zn (zinc) containing oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1 :1) is used to obtain an In-Ga-Zn-O system non-single crystal film by sputtering. In this embodiment, a DC sputtering method is used, and the flow rate of argon is set to 30 sccm, and the flow rate of oxygen is set to 100 sccm. The flow rate is set to 15 sccm, and the substrate temperature is set to room temperature.

[0088] In addition, the oxide semiconductor film 215 is heated to a temperature of 1000° C. for 1 hour so that moisture, hydrogen, and a hydroxy group contained in the oxide semiconductor film 215 are eliminated. Heat treatment under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) Regarding the conditions of the heat treatment, reference can be made to Embodiment Mode 2. By heat-treating the oxide semiconductor film 215, the oxide semiconductor film 215 is Water, hydrogen, and hydroxyl groups are eliminated.

[0089] The oxide insulating film 218 was formed by a sputtering method so as to be in contact with the island-shaped oxide semiconductor film 215. The oxide insulating film 218 is formed using the same material and stacked structure as those in Embodiment 2. The manufacturing method described in Embodiment Mode 2 can be used.

[0090] After the oxide insulating film 218 is formed, an inert gas such as nitrogen or a rare gas is under a gas atmosphere, oxygen gas atmosphere, or ultra-dry air (CRDS) cavity ring down When measured using a laser spectroscopic dew point meter, the moisture content was 20 ppm (dew point equivalent). -55°C or less, preferably 1 ppm or less, preferably 10 ppb or less in air In this case, the oxide semiconductor film 215 is subjected to heat treatment again. The heat treatment may be performed in such a way that the moisture, hydrogen, and hydroxyl groups present in the film are eliminated. , reference can be made to embodiment 2.

[0091] As shown in FIG. 7C, the thin film transistor 211 has a structure in which The conductive film 219 may further comprise a source electrode 216 or a drain electrode 218. The conductive film 21 can be made of the same material or have the same laminated structure as the rain electrode 217. The film thickness of 9 is 10 nm to 400 nm, preferably 100 nm to 200 nm. A resist mask is formed by photolithography and processed into the desired shape (patterning). By this, the conductive film 219 is formed so as to overlap with a channel formation region of the oxide semiconductor film 215. The conductive film 219 is in an electrically insulating floating state. In the latter case, the conductive film 219 may be in a state where a potential is applied. The potential may be the same as that of the port electrode 213, or may be a fixed potential such as ground. By controlling the level of the potential applied to the conductive film 219, the thin film transistor The threshold voltage of the transistor 211 can be controlled.

[0092] When the conductive film 219 is formed, the insulating film 220 is formed so as to cover the conductive film 219. The insulating film 220 contains as little impurities as possible, such as moisture, hydrogen, oxygen, and hydroxyl groups. Inorganic insulating films such as silicon oxide film and silicon nitride oxide film are used to block these substances from entering from the outside. Use the velum.

[0093] Thin film transistors using oxide semiconductors are different from thin film transistors using amorphous silicon. Thin-film transistors that have higher mobility than amorphous silicon Therefore, not only the pixel area but also the driving frequency area is An oxide semiconductor can be used for the semiconductor element that constitutes the driving circuit with a high wave number, and the laser A system-on-panel can be realized without using processes such as crystallization.

[0094] In addition, the gate electrode, source electrode, drain electrode, and Even when a metal material with high resistance is used as the conductive film on the oxide insulating film, the same as in the first embodiment can be obtained. As explained in , pulses are input in sequence only to the scanning lines that have pixels on the line to be displayed. By displaying an image only in a specific area of ​​the pixel section, the power consumption of the entire semiconductor display device is reduced. This reduces power consumption and improves reliability.

[0095] This embodiment mode can be implemented in combination with the above embodiment modes.

[0096] (Fourth embodiment) In this embodiment, the thin film transistor 201 shown in Embodiment 2 or the thin film transistor 202 shown in Embodiment 3 is The structure is different from that of the thin film transistor 221 shown in FIG. The structure of the thin film transistor will be described. Note that the same parts as those in the second embodiment or similar functions will be described. The functional parts and steps can be performed in the same manner as in the second embodiment, so that the repetition The explanation will be omitted.

[0097] FIG. 8(A) is a cross-sectional view of the thin film transistor 221, and FIG. 8(B) is a cross-sectional view of the thin film transistor shown in FIG. 8(A). 8B. The broken line C1-C2 in FIG. The cross-sectional view in this case corresponds to FIG. 8(A).

[0098] The thin film transistor 221 includes a gate electrode 223 formed on a substrate 222 and a gate electrode A gate insulating film 224 is formed on the gate electrode 223, and a gate electrode 224 is formed on the gate insulating film 224 at a position where the gate electrode 223 overlaps the gate electrode 223. The island-shaped oxide semiconductor film 225 formed on the gate insulating film 224 and the island-shaped oxide semiconductor film The island-shaped oxide semiconductor film 22 is formed so as to overlap with a portion of the oxide semiconductor film 225 that will become a channel formation region. 5, and a channel protection film 231 formed on the island-shaped oxide semiconductor film 225. The source electrode 226 and the drain electrode 227, the channel protective film 231, and the source electrode 226 and an oxide insulating film 228 formed over the drain electrode 227.

[0099] An insulating film serving as a base film may be provided between the gate electrode 223 and the substrate 222 . The base film can be made of the same material and with the same laminated structure as in the second embodiment. The material and laminated structure of the second embodiment can be used for the outer electrode 223. .

[0100] The thickness of the gate electrode 223 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm film is formed by sputtering using a tungsten target. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. By patterning, the gate electrode 223 is formed.

[0101] The gate insulating film 224 employs the same material and laminated structure as in the second embodiment. In this embodiment, the plasma CVD method is used. The insulating film having a thickness of 200 nm formed by the above method is used as the gate insulating film 224. The conditions are a silane gas flow rate of 4 sccm and a nitrous oxide (N2O) flow rate of 800 sccm. The substrate temperature is set to 400°C.

[0102] The island-shaped oxide semiconductor film 225 is formed using the same material and stacked structure as those in Embodiment 2. The gate insulating film 222 is formed at a position overlapping with the gate electrode 223 by the manufacturing method shown in the second embodiment. It can be formed on the film 224 .

[0103] In this embodiment, the oxide semiconductor film is formed using indium (In), gallium (Ga), and Zn (zinc) containing oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1 :1) is used to obtain an In-Ga-Zn-O system non-single crystal film by sputtering. In this embodiment, a DC sputtering method is used, and the flow rate of argon is set to 30 sccm, and the flow rate of oxygen is set to 100 sccm. The flow rate is set to 15 sccm, and the substrate temperature is set to room temperature.

[0104] In addition, the oxide semiconductor film 225 is heated to a temperature of 1000° C. for 1 hour so that moisture, hydrogen, and a hydroxy group contained in the oxide semiconductor film 225 are eliminated. Under reduced pressure, inert gas atmosphere such as nitrogen or rare gas, oxygen gas atmosphere, or ultra-dry Dry air (measured using a CRDS (cavity ring-down laser spectroscopy) dew point meter) The moisture content when the air is cooled is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. Preferably, the heat treatment is carried out in an air atmosphere of 10 ppb or less. The conditions can be referred to those in Embodiment 2. By the treatment, the oxide semiconductor film 225 is free from moisture, hydrogen, hydroxyl, and the like contained in the film. The group is eliminated.

[0105] The channel protective film 231 is formed by forming a channel formation region in the island-shaped oxide semiconductor film 225. The channel protective film 2 is formed on the island-shaped oxide semiconductor film 225 so as to overlap with the channel protective film 2. By providing the insulating film 31, the insulating film 31 can be formed in a portion that becomes a channel formation region of the oxide semiconductor film 225. Damage during subsequent processes (film reduction due to plasma or etching agent during etching) Therefore, the reliability of the thin film transistor can be improved. .

[0106] The channel protection film 231 is made of an inorganic material containing oxygen (silicon oxide, silicon oxynitride, silicon nitride oxide, etc.). The channel protection film 231 can be formed by plasma CVD or thermal CVD. The channel protection film can be formed by a vapor deposition method such as a sputtering method. After the film is formed, the shape of 231 is processed by etching. Here, silicon oxide is formed by sputtering. A base film is formed and then etched using a photolithography mask to create a chalcogenide film. A protective film 231 is formed on the substrate.

[0107] In addition, an oxide film is formed in contact with the island-shaped oxide semiconductor film 225 by a sputtering method, a PCVD method, or the like. When the channel protection film 231, which is an insulating film, is formed, oxygen is supplied from the channel protection film 231. The island-shaped oxide semiconductor film 225 is in contact with at least the channel protective film 231. The region has a carrier concentration of preferably 1×10 18 / cm 3 Less than 1×1 0 14 / cm 3 When the temperature drops below this level, the resistance increases, forming a high-resistance oxide semiconductor region. By forming the channel protection film 231, the oxide semiconductor film 225 is A high-resistance oxide semiconductor region can be provided near the interface with the first insulating film.

[0108] The source electrode 226 and the drain electrode 227 are formed by the island-shaped oxide semiconductor film 225 and the channel After forming a conductive film for the source and drain electrodes on the panel protective film 231, etching or the like is performed. The conductive film for the source and drain electrodes is formed by patterning the conductive film. The same materials, laminated structure and film thickness as those in the second embodiment can be used.

[0109] In this embodiment, the source electrode and drain electrode are formed by sputtering using a molybdenum target. After forming a conductive film for an electrode, the conductive film is processed into a desired shape by etching (patterning). By this process, a source electrode 226 and a drain electrode 227 are formed on the island-shaped oxide semiconductor film 225. Form 27.

[0110] The oxide insulating film 228 covers the island-shaped oxide semiconductor film 225, the source electrode 226, the drain electrode 227, and the oxide semiconductor film 228. The oxide insulating film 228 is formed by sputtering so as to be in contact with the gate electrode 227. The same materials and laminated structure as those in Embodiment 2 are used, and the manufacturing method shown in Embodiment 2 is used. Note that when the channel protective film 231 is formed, the oxide insulating film There is no need to form 228.

[0111] After the source electrode 226 and the drain electrode 227 are formed, an oxide insulating film 228 is formed. Before or after the formation, the mixture is heated under reduced pressure, in an inert gas atmosphere such as nitrogen or rare gas, or in an acid atmosphere. under nitrogen gas atmosphere or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) When measured using a dew point meter, the moisture content is 20 ppm (-55°C in dew point equivalent) or less. , preferably 1 ppm or less, preferably 10 ppb or less) in an atmosphere of air, The oxide semiconductor film 225 is again subjected to heat treatment to remove moisture, hydrogen, and The hydroxyl group may be eliminated. can be referred to.

[0112] As shown in FIG. 8C, the thin film transistor 221 has a structure in which The semiconductor device may further include a conductive film 229. The conductive film 229 may be a conductive film for the source electrode 226 or the drain electrode 228. The conductive film 22 can be made of the same material or with the same layer structure as the rain electrode 227. The film thickness of 9 is 10 nm to 400 nm, preferably 100 nm to 200 nm. A resist mask is formed by photolithography and processed into the desired shape (patterning). By this, the conductive film 229 is formed so as to overlap with a channel formation region of the oxide semiconductor film 225. The conductive film 229 is formed in a floating state where it is electrically insulated. In the latter case, the conductive film 229 may be in a state where a potential is applied. The potential may be the same as that of the port electrode 223, or may be a fixed potential such as ground. By controlling the potential level applied to the conductive film 229, the thin film transistor The threshold voltage of the transistor 221 can be controlled.

[0113] When the conductive film 229 is formed, the insulating film 230 is formed to cover the conductive film 229. The insulating film 230 contains as little impurities as possible, such as moisture, hydrogen, and hydroxyl groups. Inorganic insulating films such as silicon oxide film and silicon nitride oxide film are used to block external penetration. Use.

[0114] Thin film transistors using oxide semiconductors are different from thin film transistors using amorphous silicon. Thin-film transistors that have higher mobility than amorphous silicon Therefore, not only the pixel area but also the driving frequency area is An oxide semiconductor can be used for the semiconductor element that constitutes the driving circuit with a high wave number, and the laser A system-on-panel can be realized without using processes such as crystallization.

[0115] In addition, the gate electrode, source electrode, drain electrode, and Even if a metal material with high resistance is used as the conductive film on the oxide insulating film, the display Pulses are input in sequence only to the scan lines of the pixels in a specific area of ​​the pixel section. By displaying a single image, the power consumption of the entire semiconductor display device can be reduced, and reliability can be improved. can be increased.

[0116] This embodiment mode can be implemented in combination with the above embodiment modes.

[0117] (Embodiment 5) In this embodiment, an example of a specific configuration of a NOR circuit used in a decoder will be described. I will explain.

[0118] An example of a circuit diagram of a NOR circuit is shown in Figure 9. The NOR circuits shown in Figure 9 are all n-channel type. The pixel is formed using thin film transistors.

[0119] The NOR circuit shown in FIG. 9 has n transistors whose source electrodes and drain electrodes are connected to each other. The transistors 911-1 to 911-n and a transistor 912 are provided. In this specification, the term "connected" means a connection in which an electrical signal is transmitted between two electrodes. Alternatively, another conductor such as a wire may be present between the electrodes.

[0120] The source electrodes of the n transistors 911-1 to 911-n are connected to a low-level power supply voltage VS S is given. The drain electrodes of the n transistors 911-1 to 911-n are , is connected to the source electrode of the transistor 912, and the voltage of the source electrode is applied to the scan line. The drain and gate electrodes of the transistor 912 are connected to the A high-level power supply voltage VDD is applied.

[0121] The NOR circuit receives n bits selected from the control signals D1 to Dn and the control signals Db1 to Dbn. At least one of the control signals input to the NOR circuit is high. When the voltage is at the high level (Hi), one of the transistors 911-1 to 911-n is turned on. A low-level power supply voltage VSS is applied to the scan lines as a voltage Vout.

[0122] Next, when all the control signals input to the NOR circuit become low level (Lo), the The transistors 911-1 to 911-n are all turned off. Also, the transistor 912 is turned on. Therefore, a high-level power supply voltage VDD is applied to the scan lines as a voltage Vout.

[0123] Next, another example of a circuit diagram of a NOR circuit is shown in FIG. 10. The NOR circuit shown in FIG. The pixel is formed using an n-channel thin film transistor.

[0124] The NOR circuit shown in FIG. 10 has n-channel transistors in which the source and drain electrodes are connected to each other. The source electrodes and drain electrodes of the transistors 901-1 to 901-n are connected to each other. The n transistors 902-1 to 902-n, the transistor 903, and the transistor The sensor 904 is also included.

[0125] The transistors 901-1 to 901-n and the transistors 902-1 to 902-n are In other words, the gate electrodes are connected to each other, where i is selected from 1 to n. If we define it as an arbitrary number, the gate electrodes of transistors 901-i and 902-i Also, the source electrodes of n transistors 901-1 to 901-n are connected to The source electrodes of the n transistors 902-1 to 902-n are connected to a low-level power supply voltage VS S is given. The drain electrodes of the n transistors 901-1 to 901-n are , which is connected to the source electrode of the transistor 903 and the gate electrode of the transistor 904. The drain electrode and gate electrode of the transistor 903 and the drain electrode of the transistor 904 are connected to each other. A high-level power supply voltage VDD is applied to the power electrode of the transistor 904. The electrode is connected to the drain electrodes of n transistors 902-1 to 902-n. The voltages of these electrodes are applied to the scan lines as voltage Vout.

[0126] The NOR circuit receives n bits selected from the control signals D1 to Dn and the control signals Db1 to Dbn. At least one of the control signals input to the NOR circuit is high. When the voltage is at the high level (Hi), one of the transistors 901-1 to 901-n and the One of the transistors 902-1 to 902-n is turned on. A low level voltage VSS is applied to the scan line as a voltage Vout. The source electrode of the transistor 903 and the gate electrode of the transistor 904 are connected to each other via the transistor 903. The electrodes are also supplied with a low level voltage VSS.

[0127] Next, when all the control signals input to the NOR circuit become low level (Lo), the The transistors 901-1 to 901-n and the transistors 902-1 to 902-n are all turned off. Also, since the transistor 903 is on, the power supply voltage VDD is supplied to the transistor 90 A current begins to flow through transistor 903 and the gate of transistor 904. The voltage at the electrode begins to rise.

[0128] Then, the voltage between the gate electrode and source electrode of the transistor 904, that is, the gate voltage, When the power supply voltage VSS exceeds the threshold voltage Vth of the transistor 904, the transistor 90 When transistor 904 is turned on, the power supply voltage VDD is supplied to transistor A current begins to flow through 904, and the voltage at the source electrode of transistor 904, V out is also the voltage of the source electrode of transistor 903 and the gate electrode of transistor 904. It begins to rise, following suit.

[0129] The source electrode of transistor 903 is then connected to the power supply voltage VDD minus the threshold voltage of transistor 903. As the voltage approaches the threshold voltage Vth over time, the transistor 903 automatically turns off. In addition, since the transistors 902-1 to 902-n are all off, the transistor 904 Therefore, the gate electrode and the source electrode of the transistor 904 are in a floating state. The voltage difference between these two is maintained by the gate capacitance of transistor 904.

[0130] On the other hand, even after the transistor 903 is turned off, the transistor 904 remains on. Therefore, the voltage Vout at the source electrode of transistor 904 continues to rise. Therefore, the voltage of the gate electrode of the transistor 904 increases as the voltage Vout increases. The voltage difference between the gate electrode and the source electrode continues to rise. When the source electrode of 904 and the voltage Vout approach the power supply voltage VDD, the voltage Vout rises. is stopped and held at voltage VDD.

[0131] In this way, like the NOR circuit shown in FIG. 10, the gate electrode of the transistor 904 is floating. When the bootstrap operation is performed by setting the transistor 903 to the Regardless of the threshold voltage of the capacitor 904, the voltage Vout can be made equal to the voltage VDD.

[0132] The NOR circuit shown in FIG. 10 performs a bootstrap operation, so as described above, The gate electrode of transistor 904 must be left floating. When the gate electrode of the transistor 904 is in a floating state, the current leaking from the gate electrode of the transistor 904 The larger the load, the greater the rise in potential at the gate electrode due to the bootstrap operation. In particular, in the NOR circuit shown in FIG. The gate electrode of the transistor 904 is connected to the transistors 901-1 to 901-n. Therefore, the number of transistors connected to the gate electrode of the transistor 904 is large. Therefore, the charge leakage from the transistor 904 causes the gate electrode of the transistor 904 to The potential tends to be low.

[0133] Therefore, we have developed a NOR circuit using oxide semiconductors as the channel transistors. A transistor having an oxide semiconductor in a channel formation region is used. Since the off-state current of the transistor is low, the amount of charge leaking from the gate electrode of the transistor 904 is As a result, when bootstrap operation is performed, the transistor The potential of the gate electrode of transistor 904 can be increased. Since the gate voltage of 4 can be increased, the rise time of the voltage Vout can be shortened. In addition, the amplitude of the potential of the control signals D1 to Dn and Db1 to Dbn can be reduced. Since the number of bits can be reduced, the power consumption of the NOR circuit can be reduced.

[0134] This embodiment mode can be implemented in combination with the above embodiment modes.

[0135] (Sixth embodiment) In this embodiment, an example of the overall configuration of a semiconductor display device of the present invention will be described. 11 shows a block diagram of a semiconductor display device of the present invention.

[0136] The semiconductor display device shown in FIG. 11A has a plurality of pixels each including a display element and a thin film transistor. a pixel section 300 having a number of pixels, a scanning line driving circuit 301 for selecting each pixel for each line, and a selection and a signal line driver circuit 302 for controlling the input of video signals to pixels on the lines.

[0137] In FIG. 11A, a scanning line driving circuit 301 has a decoder 303. The operation of the operation circuit 301 is controlled by n-bit control signals D1 to Dn input to the operation circuit 301. Specifically, the decoding is performed according to the combination of the values ​​of each bit of the control signals D1 to Dn. A selection signal having a pulse is inputted to the pixel section 300 in sequence from the input terminal 303 via the scanning line. Also, the display can be changed by combining the values ​​of each bit of the control signals D1 to Dn. Pulses are input in sequence only to the pixels of the lines that will be displayed, and pulses are input to the pixels of the other lines that will not be displayed. Therefore, the scanning line driving circuit 301 can be operated so that no pulse is input.

[0138] The signal line driver circuit 302 includes a shift register 304 and a sampling circuit 305. The shift register 304 has at least one drive circuit for controlling the operation of the shift register 304. The operating signals, specifically the clock signal S-CLK and the start pulse signal S-SP, are input. When these drive signals are input, a timing signal is generated in which the pulses are shifted sequentially. The input signal is input to the sampling circuit 305. The sampling circuit 305 In accordance with the timing signal, the video signal for one line period input to the signal line driving circuit 302 is The sampled video signal is then sent to the pixel section 30 via a signal line. 0 is input sequentially.

[0139] On the other hand, the scanning line driving circuit 301 controls the decoder 30 in accordance with the input control signals D1 to Dn. A selection signal having a pulse is generated in 3 and input to each scanning line. In the pixel having the scanning line, a video signal is inputted via the signal line.

[0140] The time it takes for the video signal to be written to all signal lines is called the line period. In reality, the line period includes the above line period plus the horizontal blanking period. This can happen.

[0141] The video signal may be sampled for each corresponding pixel in turn, or may be sampled for each pixel in one line. The pixels may be divided into several groups, and the processing may be performed in parallel for each pixel corresponding to each group. stomach.

[0142] In FIG. 11A, the pixel unit 300 is directly connected to the rear stage of the sampling circuit 305. However, the present invention is not limited to this configuration. A circuit for performing signal processing on the video signal output from 305 can be provided. An example of a circuit that performs this is a buffer that can shape the waveform. .

[0143] In addition, in FIG. 11(A), the timing signal for sampling the video signal is shifted. However, the present invention is not limited to this configuration. For example, As shown in FIG. 11(B), a decoder 306 is used instead of the shift register 304, A timing signal may be generated to control the operation of the decoder 306. The control signals DS1 to DSm for controlling the signal line driver 302 are input as drive signals to the signal line driver circuit 302. .

[0144] By using the decoder 306, the video signal from the signal line driver circuit 302 is It is possible to sample and input only to the signal lines of the pixels. If the pixel count is constant, rather than inputting a video signal to all pixels of the selected line, The signal line driver circuit 302 is configured to input a video signal to some of the pixels on the selected line. Since the drive frequency can be kept low, power consumption can be reduced.

[0145] The semiconductor display device shown in FIG. 11 includes a pixel portion 300, a scanning line driver circuit 301, and a signal It may also be a system-on-panel in which the line driving circuit 302 is formed on one substrate. By using a panel, the driving circuits such as the scanning line driving circuit 301 and the signal line driving circuit 302 can be easily The number of pins for connecting the driver circuit and the pixel unit 300 is reduced, and connection failure between the driver circuit and the pixel unit is prevented. To avoid the resulting yield reduction and low mechanical strength at the connection points using pins, Furthermore, it is possible to not only miniaturize the display device but also reduce the assembly and inspection processes. The realization of a system on panel also makes it possible to reduce costs through the use of a system on panel. In the case of a flexible printed circuit (FPC) or other connection parts, Various signals such as control signals, video signals, and drive signals are transmitted from the controller via the The voltage is supplied to the pixel section 300, the scanning line driving circuit 301, or the signal line driving circuit 302. .

[0146] 11 is not limited to a system-on-panel display. For example, the sampling circuits of the scanning line driver circuit 301 and the signal line driver circuit 302 The analog switches used in the circuit 305 are formed on the same substrate as the pixel section 300. However, the remaining shift register 304 and decoder 306, which have a relatively high driving frequency, are driven by a different base. In this case, a circuit with a high driving frequency can be formed on a substrate using a single crystal semiconductor. The pixel section 300 and the circuit with a low driving frequency are formed of a semiconductor element using an oxide semiconductor. In this way, the system on panel can be partially adopted. By using this, the yield reduction caused by the above-mentioned connection failure and the problem of the connection part using the pin can be prevented. This avoids the low mechanical strength that can be caused by the assembly process and inspection process, reducing costs. Furthermore, the pixel section 300, the driving section 301, and the like can be used to some extent. A system-on-chip in which the scan line driver circuit 301 and the signal line driver circuit 302 are all formed on one substrate. Compared to single crystals, it can improve the performance of circuits with high drive frequencies. It is possible to form a large pixel area, which is difficult to achieve when using semiconductors. .

[0147] This embodiment mode can be implemented in combination with the above embodiment modes.

[0148] (Embodiment 7) In this embodiment, a specific structure of a pixel portion included in a semiconductor display device according to one embodiment of the present invention will be described. An example of the configuration will be described below.

[0149] FIG. 12 shows a light-emitting device in which each pixel is provided with a light-emitting element, typically an organic light-emitting diode (OLED). 12 is a circuit diagram of a pixel unit. The pixel unit shown in FIG. 12 includes a plurality of signal lines S1 to Sx, a plurality of power supply lines S1 to Sx, and a plurality of power supply lines S2 to Sx. The pixels 310 each have a signal line S 1 to Sx, one of the power supply lines V1 to Vx, and one of the scanning lines G1 to Gy. It also has

[0150] Each pixel 310 includes a light emitting element 313 and a switch that controls the input of a video signal to the pixel 310. A switching transistor 311 and a driving transistor for controlling the current value supplied to the light emitting element 313 are provided. The gate electrode of the switching transistor 311 is The switching transistor 311 is connected to one of the scanning lines G1 to Gy. One of the source electrode and the drain electrode is connected to one of the signal lines S1 to Sx, and the other is connected to the drive The gate electrode of the driving transistor 312 is connected to the One of the source electrode and the drain electrode is connected to one of the power supply lines V1 to Vx, and the other is connected to the The pixel 310 is connected to the pixel electrode of the photoelement 313. The pixel 310 also has a storage capacitor 314. The storage capacitor 314 has one electrode connected to one of the power supply lines V1 to Vx, and the other electrode connected to one of the power supply lines V1 to Vx. One electrode is connected to the gate electrode of the driving transistor 312 .

[0151] The light emitting element 313 has an anode, a cathode, and an electroluminescent layer provided between the anode and the cathode. One of the anode and cathode is used as a pixel electrode, and the other is used as a counter electrode. When the anode is connected to the source or drain electrode of the pixel transistor 312, The cathode is the source electrode of the driving transistor 312, and the cathode is the counter electrode. When connected to the drain electrode, the cathode serves as the pixel electrode and the anode serves as the counter electrode.

[0152] A voltage is applied from a power source to the counter electrode of the light emitting element 313 and the power line. The voltage difference between the counter electrode and the power supply line causes light to be emitted when the driving transistor 312 is turned on. The voltage is maintained at a value such that a forward bias voltage is applied to the element.

[0153] The switching transistor 311 is turned on by the pulse of the selection signal input to the scanning line. When this occurs, the voltage of the video signal input to the signal line is applied to the gate of the driving transistor 312. The voltage of the input video signal is applied to the driving transistor 31. The gate voltage (voltage difference between the gate electrode and the source electrode) of 2 is determined. The drain current of the driving transistor 312 is supplied to the light emitting element 313 according to the This causes the light emitting element 313 to emit light.

[0154] When displaying an image in a specific area, pulses are sent only to the scanning lines of the pixels in that area. Then, a selection signal having a pixel signal is inputted only to the signal lines of the pixels in the area. By inputting a video signal containing image information, an image can be displayed only in a specific area. It is possible.

[0155] The light emitting device controls the time during which a pixel displays white during one frame period. It may be a time gradation drive that displays gradation, or a video signal having analog image information. It may be an analog gray scale drive using

[0156] The configuration of the pixel 310 shown in FIG. 12 is just one example of the pixel included in the semiconductor display device of the present invention. The present invention is not limited to the pixel configuration shown in FIG.

[0157] FIG. 13 is a circuit diagram of a pixel portion of a liquid crystal display device in which each pixel is provided with a liquid crystal element. The pixel portion shown has a plurality of signal lines S1 to Sx and a plurality of scanning lines G1 to Gy. Each pixel 320 is connected to at least one of the signal lines S1 to Sx and one of the scanning lines G1 to Gy. It has.

[0158] The pixel 320 includes a transistor 321 that functions as a switching element and a liquid crystal element 322. and a storage capacitor 323. The gate electrode of the transistor 321 is connected to the scanning lines G1 to G5. The source and drain electrodes of the transistor 321 are connected to one of the scan lines Gy. One end is connected to one of the signal lines S1 to Sx, and the other end is connected to the pixel electrode of the liquid crystal element 322. The liquid crystal element 322 is connected to a pixel electrode, a counter electrode, and a The storage capacitor 323 is connected to the pixel electrode of the liquid crystal element 322 and the counter electrode. Specifically, the storage capacitor 323 is provided to hold the voltage applied between the electrodes. One of the pair of electrodes is connected to the pixel electrode of the liquid crystal element 322, and the other is connected to a constant voltage. Pressure is being applied.

[0159] When the scanning lines G1 to Gy are selected in order, in the pixel 320 having the selected scanning line, The transistor 321 is turned on. Then, the video signals input to the signal lines S1 to Sx are A voltage is applied to the pixel electrode of the liquid crystal element 322 via the transistor 321 that is on. In the liquid crystal element 322, when a voltage is applied, the orientation of the liquid crystal molecules changes, and the bending of the liquid crystal also changes. Therefore, the transmittance changes according to the voltage of the video signal, Gradation can be expressed in the sub-pixel 322.

[0160] When displaying an image in a specific area, pulses are sent only to the scanning lines of the pixels in that area. Then, a selection signal having a pixel signal is inputted only to the signal lines of the pixels in the area. By inputting a video signal containing image information, an image can be displayed only in a specific area. It is possible.

[0161] The configuration of the pixel 320 shown in FIG. 13 is just one example of the pixel included in the semiconductor display device of the present invention. The present invention is not limited to the pixel configuration shown in FIG.

[0162] (Embodiment 8) In this embodiment, an electronic paper or digital display device, which is one of the semiconductor display devices of the present invention, is used. A semiconductor display device called "paper" will now be described.

[0163] Electronic paper can control the gradation by applying voltage and has memory properties. Specifically, the display element used in the electronic paper is a non-aqueous electrophoretic display element. A dynamic display element, in which liquid crystal droplets are dispersed in a polymer material between two electrodes. LC (polymer dispersed liquid crystal) method table Display element, display having chiral nematic liquid crystal or cholesteric liquid crystal between two electrodes The element has charged particles between two electrodes, and the particles are moved through the powder by an electric field. A powder migration type display element can be used. Also, a non-aqueous electrophoretic type display element can be used. is a display element in which a dispersion liquid in which charged particles are dispersed is sandwiched between two electrodes, and A display element having a dispersion liquid in which fine particles are dispersed on two electrodes sandwiching an insulating film, A twisting ball with two differently charged hemispheres is placed between two electrodes. a display element in which charged particles are dispersed in a solvent, a micro-element in which charged particles are dispersed in a solution, This includes a display element having a chlorocapsule between two electrodes.

[0164] FIG. 14A shows a pixel portion 700 of electronic paper, a signal line driver circuit 701, and a scanning line driver circuit 702. A top view of the circuit 702 is shown.

[0165] The pixel portion 700 has a plurality of pixels 703. A signal line driver circuit 701 outputs a plurality of A signal line 707 is routed to the inside of the pixel portion 700. The scanning lines 708 are routed to the inside of the pixel section 700 .

[0166] Each pixel 703 has a transistor 704, a display element 705, and a storage capacitor 706. The gate electrode of the transistor 704 is connected to one of the scanning lines 708. The source electrode and the drain electrode of the transistor 704 are connected to one of the signal lines 707 and the other to It is connected to the pixel electrode of the display element 705 .

[0167] In FIG. 14A, the voltage applied between the pixel electrode and the counter electrode of the display element 705 is maintained. A storage capacitor 706 is connected in parallel to the display element 705 to maintain the If the memory capacity of 05 is high enough to maintain the display, then a retention capacity of 70 It is not necessary to provide 6.

[0168] In FIG. 14A, each pixel has one transistor functioning as a switching element. The structure of the active matrix pixel portion provided with the pixel electrode has been described. The electronic paper is not limited to this configuration. In addition to the transistor and capacitance, elements such as resistors and coils may also be connected. good.

[0169] FIG. 14(B) shows an example of electrophoretic electronic paper with microcapsules, 7 shows a cross-sectional view of a display element 705 provided on a substrate 703.

[0170] The display element 705 includes a pixel electrode 710, a counter electrode 711, and a pair of the pixel electrode 710 and the counter electrode The microcapsule 712 has a voltage applied thereto by the transistor 711. One of the four source or drain electrodes 713 is connected to the pixel electrode 710 .

[0171] The microcapsules 712 contain a positively charged white pigment such as titanium oxide and carbon dioxide. Negatively charged black pigments such as lanthanum black are enclosed together with a dispersion medium such as oil. The voltage of the pixel electrode and the counter electrode changes in accordance with the voltage of the video signal applied to the pixel electrode 710. By applying a voltage between them, the black pigment is attracted to the positive electrode side and the white pigment to the negative electrode side. , and gradation display can be performed.

[0172] In FIG. 14B, the microcapsules 712 are disposed between the pixel electrode 710 and the counter electrode 711. However, the present invention uses this structure. The structure is not limited to the microcapsules 712, the pixel electrodes 710, and the counter electrodes 711. The space formed may be filled with a gas such as air or an inert gas. In this case, the microcapsules 712 are attached to the pixel electrodes 710 and the counter electrodes 711 by adhesive or the like. It is desirable to fix both or either one of them.

[0173] The number of microcapsules 712 included in the display element 705 is as shown in FIG. It is not necessarily the case that one display element 705 has a plurality of microcapsules 712. Alternatively, a plurality of display elements 705 may have one microcapsule 712. For example, two display elements 705 may share one microcapsule 712, and one A positive voltage is applied to the pixel electrode 710 of the display element 705, and a negative voltage is applied to the pixel electrode 710 of the other display element 705. In this case, a positive voltage is applied to the pixel electrode 710. In the area overlapping with the applied pixel electrode 710, a black face is formed within the microcapsule 712. The white pigment is attracted to the pixel electrode 710 side, and the white pigment is attracted to the counter electrode 711 side. Conversely, in the area overlapping with the pixel electrode 710 to which a negative voltage is applied, the microcapsules In the cell 712, the white pigment is attracted to the pixel electrode 710 side, and the black pigment is attracted to the counter electrode 71 It is drawn to one side.

[0174] Next, regarding the specific driving method of the electronic paper, the electrophoretic electronic paper described above will be Let me explain with an example.

[0175] The operation of electronic paper can be explained by dividing it into an initialization period, a writing period, and a retention period. Yes, it is possible.

[0176] Before switching the image to be displayed, the grayscale of each pixel in the pixel section is first reset during the initialization period. By unifying the display elements, the display elements are initialized. By initializing the display elements, afterimages are prevented from remaining. Specifically, in the electrophoretic type, each pixel is displayed in either white or black. The gray scale displayed by the microcapsules 712 of the display element 705 is adjusted.

[0177] In this embodiment, after inputting an initialization video signal to display black to the pixel, a video signal to display white is input. The initialization operation when an initialization video signal such as the one shown in the figure is input to the pixel will be explained. For example, in the case of an electrophoretic electronic paper in which an image is displayed facing the counter electrode 711 side, In this case, first, the black pigment in the microcapsules 712 is applied to the counter electrode 711 side, and the white pigment is applied to the image side. A voltage is applied to the display element 705 so that it faces the base electrode 710. The white pigment in the cell 712 faces the counter electrode 711 side, and the black pigment faces the pixel electrode 710 side. Then, a voltage is applied to the display element 705 .

[0178] Also, if the initialization video signal is input to the pixel only once, the image displayed before the initialization period will Depending on the gradation, the movement of the white pigment and the black pigment in the microcapsule 712 may be incomplete. Even after the initialization period has ended, the gray scale displayed between the pixels remains the same. Therefore, a negative voltage - Vp is applied to the pixel electrode 710 multiple times to display black, and It is desired to display white by applying a positive voltage Vp to the pixel electrode 710 multiple times. I wish.

[0179] If the gray scale displayed by the display element of each pixel before the initialization period is different, The minimum number of times that the video signal must be input varies depending on the display. The number of times the initialization video signal is input between pixels is changed according to the gradation that has been set. In this case, the pixels that no longer need to input the initialization video signal may be It is a good idea to input the supply voltage Vcom.

[0180] It should be noted that the voltage Vp or voltage −Vp of the initialization video signal is applied to the pixel electrode 710 multiple times. In order to do this, during the period when the pulse of the selection signal is given to each scanning line, the scanning line is A series of operations of inputting an initialization video signal to the pixels of the line having the By applying the voltage Vp or voltage −Vp of the initialization video signal to the pixel electrode 710 multiple times, This allows the movement of the white pigment and black pigment within the microcapsules 712 to converge, resulting in a uniform distribution of the white pigment and black pigment between the pixels. This can prevent a difference in gray level from occurring in the pixel portion and initialize the pixels in the pixel portion.

[0181] During the initialization period, each pixel does not display black and then white. Alternatively, in the initialization period, the pixels may be configured to display black after the initial state. It is also possible to display white, then black, and then white again.

[0182] The timing at which the initialization period starts is the same for all pixels in the pixel section. For example, it is not necessary to do it for each pixel, or for each pixel that belongs to the same line. The timing at which the initialization period starts may be varied.

[0183] Next, in the writing period, a video signal having image information is input to the pixels.

[0184] When an image is displayed on the entire pixel area, power is applied to all the scanning lines in sequence during one frame period. A selection signal with a shifted voltage pulse is input. Then, a pulse appears in the selection signal. During one line period, video signals containing image information are input to all signal lines. do.

[0185] The white light in the microcapsules 712 changes in response to the voltage of the video signal applied to the pixel electrode 710. The color pigment and the black pigment move to the pixel electrode 710 side or the counter electrode 711 side, thereby forming a display element. The child 705 displays the gray scale.

[0186] In the writing period, as in the initialization period, the voltage of the video signal is applied to the pixel electrode 710 multiple times. Therefore, during the period when the pulse of the selection signal is applied to each scanning line, In this case, a series of operations of inputting a video signal to pixels of a line having the scanning line is performed as follows: Do this multiple times.

[0187] Next, in the holding period, a common voltage Vcom is input to all pixels via the signal line, and then the scanning No selection signal is input to the line or a video signal is input to the signal line. The white pigment and the black pigment in the microcapsule 712 of 705 are opposite to the pixel electrode 710. The arrangement is maintained unless a positive or negative voltage is applied between the opposing electrodes 711. Therefore, the gray scale displayed by the display element 705 is maintained. The displayed image is maintained during the retention period.

[0188] In addition, when an image is displayed only in a part of the area, the above-mentioned initialization period and writing period are The initialization period may be omitted from the hold period. In the frame period, there are an initialization period Ta for black display, an initialization period Tb for white display, and a writing period The order in which the initialization period Ta and the retention period Td appear is shown in Fig. The order of the above may be reversed. Also, in FIG. 16(B), the image is displayed only in a part of the area. When displaying data, if the initialization period is omitted, the write period Tc and the hold period Td will appear. The scanning order is shown in the figure. By omitting the initialization period or reducing the number of initializations, This reduces the number of times, and the power consumption of the scanning line driver circuit can be reduced.

[0189] When an image is displayed only in pixels of a part of the area, the area A selection signal in which voltage pulses are shifted in sequence only to the scanning lines of the pixels in the image is input, and The other scan lines have no pulse, i.e., a selection signal with a flat voltage. Then, during the one line period in which a pulse appears in the selection signal, A video signal having image information is input only to the signal line of the pixel of the inputs a video signal that does not contribute to the display of an image.

[0190] Even when an image is displayed in a partial area, the pixel electrode 710 It is desirable to apply the voltage of the video signal to the pixel multiple times. During the period given to the scan line, a video signal is input to the pixels of the line having the scan line. This series of actions, including pushing, is performed multiple times.

[0191] In addition, the display element 705 used in the electronic paper has a high memory property, so it does not need to be initialized. In this case, in pixels where the gray level does not change over consecutive frame periods, a voltage is applied to the display element. For example, as shown in Figure 15(A), a black circle on a white background can be used. After displaying the image with the black circle, the position of the black circle changes to that of the image in Figure 15(A), as shown in Figure 15(B). When an image different from the image shown in FIG. 1 is displayed, the gradation displayed by the display element 705 is White to white, black to white in area B, black to black in area C, white to black in area D In FIG. 17, the voltages applied to the pixel electrodes 710 in the pixels in the regions A to D are 10 shows a timing chart of the voltage of the selection signal input to each scanning line.

[0192] In the area A, the gradation does not change even when the image is switched, so the common voltage V Since the common voltage Vcom is also applied to the counter electrode 711, The display element in area A does not change gradation and continues to display white. In area B, the image is switched. When the pixel electrode 710 is turned on, the gray level changes from black to white, and a voltage −Vp is applied to the pixel electrode 710. In area C, the display element in area B displays black, and the image changes without changing gradation. Since there is no change, the common voltage Vcom is applied to the pixel electrode 710. Since the voltage is also applied between the counter electrodes 711, the display element in the region C continues to operate without changing the gray scale. In area D, the gradation changes from white to black when the image changes, so the image A voltage Vp is applied to the element electrode 710. Therefore, the display elements in region D display white.

[0193] In this way, in pixels where the gray level does not change over successive frame periods, When no voltage is applied, the power consumption of the signal line driver circuit can be reduced.

[0194] This embodiment mode can be implemented in combination with the above embodiment modes.

[0195] (Embodiment 9) In this embodiment mode, a configuration of a signal line driver circuit using n-channel transistors will be described. Reveal.

[0196] The signal line driver circuit shown in FIG. 18A includes a shift register 5601 and a sampling circuit The sampling circuit 5602 includes a plurality of switching circuits 5602_1 5602_1 to 5602_N (N is a natural number). are each a plurality of n-channel transistors 5603_1 to 5603_k (k is a natural number). It has.

[0197] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. Note that either the source electrode or the drain electrode of the transistor is connected to the first The other terminal will be referred to as the first terminal.

[0198] The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The wirings 5604_1 to 5604_k are connected to the video signals. The second terminals of the transistors 5603_1 to 5603_k are connected to the signal line S1. The gate electrodes of the transistors 5603_1 to 5603_k are connected to the It is connected to the line 5605_1.

[0199] The shift register 5601 sequentially supplies higher level voltages to the wirings 5605_1 to 5605_N. (H level), and the switching circuits 5602_1 to 560 It has the function of selecting 2_N in order.

[0200] The switching circuit 5602_1 is a switch for transistors 5603_1 to 5603_N. By this, the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are in a conductive state (first terminal The function of controlling the conduction between the first terminal and the second terminal, that is, the function of controlling the conduction between the first terminal and the second terminal of the wiring 5604_1 to 5604_k. The control circuit has a function of controlling whether or not the voltage is supplied to the signal lines S1 to Sk.

[0201] Next, the operation of the signal line driver circuit of FIG. 18(A) will be explained with reference to the timing chart of FIG. 18(B). 18B, the shift register 5601 is connected to the wiring 5605. Timing signals Sout_1 to Sout_N input to input terminals 1 to 5605_N, respectively; Video signals Vdata_1 to Vd input to wirings 5604_1 to 5604_k, respectively The timing chart of ata_k is shown as an example.

[0202] One operation period of the signal line driver circuit corresponds to one line period in the display device. 8(B) shows an example in which one line period is divided into periods T1 to TN. T1 to TN are periods for writing a video signal to one pixel belonging to a selected row. is.

[0203] During the period T1 to the period TN, the shift register 5601 outputs a timing signal of H level. For example, in the period T1, the shift The register 5601 outputs a high-level signal to the wiring 5605_1. The transistors 5603_1 to 5603_k included in the switching circuit 5602_1 are turned on. Then, the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are brought into a conductive state. Then, Data(S1) to Data(Sk) are input to the wiring 5604_1 to 5604_k. Data(S1) to Data(Sk) are respectively connected to transistors 5603_1 to 5603_5. 603_k, writing is performed on the pixels in the first to kth columns among the pixels belonging to the selected row. In this way, in the periods T1 to TN, pixels belonging to the selected row are sequentially shifted by k columns. The video signal is written in the order.

[0204] As described above, the video signal is written to the pixels in multiple columns. This reduces the number of connections to external circuits such as controllers. In addition, the video signal is written to the pixels in multiple columns, Therefore, the write time can be extended, and insufficient writing of the video signal can be prevented. can be done.

[0205] Next, one mode of a shift register used in a signal line driver circuit will be described with reference to FIGS. 19 and 20. I will explain.

[0206] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( The first pulse output circuit 10_1 has a first pulse width (N≧3, a natural number) (see FIG. 19A). To the N-th pulse output circuits 10_N, a first clock signal CK1 is supplied from a first wiring 11. A second clock signal CK2 is transmitted from the second wiring 12, and a third clock signal CK3 is transmitted from the third wiring 13. CK3, and a fourth clock signal CK4 is supplied from the fourth wiring 14. In the output circuit 10_1, a start pulse SP1 (first start pulse) is input from the fifth wiring 15. In addition, the n-th pulse output circuit 10_n (n is 2≦n≦ N is a natural number), the signal from the previous stage pulse output circuit (previous stage signal OUT(n-1) In the first pulse output circuit 10_1, a two-stage A signal from the third pulse output circuit 10_3 at the subsequent stage is input. In the nth pulse output circuit 10_n, the (n+2)th pulse output circuit 10_(n A signal from the next stage (called the next stage signal OUT(n+2)) is input. From the pulse output circuit, a signal is output to the next stage and / or the next stage before the pulse output circuit. The first output signal (OUT(1)(SR) to OUT(N)) is electrically connected to another wiring, etc. The second output signals (OUT(1) to OUT(N)) are output. As shown in the figure, the last two stages of the shift register receive the next stage signal OUT(n+2). Therefore, for example, the second start pulse SP2 and the third start pulse SP3 are separately generated. The configuration may be such that the signal SP3 is input to each of the devices.

[0207] The clock signal (CK) alternates between H level and L level (low level voltage) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal ( CK4) are sequentially delayed by 1 / 4 cycle. The fourth clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit. conduct.

[0208] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0209] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 19B, the input terminal 25, the first output terminal 26, and the second output terminal 27 are provided. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0210] Next, an example of a specific circuit configuration of the pulse output circuit is shown in FIG.

[0211] Each pulse output circuit has a first transistor 31 to a thirteenth transistor 43. (See FIG. 20(A)). In addition, the first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a first high power supply potential VDD is supplied. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is sent from the power supply line 53 to the first transistor 31 to the thirteenth transistor 43. Here, the relationship between the levels of the power supply potentials of the power supply lines in FIG. 20(A) is as follows: The first power supply potential VDD>the second power supply potential VCC>the third power supply potential VSS. The first clock signal (CK1) to the fourth clock signal (CK4) go high at regular intervals. It is a signal that alternates between high and low levels, but when it is high it is VDD and when it is low it is VSS. It should be noted that the potential VDD of the power supply line 51 is set higher than the potential VCC of the power supply line 52. This allows the potential applied to the gate electrode of the transistor to be lowered without affecting its operation. This reduces the shift in the threshold voltage of the transistor and suppresses degradation. can be done.

[0212] In FIG. 20A, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; is electrically connected to the fourth input terminal 24. The second transistor 32 is is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. The gate electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 35. The third transistor 33 has a first terminal electrically connected to the first input terminal 21, The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, The second terminal is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 of No. 6 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second Electrically connected to the gate electrode of the transistor 32 and the gate electrode of the fourth transistor 34 The seventh transistor has a gate electrode electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. The gate electrode of the fourth transistor 34 is electrically connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrode is electrically connected to the power supply line 52. The resistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The first terminal of the eleventh transistor 41 is electrically connected to the power supply line 53. the second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the second transistor The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the seventh transistor 37 is electrically connected to the second output terminal 27. The first terminal of the thirteenth transistor 43 is electrically connected to the power supply line 5. 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 37 .

[0213] In FIG. 20A, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 20(A)).

[0214] The timing chart of the shift register having a plurality of pulse output circuits shown in FIG. The above is shown in FIG. 20(B).

[0215] As shown in FIG. 20A, the ninth power supply voltage Vcc is applied to the gate electrode. By providing the transistor 39, the following occurs before and after the bootstrap operation: The advantages are as follows:

[0216] If the ninth transistor 39 having the second potential VCC applied to its gate electrode is not present, the boot When the potential at node A rises due to the strapping operation, the second terminal of the first transistor 31 The potential of the source electrode, which is at VDD, rises and becomes higher than the first power supply potential VDD. The source electrode of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate electrode and the source electrode are A large bias voltage is applied between the gate and drain electrodes, which causes a large stress. Therefore, the gate electrode is supplied with a second power supply potential VC By providing a ninth transistor 39 to which C is applied, bootstrap operation Although the potential of the node A rises due to this, the potential of the second terminal of the first transistor 31 does not rise. In other words, by providing the ninth transistor 39, As a result, a negative bias voltage is applied between the gate electrode and the source electrode of the first transistor 31. Therefore, by using the circuit configuration of this embodiment, , a negative bias voltage applied between the gate electrode and the source electrode of the first transistor 31 Since the resistance can be reduced, deterioration of the first transistor 31 due to stress can be suppressed. Cut.

[0217] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate electrode of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a plurality of pulse output circuits may be provided. In the case of a shift register, the signal line driver circuit has more stages than the scanning line driver circuit. The transistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0218] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-state current of the transistor is reduced, and the on-state current and the electric field This can increase the effective mobility and reduce the degree of degradation, making it possible to In addition, a transistor using an oxide semiconductor can reduce malfunctions within the Compared to transistors using fast silicon, a high potential is applied to the gate electrode. Therefore, the power supply that supplies the second power supply potential VCC is The same operation can be obtained by supplying the first power supply potential VDD to the line, and the power supply potential VDD drawn between the circuits can be Since the number of source lines can be reduced, the circuit can be made smaller.

[0219] The gate electrode of the seventh transistor 37 is connected to the clock signal supplied from the third input terminal 23. A lock signal, supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38 The clock signal to be output is input to the gate electrode of the seventh transistor 37 by the second input terminal 22. the gate electrode of the eighth transistor 38 is connected to the third input terminal 23 The same effect can be achieved by switching the wiring so that the clock signal is supplied by At this time, in the shift register shown in FIG. 20(A), the seventh transistor 37 and eighth transistor 38 are both on, the seventh transistor 37 is off, and the The eighth transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the transistor 38, the second input terminal 22 and the third input terminal The potential drop at node B caused by the potential drop at node 23 causes the seventh transistor 37 due to a decrease in the potential of the gate electrode of the eighth transistor 38 On the other hand, if the shift register shown in FIG. 20(A) is changed to the shift register shown in FIG. 20(B), As in the period, the seventh transistor 37 and the eighth transistor 38 are both in the ON state. Then, the seventh transistor 37 is turned on and the eighth transistor 38 is turned off. By turning off the seventh transistor 37 and the eighth transistor 38, , the potential of the second input terminal 22 and the third input terminal 23 decreases, The potential drop is reduced once by the drop in the potential of the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 is connected to the third input terminal 23. A clock signal is supplied from the second input terminal 22 to the gate electrode of the eighth transistor 38. It is preferable to have a wired connection in which a clock signal is supplied from the node B. This is because the number of times the potential changes can be reduced and noise can also be reduced.

[0220] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0221] This embodiment mode can be implemented in combination with the above embodiment modes.

[0222] (Embodiment 10) In this embodiment, a manufacturing method of a semiconductor display device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using Figure 26.

[0223] In FIG. 21(A), a light-transmitting substrate 400 is made of aluminosilicate glass, Various glass materials used in the electronics industry, such as sodium borosilicate glass and aluminoborosilicate glass A glass substrate can be used. Also, a substrate made of flexible synthetic resin such as plastic can be used. The substrates used generally tend to have low heat resistance, but they are also able to withstand the processing temperatures in the subsequent manufacturing processes. If the substrate can be obtained, it can be used as the substrate 400. Polyesters such as polyethylene terephthalate (PET), polyether sulfonates Polyethylene naphthalate (PEN), Polycarbonate (PC), Poly Ether ether ketone (PEEK), polysulfone (PSF), polyetherimide ( PEI), polyarylate (PAR), polybutylene terephthalate (PBT), poly Acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, Examples of the resin include vinyl acetate and acrylic resin.

[0224] Next, a conductive film is formed on the entire surface of the substrate 400, and then a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gate A gate wiring including an electrode 401, a capacitance wiring 408, and a first terminal 421 are formed. At this time, etching is performed so that a tapered shape is formed at least at the end of the gate electrode 401. do.

[0225] The material of the conductive film may be molybdenum, titanium, chromium, tantalum, tungsten, or neodymium. Metallic materials such as zinc and scandium, alloy materials containing these metallic materials as the main components, or The nitride of the metal can be used in a single layer or a laminated layer. If the metal material can withstand the heat treatment temperature, aluminum and copper may be used. It is also possible to do this.

[0226] For example, a conductive film having a two-layer laminated structure may be formed by laminating a titanium nitride film and a molybdenum film. As for a three-layer laminated structure, a tungsten film or a nitride film is preferable. A tungsten film and an aluminum-silicon alloy film or an aluminum-titanium alloy film It is preferable to form a three-layer structure by laminating a titanium nitride film or a titanium film.

[0227] Next, as shown in FIG. 21(B), the gate electrode 401, the capacitance wiring 408, and the first terminal 4 A gate insulating film 402 is formed on the substrate 21. The gate insulating film 402 is formed by a sputtering method or a PCVD method. The film thickness is set to 50 to 250 nm.

[0228] For example, a silicon oxide film is used as the gate insulating film 402 by sputtering to a thickness of 100 nm. Of course, the gate insulating film 402 is not limited to such a silicon oxide film. Other insulating films such as silicon oxynitride film, silicon nitride film, aluminum oxide film, and tantalum oxide film The insulating film may be formed as a single layer or a laminated structure made of these materials.

[0229] Next, an oxide semiconductor film 403 (In—Ga—Zn—O based non-single crystal oxide film) is formed on the gate insulating film 402. After plasma treatment, an In-Ga-Zn-O system non-single crystal film is formed without exposure to the atmosphere. By forming a crystal film, dust and moisture are prevented from being present at the interface between the gate insulating film 402 and the oxide semiconductor film 403. Here, an 8-inch diameter In, Ga, and Zn containing Oxide semiconductor target (In-Ga-Zn-O system oxide semiconductor target (In2O3 :Ga2O3:ZnO=1:1:1) to adjust the distance between the substrate 400 and the target. 170mm, pressure 0.4Pa, direct current (DC) power supply 0.5kW, oxygen only, argon only, Alternatively, the film is formed under an argon and oxygen atmosphere. When a pulsed direct current (DC) power supply is used, This is preferable because it reduces dust generated by film formation and makes the film thickness distribution uniform. The thickness of the Zn—O-based non-single crystal film is set to 5 nm to 200 nm. A 50 nm thick In-Ga-Zn-O based non-single crystal film is deposited.

[0230] The oxide semiconductor film 403 for forming a channel formation region is formed by using the above-described semiconductor specific An oxide material having such a property may be used.

[0231] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0232] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0233] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0234] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0235] Next, as shown in FIG. 21(C), a second photolithography process is performed to form a resist mask. For example, a mixture of phosphoric acid, acetic acid, and nitric acid is used to form a mask, and then the oxide semiconductor film 403 is etched. Unnecessary portions are removed by wet etching using a solution to form an island-shaped oxide semiconductor film 4 404 is formed so as to overlap the gate electrode 401. The etching is not limited to hot etching, and dry etching may also be used.

[0236] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0237] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0238] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0239] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. TO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0240] In addition, after wet etching, the etching solution is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor film may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0241] The etching conditions (etchant, etchant) are adjusted to suit the material so that it can be processed into the desired shape. Adjust cooking time, temperature, etc. as appropriate.

[0242] Next, as shown in FIG. 22(A), the substrate is heated in an inert gas atmosphere such as nitrogen or a rare gas under a reduced pressure. under an oxygen gas atmosphere or ultra-dry air (CRDS (Cavity Ring Down Laser) When measured using a dew point meter using the spectroscopic method, the moisture content was 20 ppm (equivalent to a dew point of -55°C). ) or less, preferably 1 ppm or less, preferably 10 ppb or less in air) atmosphere The oxide semiconductor film 404 is subjected to heat treatment, whereby an oxide semiconductor film 405 is formed. Specifically, in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.), The temperature range is 400°C or higher and 700°C or lower, preferably 450°C or higher and 650°C or lower. The oxide semiconductor film 404 is subjected to heat treatment, and then heated to a temperature higher than or equal to room temperature for 100 The oxide semiconductor film 404 is subjected to heat treatment in the above atmosphere. As a result, moisture, hydrogen, and a hydroxy group contained in the oxide semiconductor film 404 are released. Therefore, a thin film transistor in which a channel formation region is formed using the oxide semiconductor film 405 The MOSFET can achieve a high on-state current.

[0243] Heat treatment is carried out using an electric furnace, a GRTA (Gas Rapture Treatment) method using heated gas, etc. id Thermal Anneal (LRTA) method or lamp light Rapid Thermal Annealing (RTA) and other instantaneous heating methods can be used. For example, when heat treatment is performed using an electric furnace, the temperature rise rate can be set to 0.1°C / min or more. 20℃ / min or less, and the temperature drop characteristic can be 0.1℃ / min to 15℃ / min. preferable.

[0244] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0245] After the heat treatment, the island-shaped oxide semiconductor film 405 may be partly or entirely crystallized. stomach.

[0246] After the heat treatment on the oxide semiconductor film 405, the oxide semiconductor film By performing heat treatment on the oxide semiconductor film 405, impurities such as moisture contained in the oxide semiconductor film 405 are removed. Then, the oxide semiconductor film 405 is removed by heat treatment in an oxygen atmosphere. By making the temperature of the heat treatment in an oxygen atmosphere excessive, the resistance can be increased. , the temperature at which metals with low melting points such as Zn that make up the oxide semiconductor do not easily vaporize, e.g., 1 The temperature is 00°C or higher and lower than 350°C, preferably 150°C or higher and lower than 250°C. It is preferable that the oxygen gas used in the heat treatment below does not contain moisture, hydrogen, or the like. Alternatively, the purity of the oxygen gas introduced into the heat treatment device is preferably 6N (99.9999%) or more. Preferably 7N (99.99999%) or more (i.e., impurity concentration in oxygen is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0247] In addition, the cross-sectional view within the range of the dashed line C1-C2 in FIG. 22(A) and the cross-sectional view within the range of the dashed line D1-D2 are The plan view is a cross-sectional view taken along dashed line C1-C2 in the plan view shown in FIG. 24 and a cross-sectional view taken along dashed line D1-D2 in the plan view shown in FIG. This corresponds to a cross-sectional view of the

[0248] Next, as shown in FIG. 22B, a conductive film 4 made of a metal material is formed on the oxide semiconductor film 405. The conductive film 406 is formed by sputtering or vacuum evaporation. , chromium, tantalum, titanium, manganese, magnesium, molybdenum, tungsten, An element selected from zinc, beryllium, and yttrium, or one or more of the above elements An alloy containing multiple components can be used. When the heat treatment is performed, it is preferable that the conductive film 406 has heat resistance to the heat treatment. Aluminum alone has problems such as poor heat resistance and susceptibility to corrosion, so conductive When heat treatment is performed after the formation of the film 406, the conductive film 40 is formed by combining with a heat-resistant conductive material. 6. Heat-resistant conductive materials that can be combined with aluminum include titanium, tantalum, and Elements selected from the group consisting of zinc, tungsten, molybdenum, chromium, neodymium, and scandium, or alloys containing one or more of the above elements, or nitrogen containing the above elements as components Compounds such as benzophenone are preferred.

[0249] Next, as shown in FIG. 22(C), a third photolithography process is performed to form a resist mask. Then, unnecessary portions are removed by etching to form a source electrode 407a or a drain electrode The electrode 407b and the second terminal 420 are formed by wet etching. For example, the conductive film 406 is formed by etching or dry etching. Or, when an aluminum alloy film is used, a wet etching process using a solution of phosphoric acid, acetic acid, and nitric acid is used. Wet etching using ammonia hydrogen peroxide can also be performed. The conductive film 406 is etched by the etching to form the source electrode 407a or the drain electrode 407b. It may be formed.

[0250] In this etching step, the exposed region of the oxide semiconductor film 405 is also partly etched. In this case, the oxide semiconductor between the source electrode 407a or the drain electrode 407b The body membrane 409 is a thin region.

[0251] In this third photolithography step, the source electrode 407a or the drain electrode 40 The second terminal 420 made of the same material as 7b is left at the terminal portion. The source wiring (including the source electrode 407a or the drain electrode 407b) is electrically connected to the It continues.

[0252] Also, a resist having regions of multiple (for example, two types) thicknesses formed by a multi-tone mask By using a mask, the number of resist masks can be reduced, which simplifies the process and reduces costs. It is possible to achieve this.

[0253] Next, the resist mask is removed, and the substrate is etched under a reduced pressure atmosphere or an inert gas atmosphere such as nitrogen or a rare gas. , oxygen gas atmosphere, or ultra-dry air (CRDS (Cavity Ring Down Laser Dispersion) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). In an atmosphere of 1 ppm or less, preferably 10 ppb or less (air), The oxide semiconductor film 409 is subjected to heat treatment again, and the moisture and water contained in the oxide semiconductor film 409 are removed. The source electrode 407a or the drain electrode 407b may be formed by removing a hydroxyl group. The heat treatment after forming 407b is performed to improve the resistance of the source electrode 407a or the drain electrode 407b. In consideration of thermal properties, a heat treatment is performed before forming the source electrode 407a or the drain electrode 407b. Specifically, it is preferable to carry out the treatment at a temperature lower than that of the conventional treatment. It is preferable to carry out the treatment at a temperature in the range of 400°C or more and 600°C or less.

[0254] In addition, the cross-sectional view within the range of the dashed line C1-C2 in FIG. 22(C) and the cross-sectional view within the range of the dashed line D1-D2 are The plan view is a cross-sectional view taken along dashed line C1-C2 in the plan view shown in FIG. 25 and a cross-sectional view taken along dashed line D1-D2 in the plan view shown in FIG. This corresponds to a cross-sectional view of the

[0255] Next, as shown in FIG. 23A, the gate insulating film 402, the oxide semiconductor film 409, the source An oxide insulating film 411 is formed to cover the electrode 407a or the drain electrode 407b. The insulating film 411 is a silicon oxynitride film formed by the PCVD method. The exposed region of the oxide semiconductor film 409 and the oxide insulating film 408 are formed between the drain electrodes 407b. The silicon oxynitride film 411 is provided in contact with the silicon oxynitride film, and oxygen is supplied to the silicon oxynitride film 411. The region of the oxide semiconductor film 409 in contact with the oxide insulating film 411 becomes highly resistive (the carrier concentration decreases). , preferably 1 x 10 18 / cm 3 (less than 1000 Ω) and an oxide having a highly resistive channel forming region. A compound semiconductor film 412 can be formed.

[0256] Next, after the oxide insulating film 411 is formed, heat treatment may be performed. In an atmosphere or a nitrogen atmosphere, the temperature is 350°C or higher and 650°C or lower, preferably 400°C or higher. The heat treatment is preferably performed at a temperature in the range of from 600° C. to 600° C. When the heat treatment is performed, the oxide semiconductor film 412 The oxide insulating film 411 is heated, and the oxide semiconductor film 412 By increasing the resistance of the There are no particular limitations on the type of heat treatment as long as it is performed after the oxide insulating film 411 is formed. Other processes, such as heat treatment during resin film formation and heat treatment for reducing the resistance of transparent conductive films, By combining this with the theory, it can be done without increasing the number of steps.

[0257] Through the above steps, the thin film transistor 413 can be manufactured.

[0258] Next, a fourth photolithography step is performed to form a resist mask, and an oxide insulating film 4 The contact holes are formed by etching the gate insulating film 402 and the drain electrode. A part of the pole 407b, a part of the first terminal 421, and a part of the second terminal 420 are exposed. After removing the resist mask, a transparent conductive film is formed. , indium oxide (In2O3) and indium tin oxide (In2O3-SnO2, ITO The electrode made of such a material is formed by sputtering or vacuum deposition. Etching is performed using a hydrochloric acid solution. However, etching ITO in particular leaves residue. Therefore, indium oxide zinc oxide alloy (In2 O3-ZnO) may also be used. In addition, a heat treatment is performed to reduce the resistance of the transparent conductive film. In this case, the resistance of the oxide semiconductor film 412 is increased, thereby improving the electrical characteristics of the transistor. This can also serve as a heat treatment to reduce variations in electrical characteristics.

[0259] Next, a fifth photolithography step is performed to form a resist mask, and then etching is performed. The unnecessary portion is removed to form the pixel electrode 414 connected to the drain electrode 407b and the first terminal The transparent conductive film 415 connected to the first terminal 421 and the transparent conductive film 420 connected to the second terminal 420 are 16 and form.

[0260] The transparent conductive films 415 and 416 serve as electrodes or wiring used for connection with the FPC. The transparent conductive film 415 formed on the terminal 421 is a contact that functions as an input terminal of the gate wiring. The transparent conductive film 416 formed on the second terminal 420 serves as a terminal electrode for source wiring. This is a terminal electrode for connection that functions as an input terminal for a line.

[0261] In this fifth photolithography step, the gate insulating film 402 and the oxide insulating film 41 A storage capacitor is formed by the capacitor wiring 408 and the pixel electrode 414, with the dielectric 1 serving as the dielectric.

[0262] The cross-sectional view at the stage where the resist mask is removed is shown in FIG. The cross-sectional view within the range of the dashed line C1-C2 and the cross-sectional view within the range of the dashed line D1-D2 are shown in FIG. It corresponds to the cross-sectional view taken along dashed lines C1-C2 and D1-D2 in the plan view. .

[0263] In this way, five photolithography processes were performed using five photomasks to create the bottom A gate-type staggered thin film transistor 413 and a storage capacitor can be completed. These are then arranged in a matrix to correspond to the individual pixels to form the pixel section. It can be used as one of the substrates for manufacturing an active matrix display device. For convenience, this type of substrate is referred to as an active matrix substrate in this specification.

[0264] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The opposing substrate is fixed.

[0265] In addition, the capacitance wiring is not provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel, the oxide insulating film, and the gate A storage capacitor may be formed by stacking the layers with an insulating film interposed therebetween.

[0266] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0267] When a light-emitting display device is manufactured, a partition made of an organic resin film is provided between each of the organic light-emitting elements. In this case, the organic resin film is subjected to a heat treatment, so that the heat treatment of the organic resin film In addition, the resistance of the oxide semiconductor film 412 is increased, thereby improving the electrical characteristics of the transistor and This can also serve as a heat treatment to reduce variations in thermal properties.

[0268] By forming the thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, the reduction of impurities such as moisture, hydrogen, and OH by heat treatment makes it possible to To increase the purity of the semiconductor film, thin film transistors with good electrical characteristics and high reliability are produced. A semiconductor display device can be manufactured.

[0269] Since the semiconductor film in the channel formation region is a high resistance region, the electrical characteristics of the thin film transistor are This stabilizes the device and prevents an increase in off-state current. This results in good electrical characteristics and reliability. It is possible to provide a semiconductor display device having thin film transistors with excellent performance.

[0270] This embodiment mode can be implemented in combination with the above embodiment modes.

[0271] (Embodiment 11) In this embodiment, a structure of a liquid crystal display device according to one embodiment of the present invention will be described.

[0272] FIG. 27 illustrates an example of a cross-sectional view of a liquid crystal display device according to one embodiment of the present invention. The thin film transistor 1401 has a gate electrode 1402 formed on an insulating surface and a gate electrode 1403. A gate insulating film 1403 is formed to cover the electrode 1402, and the gate insulating film 1403 is The oxide semiconductor film 1404 is sandwiched between the gate electrode 1402 and the oxide semiconductor film 1404 so as to overlap with the gate electrode 1402. A pair of semiconductor layers, each functioning as a source region or a drain region, formed on the semiconductor layer 1404 The pair of semiconductor films 1405 and the source electrode or the drain electrode formed on the semiconductor film 1405 The semiconductor device has a pair of conductive films 1406 and an oxide insulating film 1407 which function as gate electrodes. The oxide insulating film 1407 is in contact with at least the oxide semiconductor film 1404 and is 402, a gate insulating film 1403, an oxide semiconductor film 1404, and a pair of semiconductor films 140 5 and the pair of conductive films 1406.

[0273] An insulating film 1408 is formed over the oxide insulating film 1407. An opening is provided in a part of the insulating film 1408, and the conductive film 1406 is A pixel electrode 1410 is formed so as to contact one of them.

[0274] Moreover, on the insulating film 1408, a spacer 141 for controlling the cell gap of the liquid crystal element is formed. The spacer 1417 is formed by etching the insulating film into a desired shape. However, by dispersing filler on the insulating film 1408, the cell gap can be reduced. The loop may be controlled.

[0275] An alignment film 1411 is formed on the pixel electrode 1410. For example, the pixel electrode 14 can be formed by rubbing the insulating film. A counter electrode 1413 is provided at a position facing the pixel 10. An alignment film 1414 is formed on the side closer to the electrode 1410. The liquid crystal 1415 is disposed in the area surrounded by the sealant 1416 between the counter electrode 1413 and the liquid crystal 1415. The sealing material 1416 may contain filler.

[0276] The pixel electrode 1410 and the counter electrode 1413 are made of, for example, indium tin oxide (I TSO), indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide ( Transparent conductive materials such as zinc oxide doped with gallium (IZO) and zinc oxide doped with gallium (GZO) can be used. In this embodiment mode, the pixel electrode 1410 and the counter electrode 1413 are provided with a light-transmitting layer. An example of fabricating a transmissive liquid crystal element using a conductive film will be shown, but the present invention is not limited to this configuration. The liquid crystal display device according to one embodiment of the present invention may be a semi-transmissive type or a reflective type.

[0277] Color filters and shielding films (black matrices) to prevent disclination Any of these may be provided in the liquid crystal display device shown in FIG.

[0278] In this embodiment, the liquid crystal display device is a TN (Twisted Nematic) ) type, but VA (Vertical Alignment) type, OCB (opti cally compensated Birefringence) type, IPS(In The thin film of the present invention can also be used in other liquid crystal display devices such as a two-plane switching type. A transistor can be used.

[0279] The liquid crystal display device according to one aspect of the present invention has high reliability.

[0280] This embodiment mode can be freely combined with other embodiment modes.

[0281] (Embodiment 12) In this embodiment, a thin film transistor according to one embodiment of the present invention is used in a pixel of a light-emitting device. In this embodiment, a transistor for driving a light-emitting element is The cross-sectional structure of a pixel in the case of n-type will be described with reference to FIG. The case where the first electrode is a cathode and the second electrode is an anode will be explained. The second electrode may be a cathode.

[0282] In FIG. 28(A), a transistor 6031 is an n-type transistor, and light emitted from a light emitting element 6033 is A cross-sectional view of the pixel when taken out from the first electrode 6034 side is shown. The insulating film 6037 is covered with a partition wall 6038 having an opening. The first electrode 6034 is partially exposed at the opening of the partition wall 6038. In the opening, a first electrode 6034, an electroluminescent layer 6035, and a second electrode 6036 are arranged in this order. are stacked on top of each other.

[0283] The first electrode 6034 is formed of a material or a film thickness that transmits light and has a small work function. The conductive material can be formed of a metal, an alloy, an electrically conductive compound, or a mixture thereof. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr metals, alloys containing these (Mg:Ag, Al:Li, Mg:In, etc.), and their compounds In addition to compounds (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er can also be used. When an electron injection layer is provided, other conductive layers such as aluminum may be used. The first electrode 6034 is formed to a thickness that allows light to pass through (preferably 5 Furthermore, the conductive layer is formed to a thickness of about 1000 nm to 3000 nm. A conductive layer having light-transmitting properties is formed by using a conductive oxide material so as to be in contact with the upper or lower surface of the substrate. In this case, the sheet resistance of the first electrode 6034 may be reduced. Oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-added Only conductive layers using other transparent oxide conductive materials such as zinc oxide (GZO) are used. It is also possible to use an indium-based film containing ITO and silicon oxide for the first electrode 6034. Indium tin oxide (ITSO) and silicon oxide are also used. A mixture of up to 20% zinc oxide (ZnO) may also be used. When used, it is desirable to provide an electron injection layer in the electroluminescent layer 6035 .

[0284] The second electrode 6036 is formed of a material and a film thickness that reflects or blocks light. It is made of a material suitable for use as an anode, such as titanium nitride, zirconium nitride, One or more of titanium, tungsten, nickel, platinum, chromium, silver, aluminum, etc. In addition to the single layer film, titanium nitride and aluminum-based films are also available. The three-layer structure of the film, the film mainly composed of aluminum, and the titanium nitride film is formed as the second electrode 6036. It can be used for.

[0285] The electroluminescent layer 6035 is composed of one or more layers. In this case, these layers are classified into a hole injection layer, a hole transport layer, a light emitting layer, and a It can be classified into an electron transport layer, an electron injection layer, etc. The electroluminescent layer 6035 is a light-emitting layer as well as When the layer has any one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, From the first electrode 6034, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed in this order. The boundaries between the layers do not necessarily need to be clear, and the layers that make up each other may be stacked one on top of the other. In some cases, the materials are mixed together and the interface is unclear. Organic materials can be used. It is possible to use any material of molecular type. The number of repeats (degree of polymerization) corresponds to a low polymer of about 2 to 20. The distinction between these is not necessarily strict, and these are the types in which hole transport properties (hole mobility) are particularly important. For convenience, the hole injection layer is the layer that contacts the anode, and the The layer in contact with the hole injection layer is called the hole transport layer to distinguish it from the electron transport layer and electron injection layer. Similarly, the layer in contact with the cathode is called the electron injection layer, and the layer in contact with the electron injection layer is called the electron transport layer. The light-emitting layer may also function as an electron transport layer, and is therefore also called a light-emitting electron transport layer.

[0286] In the case of the pixel shown in FIG. 28(A), light emitted from the light emitting element 6033 is indicated by a white arrow. As shown, it can be taken out from the first electrode 6034 side.

[0287] Next, in FIG. 28(B), a transistor 6041 is an n-type transistor, and a light emitting element 6043 emits light. 10 is a cross-sectional view of a pixel in the case where light is extracted from the second electrode 6046 side. 41 is covered with an insulating film 6047, and a partition wall 604 having an opening is formed on the insulating film 6047. 8 is formed. The first electrode 6044 is partially exposed at the opening of the partition wall 6048. In the opening, a first electrode 6044, an electroluminescent layer 6045, and a second electrode 6046 are disposed. are stacked in order.

[0288] The first electrode 6044 is formed of a material and a film thickness that reflects or blocks light and has a workability. Formation of low-function metals, alloys, electrically conductive compounds, and mixtures thereof Specifically, alkali metals such as Li and Cs, and aluminum metals such as Mg, Ca, and Sr can be used. Potassium earth metals and alloys containing them (Mg:Ag, Al:Li, Mg:In, etc.), and In addition to these compounds (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er When an electron injection layer is provided, other conductive layers such as aluminum can be used. It is also possible to use

[0289] The second electrode 6046 is formed of a material or a film thickness that transmits light and also serves as an anode. The substrate is made of a material suitable for use. For example, indium tin oxide (ITO), zinc oxide ( ZnO), indium zinc oxide (IZO), gallium-doped zinc oxide (GZO), etc. Other transparent conductive oxide materials can be used for the second electrode 6046. Indium tin oxide containing TO and silicon oxide (hereinafter referred to as ITSO), and silicon oxide containing The second layer is made of soldered indium oxide mixed with 2 to 20% zinc oxide (ZnO). It may be used for the electrode 6046. In addition to the above-mentioned transparent oxide conductive materials, for example, titanium nitride , zirconium nitride, titanium, tungsten, nickel, platinum, chromium, silver, aluminum In addition to single layer films consisting of one or more of titanium nitride and aluminum, a three-layer structure consisting of a titanium nitride film, a film mainly composed of aluminum, and a titanium nitride film, etc. However, a material other than the conductive transparent oxide material can be used for the second electrode 6046. When used, the second electrode is formed to a thickness that allows light to pass through (preferably, about 5 nm to 30 nm). Form pole 6046.

[0290] The electroluminescent layer 6045 can be formed in the same manner as the electroluminescent layer 6035 in FIG. 28(A). do.

[0291] In the case of the pixel shown in FIG. 28(B), light emitted from the light emitting element 6043 is indicated by a white arrow. As shown, it can be taken out from the second electrode 6046 side.

[0292] Next, in FIG. 28(C), a transistor 6051 is an n-type transistor, and a light emitting element 6053 emits light. 6 is a cross-sectional view of a pixel when light is extracted from the first electrode 6054 side and the second electrode 6056 side. The transistor 6051 is covered with an insulating film 6057. A partition wall 6058 having an opening is formed. The first electrode The first electrode 6054 is partially exposed through the opening, and the electroluminescent layer 60 55 and a second electrode 6056 are laminated in this order.

[0293] The first electrode 6054 can be formed in the same manner as the first electrode 6034 in FIG. 28(A). The second electrode 6056 is formed in the same manner as the second electrode 6046 in FIG. The electroluminescent layer 6055 can be formed in the same manner as the electroluminescent layer 6035 in FIG. It is possible.

[0294] In the case of the pixel shown in FIG. 28(C), light emitted from the light emitting element 6053 is indicated by a white arrow. As shown in FIG. 6, the light can be extracted from the first electrode 6054 side and the second electrode 6056 side. .

[0295] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0296] (Embodiment 13) In this embodiment, a structure of a liquid crystal display device according to one embodiment of the present invention will be described.

[0297] 29 is a perspective view showing an example of the structure of a liquid crystal display device of the present invention. The display device includes a liquid crystal panel 1601 having a liquid crystal element formed between a pair of substrates, and a first diffusion plate 1602. 602, a prism sheet 1603, a second diffusion plate 1604, a light guide plate 1605, and a reflector. It has a reflector 1606 , a light source 1607 , and a circuit board 1608 .

[0298] A liquid crystal panel 1601, a first diffusion plate 1602, a prism sheet 1603, and a second diffusion plate 1604 are included. The scattering plate 1604, the light guide plate 1605, and the reflector 1606 are stacked in this order. 607 is provided at the end of the light guide plate 1605, and is a light source diffused inside the light guide plate 1605. The light from 1607 passes through the first diffusion plate 1602, the prism sheet 1603 and the second diffusion plate The liquid crystal panel 1601 is uniformly illuminated by the light 1604 .

[0299] In this embodiment, a first diffusion plate 1602 and a second diffusion plate 1604 are used. However, the number of the diffusion plates is not limited to this, and may be one or three or more. The scattering plate may be provided between the light guide plate 1605 and the liquid crystal panel 1601. Even if the diffusion plate is provided only on the side closer to the liquid crystal panel 1601 than the reflective sheet 1603, The diffusing plate is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603. It's okay to have it.

[0300] The cross section of the prism sheet 1603 is not limited to the sawtooth shape shown in FIG. It is sufficient if the shape can condense the light from the plate 1605 onto the liquid crystal panel 1601 side.

[0301] The circuit board 1608 includes a circuit for generating various signals to be input to the liquid crystal panel 1601, In FIG. 29, the circuit board 16 is provided with circuits for processing these signals. 08 and the LCD panel 1601 are connected by FPC (Flexible Printed Circuit) The above circuit is connected via a COG (Chip On Ground) 1609. The liquid crystal panel 1601 may be connected using the glass method, or one of the above circuits may be connected using the glass method. Even if the part is connected to FPC1609 using the COF (Chip On Film) method, good.

[0302] In FIG. 29, a control circuit for controlling the driving of a light source 1607 is provided on a circuit board 1608. The control circuit and the light source 1607 are connected via an FPC 1610. However, the control circuit may be formed on the liquid crystal panel 1601. In this case, the liquid crystal panel 1601 and the light source 1607 are connected by an FPC or the like. do.

[0303] 29 shows an edge-light type light source in which a light source 1607 is arranged at the edge of a liquid crystal panel 1601. In the liquid crystal display device of the present invention, the light source 1607 is located directly below the liquid crystal panel 1601. It may also be a direct type that is placed in the

[0304] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0305] By using a semiconductor display device according to one embodiment of the present invention, highly reliable electronic devices with low power consumption can be realized. It is possible to provide portable devices that are difficult to receive power supply all the time. In the case of a slave device, by adding a semiconductor display device according to one embodiment of the present invention to its components, This also has the advantage of extending the continuous usage time.

[0306] In addition, in the semiconductor display device of the present invention, the temperature of the heat treatment in the manufacturing process can be suppressed. Therefore, it is made of flexible synthetic resin such as plastic, which has lower heat resistance than glass. It is possible to fabricate thin film transistors with excellent characteristics and high reliability even on substrates with Therefore, by using the manufacturing method according to one embodiment of the present invention, it is possible to obtain a highly reliable It is possible to provide a semiconductor display device that is low in power consumption, lightweight, and flexible. As a plastic substrate, polyester, typified by polyethylene terephthalate (PET), Polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate Polycarbonate (PC), Polyetheretherketone (PEEK), Polysulfone (PSF) , polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate Polyvinyl chloride (PBT), polyimide, acrylonitrile butadiene styrene resin Examples of the resin include polyethylene, polypropylene, polyvinyl acetate, and acrylic resin.

[0307] The semiconductor display device according to one aspect of the present invention is applicable to a display device, a notebook personal computer, Image playback devices equipped with recording media (typically DVD: Digital Versatile (Devices with a display that can play recording media such as eDiscs and display the images) In addition, the semiconductor display device according to one embodiment of the present invention can be used in Electronic devices that can be used include mobile phones, portable game consoles, personal digital assistants, e-books, and video cameras. Camera, digital still camera, goggle-type display (head-mounted display) , navigation systems, sound reproduction devices (car audio, digital audio players) Copiers, fax machines, printers, printer-combined machines, automated teller machines Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 30. .

[0308] FIG. 30A shows an electronic book having a housing 7001, a display portion 7002, and the like. The semiconductor display device according to this embodiment can be used in the display portion 7002. By using a semiconductor display device according to one embodiment of the present invention, highly reliable electronic devices with low power consumption can be realized. Furthermore, by using a flexible substrate, the display unit 700 Since the semiconductor display device used in the device 2 can be made flexible, it is highly reliable and has low The power consumption allows us to provide flexible, lightweight, and easy-to-use e-books.

[0309] FIG. 30B shows a display device, which includes a housing 7011, a display portion 7012, a support base 7013, and the like. The semiconductor display device according to one embodiment of the present invention can be used in the display portion 7012. By using a semiconductor display device according to one embodiment of the present invention for the display portion 7012, the reliability is high. It is possible to provide a display device with low power consumption. This includes all display devices for displaying information, such as for computers, TV broadcast reception, and advertising displays.

[0310] FIG. 30C shows a display device, which includes a housing 7021, a display portion 7022, and the like. The semiconductor display device according to this embodiment can be used in the display portion 7022. By using a semiconductor display device according to one embodiment of the present invention, a highly reliable display device with low power consumption can be achieved. In addition, by using a flexible substrate, the display portion 702 2 and other signal processing circuits can be made flexible. This allows for the realization of a highly reliable, low-power consumption, flexible, and lightweight display device. Therefore, as shown in Figure 30(C), the display device can be used by fixing it to a fabric or the like. This significantly widens the range of applications for semiconductor display devices.

[0311] FIG. 30D shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The semiconductor display device according to one embodiment of the present invention includes a display portion 7033, a display area 7038, and the like. It can be used for the display portion 7034. The display portion 7033 and the display portion 7034 can be used as one embodiment of the present invention. By using the semiconductor display device, a highly reliable and low power consumption portable game machine can be realized. The portable game machine shown in FIG. 30(D) has two display units 7 033 and a display unit 7034, the number of display units that a portable game machine has is Not limited to.

[0312] FIG. 30(E) shows a mobile phone, which includes a housing 7041, a display unit 7042, an audio input unit 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The semiconductor display device according to one embodiment of the present invention can be used for the display portion 7042. By using a semiconductor display device according to one embodiment of the present invention in the display device, high reliability and low power consumption can be achieved. Power mobile phone can be provided.

[0313] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0314] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 42 transistors 43 Transistor 51 Power line 52 Power line 53 Power line 100 pixel unit 101 Scanning line driving circuit 102 Signal line driver circuit 103 Decoder 104 Area 105 each pixel 106 NOR circuit 201 Thin-film transistor 202 Substrate 203 Gate electrode 204 Gate insulating film 205 Oxide semiconductor film 206 Source electrode 207 Drain electrode 208 Oxide insulating film 209 Conductive Film 210 insulating film 211 Thin-film transistor 212 Substrate 213 Gate electrode 214 Gate insulating film 215 Oxide semiconductor film 216 Source electrode 217 Drain electrode 218 Oxide insulating film 219 Conductive Film 220 insulating film 221 Thin-film transistor 222 Substrate 223 Gate electrode 224 Gate insulating film 225 Oxide semiconductor film 226 Source electrode 227 Drain electrode 228 Oxide insulating film 229 Conductive Film 230 insulating film 231 Channel protection film 300 pixel unit 301 Scanning line driving circuit 302 Signal line driver circuit 303 decoder 304 Shift Register 305 Sampling Circuit 306 Decoder 310 pixels 311 Switching Transistor 312 Drive transistor 313 Light-emitting element 314 holding capacity 320 pixels 321 Transistor 322 Liquid crystal element 323 holding capacity 400 boards 401 Gate electrode 402 Gate insulating film 403 Oxide semiconductor film 404 Oxide semiconductor film 405 Oxide semiconductor film 406 Conductive film 408 Capacitance wiring 409 Oxide semiconductor film 411 Oxide insulating film 412 Oxide semiconductor film 413 Thin-film transistor 414 pixel electrode 415 Transparent conductive film 416 Transparent conductive film 420 terminal 421 terminal 700 pixel unit 701 Signal line driver circuit 702 Scanning line driving circuit 702 Scanning line drive circuit 703 pixels 704 Transistor 705 Display element 706 holding capacity 707 Signal Line 708 scan lines 710 pixel electrode 711 Counter electrode 712 Microcapsules 713 Drain electrode 714 Resin 901 Transistor 902 Transistor 903 Transistor 904 Transistor 911 Transistor 912 Transistor 1401 Thin-film transistor 1402 gate electrode 1403 Gate insulating film 1404 Oxide semiconductor film 1405 Semiconductor film 1406 Conductive film 1407 Oxide insulating film 1408 insulating film 1410 pixel electrode 1411 Alignment film 1413 Counter electrode 1414 Alignment film 1415 LCD 1416 Sealing material 1417 Spacer 1601 LCD panel 1602 Diffuser 1603 Prism Sheet 1604 Diffuser 1605 Light guide plate 1606 Reflector 1607 Light source 1608 Circuit Board 1609 FPC 1610 FPC 407a Source electrode 407b Drain electrode 5601 Shift Register 5602 Sampling Circuit 5602 Switching Circuit 5603 n-channel transistor 5603 Transistor 5604 Wiring 5605 Wiring 6031 Transistor 6033 Light-emitting element 6034 Electrode 6035 Electroluminescent layer 6036 Electrode 6037 Insulating film 6038 Bulkhead 6041 Transistor 6043 Light-emitting element 6044 Electrode 6045 Electroluminescent layer 6046 Electrode 6047 Insulating film 6048 Bulkhead 6051 transistor 6053 Light-emitting element 6054 Electrode 6055 Electroluminescent layer 6056 Electrode 6057 Insulating film 6058 Bulkhead 7001 Case 7002 Display section 7011 Case 7012 Display section 7013 Support stand 7021 Housing 7022 Display section 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section

Claims

1. a first wiring, a second wiring, and a third wiring; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the third transistor; one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the sixth transistor is always electrically connected to one of the source and the drain of the fifth transistor; one of the source and the drain of the sixth transistor is always electrically connected to one of the source and the drain of the fourth transistor; one of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fifth transistor is always electrically connected to one of the source and the drain of the eighth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to one of the source and the drain of the seventh transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the second transistor; a gate of the eighth transistor is always electrically connected to a gate of the seventh transistor; a gate of the fifth transistor is always electrically connected to a gate of the third transistor; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; When the first transistor is on, a potential of the second wiring is input to the first wiring through a channel formation region of the first transistor, a potential of the gate of the first transistor can be controlled separately from a potential of the gate of the sixth transistor.

2. a first wiring, a second wiring, and a third wiring; the first to eighth transistors each include an In—O-based oxide semiconductor in a channel formation region, one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the third transistor; one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the sixth transistor is always electrically connected to one of the source and the drain of the fifth transistor; one of the source and the drain of the sixth transistor is always electrically connected to one of the source and the drain of the fourth transistor; one of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; the other of the source and the drain of the fifth transistor is always electrically connected to one of the source and the drain of the eighth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to one of the source and the drain of the seventh transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the other of the source and the drain of the second transistor; a gate of the eighth transistor is always electrically connected to a gate of the seventh transistor; a gate of the fifth transistor is always electrically connected to a gate of the third transistor; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; When the first transistor is on, a potential of the second wiring is input to the first wiring through a channel formation region of the first transistor, a potential of the gate of the first transistor can be controlled separately from a potential of the gate of the sixth transistor.

3. In claim 1 or claim 2, a pixel region and a scanning line driving circuit that inputs a selection signal to the pixel region; the scanning line driving circuit includes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor; The pixel region includes a ninth transistor and a liquid crystal layer above the ninth transistor.

Images