Substrate manufacturing method and buried substrate

Abstract

To provide a substrate manufacturing method, an embedded substrate and a semiconductor that can reduce substrate warping while completing device embedding.SOLUTION: A substrate manufacturing method includes the steps of: manufacturing a first semi-finished substrate including first circuit layers and first dielectric layers provided alternately laminated; providing a viscous material layer on the first circuit layer to form a device adhering area; adhering an embedded device on the device adhering area, where a pin face of the embedded device is provided away from the viscous material layer; press-bonding a second dielectric layer onto the first circuit layer, the second dielectric layer covering the viscous material layer and the embedded device; and manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer, the first conductive pillar penetrating the second dielectric layer and the first conductive pillar being used for connecting the second circuit layer with the first circuit layer, the second conductive pillar being used for connecting the embedded device with the second circuit layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to the technical field of semiconductor fabrication, and in particular to a method for fabricating a substrate and Embedded group On the board Regarding. [Background technology]

[0002] With the continuous development of the electronics industry, electronic products are becoming more multifunctional and smaller. In the field of packaging substrates, embedding components in a substrate can help electronic products meet the needs for high integration, multifunctionality, and miniaturization. In conventional technologies, fabricating a substrate for embedding components typically involves first creating a cavity in the substrate, then attaching the embedded component to the cavity, and then compressing a dielectric material to fill the cavity and cover the embedded component. However, this fabrication method requires the cavity to be fabricated first, which results in a long process flow, high costs, and a tendency for warpage during the substrate fabrication process. Therefore, a new method for fabricating substrates is urgently needed. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure aims to solve at least to some extent one of the technical problems existing in the prior art.

[0004] Therefore, one object of an embodiment of the present disclosure is to provide a method for manufacturing a substrate that can reduce warpage of the substrate while completing embedding of elements. and Embedded group Board The purpose is to provide. [Means for solving the problem]

[0005] To achieve the above technical objective, the technical solution adopted in the embodiment of the present disclosure includes a method for fabricating a substrate, the method comprising the steps of: fabricating a first semi-finished substrate, the first semi-finished substrate including several first circuit layers and at least one first dielectric layer that are electrically connected to each other, the first circuit layers and the first dielectric layers being alternately stacked, the number a of the first circuit layers and the number b of the first dielectric layers satisfying a relationship a=b+1, where a≧2; providing a viscous material layer on the first circuit layer to form a device attachment region, the projected area of ​​the viscous material layer in a direction perpendicular to the substrate being smaller than the projected area of ​​the device in a direction perpendicular to the substrate; The method includes the steps of: attaching an embedded element, wherein a pin surface of the embedded element is spaced apart from the viscous material layer; pressing a second dielectric layer onto the first circuit layer, wherein the second dielectric layer covers the viscous material layer and the embedded element; and creating a first conductive pillar, a second conductive pillar, and a second circuit layer, wherein the first conductive pillar penetrates the second dielectric layer, the first conductive pillar is used to connect the second circuit layer to the first circuit layer, and the second conductive pillar is used to connect the embedded element to the second circuit layer.

[0006] Furthermore, the method for manufacturing a substrate according to the above embodiment of the present disclosure may have the following additional technical features: Furthermore, in the embodiment of the present disclosure, the step of providing a viscous material layer on the first circuit layer to form an element attachment area specifically includes the step of providing a PID material layer on the first circuit layer or providing a DAF material layer on the first circuit layer to form an element attachment area.

[0007] Furthermore, in an embodiment of the present disclosure, the step of providing a PID material layer on the first circuit layer includes the steps of providing a PID material layer on the first circuit layer to cover the first circuit layer, and performing a photolithography process on the PID material layer to form an element attachment area.

[0008] Furthermore, in an embodiment of the present disclosure, the step of fabricating a first conductive pillar, a second conductive pillar, and a third circuit layer specifically includes the steps of drilling holes in the second dielectric layer to form first via holes and second via holes, and exposing the first circuit layer and pins of the embedded elements; performing hole-filling electroplating on the first via holes and the second via holes to obtain the first conductive pillar, the second conductive pillar, and a second seed layer formed on the second dielectric layer; and performing a photolithography process on the second seed layer to obtain a second circuit layer.

[0009] Furthermore, in an embodiment of the present disclosure, the step of providing a PID material layer on the first circuit layer or providing a DAF material layer on the first circuit layer specifically includes a step of pressing a PID material layer onto the first circuit layer or coating a DAF material at a predetermined position on the first circuit layer.

[0010] Furthermore, in an embodiment of the present disclosure, the step of preparing a first semi-finished substrate specifically includes the steps of pressing Nth dielectric layers onto the surface of the Nth metal layer and providing an N+1th metal layer on the Nth dielectric layer; and performing photolithography on the Nth metal layer and performing photolithography on the N+1th metal layer to form N+1 first circuit layers, wherein the N+1 first circuit layers are connected to each other via conductive pillars, and N≧1.

[0011] Meanwhile, an embodiment of the present disclosure further includes a substrate fabricated by the method for fabricating a substrate according to any one of the above embodiments, the substrate comprising: a semifinished substrate including several first circuit layers and at least one first dielectric layer that are electrically connected to each other, the first circuit layers and the first dielectric layers being alternately stacked, the number a of the first circuit layers and the number b of the first dielectric layers satisfying the relationship a=b+1, where a≧2; a viscous material layer provided between the embedded element and the semifinished substrate; embedded elements whose pin faces are provided away from the first circuit layer of the semifinished substrate; a second circuit layer connected to the embedded element and the first circuit layer of the semifinished substrate; and a second dielectric layer provided between the semifinished substrate and the second circuit layer and covering the embedded element.

[0012] Furthermore, in embodiments of the present disclosure, the embedded elements include active elements and passive elements.

[0013] Furthermore, in an embodiment of the present disclosure, the viscous material layer includes a PID material layer or a DAF material layer.

[0014] The present disclosure also provides a semiconductor device comprising at least one buried substrate according to any one of the above embodiments.

[0015] The advantages and beneficial effects of the present disclosure will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. The present disclosure allows embedded elements to be placed directly in a dielectric layer between circuit layers without creating a cavity for placing the embedded elements, and since the semi-finished product before embedding the elements of the present disclosure has a symmetrical structure, warpage can be reduced in the manufacturing process and product yield can be improved. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic diagram of steps in a method for fabricating a substrate in accordance with one specific embodiment of the present disclosure. [Figure 2] FIG. 2 is a structural schematic diagram of an embedded substrate in one specific embodiment of the present disclosure. [Figure 3] 1 is a schematic diagram of structural changes in a substrate fabrication process in one specific embodiment of the present disclosure. [Figure 4] 10A and 10B are schematic diagrams illustrating structural changes in a manufacturing process of another substrate in a specific embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0017] The principles and processes of a substrate manufacturing method according to an embodiment of the present disclosure will be described below with reference to the drawings.

[0018] Referring to FIG. 1, the method for producing a substrate according to the present disclosure includes the following steps S1 to S5.

[0019] In step S1, a first semi-finished substrate is prepared, the first semi-finished substrate including several first circuit layers that are electrically connected to each other and at least one first dielectric layer, the first circuit layers and the first dielectric layers are alternately stacked, and the number a of the first circuit layers and the number b of the first dielectric layers satisfy the relationship a=b+1, where a≧2.

[0020] In this step, a semi-finished substrate can be prepared in advance, and the semi-finished substrate may include two or more circuit layers and at least one dielectric layer. The first circuit layer may be alternately stacked on the first dielectric layer, and the number of circuit layers is equal to the number of dielectric layers + 1. That is, in the direction perpendicular to the semi-finished substrate, whether the semi-finished substrate has two or N circuit layers, the circuit layer is always located on the surface of the semi-finished substrate, and the dielectric layer is always located between the two circuit layers. Providing a semi-finished substrate with a symmetrical structure can prevent warpage defects caused by differences in the copper residual ratio on both sides during the subsequent compression bonding process.

[0021] In step S2, a viscous material layer is provided on the first circuit layer to form an element attachment region, and the projected area of ​​the viscous material layer in a direction perpendicular to the substrate is smaller than the projected area of ​​the element in a direction perpendicular to the substrate.

[0022] In this step, the circuit layer is always located on two surfaces of the semi-finished substrate in a direction perpendicular to the substrate, so a viscous material layer can be applied to any circuit layer on any surface. The projected area of ​​the viscous material layer in a direction perpendicular to the substrate is smaller than the projected area of ​​the device in a direction perpendicular to the substrate, resulting in the formation of a device attachment region. Because the projected area of ​​the viscous material layer is smaller than the projected area of ​​the device, overflow of the viscous material layer during device attachment can be prevented from affecting subsequent processes. The device attachment region can be located at any position on the first circuit layer. The viscous material fixes the embedded device, preventing the device from being offset during subsequent processes.

[0023] In step S3, an embedded element is attached to the element attachment region, and the pin surface of the embedded element is spaced apart from the viscous material layer.

[0024] In this step, the embedding can be attached to the element attachment area. The element may include an active element or a passive element. The active element may include a chip, a transistor, etc., and the passive chip may include a resistor, a capacitor, etc. Since the element has a pin side and a package side, the package side and the pin side of the chip are generally arranged opposite each other. During attachment, the pins of the element can be separated from the first circuit layer and the package side can be attached to the viscous material layer. For example, if the first circuit layer faces up, the pins of the embedded element should also face up during attachment.

[0025] In step S4, a second dielectric layer is pressed onto the first circuit layer, and the second dielectric layer covers the viscous material layer and the embedded element.

[0026] In this step, after the element is attached, a second dielectric layer can be pressed onto the first circuit layer. The second dielectric layer may be a dielectric layer made of a material such as resin. When pressed, the second dielectric layer must completely cover the first dielectric layer, the viscous material layer, and the embedded element. Therefore, the thickness of the second dielectric layer must be greater than the sum of the thicknesses of the viscous material layer and the embedded element.

[0027] In step S5, a first conductive pillar, a second conductive pillar, and a second circuit layer are fabricated, the first conductive pillar penetrates the second dielectric layer, the first conductive pillar is used to connect the second circuit layer to the first circuit layer, and the second conductive pillar is used to connect the embedded element to the second circuit layer.

[0028] In this step, after the second dielectric layer is pressed, a first conductive pillar penetrating the second dielectric layer, a second via hole for connecting the embedded element and the subsequent circuit layer, and a second circuit layer for connecting the semi-finished substrate and the embedded element can be fabricated on the second dielectric layer, which can be fabricated by first performing laser drilling on the second dielectric layer, then forming the first conductive pillar and the second conductive pillar by electroplating, subsequently performing electroplating to form a metal layer with a sufficient thickness for fabricating the second circuit layer, and finally performing photolithography on the metal layer to obtain the second circuit layer.

[0029] Furthermore, the step of providing a viscous material layer on the first circuit layer and forming an element attachment area may specifically include the step of providing a PID material layer or a DAF material layer on the first circuit layer to form an element attachment area.

[0030] In an embodiment of the present disclosure, the viscous material layer may be a PID material layer or a DAF material layer. Both the PID material layer and the DAF material layer are viscous material layers that can fix the embedded devices and prevent misalignment in subsequent processes, which can affect product quality. In practical applications, the PID material layer is often a thin film that covers the entire first circuit layer. Therefore, when providing the PID material layer, it is necessary to remove other PID layers on the first circuit layer that do not require device attachment areas.

[0031] Furthermore, the step of providing a PID material layer on the first circuit layer may include the steps of providing a PID material layer on the first circuit layer to cover the first circuit layer, and performing a photolithography process on the PID material layer to form an element attachment area.

[0032] In the embodiment of the present disclosure, the PID material is thin enough to cover the entire first circuit layer, so that the PID material in the non-device-attached areas must be removed to avoid electrically insulating other areas of the first circuit layer by the thin film. The remaining PID material can be removed by a photolithography process to leave only the PID material layer in the device-attached areas.

[0033] Furthermore, the step of providing a PID material layer on the first circuit layer or providing a DAF material layer on the first circuit layer may specifically include a step of pressing a PID material layer onto the first circuit layer or coating a DAF material at a predetermined position on the first circuit layer.

[0034] In an embodiment of the present disclosure, the PID material may be applied to the first circuit layer by crimping, and the DAF material may be applied to any position on the first circuit layer by coating, thereby forming an element attachment area.

[0035] Furthermore, the step of fabricating the first conductive pillar, the second conductive pillar, and the third circuit layer may specifically include the following steps S41 to S43.

[0036] In step S41, holes are drilled in the second dielectric layer to form first and second via holes, exposing the first circuit layer and the pins of the embedded elements.

[0037] In step S42, hole-filling electroplating is performed on the first via hole and the second via hole to obtain a first conductive pillar, a second conductive pillar, and a second seed layer formed on the second dielectric layer.

[0038] In step S43, a photolithography process is performed on the second seed layer to obtain a second circuit layer.

[0039] Specifically, in an embodiment of the present disclosure, holes are first drilled in the second dielectric layer, and multiple via holes are formed in the second dielectric layer, which partially expose the first circuit layer and the pins of the embedded devices. Next, based on the first circuit layer and the pins of the devices, an electroplating process is performed to form first conductive pillars that penetrate the second dielectric layer on the via holes and second conductive pillars that connect the subsequent circuit layer and the embedded devices. Electroplating is continued until a second seed layer of sufficient thickness to form the circuit layer is formed on the second dielectric layer, and finally, a photolithography process is performed on the second seed layer to form the final second circuit layer.

[0040] Furthermore, the step of fabricating the first semi-finished substrate may specifically include the following steps S51 to S52.

[0041] In step S51, N-th dielectric layers are pressure-bonded to the surface of the N-th metal layer, and an N+1-th metal layer is provided on the N-th dielectric layers.

[0042] In step S52, photolithography is performed on the Nth metal layer, and photolithography is performed on the N+1th metal layer to form N+1 first circuit layers, and the N+1 first circuit layers are connected to each other through conductive pillars, where N≧1.

[0043] In an embodiment of the present disclosure, for example, a first semi-finished substrate includes three first circuit layers and two dielectric layers. The first dielectric layer can be first pressed onto the surface of the first metal layer, a second metal layer can be applied to the first dielectric layer, conductive pillars can be applied to connect the first and second metal layers, photolithography can be performed on the first and second metal layers to form two first circuit layers, a second dielectric layer can be pressed onto the first circuit layer, a third metal layer can be applied to the second dielectric layer, conductive pillars can be applied to connect the first and third circuit layers, and photolithography can be performed on the third metal layer to form three interconnected first circuit layers. The number of circuit layers in the first semi-finished substrate is not limited to two or three, but can be four or more. If the number of circuit layers exceeds three, one dielectric layer and one metal layer can be pressed onto the third circuit layer using the above method, and then photolithography can be performed on the metal layer to form a new circuit layer.

[0044] Also, referring to Figure 2, corresponding to the method of Figure 1, an embodiment of the present disclosure further provides a substrate, which may include a semi-finished substrate 101 that may include several first circuit layers that are conductive to each other and at least one first dielectric layer, wherein the first circuit layers and the first dielectric layers are alternately stacked, a viscous material layer 102 that may be provided between the embedded element and the semi-finished substrate and can fix the element, an embedded element 103 whose pin surface may be provided away from the first circuit layer of the semi-finished substrate, a second circuit layer 104 that can be connected to the embedded element and the first circuit layer of the semi-finished substrate via a conductive pillar, and a second dielectric layer that is provided between the semi-finished substrate and the second circuit layer and can completely cover the embedded element.

[0045] Furthermore, embedded elements may include active and passive elements, and the particular element type selected may be determined according to the function to be realized by a particular circuit.

[0046] Furthermore, the viscous material layer may include a PID material layer or a DAF material layer. The PID material layer completely covers all areas of the first circuit layer when pressed, resulting in subsequent processing being required to obtain a portion of the PID layer that is only used for attaching the device. The DAF can be coated onto the circuit layer, allowing for spot coating.

[0047] The present disclosure also provides a semiconductor. The semiconductor of this embodiment may be obtained by connecting two or more of the embedded substrates described in the above embodiments to each other, or by connecting various different elements or circuit layer structures to the outside of the embedded substrate of the above embodiment. This semiconductor can improve warpage, enhance product quality, and has a simple structure.

[0048] The method for producing a substrate according to the present disclosure will be described below with reference to the drawings.

[0049] (Embodiment 1) Referring to Figures 3a-3f, a semi-finished substrate 200 is provided, which includes two interconnected first circuit layers 201 and one dielectric layer 202. The horizontally symmetrical circuit design prevents warping caused by differences in the copper content of the circuits on both sides during fabrication. A viscous material layer is applied to the first circuit layer 201 on any side of the semi-finished substrate 200. In this embodiment, the viscous material layer is a PID material layer 203. A photolithography process is performed on the PID material layer 203, leaving a portion of the PID material layer covering the first circuit layer 201 for attaching the device. The PID material coverage area of ​​the remaining portion is smaller than the back surface of the embedded device 204, preventing overflow of the PID material layer during attachment and affecting product quality. The embedded device 204 is attached to the remaining portion of the PID material layer, with the pins of the embedded device 204 facing upward and the non-pin side adhering to the PID material layer 203. Next, a second dielectric layer 205 is pressed onto the first dielectric layer 205, completely covering the first circuit layer 201, the embedded element 204, and the remaining PID material layer 203. A first via hole 206 and a second via hole 207 are then formed in the second dielectric layer 205, and a first conductive pillar 208 and a second conductive pillar 209 are formed in the first via hole 206 and the second via hole 207 by electroplating. The first conductive pillar 208 can provide electrical continuity between the first circuit layer 201 and the subsequent circuit layer, and the second conductive pillar 209 can provide electrical continuity between the embedded element 204 and the subsequent circuit layer. After the electroplating of the conductive pillars is completed, a metal layer 210 can be formed on the second dielectric layer 205 by continuing the electroplating process, and a second circuit layer 211 can be obtained by performing a conventional photolithography process on the metal layer 210.

[0050] (Embodiment 2) Referring to Figures 4a-4e, a semi-finished substrate 300 is provided, which includes three interconnected first circuit layers 301 and two dielectric layers 302. The horizontally symmetrical circuit design prevents warpage defects caused by differences in the copper residual ratios of the circuits on multiple sides during fabrication. A DAF material layer 303 is coated on the first circuit layer 301 on any side of the semi-finished substrate 300. An embedded element 304 is then attached to the DAF material layer 303, with the pins of the embedded element 304 facing upward and the non-pin side adhering to the DAF material layer 303. A second dielectric layer 305 is then pressed onto the first circuit layer 301, the embedded element 304, and the DAF material layer 303, completely covering the first circuit layer 301, the embedded element 304, and the DAF material layer 303. Because the projected area of ​​the DAF material layer 303 is smaller than the vertical projected area of ​​the embedded element 304, overflow of the DAF material layer 303 during attachment can be prevented, thereby preventing product quality from being affected. Next, a first via hole 306 and a second via hole 307 are formed in the second dielectric layer 305, and then a first conductive pillar 308 and a second conductive pillar 309 are formed in the first via hole 306 and the second via hole 307 by electroplating. The first conductive pillar 308 can provide electrical continuity between the first circuit layer 301 and a subsequent circuit layer, and the second conductive pillar 309 can provide electrical continuity between the embedded element 304 and a subsequent circuit layer. After the electroplating of the conductive pillars is completed, electroplating is continued to form a metal layer 310 in the second dielectric layer 305, and a conventional photolithography process is performed on the metal layer 310 to obtain a second circuit layer 311.

[0051] The contents in the above method embodiments are all applicable to the present device embodiment, the functions specifically realized in the present device embodiment are the same as those in the above method embodiment, and the beneficial effects achieved are also the same as those in the above method embodiment.

[0052] In the description herein above, a description that refers to terms such as "one embodiment / example," "another embodiment / example," or "some embodiments / examples" means that the specific feature, structure, material, or characteristic described in an embodiment or example is included in at least one embodiment or example of the present disclosure. As used herein, exemplary uses of the terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0053] Although embodiments of the present disclosure have been illustrated and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present disclosure, and that the scope of the present disclosure is limited by the claims and their equivalents.

[0054] The above is a specific description of a preferred embodiment of the present disclosure, but the present disclosure is not limited to the above embodiment. A person skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present disclosure, and all of these equivalent modifications or substitutions are included in the scope defined by the claims of this application.

Claims

1. A method for manufacturing a substrate, comprising: a step of producing a semi-finished substrate, the semi-finished substrate including several first circuit layers and at least one first dielectric layer that are electrically connected to each other, the first circuit layers and the first dielectric layers being alternately stacked, the number a of the first circuit layers and the number b of the first dielectric layers satisfying a relational expression a=b+1, a≧2, and the first circuit layers of the semi-finished substrate having the same shape when viewed in a stacking direction in which the first circuit layers and the first dielectric layers are alternately stacked; providing a viscous material layer on the first circuit layer to form an element attachment region, wherein a projected area of ​​the viscous material layer in a direction perpendicular to the substrate is smaller than a projected area of ​​the element in a direction perpendicular to the substrate; attaching an embedded element to the element attachment region, wherein a pin surface of the embedded element is spaced apart from the viscous material layer; pressing a second dielectric layer onto the first circuit layer, the second dielectric layer covering the viscous material layer and the embedded element; fabricating a first conductive pillar, a second conductive pillar, and a second circuit layer, wherein the first conductive pillar penetrates the second dielectric layer, the first conductive pillar is used to connect the second circuit layer to the first circuit layer, and the second conductive pillar is used to connect the embedded element to the second circuit layer; The step of fabricating the semi-finished substrate specifically includes: pressing an Nth dielectric layer onto a surface of the Nth metal layer, and providing an (N+1)th metal layer on the Nth dielectric layer; performing photolithography on the Nth metal layer and performing photolithography on the N+1th metal layer to form N+1 first circuit layers, wherein the N+1 first circuit layers are connected to each other via conductive pillars, and N≧1; A method for manufacturing a substrate, comprising:

2. Specifically, the step of providing a viscous material layer on the first circuit layer and forming an element attachment region includes:

2. The method for manufacturing a substrate according to claim 1, further comprising the step of providing a PID material layer on the first circuit layer or providing a DAF material layer on the first circuit layer to form an element attachment region.

3. The step of providing a layer of PID material on the first circuit layer comprises: providing a layer of PID material on the first circuit layer overlying the first circuit layer; 3. The method for manufacturing a substrate according to claim 2, further comprising the step of: performing a photolithography process on the PID material layer to form an element attachment region.

4. The step of fabricating the first conductive pillar, the second conductive pillar, and the third circuit layer specifically includes: drilling holes in the second dielectric layer to form first and second via holes, exposing the first circuit layer and pins of the embedded elements; performing hole-filling electroplating on the first via hole and the second via hole to obtain a first conductive pillar, a second conductive pillar, and a second seed layer formed on the second dielectric layer; 2. The method for manufacturing a substrate according to claim 1, further comprising: performing a photolithography process on the second seed layer to obtain a second circuit layer.

5. The step of providing a PID material layer on the first circuit layer or providing a DAF material layer on the first circuit layer specifically includes:

3. The method for manufacturing a substrate according to claim 2, further comprising the step of pressing a PID material layer onto the first circuit layer or coating a DAF material at a predetermined position on the first circuit layer.

6. A semi-finished substrate comprising several first circuit layers that are conductive to each other and at least one first dielectric layer, the first circuit layers and the first dielectric layers being alternately stacked, the number a of the first circuit layers and the number b of the first dielectric layers satisfying the relation a=b+1, where a≧2, the first circuit layers having the same shape when viewed from the stacking direction in which the first circuit layers and the first dielectric layers are alternately stacked, and the first circuit layers communicating with each other via conductive pillars; an embedded element having a pin surface spaced apart from the first circuit layer of the semi-finished substrate; a layer of viscous material disposed between the embedded element and the semi-finished substrate; a second circuit layer connected to the embedded device and the first circuit layer of the semi-finished substrate; a second dielectric layer disposed between the semi-finished substrate and the second circuit layer and covering the embedded elements.

7. 7. The buried substrate according to claim 6, wherein the buried elements include active elements and passive elements.

8. The embedded substrate of claim 6 , wherein the viscous material layer comprises a PID material layer or a DAF material layer.

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