DrMOS, integrated circuits, electronic devices, and manufacturing methods

Abstract

A driver metal oxide semiconductor field effect transistor (DrMOS) (60), an integrated circuit (101), an electronic device, and a manufacturing method are provided. The DrMOS (60) mainly includes a first die (61) and a second die (62). The first die (61) includes a drive circuit (3) and a first switching transistor (1), with the drive circuit (3) connected to the gate (G1) of the first switching transistor (1). The second die (62) includes a second switching transistor (2), with the drive circuit (3) connected to the gate (G2) of the second switching transistor (2) via a first conductor. The drive circuit (3) and the first switching transistor (1) are provided on the same die (61), which helps reduce the area, loss, and cost of the DrMOS (60). The first switching transistor (1) and the second switching transistor (2) are provided on different dies (61, 62), which helps reduce type selection restrictions for the first switching transistor (1) and the second switching transistor (2).

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and in particular to DrMOS, integrated circuits, electronic devices, and manufacturing methods. [Background technology]

[0002] A driver metal-oxide-semiconductor field-effect transistor (DrMOS) is a device that integrates a driver circuit and multiple switching transistors, and is widely used in integrated circuits that integrate driver circuits and switching power supply circuits.

[0003] Specifically, a switching power supply circuit typically includes multiple switching transistors, each of which is connected to a drive circuit, and the drive circuit controls the switching on and off of each switching transistor, thereby adjusting the output current and / or output voltage of the switching power supply circuit. In an integrated circuit, the drive circuit and multiple switching transistors in the switching power supply circuit can be integrated into one device (i.e., DrMOS). In this case, the connection lines between the drive circuit and each switching transistor are short. This helps reduce the area of ​​the integrated circuit and increase the power density of the integrated circuit.

[0004] However, most current DrMOSs use a die co-package structure, in which the driver circuit and multiple switching transistors are placed on separate dies, with different switching transistors placed on different dies. The die containing the driver circuit is connected to each of the multiple dies containing the switching transistors via leads. This implementation results in a complex manufacturing process and high costs. Furthermore, the integration density of the die co-package structure is low, and the area of ​​the DrMOS needs to be further reduced. Furthermore, excessive leads also lead to problems such as parasitic inductance, parasitic capacitance, and parasitic resistance, increasing the loss of the DrMOS.

[0005] In summary, the current DrMOS needs further study. Summary of the Invention

[0006] This application provides a DrMOS, an integrated circuit, an electronic device, and a manufacturing method that reduces the area, cost, and loss of the DrMOS.

[0007] According to a first aspect, an embodiment of the present application provides a DrMOS mainly including a first die and a second die, the first die including a drive circuit and a first switching transistor, the drive circuit being connected to a gate of the first switching transistor, and the second die including a second switching transistor, the drive circuit being connected to a gate of the second switching transistor via a first conductor.

[0008] For example, the driving circuit may connect a metal gate in the first die to the gate of the first switching transistor. wiring In other words, the first die can be connected via a metal wiringIn this case, no additional leads are required to realize the connection between the driving circuit and the first switching transistor. This therefore simplifies the manufacturing process of the DrMOS and helps reduce the process cost of the DrMOS. Also, the number of leads in the DrMOS can be reduced, which helps alleviate problems caused by the leads, such as parasitic inductance, parasitic capacitance, and parasitic resistance, and further helps reduce the loss of the DrMOS. In addition, the driving circuit and the first switching transistor are provided on the same die (first die), and therefore the driving circuit and the first switching transistor are close to each other. This helps reduce the area of ​​the DrMOS.

[0009] In addition, in the DrMOS provided in this embodiment of the present application, the first switching transistor and the second switching transistor are provided on different dies. Therefore, there is no need to consider the compatibility issue of the manufacturing process between the first switching transistor and the second switching transistor. This helps reduce the type selection restrictions for the first switching transistor and the second switching transistor. The types of the first switching transistor and the second switching transistor can be flexibly selected based on the application scenario. Furthermore, the drive circuit is connected to the second switching transistor through the first conductor, so the drive circuit can maintain the ability to control the second switching transistor.

[0010] It can be understood that the DrMOS provided in this embodiment of the present application can be applied to the implementation of multiple types of switching power supply circuits. In some switching power supply circuits, such as a buck circuit, the source of a first switching transistor is connected to the drain of a second switching transistor. To accommodate such circuits, the DrMOS provided in this embodiment of the present application can have the source of the first switching transistor connected to the drain of the second switching transistor via a second conductor.

[0011] Next, the application of DrMOS in a buck circuit will be used as an example to further describe the DrMOS provided in this embodiment of this application. When DrMOS is used in a buck circuit, the first switching transistor of DrMOS can be the driving switching transistor of the buck circuit, the second switching transistor of DrMOS can be the rectifier switching transistor of the buck circuit, and the driving circuit of DrMOS can be the driving circuit of the buck circuit.

[0012] According to the working principle of the buck circuit, the following conclusions can be drawn: the first switching transistor can be implemented with a transistor having a high switching speed, which helps to reduce the losses of the first switching transistor. For example, the first switching transistor can be an LDMOS transistor. The second switching transistor can be implemented with a transistor having a low on-resistance, which helps to reduce the losses of the second switching transistor. For example, the second switching transistor can be an SGT MOS transistor.

[0013] Since the source and drain of the SGT MOS transistor are located on two opposite surfaces, respectively, the SGT MOS transistor can be fixed to the surface of a substrate using a flip-chip structure to simplify the connection between the first switching transistor and the second switching transistor. Specifically, the DrMOS can further include a substrate. The substrate can support a first die and a second die, where a first surface of the first die is located on the side facing away from the substrate, where the first surface is the surface of the first die where the source of the first switching transistor is located, and a second surface of the second die is located on the side facing away from the substrate, where the second surface is the surface of the second die where the drain of the second switching transistor is located, and the source of the first switching transistor is connected to the drain of the second switching transistor via a second conductor.

[0014] The second die may be flip-chip mounted on the surface of the substrate, exposing the drain of the second switching transistor and allowing the source of the second switching transistor to directly contact the substrate, where the drain of the second switching transistor may be connected to the source of the first switching transistor via a lead, and the source of the second switching transistor may be connected to a metal layer on the substrate. line can be grounded via

[0015] To further reduce the losses of the DrMOS, in one possible implementation, the second die may further integrate a Schottky barrier diode SBD, whose anode is connected to the source of the second switching transistor and whose cathode is connected to the drain of the second switching transistor.

[0016] The SBD has a low conduction voltage drop VF and a small reverse recovery charge Qrr, which helps further reduce the loss of the second die. We use the conduction voltage drop VF as an example. There is a dead time between the charging stage and the rectifying stage due to the inherent delay between switching on and off of the switching transistor. During the dead time, the second switching transistor does not switch on completely. In this case, current can be transmitted through the SBD in parallel with the second switching transistor. The low conduction voltage drop VF of the SBD helps reduce the loss that occurs in the process of the SBD transmitting current, which helps further reduce the loss of the second die.

[0017] It can be understood that in addition to the driving circuit, the first switching transistor, and the second switching transistor, other structures may be integrated into the DrMOS provided in this embodiment of this application to implement more functions, for example, the DrMOS may further include a temperature sensor, and an external component may use the temperature sensor to obtain temperature information of the DrMOS.

[0018] In another example, the DrMOS may further include a current sensor that allows an external component to detect the magnitude of the current flowing through the first switching transistor when the first switching transistor is switched on. For example, the current sensor may be integrated into the first die.

[0019] According to a second aspect, an embodiment of this application further provides an integrated circuit. The integrated circuit may include the DrMOS provided in any implementation of the first aspect. For technical effects of the corresponding solution in the second aspect, please refer to the technical effects that can be achieved by the corresponding solution in the first aspect. Details will not be described again here.

[0020] For example, in addition to the DrMOS, the integrated circuit may include an inductor and a capacitor. The first and second switching transistors of the DrMOS may form a buck circuit with the inductor and the capacitor. One end of the inductor is connected to the source of the first switching transistor, the other end of the inductor is connected to one end of the capacitor, and the other end of the inductor is configured to output an output voltage, and the source of the second switching transistor and the other end of the capacitor are grounded.

[0021] According to a third aspect, an embodiment of this application further provides an electronic device. The electronic device may include an integrated circuit provided in any implementation of the second aspect. For example, the electronic device may be a smartphone, a personal computer, an intelligent driving vehicle, a router, or a switch. A chip is mounted on the electronic device. The integrated circuit provided in this embodiment of this application can supply power to the chip of the electronic device.

[0022] According to a fourth aspect, an embodiment of this application further provides a DrMOS manufacturing method, which can be used to manufacture the DrMOS provided in any of the embodiments of the first aspect. For example, the DrMOS manufacturing method mainly includes the following steps: separately preparing a first die and a second die; and connecting a driving circuit to the gate of a second switching transistor through a first conductor, wherein: The first die includes a driving circuit and a first switching transistor, the driving circuit being connected to a gate of the first switching transistor, and the second die includes a second switching transistor. For example, the first die may be prepared using a bipolar junction transistor-complementary metal oxide semiconductor-diffused metal oxide semiconductor (BCD) process, such that the first die integrates the driving circuit and the first switching transistor, and the driving circuit is connected to the gate of the first switching transistor. The second switching transistor may also be prepared using the BCD process. This is not a limitation in this embodiment of the application.

[0023] In some switching power supply circuits, the source of the first switching transistor can also be connected to the drain of the second switching transistor. In this case, the source of the first switching transistor of the first die can also be connected to the drain of the second switching transistor of the second die using a second conductor. Thus, DrMOS can be adapted to this type of switching power supply circuit.

[0024] A buck circuit is used as an example. In this embodiment of the present application, the first switching transistor can be used as a drive switching transistor of the buck circuit, and the second switching transistor can be used as a rectifier switching transistor of the buck circuit. In this case, the first switching transistor can be implemented by a transistor with a high switching speed. For example, the first switching transistor can be an LDMOS transistor. The second switching transistor can be implemented by a transistor with a low on-resistance. For example, the second switching transistor can be an SGT MOS transistor.

[0025] When the DrMOS is used in a buck circuit, the source of the first switching transistor needs to be connected to the drain of the second switching transistor in the DrMOS. Specifically, after the first die and the second die are separately prepared, the first die and the second die are first fixed on the same surface of a substrate, and then a driving circuit is connected to the gate of the second switching transistor using a first conductor.

[0026] In fixing the first die, the first surface of the first die can be placed on the side not facing the substrate, and the first surface can be the surface where the source of the first switching transistor (LDMOS transistor) is located. In fixing the second die, the second surface of the second die can be placed on the side not facing the substrate, and the second surface can be the surface where the drain of the second switching transistor (SGT MOS transistor) is located. Furthermore, the source of the first switching transistor can be directly connected to the drain of the second switching transistor via a second conductor. The second conductor can be a lead or a conductor clip. This is not limited in this embodiment of this application.

[0027] To further reduce losses in the second switching transistor, in one possible implementation, the second die may further include a Schottky barrier diode SBD. The anode of the SBD is connected to the source of the second switching transistor, and the cathode of the SBD is connected to the drain of the second switching transistor. The SBD has a low conduction voltage drop VF and a small reverse recovery charge Qrr, which helps reduce losses in the second switching transistor that occur during dead time.

[0028] These and other aspects of the present application will become clearer and easier to understand in the description of the embodiments that follow. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a schematic diagram illustrating a configuration of an electronic device. [Figure 2] 1 is a schematic diagram of the DrMOS configuration. [Figure 3] 1 is a schematic diagram of an integrated circuit configuration. [Figure 4] FIG. 4 is a schematic diagram of a driving signal for a buck circuit. [Figure 5] 1 is a schematic diagram of the DrMOS configuration. [Figure 6] FIG. 1 is a schematic diagram of a DrMOS correction according to one embodiment of the present application. [Figure 7] FIG. 1 is a schematic diagram of a DrMOS correction according to one embodiment of the present application. [Figure 8] 1 is a schematic diagram of the structure of an LDMOS transistor. [Figure 9] 1 is a schematic diagram of the structure of an SGT MOS transistor. [Figure 10] FIG. 1 is a schematic diagram of a structure obtained by side-cutting a DrMOS according to an embodiment of the present application. [Figure 11] 1 is a schematic flow chart of a DrMOS manufacturing method according to one embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. A specific operation method in a method embodiment may also be applied to an apparatus embodiment or a system embodiment. In the description of this application, "at least one" means one or more, and "plurality" means two or more. In light of this, "plurality" can also be understood as "at least two" in the embodiments of the present invention. The term "and / or" describes a relational relationship for describing related objects and indicates that three relationships may exist. For example, A and / or B may represent three cases: only A exists, both A and B exist, and only B exists. Furthermore, the character " / " generally indicates an "or" relationship between related objects. It should be understood that in the description of this application, terms such as "first" and "second" are used only for distinction and explanation, and should not be understood as indicating or implying relative importance or order. In the embodiments of this application, a "die" can be understood as a chip with a specific function cut out from a wafer.

[0031] In modern electronic devices, an integrated circuit with voltage regulation capability usually needs to be placed around a chip to supply the chip with a voltage that meets the chip's operating requirements. As shown in FIG. 1, an electronic device 100 includes an integrated circuit 101 and a chip 102. The electronic device 100 may be a smartphone, a personal computer, an intelligent driving vehicle, a router, a switch, or the like. The integrated circuit 101 may receive an input voltage. The input voltage may be provided by a battery 103 within the electronic device 100 or by a power source external to the electronic device 100. This is not limited to this embodiment of the present application.

[0032] The chip 102 may be any chip or circuit within the electronic device 100, such as a processor chip, a power management chip, a charging chip, or a field programmable gate array (FPGA), without listing them one by one. The integrated circuit 101 may adjust the received input voltage Vin to provide the chip 102 with an output voltage Vo that meets the operating requirements of the chip 102.

[0033] Generally, the integrated circuit 101 mainly includes a driving circuit and a switching power supply circuit. For example, the switching power supply circuit may be a boost circuit, a buck circuit, a DC-DC converter circuit, an AC-DC converter circuit, and the like, which is not limited to this embodiment of the present application. Under the control of the driving circuit, the switching power supply circuit may adjust the received input voltage to output an output voltage that can meet the operating requirements of the chip 102.

[0034] Specifically, the electronic device 100 may further include a controller 104. The controller 104 may send control commands to the driving circuitry in the integrated circuit 101. The control commands may be commands to instruct the integrated circuit 101 to adjust the output voltage Vo, commands to instruct the integrated circuit 101 to start or stop an operation, or the like, which is not limited to this embodiment of the present application.

[0035] The drive circuit may further adjust the drive signal provided to the switching power supply circuit based on the received control command, for example, the drive circuit may adjust the duty cycle of the drive signal, the signal frequency of the drive signal, and the like, to adjust the output voltage V.

[0036] As the demand for integration of electronic devices 100 increases, DrMOS is widely used in integrated circuits 101 due to its small area advantage. FIG. 2 shows an example of a typical DrMOS configuration. As shown in FIG. 2, DrMOS 20 mainly includes die 21, die 22, and die 23. Switching transistor 1 is provided on die 21, switching transistor 2 is provided on die 22, and driving circuit 3 is provided on die 23. Die 21, die 22, and die 23 are in a three-die co-package structure. Specifically, leads are connected between die 23 and die 21 and between die 23 and die 22, and driving circuit 3 can be connected to the gates of switching transistor 1 and switching transistor 2 via the leads.

[0037] The integrated circuit 101 includes a switching power supply circuit and a driving circuit. The switching transistor 1 and the switching transistor 2 of the DrMOS 20 shown in FIG. 2 can be used as the switching transistor of the switching power supply circuit, and the driving circuit 3 can be used as the driving circuit of the switching power supply circuit.

[0038] Take a buck circuit as an example. As shown in Figure 3, the buck circuit mainly includes a switching transistor 1, a switching transistor 2, an inductor L, and a capacitor C. The drain of the switching transistor 1 is configured to receive an input voltage Vin, the source of the switching transistor 1 is connected to both the drain of the switching transistor 2 and one end of the inductor L, and the other end of the inductor L is connected to one end of the capacitor C, and the other end of the inductor L can output an output voltage Vo. .vinegar Switching transistor 2 The source of the capacitor C and the other end of the capacitor C are grounded.

[0039] The gate of the switching transistor 1 and the gate of the switching transistor 2 are respectively connected to the driving circuit 3. The driving circuit 3 can provide driving signals to the gate of the switching transistor 1 and the gate of the switching transistor 2, respectively, to control the switching on and off of the switching transistor 1 and the switching transistor 2, and further control the buck circuit to complete the voltage conversion. For example, when the driving circuit 3 provides a high-level driving signal to the switching transistor 1, the switching transistor 1 can be switched on, and the driving circuit 3 can turn on the switching transistor 1. 1 When a low level drive signal is applied to the transistor 1, the switching transistor 1 can be switched off, and the same applies to the switching transistor 2. The details will not be described again here.

[0040] Specifically, the buck circuit is a DC-DC buck circuit. Specifically, the input voltage Vin and the output voltage Vo are DC voltages, and the output voltage Vo is lower than the input voltage Vin. The voltage reduction process of the buck circuit is mainly divided into a charging stage and a rectifying stage. Next, the charging stage and the rectifying stage will be described separately using the driving signals shown in FIG. 4 as an example. Driving signal 1 is the driving signal provided by driving circuit 3 to switching transistor 1, and driving signal 2 is the driving signal provided by driving circuit 3 to switching transistor 2.

[0041] It can be seen that in FIG. 4, both switching transistor 1 and switching transistor 2 can be switched on when the drive signal is at a high level and switched off when the drive signal is at a low level. In actual implementation, instead, switching transistor 1 and switching transistor 2 can be switched on when the drive signal is at a high level and switched off when the drive signal is at a low level. low It switches on when the drive signal is at the high It may be switched off when it is at a low level, which is not a limitation in this embodiment of this application.

[0042] 1.Charging stage During the charging stage, the driving circuit 3 can turn on the switching transistor 1 and turn off the switching transistor 2. The switching transistor 1 can also be referred to as the driving switching transistor or the upper transistor. Current is input from the drain of the switching transistor 1 and passes through the switching transistor 1 and the inductor L before being output. During this process, the inductor L charges, converting electrical energy into magnetic energy and storing it. During the charging process of the inductor L, the inductor L acts as a load and can generate a voltage drop, resulting in the output voltage Vo of the buck circuit being lower than the input voltage Vin. By lengthening the charging process of the inductor L, the voltage drop generated by the inductor L gradually decreases, and the output voltage Vo gradually increases.

[0043] 2. Rectifier stage In the rectifier stage, the driver circuit 3 can switch off the switching transistor 1 and switch on the switching transistor 2. The switching transistor 2 can also be called a rectifier switching transistor or a lower transistor. The magnetic energy stored in the inductor L is converted into electrical energy and released; in other words, the inductor L discharges. When the inductor L discharges, the output voltage Vo approaches the inductance voltage of the inductor L. If the discharge process of the inductor L is prolonged, the inductance voltage of the inductor L gradually decreases, and the output voltage Vo gradually decreases.

[0044] The driving circuit 3 controls the switching transistors 1 and 2 to be switched on and off so that the buck circuit continuously outputs the output voltage Vo, thereby controlling the buck circuit to alternate between the charging stage and the rectifying stage. As shown in Figure 3, the buck circuit further includes a capacitor C. The capacitor C can filter the output voltage Vo to reduce the pulsation of the output voltage Vo and improve the stability of the output voltage Vo.

[0045] 3, the switching transistor 1, the switching transistor 2, and the driving circuit 3 of the buck circuit can be implemented using a DrMOS 20. In other words, the switching transistor 1, the switching transistor 2, and the driving circuit 3 can be integrated into the same DrMOS 20. Also, the switching transistor 1, the switching transistor 2, and the driving circuit 3 are close to each other, which helps reduce the area of ​​the integrated circuit 101 and increase the power density of the integrated circuit 101.

[0046] However, because the DrMOS 20 has a three-die co-package structure, there are still gaps between any two of the switching transistor 1, switching transistor 2, and drive circuit 3, resulting in a large area and a low integration density. Furthermore, the switching transistor 1, switching transistor 2, and drive circuit 3 must be electrically connected using leads, which complicates the manufacturing process and increases the cost of the DrMOS 20. Finally, because the dies within the DrMOS 20 must be connected to each other using leads, there are many leads within the DrMOS 20, which further leads to problems such as parasitic inductance, parasitic capacitance, and parasitic resistance, increasing the loss of the DrMOS 20.

[0047] In view of this, there is currently another DrMOS configuration as shown in Figure 5. This DrMOS 50 includes a die 51 and a die 52, and the die 52 includes a switching transistor 1 and a switching transistor 2. Since the switching transistor 1 and the switching transistor 2 are provided on the same die, the switching transistor 1 and the switching transistor 2 are close to each other, which helps to further reduce the area of ​​the DrMOS 50.

[0048] However, since the switching transistor 1 and the switching transistor 2 are provided on the same die (die 52), the manufacturing process of the switching transistor 1 and the manufacturing process of the switching transistor 2 need to be compatible with each other, which in turn increases the process development cost and limits the type selection of the switching transistor 1 and the switching transistor 2.

[0049] For example, the fabrication processes for laterally diffused metal-oxide-semiconductor (LDMOS) transistors and split-gate trench metal-oxide-semiconductor (SGT MOS) transistors are incompatible with each other. In this case, it is quite difficult to fabricate both LDMOS and SGT MOS transistors within one die. In the DrMOS 50 shown in FIG. 5, it is quite difficult to fabricate both LDMOS and SGT MOS transistors within die 52.

[0050] In view of this, one embodiment of this application provides a new DrMOS configuration, which not only helps reduce the loss, cost, and area of ​​the DrMOS, but also helps reduce the type selection restrictions of the switching transistor in the DrMOS. For example, as shown in FIG. 6, the DrMOS 60 provided in this embodiment of this application mainly includes a die 61 and a die 62. The die 61 includes a driving circuit 3 and a switching transistor 1, and the die 62 includes a switching transistor 2.

[0051] Within the die 61, the driving circuit 3 is connected to the gate of the switching transistor 1. For example, the driving circuit 3 is connected to a metal wiring The process of preparing the die 61 involves connecting the metal layer between the driver circuit 3 and the switching transistor 1 to the gate of the switching transistor 1 via the wiring The metal layer between the driving circuit 3 and the switching transistor 1 is wiring is located inside the die 61.

[0052] Therefore, the die 61 is connected to the metal between the driver circuit 3 and the switching transistor 1. wiring , and no additional leads are required to realize the connection between the driving circuit 3 and the first switching transistor 1. This helps simplify the manufacturing process of the DrMOS 60 and reduces the process cost of the DrMOS 60. This further mitigates problems caused by leads, such as parasitic inductance, parasitic capacitance, and parasitic resistance, and further helps reduce losses in the DrMOS 60. In addition, the driving circuit 3 and the switching transistor 1 are provided on the same die (die 61), and therefore the driving circuit 3 and the switching transistor 1 are close to each other. This helps reduce the area of ​​the DrMOS 60.

[0053] The switching transistor 1 and the switching transistor 2 are provided on different dies. Therefore, there is no need to consider the compatibility issue of the manufacturing process between the switching transistor 1 and the switching transistor 2. This helps to reduce the type selection restriction for the switching transistor 1 and the switching transistor 2. Furthermore, the driving circuit 3 is connected to the switching transistor 2 through the first conductor, and therefore the driving circuit 3 can maintain the ability to control the switching transistor 2. For example, the first conductor can be a lead, and can be a metal lead such as a copper wire, a gold wire, or a silver wire.

[0054] It can be understood that the DrMOS 60 provided in this embodiment of the present application can be applied to the implementation of multiple types of switching power supply circuits. In some switching power supply circuits, such as the buck circuit shown in FIG. 3, the source of the switching transistor 1 is connected to the drain of the switching transistor 2. Adapting to the circuit shown in FIG. 3, in the DrMOS 60 provided in this embodiment of the present application, the source of the switching transistor 1 can be connected to the drain of the switching transistor 2 via the second conductor, as shown in FIG.

[0055] Next, the DrMOS 60 provided in the embodiment of this application will be further described using an example in which the DrMOS 60 shown in Fig. 7 is in an integrated circuit 101. The integrated circuit 101 uses a buck circuit as a switching power supply circuit.

[0056] As mentioned above, the switching transistor 1 is switched on in the charging stage and switched off in the rectifying stage. It can be seen from the driving signal 1 shown in Fig. 4 that the switch-on time of the switching transistor 1 is much shorter than the switch-off time of the switching transistor 1, and the loss generated by the switching transistor 1 is mainly due to the loss generated when the switching transistor 1 is switched on and off. This loss is mainly related to the switching speed of the switching transistor 1. Therefore, the switching transistor 1 can be a transistor with a high switching speed. For example, the switching transistor 1 can be an LDMOS transistor.

[0057] For example, the structure of an LDMOS transistor can be shown in FIG. 8. The LDMOS mainly includes a substrate, a drift region, a source region, a drain region, and gate polysilicon. The substrate is heavily N-type doped (N+). The drift region is located on the surface of the substrate and is lightly N-type doped (N-). A base region and a drain region are fabricated in the drift region away from the substrate. The base region is P-type doped, and the drain region is heavily N-type doped (N+). The base region and the drain region are separated from each other by the drift region. A source region is further fabricated in the base region away from the substrate, and the source region is heavily N-type doped (N+). A source S is fabricated on the surface of the source region, a drain D is fabricated on the surface of the drain region, gate polysilicon is fabricated between the source S and the drain D, and a gate G is further fabricated on the surface of the gate polysilicon.

[0058] The switching speed of the LDMOS transistor is high. Therefore, using the LDMOS as the switching transistor 1 helps to reduce the loss of the switching transistor 1. In addition, the gate, drain, and source of the LDMOS are located on the same plane of the LDMOS, and therefore the manufacturing process of the LDMOS transistor is highly compatible with the complementary metal-oxide semiconductor (CMOS) process, and the LDMOS transistor and the driving circuit 3 can be integrated on the same die (die 61).

[0059] 4, it can be seen that the switch-on time of the switching transistor 2 is much longer than the switch-off time of the switching transistor 2, and the loss generated by the switching transistor 2 is mainly related to the on-resistance of the switching transistor 2. Therefore, the switching transistor 2 can be a switching transistor with a low on-resistance, for example, an SGT MOS transistor.

[0060] For example, the structure of an SGT MOS transistor can be shown in FIG. 9. The SGT MOS transistor mainly includes a drain region, a drift region, a source region, gate polysilicon, source polysilicon, and a base region. The drain region is heavily N-type doped (N+). The drift region is disposed adjacent to the drain region and is lightly N-type doped (N-). A base region is further disposed on the side of the drift region away from the drain region, and the base region is P-type doped. Gate polysilicon and source polysilicon are further fabricated on the sides adjacent to the base region and drift region. A source region is further fabricated in a region away from the drain region in the base region, and the source region is heavily N-type doped (N+). A drain D is further provided on the surface of the drain region, and a P-type doped P-type ... sauce S is provided.

[0061] The on-resistance of the SGT MOS transistor is low. Therefore, using the SGT MOS transistor as the switching transistor 2 helps to reduce the loss of the switching transistor 2. As can be seen from FIGS. 8 and 9 , the source and drain of the LDMOS transistor are on the same plane, and the other side of the plane is the substrate, whereas in the SGT MOS transistor, one side is the source and the other side is the drain. Due to the different relative positions between the source and drain, the manufacturing process of the SGT MOS transistor is hardly compatible with the manufacturing process of the LDMOS transistor. In this embodiment of the present application, the SGT MOS transistor and the LDMOS transistor can be located on different dies. Therefore, compatibility issues between the manufacturing processes of the SGT MOS transistor and the LDMOS transistor can be avoided.

[0062] When the switching transistor 1 is an LDMOS transistor and the switching transistor 2 is an SGT MOS transistor, the switching transistor 2 can be arranged using a flip chip structure. Specifically, as shown in Figure 10, the DrMOS 60 can generally further include a substrate 63, and the substrate 63 can support the die 61 and the die 62.

[0063] Die 1 and die 2 are fixed on a substrate 63. A first surface of die 1 is placed on the side not facing the substrate 63. The first surface may be the surface on which a source S1 of a switching transistor 1 in die 1 is located. A second surface of die 2 is placed on the side not facing the substrate 63, and the second surface may be the surface on which a drain D2 of a switching transistor 2 in die 2 is located, and a source S2 of the switching transistor 2 is in contact with the substrate 63. The source S2 of the switching transistor 2 is connected to a metal line The drain D2 of the switching transistor 2 may be connected to the source S1 of the switching transistor 1 via a second conductor.

[0064] For example, the second conductor may be a lead or a conductor clip. As shown in FIG. 10 , the second conductor is a conductor clip, which can be understood as a metal plate with a bent structure. A first side of the conductor clip is connected to the source S1 of the switching transistor 1, the conductor clip covers the drain D2 of the switching transistor 2, and the side of the drain D2 away from the source S1 is bent toward the substrate 63. A second side of the conductor clip opposite the first side is bent toward the substrate 63 and fixed to the substrate 63. The second side of the conductor clip may be used as one of the connection ends for connecting the DrMOS 60 to another component. For example, in a buck circuit, the second side of the conductor clip may be used to connect the inductor L. The conductor clip has a larger current-carrying cross-sectional area than the lead, thereby reducing the current transmission loss between the source S1 of the switching transistor 1 and the drain D2 of the switching transistor 2.

[0065] To further reduce the losses of the DrMOS 60, in one possible implementation, the die 62 may further integrate a Schottky barrier diode (SBD). As shown in FIG. 7, the die 62 may further include an SBD. The anode of the SBD is connected to the source of the switching transistor 2, and the cathode of the SBD is connected to the drain of the switching transistor 2.

[0066] The SBD has a low conduction voltage drop VF and a small reverse recovery charge Qrr, which helps further reduce the loss of die 62. We use the conduction voltage drop VF as an example. As shown in FIG. 4, there is a dead time between the charging stage and the rectifying stage due to the inherent delay between switching on and off of the switching transistor. During the dead time, switching transistor 2 does not fully switch on. In this case, current can be transmitted through the SBD in parallel with switching transistor 2. The low conduction voltage drop VF of the SBD helps reduce the loss that occurs in the process of the SBD transmitting current, which helps further reduce the loss of die 62.

[0067] It can be understood that in addition to the driving circuit 3, the switching transistor 1, and the switching transistor 2, other structures may be integrated into the DrMOS provided in this embodiment of the present application to implement more functions. For example, the DrMOS may further include a temperature sensor, and an external component (e.g., the controller 104) may use the temperature sensor to obtain temperature information of the DrMOS. For example, the temperature sensor may be disposed in the die 61 or the die 62, or may be disposed independently of the die 61 and the die 62. This is not a limitation of this embodiment of the present application.

[0068] In another example, the DrMOS may further include a current sensor that allows an external component (e.g., the controller 104) to detect the magnitude of the current flowing through the switching transistor 1 when the switching transistor 1 is switched on. For example, the current sensor may be integrated into the die 61.

[0069] Based on the same technical concept, one embodiment of this application further provides a DrMOS manufacturing method, which can be used to manufacture the DrMOS provided in any of the above-mentioned embodiments. For example, as shown in FIG. 11, the DrMOS manufacturing method mainly includes the following steps:

[0070] S1101: Separately provide a first die and a second die, the first die including a driving circuit and a first switching transistor, the driving circuit being connected to a gate of the first switching transistor, and the second die including a second switching transistor, it should be understood that the driving circuit and the gate of the first switching transistor are connected to a metal layer in the first die. wiring For example, the first die may be prepared using a bipolar junction transistor-complementary metal oxide semiconductor-diffused metal oxide semiconductor (BCD) process, such that the first die integrates a driving circuit and a first switching transistor, and the driving circuit is connected to the gate of the first switching transistor. The second switching transistor may also be prepared using the BCD process. This is not limited in this embodiment of the application.

[0071] S1102: Connect the drive circuit to the gate of the second switching transistor via the first conductor.

[0072] In some switching power supply circuits, the source of the first switching transistor can also be connected to the drain of the second switching transistor. In this case, the source of the first switching transistor of the first die can also be connected to the drain of the second switching transistor of the second die using a second conductor. Thus, DrMOS can be adapted to this type of switching power supply circuit.

[0073] A buck circuit is used as an example. In this embodiment of the present application, the first switching transistor can be used as a drive switching transistor of the buck circuit, and the second switching transistor can be used as a rectifier switching transistor of the buck circuit. In this case, the first switching transistor can be implemented by a transistor with a high switching speed. For example, the first switching transistor can be an LDMOS transistor. The second switching transistor can be implemented by a transistor with a low on-resistance. For example, the second switching transistor can be an SGT MOS transistor.

[0074] When the DrMOS is used in a buck circuit, the source of the first switching transistor needs to be connected to the drain of the second switching transistor in the DrMOS. Specifically, after S1101 is performed, the first die and the second die are first fixed on the same surface of the substrate, and then S1102 is performed to connect a driving circuit to the gate of the second switching transistor using a first conductor.

[0075] In fixing the first die, the first surface of the first die can be placed on the side not facing the substrate, and the first surface can be the surface where the source of the first switching transistor (LDMOS transistor) is located. In fixing the second die, the second surface of the second die can be placed on the side not facing the substrate, and the second surface can be the surface where the drain of the second switching transistor (SGT MOS transistor) is located. Furthermore, the source of the first switching transistor can be directly connected to the drain of the second switching transistor via a second conductor. The second conductor can be a lead or a conductor clip. This is not limited in this embodiment of this application.

[0076] To further reduce losses in the second switching transistor, in one possible implementation, the second die may further include a Schottky barrier diode SBD. The anode of the SBD is connected to the source of the second switching transistor, and the cathode of the SBD is connected to the drain of the second switching transistor. The SBD has a low conduction voltage drop VF and a small reverse recovery charge Qrr, which helps reduce losses in the second switching transistor that occur during dead time.

[0077] Based on the same technical concept, an embodiment of this application further provides an integrated circuit. The integrated circuit may include the DrMOS provided in any of the above-described embodiments. For example, the integrated circuit may be the integrated circuit 101 shown in FIG. 8. In addition to the DrMOS 60 provided in this embodiment of this application, the integrated circuit may include an inductor L and a capacitor C. The switching transistor 1 and the switching transistor 2 of the DrMOS 60 may form a buck circuit with the inductor L and the capacitor C. One end of the inductor L is connected to the source of the switching transistor 1, and the other end of the inductor L is connected to one end of the capacitor C. The other end of the inductor L is configured to output an output voltage Vo, and the source of the switching transistor 2 and the other end of the capacitor C are grounded.

[0078] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application, and this application intends to cover those modifications and variations of this application as long as they fall within the scope of protection defined by the following claims and their equivalents.

Claims

1. 1. A driver metal oxide semiconductor field effect transistor (DrMOS) having a first die and a second die, the first die has a drive circuit and a first switching transistor, the drive circuit being connected to a gate of the first switching transistor via metal wiring within the first die; the second die has a second switching transistor, the drive circuit being connected to a gate of the second switching transistor via a first conductor; the first switching transistor is a laterally diffused metal oxide semiconductor (LDMOS) transistor and the second switching transistor is a split gate trench metal oxide semiconductor (SGT MOS) transistor; The DrMOS further comprises a substrate configured to carry the first die and the second die; a first surface of the first die is placed on a side facing away from the substrate, the first surface being a surface of the first die on which a source of the first switching transistor is located; a second surface of the second die is placed on a side facing away from the substrate, the second surface being a surface of the second die on which a drain of the second switching transistor is located; the source and the gate of the second switching transistor contact the substrate; the source of the first switching transistor is connected to the drain of the second switching transistor via a second conductor, the second conductor being a metal plate; DrMOS.

2. 2. The DrMOS of claim 1, wherein the DrMOS is used in a buck circuit, the first switching transistor is a drive switching transistor, and the second switching transistor is a rectifier switching transistor.

3. 3. The DrMOS of claim 2, wherein the second die further comprises a Schottky barrier diode (SBD), the anode of the SBD being connected to the source of the second switching transistor and the cathode of the SBD being connected to the drain of the second switching transistor.

4. The DrMOS according to claim 1 , further comprising a temperature sensor and / or a current sensor.

5. An integrated circuit comprising the DrMOS of any one of claims 1 to 4.

6. The integrated circuit further comprises an inductor and a capacitor; one end of the inductor is connected to the source of the first switching transistor, the other end of the inductor is connected to one end of the capacitor, and the other end of the inductor is configured to output an output voltage, and the source of the second switching transistor and the other end of the capacitor are grounded.

6. The integrated circuit of claim 5.

7. 7. An electronic device comprising the integrated circuit according to claim 5 or 6.

8. A DrMOS manufacturing method comprising the steps of: a first die and a second die are separately prepared, the first die has a driving circuit and a first switching transistor, the driving circuit is connected to a gate of the first switching transistor via a metal wiring in the first die, and the second die has a second switching transistor; the first die and the second die are fixed to a surface of a substrate, a first surface of the first die is placed on a side not facing the substrate, the first surface being a surface of the first die on which a source of the first switching transistor is located, a second surface of the second die is placed on a side not facing the substrate, the second surface being a surface of the second die on which a drain of the second switching transistor is located, and a source and a gate of the second switching transistor are in contact with the substrate; connecting the drive circuit to the gate of the second switching transistor via a first conductor; the source of the first switching transistor is connected to the drain of the second switching transistor via a second conductor, the second conductor being a metal plate; Having that, the first switching transistor is a laterally diffused metal oxide semiconductor (LDMOS) transistor, and the second switching transistor is a split gate trench metal oxide semiconductor (SGT MOS) transistor; method.

9. 9. The method of claim 8, wherein a DrMOS is used in a buck circuit, the first switching transistor being a drive switching transistor, and the second switching transistor being a rectifier switching transistor.

10. 10. The method of claim 8 or 9, wherein the second die further comprises a Schottky barrier diode (SBD), an anode of the SBD connected to the source of the second switching transistor, and a cathode of the SBD connected to the drain of the second switching transistor.

11. The separately preparing the first die and the second die includes: preparing the first die and / or the second die by using a bipolar junction transistor-complementary metal oxide semiconductor-diffused metal oxide semiconductor (BCD) process; 11. The method of any one of claims 8 to 10, comprising:

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