Switching element drive circuit and switching circuit

Abstract

To provide a switching element driving circuit in which a gate surge is reduced while reverse conduction loss is reduced.SOLUTION: A gate driving circuit is connected to a gate terminal and a switch terminal of a first switching element, and turns on / off the first switching element. The gate driving circuit comprises: a control unit that includes a first switch having a first terminal connected to the gate terminal and a second terminal connected to the source terminal, and being disposed between the first terminal and a power source, and a second switch disposed between the first terminal and the second terminal, and that closes the first switch to supply current from the first terminal to the gate terminal; a first resistor and a first capacitor having one end connected to the gate terminal and the other end connected to the first terminal, and being connected in parallel with each other; a second capacitor having one end connected to the source terminal and the other end connected to the second terminal; and a first Zener diode having a cathode terminal connected to the source terminal and an anode terminal connected to the second terminal, and being connected in parallel with the second capacitor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a driving circuit for a switching element and a switching circuit. [Background technology]

[0002] Conventionally, a technology has been proposed that uses a JFET or the like made of silicon carbide (SiC) as a switching element in a power converter or the like. In the drive circuit of such a switching element, a capacitor having a capacitance larger than the stray capacitance generated between the drain and gate is provided between the gate and source of the switching element to prevent malfunction. Furthermore, a technology has been proposed that uses a speed-up capacitor CgD to achieve negative biasing to prevent malfunction (see, for example, Patent Document 1). Similarly, a technology has also been proposed that uses a Zener diode to achieve negative biasing (see, for example, Patent Document 2).

[0003] Here, in the case of a negative bias voltage in the driving circuit of the conventional switching element as described above, there are cases where the gate surge of the switching element becomes large and the reverse conduction loss due to the internal diode increases. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-99133 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-93586 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-described problems, and aims to provide a technology that can reduce the gate surge of a switching element and reduce reverse conduction loss in a gate drive circuit of the switching element. [Means for solving the problem]

[0006] To solve the above problems, the present invention provides: a gate drive circuit connected to a gate terminal and a source terminal of the first switching element to turn on and off the first switching element, a control unit having a first terminal connected to the gate terminal and a second terminal connected to the source terminal, the control unit including a first switch provided between the first terminal and a voltage source, and a second switch provided between the first terminal and the second terminal, the control unit closing the first switch to supply a current from the first terminal to the gate terminal; a first resistor and a first capacitor, one end of which is connected to the gate terminal and the other end of which is connected to the first terminal, connected in parallel with each other; a second capacitor having one end connected to the source terminal and the other end connected to the second terminal; a first Zener diode having a cathode terminal connected to the source terminal and an anode terminal connected to the second terminal, the first Zener diode being connected in parallel to the second capacitor; The present invention is characterized by the following.

[0007] According to the present invention, when the gate of the first switching element is turned on, the first capacitor, the second capacitor, and the input capacitance of the first switching element are charged by a current supplied from the first terminal of the control unit to the gate terminal, and when the gate of the first switching element is turned off, the accumulated charge is discharged through the first resistor, so that a negative bias voltage is applied to the first switching element. The negative bias voltage applied in this manner does not increase suddenly when the gate of the first switching element is turned off, so that it is possible to reduce the gate surge of the first switching element and also reduce reverse conduction loss.

[0008] In addition, in the present invention, A Miller clamp circuit may be provided between the gate terminal and the one end of the first resistor and the first capacitor, and between the other end of the second capacitor and the anode terminal and the second terminal of the first Zener diode.

[0009] In this way, the gate voltage can be kept low when switching noise occurs in the first switching element, and it is possible to prevent a large voltage such as a surge voltage from being applied.

[0010] In addition, in the present invention, the Miller clamp circuit includes a second switching element that is turned on when a voltage vqs between the gate terminal and the one end of the first resistor and the first capacitor, and a voltage vqs between the other end of the second capacitor and the anode terminal of the first Zener diode and the second terminal becomes equal to or lower than a threshold voltage Vth, When the first switching element sequentially transitions through a plurality of modes including a first mode in which an input capacitance of the first switching element is charged and the first switching element is turned on, and a second mode in which the first switch is turned on, the second switch is turned off, and the first switching element is turned off, When the terminal voltage and capacitance of the first capacitor are vcp and Cp, respectively, the terminal voltage and capacitance of the second capacitor are vcs and Cs, respectively, the gate charge amount and input capacitance of the first switching element are Qg and Ciss, respectively, vcp and vcs at the end of the first mode are vcp_1 and vcs_1, respectively, the drain-source voltage of the second switching element at the end of the second mode is Vqs_2, and the terminal voltage of the first capacitor at the end of the second mode is Vcp_2,

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[0011] In this way, it is possible to realize two-stage turn-off of the first switching element, thereby realizing reductions in gate surge, switching noise, and reverse conduction loss.

[0012] In addition, in the present invention, The control unit may further include a second resistor having one end connected between the source terminal and the one end of the second capacitor and the cathode terminal of the first Zener diode, and the other end connected directly to the voltage source and a third terminal of the control unit.

[0013] This allows current to be supplied to the first Zener diode and the second capacitor from the voltage source, so that when the voltage source is present, the Zener potential, i.e., the negative bias voltage, can be maintained, improving noise immunity.

[0014] In addition, in the present invention, a third resistor having one end connected to the other end of the first capacitor and the other end connected to the other end of the first resistor; a fourth resistor and a first diode connected in series; One end of the fourth resistor may be connected to the other end of the first capacitor, the other end of the fourth resistor may be connected to the anode terminal of the first diode, and the cathode terminal of the first diode may be connected to the other end of the first resistor.

[0015] In this way, the switching speed of the first switching element can be adjusted by the resistance values ​​of the third resistor and the fourth resistor, thereby reducing the gate surge of the first switching element and also reducing switching noise.

[0016] In addition, in the present invention, The power supply may further include a Schottky diode having a cathode terminal connected to the first resistor and the one end of the first capacitor, and an anode terminal connected to the other end of the second capacitor and the anode terminal of the first Zener diode.

[0017] In this way, the gate surge of the first switching element can be reduced by the Schottky diode.

[0018] In addition, in the present invention, The power supply may further include a second Zener diode having a cathode terminal connected to the first resistor and the one end of the first capacitor, and an anode terminal connected to the one end of the second capacitor and the cathode terminal of the first Zener diode.

[0019] According to this, the second Zener diode can reduce the gate surge of the first switching element.

[0020] The present invention also provides a plurality of switching elements connected in series; a gate drive circuit connected to a gate terminal and a source terminal of the switching element to turn the switching element on and off; The switching circuit is characterized by comprising:

[0021] This makes it possible to reduce gate surges and reverse conduction losses in the switching elements that make up the switching circuit, thereby preventing malfunction of the switching circuit, reducing noise generation, and enabling higher efficiency. [Effects of the Invention]

[0022] According to the present invention, in a gate drive circuit for a switching element, it is possible to reduce the gate surge of the switching element and also reduce reverse conduction loss. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 2 is a diagram showing a circuit configuration of a gate drive circuit according to the first embodiment. [Figure 2] 1 is a diagram illustrating a circuit configuration of a synchronous rectification boost chopper circuit according to a first embodiment. [Figure 3] 4 is an operation sequence diagram of a switching element by the gate drive circuit according to the first embodiment. FIG. [Figure 4] 11A and 11B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 11. [Figure 5] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 12. [Figure 6] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 13. [Figure 7] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 14. [Figure 8] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 15. [Figure 9] 3 is an operation sequence diagram of the synchronous rectification type boost chopper circuit according to the first embodiment. FIG. [Figure 10] FIG. 10 is a diagram showing a circuit configuration of a gate drive circuit according to a second embodiment. [Figure 11] FIG. 10 is an operation sequence diagram of a switching element by a gate drive circuit according to a second embodiment. [Figure 12] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 21. [Figure 13] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 22. [Figure 14] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 23. [Figure 15] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 24. [Figure 16] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram illustrating mode 25. [Figure 17] 10A and 10B are an equivalent circuit diagram and an operation sequence diagram for explaining mode 26. [Figure 18] FIG. 10 is an operation sequence diagram of the synchronous rectification boost chopper circuit according to the second embodiment. [Figure 19] FIG. 10 is a diagram showing a circuit configuration of a gate drive circuit according to a third embodiment. [Figure 20] FIG. 10 is a diagram showing a circuit configuration of a gate drive circuit according to a fourth embodiment. [Figure 21] FIG. 10 is a diagram showing a circuit configuration of a gate drive circuit according to a fifth embodiment. [Figure 22] FIG. 10 is a diagram showing a circuit configuration of a gate drive circuit according to a sixth embodiment. [Figure 23] FIG. 2 is a simulation model circuit diagram of the gate drive circuit according to the first embodiment. [Figure 24] 4 is a graph showing a simulation result of the gate drive circuit according to the first embodiment. [Figure 25] FIG. 10 is a simulation model circuit diagram of a gate drive circuit according to a second embodiment. [Figure 26] 10 is a graph showing a simulation result of the gate drive circuit according to the second embodiment. [Figure 27] FIG. 10 is a diagram showing a schematic configuration of a switching circuit according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0024] [Application example] Hereinafter, application examples of the present invention will be described with reference to the drawings. A gate drive circuit 10 to which the present invention is applied can be used, for example, in gate drive circuits 10a and 10b of a synchronous rectification boost chopper circuit 100 shown in FIG. The synchronous rectifier boost chopper circuit 100 includes switching elements Q1 and Q2, gate drive circuits 10a and 10b, an input power supply Vin, a reactor L1, bypass capacitors C1 and C2, and a load Rout. In this synchronous rectifier boost chopper circuit 100, two switching elements Q1 and Q2 are connected in series, and gate drive circuits 10a and 10b are connected to them, respectively. The gate drive circuits 10a and 10b switch the switching elements Q1 and Q2 in accordance with input control signals In1 and In2, respectively, thereby boosting the input voltage Vin to a desired voltage and applying it to the load Rout.

[0025] 3 is an operation sequence diagram of the gate drive circuit 10. By switching the switches S1 and S2 of the control unit on and off as shown in the lower graph, the gate-source voltage vgs of the switching element Q1 changes as shown in the top graph. At this time, the gate-source voltage vgs transitions through each of the modes mode 11 to mode 15 in order.

[0026] As shown in Figure 3, in mode 13, which transitions from mode 12 in which switching element Q1 is turned on, switching element Q1 is turned off. This keeps the gate-source voltage vgs high and reduces surge voltage Sr1, thereby preventing breakdown of switching element Q1 and reducing reverse conduction loss. Furthermore, in the following mode 14, keeping the gate-source voltage low when switching noise occurs prevents false ignition.

[0027] FIG. 9 shows an operational sequence diagram when the gate drive circuit 10 according to the present invention is used in a switching circuit such as a synchronous rectifier boost chopper circuit 100. Maintaining high gate-source voltages vgs_Q1 and vgs_Q2 during gate turn-off of switching elements Q1 and Q2 reduces gate surges Sr11 and Sr12 during dead times DT11 and DT12 when both switching elements Q1 and Q2 are off, thereby maintaining the absolute maximum rating Vrat or higher. This prevents breakdown of switching elements Q1 and Q2 and reduces reverse conduction loss. Furthermore, maintaining low gate-source voltage vgs_Q1 below threshold voltage Vth0 during switching noise Sn1 generation prevents false firing. False firing of switching element Q2 can be similarly prevented. Such switching circuits may be half-bridge or full-bridge circuits, as long as they are circuits that perform switching by connecting multiple switching elements in series. These circuits include, but are not limited to, DC / DC converters and inverters.

[0028] Example 1 The gate drive circuit 10 according to the embodiment of the present invention will be described in more detail below with reference to the drawings.

[0029] <Device configuration> Fig. 1 shows a gate drive circuit 10 according to this embodiment. Fig. 2 shows a synchronous rectification boost chopper circuit 100 to which the gate drive circuit 10 is applied.

[0030] First, the synchronous rectification type boost chopper circuit 100 will be described. The synchronous rectifier boost chopper circuit 100 includes switching elements Q1 and Q2, gate drive circuits 10a and 10b, an input power supply Vin, a reactor L1, bypass capacitors C1 and C2, and a load Rout. In the synchronous rectifier boost chopper circuit 100, two switching elements Q1 and Q2 are connected in series, and gate drive circuits 10a and 10b are connected to them, respectively. The gate drive circuits 10a and 10b boost the input voltage Vin to a desired voltage and apply it to the load Rout by switching the switching elements Q1 and Q2 in accordance with input control signals In1 and In2, respectively. The following describes the gate drive circuit 10 applied to the gate drive circuit 10a of the synchronous rectifier boost chopper circuit 100, but the gate drive circuit 10 can also be applied to the gate drive circuit 10b.

[0031] Next, the gate drive circuit 10 will be described. One end of a capacitor Cp, which functions as a speed-up capacitor, is connected to the gate terminal G of the switching element Q1. A resistor Rp, which functions as a limiting resistor for allowing a small current to flow when the switching element Q1 is on, is connected in parallel to this capacitor Cp. The other end of this capacitor Cp is connected to the output terminal Vout of the gate driver 11. The source terminal S of the switching element Q1 is connected to the reference potential terminal GND of the gate driver 11 via a parallel-connected capacitor Cs and Zener diode Ds. That is, one end of the capacitor Cs is connected to the source terminal S of the switching element Q1, and the other end is connected to the reference potential terminal GND of the gate driver 11. The cathode terminal of the Zener diode Ds is connected to the source terminal S of the switching element Q1, and the anode terminal is connected to the reference potential terminal GND of the gate driver 11. The gate driver 11 has two switches S1 and S2 connected in series between the positive and negative terminals of a voltage source Vs. The switches S1 and S2 are, for example, formed of an n-channel MOSFET and a p-channel MOSFET. The midpoint between the switches S1 and S2 is connected to the other end of the capacitor Cp as an output terminal Vout. The gate driver 11 switches the switches S1 and S2 on and off based on an input signal Vsig. By turning on switch S1 and turning off switch S2, the other end of capacitor Cp is connected to the positive terminal of voltage source Vs via output terminal Vout, and gate current flows through switching element Q1 via capacitor Cp and resistor Rp. By turning off switch S1 and turning on switch S2, the other end of capacitor Cp is connected to reference potential terminal GND and the other end of capacitor Cs via output terminal Vout, and a negative bias voltage is applied between the gate and source of switching element Q1. Here, switching element Q1 corresponds to the first switching element of the present invention, capacitor Cp corresponds to the first capacitor of the present invention, resistor Rp corresponds to the first resistor of the present invention, capacitor Cs corresponds to the second capacitor of the present invention, Zener diode Ds corresponds to the first Zener diode of the present invention, gate driver 11 corresponds to the control unit of the present invention, output terminal Vout corresponds to the first terminal of the present invention, reference potential terminal GND corresponds to the second terminal of the present invention, switch S1 corresponds to the first switch of the present invention, and switch S2 corresponds to the second switch of the present invention.

[0032] The switching element Q1 (and Q2) can be, for example, a JFET, but is not limited to this. In Figure 1, the switching element Q1 is shown including the capacitance between each electrode: drain-source capacitance Cds, gate-drain capacitance Cgd, and gate-source capacitance Cgs. The input capacitance Ciss of the switching element Q1 is expressed as the sum of Cgs and Cgd.

[0033] The operating principle of the gate drive circuit 10 according to this embodiment will be described. FIG. 3 is an operation sequence diagram showing changes in the gate-source voltage vgs, the voltage vcp of the capacitor Cp, and the voltage vcs of the capacitor Cs when the switches S1 and S2 of the gate driver 11 of the gate drive circuit 10 are turned on and off. The gate drive circuit 10 transitions through five modes, namely, mode 11, mode 12, mode 13, mode 14, and mode 15, in order from when the switch S1 is turned on and then off, to when the switch S2 is turned on and then off, and finally when the switch S1 is turned on again. The gate-source voltage vgs of the switching element Q1 changes as shown in FIG. 3 according to the transitions from mode 11 to mode 15.

[0034] Figure 4(A) is an equivalent circuit of the gate drive circuit 10 in mode 11 when switch S1 is turned on, and Figure 4(B) is an operational sequence diagram in which mode 11 is shaded. In the equivalent circuit, dashed arrows indicate the current path and direction (this also applies to the equivalent circuits shown below). At this time, the input capacitance Ciss of switching element Q1 is charged through capacitor Cp, capacitor Cs, and Zener diode Ds, and as shown in Figure 4(B), the gate-source voltage vgs increases, causing switching element Q1 to transition to the turn-on state.

[0035] FIG. 5(A) is an equivalent circuit of the gate drive circuit 10 in mode 12, and FIG. 5(B) is an operation sequence diagram in which mode 12 is shaded. This is the period during which the input capacitance Ciss of the switching element Q1 is charged and the turn-on state continues. At this time, due to the parasitic diode of the switching element Q1, the gate-source voltage vgs of the switching element Q1 is kept constant at a constant voltage V, as shown in FIG. 5(B). F is clamped to

[0036] Figure 6(A) shows the equivalent circuit of the gate drive circuit 10 in mode 13 when switch S2 is turned on, and Figure 6(B) is an operational sequence diagram showing mode 13 shaded. At this time, the input capacitance Ciss of switching element Q1 is discharged through capacitor Cp, capacitor Cs, and Zener diode Ds, and switching element Q1 transitions to the turn-off state. As shown in Figure 6(B), in mode 13, the gate-source voltage vgs is turned off at a high voltage, reducing gate surge Sr1.

[0037] 7A is an equivalent circuit of the gate drive circuit 10 in mode 14, and FIG. 7B is an operation sequence diagram in which mode 14 is shaded. At this time, the switching element The input capacitance Ciss, capacitor Cp, and capacitor Cs of Q1 are charged and discharged through the Zener diode Ds. As shown in Figure 7(B), the gate-source voltage vgs of the switching element Q1 is maintained at a high voltage, reducing reverse conduction loss.

[0038] Figure 8(A) is an equivalent circuit of the gate drive circuit 10 in mode 15, and Figure 8(B) is an operation sequence diagram showing mode 15 shaded. At this time, the input capacitance Ciss and capacitor Cs of the switching element Q1 are discharged through resistor Rp and Zener diode Ds. By increasing the capacitance of capacitor Cs, the gate-source voltage vgs of the switching element Q1 is maintained at the Zener potential VN of the Zener diode Ds, as shown in Figure 8(B).

[0039] Fig. 9 shows an operation sequence diagram of a synchronous rectifier boost chopper circuit 100 in which the above-described gate drive circuit 10 is applied to gate drive circuits 10a and 10b. In Fig. 9, vds_Q1 and vds_Q2 indicate the drain-source voltages of switching element Q1 and switching element Q2, respectively, and vgs_Q1 and vgs_Q2 indicate the gate-source voltages of switching element Q1 and switching element Q2, respectively. In1 and In2 are input signals to gate drive circuits 10a and 10b.

[0040] As shown in Figure 9, by using gate drive circuit 10, gate-source voltages vgs_Q1 and vgs_Q2 of switching elements Q1 and Q2 are kept high during gate turn-off. This reduces gate surges Sr11 and Sr12 during dead times DT11 and DT12 when both switching elements Q1 and Q2 are off, and keeps them above the absolute maximum rating Vrat. This prevents breakdown of switching elements Q1 and Q2 and reduces reverse conduction loss. Furthermore, by keeping gate-source voltage vgs_Q1 low during switching noise Sn1, below threshold voltage Vth0, false ignition can be suppressed. False ignition can also be suppressed for switching element Q2. This makes it possible to reduce gate surges in the switching elements that make up the synchronous rectifier boost chopper circuit 100. This prevents malfunction of the synchronous rectifier boost chopper circuit 100, making it possible to achieve a highly reliable synchronous rectifier boost chopper circuit 100.

[0041] Example 2 Second Embodiment A gate drive circuit 20 according to a second embodiment of the present invention will be described below with reference to FIG. The same components as those in the first embodiment are denoted by the same reference numerals and detailed description thereof will be omitted. In this embodiment, a Miller clamp circuit 12 is provided in the gate drive circuit 10 of the first embodiment. The Miller clamp circuit 12 includes a switching element Qs and a clamp logic circuit 121. The switching element Qs is connected between the gate terminal G of the switching element Q1 and one end of the capacitor Cp and resistor Rp, and between the other end of the capacitor Cs and the anode terminal of the Zener diode Ds. Here, an n-channel MOSFET is used as the switching element Qs, and the drain terminal of the switching element Qs is connected to the gate terminal G of the switching element Q1, and the source terminal of the switching element Qs is connected to the other end of the capacitor Cs and the anode terminal of the Zener diode Ds. The gate terminal of the switching element Qs is connected to the clamp logic circuit 121. The clamp logic circuit 121 operates so that the switching element Qs is turned on when the drain voltage of the switching element Qs falls below Vth. At this time, the switching element Q1 is turned off in two stages by satisfying the following equation: Here, Vqs_23 and Vcp_23 are the drain-source voltage vqs of the switching element Qs and the voltage vcp of the capacitor Cp at the end of mode 23, respectively. Also, Vcp_22 and Vcs_22 are the terminal voltage vcp of the capacitor Cp and the terminal voltage vcs of the capacitor Cs at the end of mode 22. Cp and Cs indicate the capacitances of the capacitors Cp and Cs. Qg and Ciss are the gate charge and input capacitance of the switching element Q1. Vth is the threshold voltage at which the switching element Qs of the Miller clamp circuit 12 turns on.

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[0042] The operating principle of the gate drive circuit 20 according to this embodiment will be described. FIG. 11 is an operation sequence diagram showing changes in the gate-source voltage vgs, the voltage vcp of the capacitor Cp, and the voltage vcs of the capacitor Cs when the switches S1 and S2 of the gate driver 11 of the gate drive circuit 20 are turned on and off. The gate drive circuit 10 sequentially transitions through six modes: mode 21, mode 22, mode 23, mode 24, mode 25, and mode 26, as the switch S1 is turned on and then off, then the switch S2 is turned on and then off, and then the switch S1 is turned on again. The gate-source voltage vgs of the switching element Q1 changes as shown in FIG. 11 according to the transitions from mode 21 to mode 26.

[0043] Fig. 12(A) is an equivalent circuit of the gate drive circuit 20 in mode 21 when the switch S1 is turned on, and Fig. 12(B) is an operation sequence diagram in which mode 21 is shaded. At this time, the input capacitance Ciss of the switching element Q1 is charged through the capacitors Cp, Cs, and Zener diode Ds, and as shown in Fig. 12(B), the gate-source voltage vgs increases, and the switching element Q1 transitions to the turn-on state.

[0044] FIG. 13(A) is an equivalent circuit of the gate drive circuit 20 in mode 22, and FIG. 13(B) is an operation sequence diagram in which mode 22 is shaded. This is the period during which the input capacitance Ciss of the switching element Q1 is charged and the turn-on state continues. At this time, due to the parasitic diode of the switching element Q1, the gate-source voltage vgs of the switching element Q1 is kept constant at a constant voltage V as shown in FIG. 13(B). F is clamped to

[0045] Figure 14(A) shows the equivalent circuit of the gate drive circuit 20 in mode 23 when switch S2 is turned on, and Figure 14(B) is an operational sequence diagram showing mode 23 shaded. At this time, the input capacitance Ciss of switching element Q1 is discharged through capacitor Cp, capacitor Cs, and Zener diode Ds, and switching element Q1 transitions to the turn-off state. As shown in Figure 14(B), in mode 23, the gate-source voltage vgs is turned off at a high voltage, reducing gate surge Sr2.

[0046] FIG. 15(A) is an equivalent circuit of the gate drive circuit 20 in mode 24, and FIG. 15(B) is an operation sequence diagram in which mode 24 is shaded. At this time, switching The input capacitance Ciss, capacitor Cp, and capacitor Cs of element Q1 are charged and discharged through the Zener diode Ds and resistor Rp. As shown in Figure 15(B), the gate-source voltage vgs of switching element Q1 is maintained at a high voltage, reducing reverse conduction loss.

[0047] Figure 16(A) is an equivalent circuit of the gate drive circuit 20 in mode 25, and Figure 16(B) is an operational sequence diagram in which mode 25 is shaded. When the drain-source voltage of switching element Qs falls below vth, switching element Qs transitions to a conductive state. This achieves two-stage turn-off of switching element Q1. In this way, by increasing the negative bias value, it is possible to prevent malfunctions caused by switching noise during switching of the switching element of the opposing arm (switching element Q2 in Figure 2).

[0048] Figure 17(A) is an equivalent circuit of the gate drive circuit 20 in mode 26, and Figure 17(B) is an operation sequence diagram in which mode 26 is shaded. At this time, the input capacitance Ciss and capacitor Cs of the switching element Q1 are discharged through the switching element Qs and Zener diode Ds. By increasing the capacitance of capacitor Cs, the gate-source voltage vgs of the switching element Q1 can be maintained at the Zener potential of the Zener diode Ds.

[0049] FIG. 18 shows an operation sequence diagram of a synchronous rectifier boost chopper circuit 100 in which the above-described gate drive circuit 20 is applied to gate drive circuits 10a and 10b. In FIG. 18, vds_Q1 and vds_Q2 indicate the drain-source voltages of switching element Q1 and switching element Q2, respectively, and vgs_Q1 and vgs_Q2 indicate the gate-source voltages of switching element Q1 and switching element Q2, respectively. In1 and In2 are input signals to gate drive circuits 10a and 10b.

[0050] As shown in FIG. 18, by adding the Miller clamp circuit 12 to the gate drive circuit 20, the switching element Qs enters a conductive state when the drain voltage of the switching element Qs falls below Vth. This enables the gate-source voltage vgs of the switching element Q1 to be turned off in two stages. By turning off the switching element Q1 at a high voltage in the first stage, the gate surge Sr21 during the dead time DT21 when both the switching elements Q1 and Q2 are off is reduced. By keeping the gate surge Sr21 above Vrat (as well as Sr22 during the dead time DT22), damage to the switching element Q1 (and the switching element Q2 as well) can be prevented and reverse conduction loss can be reduced. Furthermore, by turning on the switching element Qs of the Miller clamp circuit 12 before the switching element of the opposing arm (switching element Q2 in FIG. 2) switches, the gate-source voltage vgs of the switching element Q1 can be lowered when the switching element of the opposing arm switches. This reduces malfunctions. Furthermore, by reducing the impedance of the switching noise current path by the switching element Qs, it is possible to reduce the switching noise of the switching element Q1 and suppress malfunctions.

[0051] Example 3 Third Embodiment A gate drive circuit 30 according to a third embodiment of the present invention will be described below with reference to FIG. The same components as those in the first and second embodiments are denoted by the same reference numerals and detailed description thereof will be omitted. In this embodiment, a resistor Rs is added to the gate drive circuit 20 according to the second embodiment. One end of the resistor Rs is connected between one end of the capacitor Cs and the cathode terminal of the Zener diode Ds and the source terminal S of the switching element Q1, and the other end of the resistor Rs is connected to the Vd terminal between the positive terminal of the voltage source Vs and the switch S1 of the gate driver 11. In other words, the other end of the resistor Rs is directly connected to the positive terminal of the voltage source Vs and is also connected to the Vd terminal between the positive terminal of the voltage source Vs and the gate The output terminal Vout of the output driver 11 is connected via a switch S1. Here, the resistor Rs corresponds to the second resistor of the present invention, and the Vd terminal corresponds to the third terminal of the present invention.

[0052] In the gate drive circuit 30, a current can be supplied to the Zener diode Ds and the capacitor Cs via the voltage source Vs. Therefore, the Zener potential (negative bias voltage) can be maintained by the voltage source Vs in any case.

[0053] Example 4 A gate drive circuit 40 according to a fourth embodiment of the present invention will be described below with reference to FIG. The same components as those in Examples 1 to 3 are denoted by the same reference numerals and detailed description thereof will be omitted. In this example, a resistor Rgon, a resistor Rgoff, and a diode Dp are added to the gate drive circuit 30 according to Example 3.

[0054] One end of the resistor Rgon is connected to the other end of the capacitor Cp, and the other end of the resistor Rgon is connected to the output terminal Vout of the gate driver 11 and the other end of the resistor Rp. Therefore, the resistor Rgon is connected in series with the capacitor Cp, and the resistor Rgon and the capacitor Cp are connected in parallel to the resistor Rp. Furthermore, the resistor Rgoff and diode Dp, which are connected in series, are connected in parallel to the resistor Rgon. One end of the resistor Rgoff is connected to one end of the resistor Rgon, i.e., the other end of the capacitor Cp, and the other end of the resistor Rgoff is connected to the anode terminal of the diode Dp. The cathode terminal of the diode Dp is connected to the other end of the resistor Rgon, i.e., the other end of the resistor Rp and the output terminal Vout of the gate driver 11. Here, the resistor Rgon, the resistor Rgoff, and the diode Dp correspond to the third resistor, the fourth resistor, and the first diode of the present invention, respectively.

[0055] In the gate drive circuit 40, the turn-on and turn-off switching speeds of the switching element Q1 can be changed by changing the resistance values ​​of the resistors Rgon and Rgoff.

[0056] In this embodiment, by changing the switching speed, it is possible to prevent erroneous firing and reduce gate surges.

[0057] Example 4 A gate drive circuit 50 according to a fifth embodiment of the present invention will be described below with reference to FIG. The same components as those in Examples 1 to 4 are denoted by the same reference numerals and detailed description thereof will be omitted. In this example, a Schottky diode Dt is added to the gate drive circuit 40 according to Example 4.

[0058] In the gate drive circuit 50, the cathode terminal of the Schottky diode Dt is connected to the gate terminal G of the switching element Q1, one end of the resistor Rp and the capacitor Cp, and the drain terminal of the switching element Qs of the Miller clamp circuit 12. The anode terminal of the diode Dt is connected to the other end of the capacitor Cs, the anode terminal of the Zener diode Ds, and the source terminal of the switching element Qs of the Miller clamp circuit 12, i.e., the reference potential terminal GND of the gate driver 11. Here, the Schottky diode Dt corresponds to the Schottky diode of the present invention.

[0059] In the gate drive circuit 50, the diode Dt is provided, so that the switching element The switching noise of Q1 can be reduced.

[0060] Example 5 Sixth Embodiment A gate drive circuit 60 according to a sixth embodiment of the present invention will be described below with reference to FIG. The same components as those in Examples 1 to 5 are denoted by the same reference numerals and detailed description thereof will be omitted. In this example, a Zener diode Df is added to the gate drive circuit 50 according to Example 5.

[0061] In the gate drive circuit 60, the cathode terminal of the Zener diode Df is connected between the gate terminal G of the switching element Q1 and one end of the resistor Rp and the capacitor Cp. The anode terminal of the Zener diode Df is connected between the source terminal S of the switching element Q1 and one end of the resistor Rs and the capacitor Cs as well as the cathode terminal of the Zener diode Ds. Here, the Zener diode Df corresponds to the second Zener diode of the present invention.

[0062] By providing the Zener diode Df in the gate drive circuit 60, it is possible to reduce the switching noise of the switching element Q1.

[0063] (Simulation 1) A gate drive circuit 10S shown in FIG. 23 was created as a model corresponding to the gate drive circuit 10 according to Example 1 shown in FIG. 1, and the effect of negative biasing was confirmed using circuit simulator software.

[0064] In the circuit simulator, the simulation was performed with the gate power supply set to 12 V, the drive frequency set to 100 kHz, the duty set to 50%, the resistance value of the resistor Rp set to 130 Ω, the capacitance of the capacitor Cp set to 600 pF, and the capacitance of the capacitor Cs set to 10 μF.

[0065] The simulation results are shown in Figure 24. The upper row shows the gate-source voltage vgs of the switching element Q1, and the lower row shows the input signal In. The turn-off time when the input signal In is turned off is shown shaded in Figure 23. The simulation results shown in Figure 24 confirm that the gate drive circuit 10 can achieve turn-off when the gate-source voltage vgs is high.

[0066] (Simulation 2) A gate drive circuit 20S shown in FIG. 25 was created as a model corresponding to the gate drive circuit 20 according to the second embodiment shown in FIG. 10, and the effect of negative biasing was confirmed using circuit simulator software.

[0067] In the circuit simulator, the gate power supply was set to 12 V, the drive frequency to 100 kHz, the duty to 50%, the resistance value of resistor Rp to 130 Ω, the capacitance of capacitor Cp to 600 pF, and the capacitance of capacitor Cs to 10 μF, and a MOSFET Qs functioning as a Miller clamp circuit 12 was added to perform the simulation.

[0068] Figure 26 shows the simulation results. The upper row shows the gate-source voltage vgs of the switching element Q1, and the lower row shows the input signal In. The time of turn-off when the input signal In is turned off is shown by the shaded area in Figure 23. The simulation results shown in Figure 26 confirm that the gate drive circuit 10 is able to achieve turn-off when the gate-source voltage vgs is high. Also, as shown in Figure 26, when the MOSFET Qs is turned on, the gate-source voltage vgs of the switching element Q1 attenuates sharply. This suggests that, for example, In the synchronous rectification type boost chopper circuit 100 using the gate drive circuit 20, it has been shown that by lowering the gate-source voltage vgs of the switching element Q1 when switching the opposing arm switching element (switching element Q2 in Figure 2), it is possible to reduce switching noise and suppress malfunctions.

[0069] (Variation) The synchronous rectification boost chopper circuit 100, which is a half-bridge circuit in which two switching elements are connected in series, has been described as a switching circuit to which the gate drive circuits 10 to 50 according to Examples 1 to 5 can be applied as gate drive circuits for switching elements. However, the switching circuits to which the gate drive circuits 10 to 50 according to Examples 1 to 5 can be applied as gate drive circuits for switching elements are not limited to this. For example, as shown in FIG. 27, the gate drive circuits 10 to 50 according to Examples 1 to 5 can be applied as gate drive circuits 10a to 10d for switching elements Q1 to Q4 included in a switching circuit 200 configured as a full-bridge circuit in which two switching elements Q1 and Q2 connected in series and switching elements Q3 and Q4 connected in series are connected in parallel.

[0070] Any switching circuit may be used, such as a DC / DC converter or an inverter, as long as it has a plurality of switching elements connected in series and driven by the gate drive circuit according to the embodiment of the present invention.

[0071] <Appendix 1> A gate drive circuit 10 is connected to a gate terminal (G) and a source terminal (S) of a first switching element (Q1) to turn the first switching element (Q1) on and off, a control unit (11) having a first terminal (Vout) connected to the gate terminal (G) and a second terminal (GND) connected to the source terminal (S), a first switch (S1) provided between the first terminal (Vout) and a voltage source (Vs), and a second switch (S2) provided between the first terminal (Vout) and the second terminal (GND), and closing the first switch (S1) to supply a current from the first terminal (Vout) to the gate terminal (G); a first resistor (Rp) and a first capacitor (Cp) connected in parallel to each other, one end of which is connected to the gate terminal (G) and the other end of which is connected to the first terminal (Vout); a second capacitor (Cs) having one end connected to the source terminal (S) and the other end connected to the second terminal (GND); a first Zener diode (Ds) having a cathode terminal connected to the source terminal (S) and an anode terminal connected to the second terminal (GND), the first Zener diode (Ds) being connected in parallel to the second capacitor (Cs); A gate drive circuit (10) comprising: [Explanation of symbols]

[0072] 10: Gate drive circuit 11: Gate driver 100: Synchronous rectification boost chopper circuit Q1: Switching element S1, S2: Switch Rp :Resistance Cp, Cs: Capacitor Ds: Zener diode

Claims

1. a gate drive circuit connected to a gate terminal and a source terminal of the first switching element to turn on and off the first switching element, a control unit having a first terminal connected to the gate terminal and a second terminal connected to the source terminal, the first switch being provided between the first terminal and a voltage source, and a second switch being provided between the first terminal and the second terminal, the control unit switching the first switch and the second switch to control the on / off of the first switching element; a first resistor and a first capacitor connected in parallel to each other, one end of which is connected to the gate terminal and the other end of which is connected to the first terminal; a second capacitor having one end connected to the source terminal and the other end connected to the second terminal; a first Zener diode having a cathode terminal connected to the source terminal and an anode terminal connected to the second terminal, the first Zener diode being connected in parallel to the second capacitor; a Miller clamp circuit between the gate terminal and the one end of the first resistor and the first capacitor, and between the other end of the second capacitor and the anode terminal of the first Zener diode and the second terminal; the Miller clamp circuit includes a second switching element that is turned on when a voltage vqs between the gate terminal and the one end of the first resistor and the first capacitor, and a voltage vqs between the other end of the second capacitor and the anode terminal of the first Zener diode and the second terminal becomes equal to or lower than a threshold voltage Vth, When the first switching element sequentially transitions through a plurality of modes including a first mode in which an input capacitance of the first switching element is charged and the first switching element is turned on, and a second mode in which the first switch is turned off, the second switch is turned on, and the first switching element is turned off, The terminal voltage and capacitance of the first capacitor are vcp and Cp, respectively, the terminal voltage and capacitance of the second capacitor are vcs and Cs, respectively, the gate charge amount and input capacitance of the first switching element are Qg and Ciss, respectively, vcp and vcs at the end of the first mode are vcp_1 and vcs_1, respectively, and the terminal voltage and capacitance of the second switching element are vcp_2 and vcs_3 at the end of the second mode. When the drain-source voltage of the switching element is Vqs_2 and the terminal voltage of the first capacitor at the end of the second mode is Vcp_2, [Equation 1] A gate drive circuit characterized by satisfying the above.

2. 2. The gate drive circuit according to claim 1, further comprising a second resistor having one end connected between the source terminal, the one end of the second capacitor, and the cathode terminal of the first Zener diode, and the other end connected to a third terminal of the control unit that is directly connected to the voltage source.

3. a third resistor having one end connected to the other end of the first capacitor and the other end connected to the other end of the first resistor; a fourth resistor and a first diode connected in series; 3. The gate drive circuit according to claim 1, wherein one end of the fourth resistor is connected to the other end of the first capacitor, the other end of the fourth resistor is connected to an anode terminal of the first diode, and the cathode terminal of the first diode is connected to the other end of the first resistor.

4. A gate drive circuit connected to a gate terminal and a source terminal of a first switching element, for turning on and off the first switching element, a control unit having a first terminal connected to the gate terminal and a second terminal connected to the source terminal, the first switch being provided between the first terminal and a voltage source, and a second switch being provided between the first terminal and the second terminal, the control unit switching the first switch and the second switch to control the on / off of the first switching element; a first resistor and a first capacitor connected in parallel to each other, one end of which is connected to the gate terminal and the other end of which is connected to the first terminal; a second capacitor having one end connected to the source terminal and the other end connected to the second terminal; a first Zener diode having a cathode terminal connected to the source terminal and an anode terminal connected to the second terminal, the first Zener diode being connected in parallel to the second capacitor; a second resistor having one end connected between the source terminal and the one end of the second capacitor and the cathode terminal of the first Zener diode, and the other end connected to a third terminal of the control unit that is directly connected to the voltage source.

5. A gate drive circuit connected to a gate terminal and a source terminal of a first switching element, for turning on and off the first switching element, a control unit having a first terminal connected to the gate terminal and a second terminal connected to the source terminal, the first switch being provided between the first terminal and a voltage source, and a second switch being provided between the first terminal and the second terminal, the control unit switching the first switch and the second switch to control the on / off of the first switching element; a first resistor and a first capacitor connected in parallel to each other, one end of which is connected to the gate terminal and the other end of which is connected to the first terminal; a second capacitor having one end connected to the source terminal and the other end connected to the second terminal; a cathode terminal connected to the source terminal and an anode terminal connected to the second terminal; a first Zener diode connected in parallel with the second capacitor; a third resistor having one end connected to the other end of the first capacitor and the other end connected to the other end of the first resistor; a fourth resistor and a first diode connected in series; one end of the fourth resistor is connected to the other end of the first capacitor, the other end of the fourth resistor is connected to an anode terminal of the first diode, and the cathode terminal of the first diode is connected to the other end of the first resistor.

6. A gate drive circuit connected to a gate terminal and a source terminal of a first switching element, for turning on and off the first switching element, a control unit having a first terminal connected to the gate terminal and a second terminal connected to the source terminal, the first switch being provided between the first terminal and a voltage source, and a second switch being provided between the first terminal and the second terminal, the control unit switching the first switch and the second switch to control the on / off of the first switching element; a first resistor and a first capacitor connected in parallel to each other, one end of which is connected to the gate terminal and the other end of which is connected to the first terminal; a second capacitor having one end connected to the source terminal and the other end connected to the second terminal; a first Zener diode having a cathode terminal connected to the source terminal and an anode terminal connected to the second terminal, the first Zener diode being connected in parallel to the second capacitor; a second resistor connected to a third terminal of the control unit, the second resistor having one end connected between the source terminal and the one end of the second capacitor and the cathode terminal of the first Zener diode, and the other end connected directly to the voltage source; a third resistor having one end connected to the other end of the first capacitor and the other end connected to the other end of the first resistor; a fourth resistor and a first diode connected in series; one end of the fourth resistor is connected to the other end of the first capacitor, the other end of the fourth resistor is connected to an anode terminal of the first diode, and the cathode terminal of the first diode is connected to the other end of the first resistor.

7. A gate drive circuit as described in any one of claims 4 to 6, characterized in that a Miller clamp circuit is provided between the gate terminal and the first resistor and the one end of the first capacitor, and between the other end of the second capacitor and the anode terminal and the second terminal of the first Zener diode.

8. 8. The gate drive circuit according to claim 1, further comprising a Schottky diode having a cathode terminal connected to the first resistor and the one end of the first capacitor, and an anode terminal connected to the other end of the second capacitor and the anode terminal of the first Zener diode.

9. 9. The gate drive circuit according to claim 1, further comprising a second Zener diode having a cathode terminal connected to the first resistor and the one end of the first capacitor, and an anode terminal connected to the one end of the second capacitor and the cathode terminal of the first Zener diode.

10. a plurality of switching elements connected in series; a gate drive circuit according to any one of claims 1 to 9, which is connected to a gate terminal and a source terminal of the switching element and turns the switching element on and off; A switching circuit comprising:

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