Semiconductor Devices

Abstract

To provide a semiconductor device capable of interrupting current flowing when a battery is reversely connected.SOLUTION: A semiconductor device includes a first terminal to which a first voltage is applied, a second terminal to which a second voltage lower than the first voltage is applied, a third terminal to which a load is connected, a first diode having an anode connected to the first terminal, a first MOS transistor which has a source electrode connected to the third terminal and a drain electrode connected to the cathode of the first diode, a drive circuit for controlling on / off of the first MOS transistor, a second diode which has a cathode connected to the second terminal and an anode connected to the drive circuit, and a third diode which has a cathode connected to a node where the third terminal and the source electrode of the first MOS transistor are connected, and an anode connected to the drive circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses an in-vehicle semiconductor device that cuts off current flowing in the reverse direction through a ground terminal when the battery electrodes are connected in reverse (hereinafter referred to as reverse connection). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-95159 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the semiconductor device of Patent Document 1, if the battery is connected in reverse, there is a risk that a current will flow through the terminal connected to the load.

[0005] The present invention has been made in consideration of the above-mentioned conventional problems, and its purpose is to provide a semiconductor device that can cut off the current that flows when a battery is reverse-connected. [Means for solving the problem]

[0006] The semiconductor device of the present invention, which solves the above-mentioned problems, includes a first terminal to which a first voltage is applied, a second terminal to which a second voltage lower than the first voltage is applied, a third terminal to which a load is connected, a first diode having an anode connected to the first terminal, a first MOS transistor having a source electrode connected to the third terminal and a drain electrode connected to the cathode of the first diode, a drive circuit that controls the on / off of the first MOS transistor, a second diode having a cathode connected to the second terminal and an anode connected to the drive circuit, and a third diode having a cathode connected to a node at which the third terminal and the source electrode of the first MOS transistor are connected, and an anode connected to the drive circuit. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device that can cut off a current that flows when a battery is reversely connected. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing the configuration of a motor control device 10. FIG. [Figure 2] FIG. 2 is a diagram showing the configuration of a power supply circuit 51. [Figure 3] 2 is a diagram for explaining a semiconductor substrate 200 on which a control IC 50 is formed. FIG. [Figure 4] FIG. 10 is a diagram showing the configuration of a diode D3. [Figure 5] FIG. 10 is an explanatory diagram of a comparative example in which the battery 1 is reversely connected. [Figure 6] FIG. 6A is an explanatory diagram of motor control device 10A and ECU 300 of a comparative example, and FIG. 6B is an explanatory diagram of blocking of reverse current in the comparative example. [Figure 7] FIG. 2 is an explanatory diagram of a case where the battery 1 is reverse-connected in this embodiment. [Figure 8] FIG. 10 is an explanatory diagram of a modified example (IPS31) of IPS30. DETAILED DESCRIPTION OF THE INVENTION

[0009] At least the following matters will become clear from the description of this specification and the accompanying drawings.

[0010] =====This embodiment===== FIG. 1 is a diagram showing the configuration of a motor control device 10 according to one embodiment of the present invention. The motor control device 10 of this embodiment is a device for controlling a load (here, a motor 12) provided in an automobile using power from a battery 1. The motor control device 10 includes a microcomputer 20 and an IPS (Intelligent Power Switch) 30. Although not shown, the automobile is also provided with an electronic control unit (ECU) and the like that controls the motor control device 10 using power from the battery 1.

[0011] Battery 1 is, for example, a lithium-ion battery for automobiles, and outputs a voltage Vcc (for example, 12 V). The voltage Vcc corresponds to a "first voltage." The voltage on the negative electrode side of battery 1 is a voltage Vgnd (for example, 0 V) ​​lower than the voltage Vcc, and corresponds to a "second voltage."

[0012] The microcomputer 20 controls the IPS 30 based on instructions (not shown) input from the outside (for example, an ECU). Specifically, the microcomputer 20 outputs an instruction signal Sa for controlling (controlling the on / off of) NMOS transistors M1 and M2 of the IPS 30, which will be described later.

[0013] The IPS 30 is a "semiconductor device" that switches whether or not the voltage Vcc of the battery 1 is supplied to the motor 12, which is a load, based on the instruction signal Sa output from the microcomputer 20.

[0014] Also, although details will be described later, the IPS30 of the present embodiment appropriately protects the motor 12 and the ECU when the battery 1 is reversely connected. Note that "reverse connection" refers to a state where the electrodes of the battery 1 are reversely connected. Specifically, it refers to a state where the positive electrode of the battery 1 is connected to the ground-side terminals (for example, terminals C and D), and the negative electrode of the battery 1 is connected to the power-source-side terminal (for example, terminal A).

[0015] <<<Configuration of IPS30>>> The IPS30 includes an IC (Integrated Circuit) 40 in which a switch X1 (described later) is formed, and a control IC50 that performs control for turning on and off the switch X1. Note that the IC40 corresponds to the "first chip", and the control IC50 corresponds to the "second chip".

[0016] Also, the IPS30 of the present embodiment has terminals A to D, and further includes a package capable of accommodating the IC40 and the control IC50. Thereby, the IC40, the control IC50, and the terminals A to D are integrated in the IPS30 (configured as one semiconductor module). Note that although terminals are also provided for the IC40 and the control IC50 respectively, in the present embodiment, for the sake of simplification, the illustration of the terminals of the IC40 and the control IC50 is omitted.

[0017] Terminal A is a terminal connected to the positive electrode of the battery 1, to which a power supply voltage (voltage Vcc) is applied.

[0018] Terminal B is a signal input terminal, and in the present embodiment, an instruction signal Sa is input from the microcomputer 20.

[0019] Terminal C is a terminal connected to the negative electrode of the battery 1, to which a ground voltage (voltage Vgnd) is applied.

[0020] Terminal D is connected to the motor 12, which is a load, and is also connected to the negative electrode of the battery 1 via the motor 12. As a result, when the NMOS transistors M1 and M2 are off, terminal D is grounded via the coil (not shown) of the motor 12.

[0021] In the IPS 30 of this embodiment, the terminal A corresponds to the "first terminal", the terminal C corresponds to the "second terminal", and the terminal D corresponds to the "third terminal".

[0022] <<IC40について> > IC40 is an integrated circuit including two MOS transistors that constitute a switch (hereinafter referred to as "switch X1") for switching whether or not the voltage Vcc applied to terminal A is output from terminal D. In this embodiment, the two MOS transistors are NMOS transistors M1 and M2.

[0023] The source electrode of the NMOS transistor M1 is connected to a terminal D to which a load (here, the motor 12) is connected. In this embodiment, "connection" means electrical connection. For example, an element (such as a resistor) or a terminal may be provided along the wiring (line) that makes the connection. Specifically, the IC40 is provided with a terminal (not shown) that is connected to the source electrode of the NMOS transistor M1, and the source electrode of the NMOS transistor M1 is connected to the terminal D via that terminal (a terminal of the IC40).

[0024] The drain electrode of the NMOS transistor M1 is connected to the drain electrode of the NMOS transistor M2. A diode 41 (parasitic diode) is formed as a body diode between the source electrode and drain electrode of the NMOS transistor M1. A drive voltage Vcp is applied to the gate electrode of the NMOS transistor M1 from a drive circuit 52 (described later). The NMOS transistor M1 corresponds to the "first MOS transistor."

[0025] The source electrode of the NMOS transistor M2 is connected to a terminal A to which a power supply voltage Vcc is applied.

[0026] Furthermore, a diode 42 is formed as a body diode (parasitic diode) between the source electrode and drain electrode of the NMOS transistor M2. A drive voltage Vcp is applied to the gate electrode of the NMOS transistor M2 from a drive circuit 52 (described later). The NMOS transistor M2 corresponds to the "third MOS transistor," and the diode 42 corresponds to the "first diode."

[0027] Here, the drain electrodes of the NMOS transistors M1 and M2 are connected in series, the source electrode of the NMOS transistor M1 is connected to terminal D, and the source electrode of the NMOS transistor M2 is connected to terminal A. Therefore, when the NMOS transistors M1 and M2 are both turned on, the voltage Vcc applied to terminal A is output from terminal D via the NMOS transistors M1 and M2.

[0028] The anode of diode 42 is connected to terminal A, and the cathode of diode 42 is connected to the cathode of diode 41. The anode of diode 41 is connected to terminal D. Therefore, the cathodes of diodes 41 and 42 provided between terminal A and terminal D are connected to face each other.

[0029] Therefore, when both NMOS transistors M1 and M2 are off, for example, the voltage Vcc applied to terminal A is blocked by diode 41. On the other hand, when battery 1 is reverse-connected and voltage Vcc is applied to terminal D, for example, the voltage at terminal D (here, voltage Vcc) is blocked by diode 42.

[0030] As a result, when both NMOS transistors M1 and M2 are off, switch X1 can cut off the current in the path from motor 12 to terminal D and terminal A.

[0031] <<About Control IC50>> The control IC 50 turns the switch X1 on and off (in other words, controls the on and off of the NMOS transistors M1 and M2) based on the instruction signal Sa. The control IC 50 includes a power supply circuit 51, a drive circuit 52, an NMOS transistor M3, and diodes D1 to D6. Of the diodes D1 to D6, the diodes D1 and D2 are parasitic diodes in the control IC 50, but are shown here for convenience.

[0032] <Power circuit 51> The power supply circuit 51 is a circuit that generates a power supply voltage Vdd to operate circuits such as the drive circuit 52. The power supply circuit 51 generates the power supply voltage Vdd when the switch X1 (NMOS transistors M1 and M2) is turned on, and stops generating the power supply voltage Vdd when the switch X1 is turned off.

[0033] 2 is a diagram showing an example of the configuration of the power supply circuit 51. The power supply circuit 51 shown in FIG.

[0034] A voltage Vcc is applied to the source electrode of the PMOS transistor M4, and the drain electrode is connected to the drain of the NMOS transistor M5. An instruction signal Sa from the microcomputer 20 is applied to the gate electrode of the PMOS transistor M4. The PMOS transistor M4 is turned on when the instruction signal Sa is a signal instructing the switch X1 to be on, and is turned off when the instruction signal Sa is a signal instructing the switch X1 to be off.

[0035] The NMOS transistor M5 is a transistor provided for current suppression, and is a depletion-type MOS transistor whose gate electrode and source electrode are connected and which is always on.

[0036] The cathode of diode 60 is connected to the source electrode of NMOS transistor M5 and the gate electrode of NMOS transistor M6, and the anode is grounded. Diode 60 is a Zener diode, and when the voltage (reverse voltage) applied from the cathode to the anode exceeds a certain voltage, a current begins to flow and controls the voltage of the gate electrode of NMOS transistor M6 to that certain voltage.

[0037] The drain electrode of the NMOS transistor M6 is connected to the source electrode of the PMOS transistor M4, and the voltage of the source electrode of the NMOS transistor M6 becomes the output of the power supply circuit 51.

[0038] With the above configuration, when the PMOS transistor M4 is turned on based on the instruction signal Sa, a constant voltage determined by the Zener diode D7 is applied to the gate electrode of the NMOS transistor M6. This turns on the NMOS transistor M6, and a power supply voltage Vdd (e.g., 5V) that is lower than the constant voltage by the threshold voltage is generated and output. This power supply voltage Vdd is applied to the gate of the NMOS transistor M3 and is also supplied to circuits such as the drive circuit 52.

[0039] On the other hand, when the PMOS transistor M4 is turned off based on the instruction signal Sa, no voltage is applied to the gate electrode of the NMOS transistor M6, and the NMOS transistor M6 is also turned off, so that the power supply voltage Vdd is no longer generated.

[0040] The configuration of the power supply circuit 51 is not limited to the one described above. For example, a resistor may be used instead of the depletion-type NMOS transistor M5. Also, for example, the power supply circuit 51 may be a circuit that generates the power supply voltage Vdd without using the voltage Vcc.

[0041] <Drive circuit 52> The drive circuit 52 is a circuit that controls the on / off of the switch X1. When an instruction signal Sa instructing the switch X1 to be on is input, the drive circuit 52 applies a drive voltage Vcp to the gate electrodes of the NMOS transistors M1 and M2, thereby turning on the switch X1. The drive circuit 70 is a charge pump circuit that receives a power supply voltage Vdd and has a ground voltage (voltage Vgnd) as its reference potential, and boosts the power supply voltage Vdd to generate a drive voltage Vcp that can turn on the NMOS transistors M1 and M2. The configuration and operation of charge pump circuits are well known, so a description thereof will be omitted here. As shown in FIG. 2, the drive circuit 52 of this embodiment includes, for example, an NMOS transistor M100 as an element constituting the drive circuit 52.

[0042] <Diodes D1 and D2> The diodes D1 and D2 are parasitic diodes formed by the semiconductor substrate of the control IC 50 and a circuit within the control IC 50 (for example, the NMOS transistor M100 of the drive circuit 52).

[0043] FIG. 3 is a diagram for explaining a semiconductor substrate 200 on which a control IC 50 is formed.

[0044] For convenience, Fig. 3 shows only a portion of the circuitry of the control IC 50 that is necessary to explain the diodes D1 and D2. Specifically, Fig. 3 shows terminals A and C (D), an NMOS transistor M100 included in the drive circuit 52, and the diode D1 (D2).

[0045] The semiconductor substrate 200 is, for example, an n-type substrate made of silicon, and on the front side thereof are formed a power supply electrode 214 connected to terminal A, and a gate electrode 210, source electrode 211, drain electrode 212, and substrate electrode 213 of the NMOS transistor M100. The source electrode 211 and substrate electrode 213 are also connected to terminal C (D).

[0046] Each electrode of the NMOS transistor M100 and the power supply electrode 214 are formed of a conductive material such as polysilicon or a metal electrode.

[0047] Inside the semiconductor substrate 200, there are formed a semiconductor region 220 formed by the semiconductor substrate 200, a p-type well region 230, a p+-type contact region 240, an n+-type source region 250, and an n+-type drain region 251. Hereinafter, when the term n+-type or p+-type is used, it means that the doping concentration is higher than that of the n-type or p-type.

[0048] A well region 230 and a contact region 260 are formed on the front surface side of the semiconductor region 220. A power supply electrode 214 is formed on the front surface of the contact region 260.

[0049] The well region 230 is a region containing p-type impurities, and on the front surface side of the well region 230, a contact region 240, a source region 250, and a drain region 251 are formed.

[0050] In the contact region 240, a substrate electrode 213 (“Bx”) of the NMOS transistor M100 is formed.

[0051] Furthermore, a source electrode 211 ("Sx") is formed in the source region 250, and a drain electrode 212 ("Dx") is formed in the drain region 251. A gate electrode 210 ("Gx") is formed on the front surface side of the well region 230 between the source region 250 and the drain region 251.

[0052] In this embodiment, terminal A is electrically connected to the semiconductor region 220 via the power electrode 214 and the contact region 260, and the substrate electrode 213 (“Bx”) is also electrically connected to the well region 230 via the contact region 240.

[0053] In such a semiconductor substrate 200, a diode D1 (D2) is formed between the n-type semiconductor region 220 and the p-type well region 230 as a parasitic diode.

[0054] If the battery 1 is connected in reverse, terminal A is grounded and voltage Vcc is applied to terminal C (in the case of terminal D, voltage Vcc is applied via the coil (not shown) of the motor 12). Therefore, voltage Vcc is applied to terminal C (D) and terminal A is grounded, so a "reverse current" flows through the path of terminal C (D), diode D1 (D2), and terminal A (see FIG. 5).

[0055] It should be noted that, although the parasitic diodes D1 and D2 are described here as being formed in the NMOS transistor M100 of the semiconductor substrate 200, this is not limiting. For example, when the battery 1 is reverse-connected and the voltage of the p-type region of the semiconductor substrate 200 becomes higher than the voltage of the n-type region, a reverse current flows.

[0056] <Diodes D3 and D4> 1 is a diode that allows current to flow from drive circuit 52 to terminal C, and diode D4 is a diode that allows current to flow from drive circuit 52 to terminal D. Furthermore, as will be described later, diodes D3 and D4 block the current flowing from terminal C to control IC 50 and the current flowing from terminal D to control IC 50, respectively, when battery 1 is reverse-connected.

[0057] The anode of the diode D3 is connected to the drive circuit 52, and the cathode is connected to the terminal C. The diode D3 corresponds to the "second diode."

[0058] The anode of the diode D4 is connected to the drive circuit 52, and the cathode is connected to the node N1 (the node where the terminal D and the source electrode of the NMOS transistor M1 are connected). The diode D4 corresponds to a "third diode."

[0059] The diodes D3 and D4 in this embodiment are polysilicon diodes formed of polysilicon. Fig. 4 is a diagram showing an example of the configuration of the diode D3. Although Fig. 4 shows the diode D3, the diode D4 has a similar configuration.

[0060] As shown in FIG. 4, an insulating layer 281, such as a silicon oxide film (SiO2 film), is formed on a well region 280 containing p-type impurities, and an n-type polysilicon layer 282 and a p-type polysilicon layer 283 are selectively formed thereon. Furthermore, an interlayer insulating film 284 is formed thereon, and openings are formed in the interlayer insulating film 284 above the n-type polysilicon layer 282 and the p-type polysilicon layer 283. The n-type polysilicon layer 282 and the p-type polysilicon layer 283 are in contact with each other to form a diode D3. Reference numeral 285 denotes a conductive wiring layer. The configuration of diodes D3 and D4 is not limited to the above. For example, a trench type may be used.

[0061] Diodes formed from the diffusion layer of a semiconductor substrate may operate unintentionally (allow current to flow) due to parasitics, etc., whereas diodes D3 and D4 formed from polysilicon are highly reliable and can prevent current from flowing through unintended paths. In particular, when an inductive load is connected to terminal D, the voltage at terminal D may fluctuate significantly. Even in such a case, diode D4 can more reliably block reverse current.

[0062] Furthermore, it is desirable that the forward voltage of diode D3 be smaller (lower) than the forward voltage of the body diode (diode D5) of NMOS transistor M3, which will be described later. This makes it possible to prevent electrostatic breakdown of NMOS transistor M3 due to static electricity or surge voltage being applied to the gate of NMOS transistor M3 (ESD countermeasures can be implemented).

[0063] <NMOSトランジスタM3> The NMOS transistor M3 is arranged in parallel with the diode D3, with its drain electrode connected to the terminal C and its source electrode connected to the drive circuit 52. As described above, the output (power supply voltage Vdd) of the power supply circuit 51 is applied to its gate electrode.

[0064] When the switch X1 is on, the NMOS transistor M3 is turned on by applying a power supply voltage Vdd to its gate electrode, which causes a voltage to be applied between the gate and drain. When the switch X1 is off, the NMOS transistor M3 is turned off because no power supply voltage Vdd is applied to its gate electrode. The NMOS transistor M3 corresponds to the "second MOS transistor."

[0065] Furthermore, a diode D5 is formed in the NMOS transistor M3 as a body diode (parasitic diode). The diode D5 corresponds to a "second diode." In this embodiment, the NMOS transistor M3 and the diode D3 are provided in parallel, but if the diode D5 (body diode) of the NMOS transistor M3 can block the reverse current, the diode D3 may be omitted.

[0066] Furthermore, a gate protection diode D6 is provided between the gate electrode and drain electrode of the NMOS transistor M3. The anode of the diode D6 is connected to the drain electrode of the NMOS transistor M3, and the cathode is connected to the gate electrode of the NMOS transistor M3. The diode D6 is a Zener diode, and clamps the voltage between the gate electrode and source electrode of the NMOS transistor M3 at a predetermined voltage. Note that the diode D6 is not necessarily required.

[0067] <<<When battery 1 is connected normally>>> 1, when the battery 1 is properly connected, a voltage Vcc is applied to terminal A, and a voltage Vgnd is applied (grounded) to terminal C. Furthermore, terminal D is grounded via the coil (not shown) of the motor 12.

[0068] When the instruction signal Sa is a signal instructing to turn on the switch X1, the power supply circuit 51 generates a power supply voltage Vdd, and the drive circuit 52 operates based on the power supply voltage Vdd to output a drive voltage Vcp. Then, when the switch X1 (NMOS transistors M1, M2) is turned on, a current based on the voltage Vcc of the battery 1 is supplied to the motor 12 via terminals A and D. Furthermore, the power supply voltage Vdd generated by the power supply circuit 51 is applied to the gate electrode of the NMOS transistor M3, turning on the NMOS transistor M3.

[0069] On the other hand, when the instruction signal Sa is a signal instructing to turn off the switch X1, the PMOS transistor M4 and the NMOS transistor M6 are turned off in the power supply circuit 51, and the power supply voltage Vdd is no longer generated. This stops the operation of the drive circuit 52, and the switch X1 (NMOS transistors M1 and M2) is turned off. With the switch X turned off, the current based on the voltage Vcc of the battery 1 is no longer supplied to the motor 12 (the motor 12 stops). Furthermore, since the power supply voltage Vdd is not generated in the power supply circuit 51, the NMOS transistor M3 is also turned off.

[0070] <<<If battery 1 is connected in reverse>>> The following describes a case where the battery 1 is reversely connected. Before describing this embodiment, a comparative example will first be described.

[0071] <<Comparative Example>> Fig. 5 is an explanatory diagram of a comparative example in which battery 1 is reversely connected. Fig. 6A is an explanatory diagram of motor control device 10A and ECU 300 of the comparative example, and Fig. 6B is an explanatory diagram of blocking reverse current in the comparative example. In the comparative example, parts having the same configuration as in this embodiment are assigned the same reference numerals and descriptions thereof will be omitted.

[0072] The motor control device 10A of the comparative example includes an IPS 30A, which includes a control IC 50A and an IC 40.

[0073] The control IC 50A differs from the control IC 50 of this embodiment in that it does not include diodes D3 to D6 and an NMOS transistor M3. The control IC 50A also includes a resistor RG between the drive circuit 52 and the terminal C. The resistor RG is a resistor for suppressing current.

[0074] As shown in FIG. 6A, an ECU 300 that controls the operation of motor control device 10A is provided between the positive electrode of battery 1 and motor control device 10A.

[0075] 5 and 6B, in the comparative example, when battery 1 is reverse-connected, voltage Vcc is applied to terminals C and D, and terminal A is grounded. This may cause current to flow through the path indicated by the dashed dotted line. Of these, the current through the path battery 1 → motor 12 → terminal D → switch X1 → terminal A can be blocked by diode 42.

[0076] However, in the comparative example, a reverse current flows through the path of battery 1 → terminal C → resistor RG → diode D1 → terminal A, and the path of battery 1 → motor 12 → terminal D → node N1 → diode D2 → terminal A. For this reason, in the comparative example, a protection circuit 301 is provided in ECU 300 as shown in Figures 6A and 6B.

[0077] The protection circuit 301 is configured with, for example, a relay or a fuse, and cuts off the current (reverse current) when a current flows in the reverse direction. Note that in this example, the protection circuit 301 is provided within the ECU 300, but this is not limiting, and the protection circuit 301 may be provided, for example, between the ECU 300 and the motor control device 10A. In this way, in the comparative example, it is necessary to provide a separate protection circuit 301 (relay, fuse, etc.) that protects the ECU 300.

[0078] <<Present Embodiment>> 7 is an explanatory diagram of the case where the battery 1 is reverse-connected in this embodiment. Note that the figure shows only the IPS 30 of the motor control device 10, and the current path from the positive electrode of the battery 1 is indicated by a dashed line, as in the comparative example.

[0079] 7, when the battery 1 is reverse-connected, a voltage Vcc is applied to terminals C and D, and terminal A is grounded. Here, the current in the path from battery 1 to motor 12 to terminal D to switch X1 to terminal A can be blocked by diode 42, as in the comparative example.

[0080] In this embodiment, the current in the path of battery 1 → terminal C → diode D1 → terminal A can be blocked by diode D3 and diode D5 (body diode of NMOS transistor M3).

[0081] In addition, the current flowing through the path of battery 1 → motor 12 → terminal D → node N1 → diode D2 → terminal A can be blocked by diode D4.

[0082] In this way, when the battery 1 is reverse-connected, the motor control device 10 (IPS30) of this embodiment can block the current (reverse current) flowing into the control IC 50 via terminals C and D. Therefore, even without providing the protection circuit 301 as in the comparative example, the ECU and the like can be protected from the reverse current.

[0083] ===Summary=== The motor control device 10 equipped with the IPS 30 of this embodiment has been described above. The IPS 30 includes a terminal A to which a voltage Vcc is applied, a terminal C to which a voltage Vgnd lower than the voltage Vcc is applied, and a terminal D to which the motor 12 is connected. The IPS 30 also includes a diode 42 having an anode connected to terminal A, an NMOS transistor M1 having a source electrode connected to terminal D and a drain electrode connected to the cathode of the diode 42, a drive circuit 52 that controls the on / off of the NMOS transistor M1, diodes D3 and D5 having a cathode connected to terminal C and an anode connected to the drive circuit 52, and a diode D4 having a cathode connected to a node N1 at which terminal D and the source electrode of the NMOS transistor M1 are connected and an anode connected to the drive circuit 52. This allows the current (reverse current) flowing into the control IC 50 via terminals C and D to be blocked if the battery 1 is reverse-connected. Therefore, a protection circuit 301 (such as a fuse or relay) as in the comparative example is not required.

[0084] The IPS30 also includes an NMOS transistor M3 whose drain electrode is connected to the terminal C and whose source electrode is connected to the drive circuit 52, and the diode D5 is the body diode of the NMOS transistor M3. As a result, when the battery 1 is reverse-connected, the diode D5 can block the current (reverse current) flowing from the terminal C.

[0085] Furthermore, the NMOS transistor M3 is provided in parallel with the diode D3, so that if the battery 1 is reverse-connected, the diode D3 can block the current (reverse current) flowing from the terminal C.

[0086] In addition, the diode D3 is made of polysilicon, which prevents current from flowing through unintended paths and improves reliability.

[0087] Furthermore, the forward voltage of the diode D3 is smaller than the forward voltage of the body diode (diode D5) of the NMOS transistor M3, thereby providing ESD protection for the NMOS transistor M3.

[0088] The IPS30 also includes a power supply circuit 51 that generates a power supply voltage Vdd to operate a drive circuit 52 when the NMOS transistor M1 is turned on, and stops generating the power supply voltage Vdd when the NMOS transistor M1 is turned off. The NMOS transistor M3 is turned on based on the power supply voltage Vdd. As a result, when the NMOS transistor M1 is turned off, the NMOS transistor M3 is also turned off, thereby reducing power consumption compared to when the NMOS transistor M1 is always on.

[0089] Diode D4 is made of polysilicon, which prevents current from flowing through unintended paths. This is also effective when an inductive load is connected to terminal D.

[0090] The IPS 30 also includes an NMOS transistor M2 whose source electrode is connected to the terminal A and whose drain electrode is connected to the drain electrode of the NMOS transistor M1, and the diode 42 is the body diode of the NMOS transistor M2, which allows the body diode of the NMOS transistor M2 (diode 42) to be effectively used as a diode that blocks reverse current.

[0091] The IPS30 also includes an IC40 including NMOS transistors M1 and M2, and a control IC50 including a drive circuit 52 and diodes D3 (D5) and D4. This allows the reverse current flowing through IC40 and the control IC to be blocked. Furthermore, the IPS30 can be made smaller than when the circuit for blocking the reverse current is formed using multiple components.

[0092] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof.

[0093] For example, the NMOS transistor M2 may be omitted, and instead only the diode 42 may be provided. In this case, the supply and cutoff of the voltage Vcc to the motor 12 is achieved solely by turning the NMOS transistor M1 on and off, and the diode 42 cuts off the current when the battery 1 is reverse-connected. However, in this case, the heat generated by the voltage drop and loss of the diode 42 when the NMOS transistor M1 is on is greater than when the NMOS transistor M2 is used.

[0094] Furthermore, in the above-described embodiment, the NMOS transistor M3 is configured to turn on when the instruction signal Sa is a signal instructing the switch X1 (NMOS transistors M1 and M2) to turn on (i.e., in conjunction with the switch X1), but this is not limiting. For example, the NMOS transistor M3 may be always on (regardless of the instruction signal Sa) when the voltage Vcc is applied to the terminal A. However, if the NMOS transistor M3 is turned on and off in accordance with the instruction signal Sa as in this embodiment, power consumption can be reduced, as described above.

[0095] Furthermore, in the above-described embodiment, for convenience, the diodes D3 and D4 are each configured as a single diode, but they may be configured as multiple (for example, three) diodes connected in series depending on the magnitude of the voltage Vcc of the battery 1. This prevents the diodes from breaking down when the battery 1 is reverse-connected, and more reliably prevents reverse current.

[0096] Furthermore, in the IPS 30 of the above embodiment, the voltage Vcc is applied to one terminal (terminal A), but this is not limiting.

[0097] 8 is an explanatory diagram of a modified example (IPS 31) of the IPS 30. In this modified example, parts having the same configuration as those in the above-described embodiment are given the same reference numerals, and descriptions thereof will be omitted.

[0098] The IPS 30 is provided with terminals A1 and A2 as terminals to which a voltage Vcc is applied. Terminal A1 is connected to the IC 40, and terminal A2 is connected to the control IC 50. In this way, a terminal to which a voltage Vcc is applied may be provided on each of the IC 40 side and the control IC 50 side. In this case, terminals A1 and A2 correspond to the "first terminal." [Explanation of symbols]

[0099] 1 battery 10 Motor control device 12 motors 20 Microcomputer 30 IPS 40 IC 41,42 Diode 50 Control IC 51 Power supply circuit 52 Drive circuit 60 Diode D1~D6 diodes M1, M2, M3, M5, M6 NMOS transistors M4 PMOS transistor A,B,C,D terminals

Claims

1. a first terminal to which a first voltage is applied; a second terminal to which a second voltage lower than the first voltage is applied; a third terminal to which a load is connected; a first diode having an anode connected to the first terminal; a first MOS transistor having a source electrode connected to the third terminal and a drain electrode connected to the cathode of the first diode; a drive circuit for controlling the on / off of the first MOS transistor; a second diode having a cathode connected to the second terminal and an anode connected to the drive circuit; a third diode having a cathode connected to a node where the third terminal and the source electrode of the first MOS transistor are connected and an anode connected to the drive circuit; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, a second MOS transistor having a drain electrode connected to the second terminal and a source electrode connected to the drive circuit; the second diode is a body diode of the second MOS transistor; Semiconductor device.

3. 2. The semiconductor device according to claim 1, a second MOS transistor having a drain electrode connected to the second terminal and a source electrode connected to the drive circuit so as to be in parallel with the second diode; Semiconductor device.

4. 4. The semiconductor device according to claim 3, the second diode is formed of polysilicon; Semiconductor device.

5. 4. The semiconductor device according to claim 3, a forward voltage of the second diode is smaller than a forward voltage of a body diode of the second MOS transistor; Semiconductor device.

6. 4. The semiconductor device according to claim 3, When the first MOS transistor is turned on, a power supply voltage for operating the drive circuit is generated; a power supply circuit that stops generating the power supply voltage when the first MOS transistor is turned off; The second MOS transistor is turned on based on the power supply voltage. Semiconductor device.

7. 2. The semiconductor device according to claim 1, the third diode is formed of polysilicon; Semiconductor device.

8. The semiconductor device according to any one of claims 1 to 7, a third MOS transistor having a source electrode connected to the first terminal and a drain electrode connected to the drain electrode of the first MOS transistor; the first diode is a body diode of the third MOS transistor; Semiconductor device.

9. 9. The semiconductor device according to claim 8, a first chip including the first MOS transistor and the third MOS transistor; a second chip including the driving circuit, the second diode, and the third diode; having Semiconductor device.

Images