Partial structure, interposer, and semiconductor device

Abstract

To prevent a short circuit between upper and lower conductive layers in a substrate including a through electrode.SOLUTION: A through electrode substrate includes a substrate 11 having a first surface 11a and a second surface opposite to the first surface, a plurality of through electrodes penetrating the substrate, and a first capacitor 100 arranged on the first surface side of the substrate and electrically connected to at least one of the plurality of through electrodes, the first capacitor includes a first conductive layer 12 arranged on the first surface side of the substrate and electrically connected to the through electrodes, an insulating layer 13 arranged on the first conductive layer, and a second conductive layer 14 arranged on the insulating layer, the insulating layer includes a first portion 13a arranged between the first conductive layer and the second conductive layer, and a second portion 13b covering at least a portion of a side surface of the first conductive layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a through hole electrode substrate, a semiconductor device, and a method for manufacturing a through hole electrode substrate. [Background technology]

[0002] In recent electronic devices, wiring is used on both sides of the substrate. Patent Document 1 discloses a substrate in which wiring on both sides of the substrate is connected by electrodes that penetrate the glass substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO2005 / 034594 No. Summary of the Invention [Problem to be solved by the invention]

[0004] To increase the functionality of the above-mentioned wiring board, it is necessary to form elements with various functions. However, when forming such elements on a substrate with through electrodes, unexpected problems may occur. When forming a structure in which conductive layers are arranged one above the other on this substrate, such as a capacitor, a short circuit between the conductive layers may occur depending on the structure of the two conductive layers.

[0005] One of the objects of the present disclosure is to prevent short circuits between conductive layers positioned above and below a substrate including a through electrode. [Means for solving the problem]

[0006] According to the present disclosure, there is provided a through electrode substrate having a substrate having a first surface and a second surface opposite to the first surface, a plurality of through electrodes penetrating the substrate, and a first capacitor arranged on the first surface side of the substrate and electrically connected to at least one of the plurality of through electrodes, wherein the first capacitor includes a first conductive layer arranged on the first surface side of the substrate and electrically connected to the through electrodes, an insulating layer arranged on the first conductive layer, and a second conductive layer arranged on the insulating layer, wherein the insulating layer has a first portion arranged between the first conductive layer and the second conductive layer and a second portion covering at least a portion of a side surface of the first conductive layer.

[0007] According to another example of the present disclosure, there is provided a method for manufacturing a through electrode substrate, the method including the steps of: providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a through hole penetrating the first surface and the second surface; forming a through electrode in the through hole of the substrate, the through electrode connecting the first surface and the second surface; forming a first conductive layer on the first surface of the substrate, the first conductive layer being electrically connected to the through electrode; forming a first insulating layer on an upper surface of the first conductive layer; forming a second insulating layer so as to cover at least a portion of a side surface of the first conductive layer and the first insulating layer; removing a portion of the second insulating layer located above the first conductive layer; and forming a second conductive layer in the removed portion of the second insulating layer.

[0008] According to another example of the present disclosure, there is provided a method for manufacturing a through electrode substrate, the method including the steps of: providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a through hole penetrating the first surface and the second surface; forming a first resist on the first surface; forming a through electrode in the through hole of the substrate, the through electrode electrically connecting the first surface and the second surface; and forming a first conductive layer on the first surface of the substrate, the first conductive layer being electrically connected to the through electrode; forming an intermediate layer on the first conductive layer; removing the first resist by lift-off; forming a second resist around the first conductive layer; forming a first insulating layer on an upper surface and a side surface of the intermediate layer, the side surface of the first conductive layer, the first surface, and the upper surface and a side surface of the second resist; removing the second resist by lift-off so as to leave at least a portion of the first insulating layer formed on the side surface of the second resist; and forming a second conductive layer on the first insulating layer corresponding to the position of the intermediate layer.

[0009] According to another example, there is provided a method for manufacturing a through electrode substrate, the method including the steps of: providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a through hole penetrating the first surface and the second surface; forming a first resist on the first surface; forming a through electrode in the through hole of the substrate, the through electrode connecting the first surface and the second surface; and forming a first conductive layer on the first surface of the substrate, the first conductive layer being electrically connected to the through electrode; forming a first insulating layer on the upper and side surfaces of the first conductive layer and on the first surface; forming a second conductive layer on the first insulating layer corresponding to the position of the upper surface of the first conductive layer; forming a second resist layer to cover the second conductive layer and a portion of the first insulating layer on the first surface; removing the portion of the first insulating layer that is not covered by the second resist layer; and removing the second resist layer.

[0010] The through electrode substrate can also be used as an interposer. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to prevent short circuits between conductive layers located above and below a substrate including a through electrode. Further features related to the present disclosure will become apparent from the description of the present specification and the accompanying drawings. Furthermore, problems, configurations, and advantages other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic plan view showing an interposer according to a first embodiment of the present disclosure. [Figure 2] 2 is a schematic cross-sectional view (cross-sectional view taken along line AA in FIG. 1) illustrating an interposer according to the first embodiment of the present disclosure. [Figure 3] 1 is a schematic cross-sectional view (cross-sectional view taken along line BB in FIG. 1) showing a capacitor 100 included in an interposer according to a first embodiment of the present disclosure. [Figure 4A] 2A to 2C are diagrams illustrating a method for manufacturing an interposer according to the first embodiment of the present disclosure. [Figure 4B] 2A to 2C are diagrams illustrating a method for manufacturing an interposer according to the first embodiment of the present disclosure. [Figure 4C] 2A to 2C are diagrams illustrating a method for manufacturing an interposer according to the first embodiment of the present disclosure. [Figure 4D] 2A to 2C are diagrams illustrating a method for manufacturing an interposer according to the first embodiment of the present disclosure. [Figure 4E] 2A to 2C are diagrams illustrating a method for manufacturing an interposer according to the first embodiment of the present disclosure. [Figure 4F] 5A to 5C are diagrams illustrating another example of a method for manufacturing an interposer according to the first embodiment of the present disclosure. [Figure 5] FIG. 4 is a schematic cross-sectional view showing a capacitor according to a second embodiment of the present disclosure. [Figure 6] FIG. 10 is a schematic cross-sectional view showing a capacitor according to a third embodiment of the present disclosure. [Figure 7] FIG. 10 is a schematic cross-sectional view showing a capacitor according to a fourth embodiment of the present disclosure. [Figure 8]FIG. 10 is a schematic cross-sectional view showing a capacitor according to a fifth embodiment of the present disclosure. [Figure 9] FIG. 10 is a schematic cross-sectional view showing a capacitor according to a sixth embodiment of the present disclosure. [Figure 10] FIG. 11 is a schematic cross-sectional view showing a capacitor according to a seventh embodiment of the present disclosure. [Figure 11] FIG. 13 is a schematic cross-sectional view showing a capacitor according to an eighth embodiment of the present disclosure. [Figure 12] FIG. 13 is a schematic cross-sectional view showing a capacitor according to a ninth embodiment of the present disclosure. [Figure 13] FIG. 22 is a schematic cross-sectional view showing a capacitor according to a tenth embodiment of the present disclosure. [Figure 14] FIG. 22 is a schematic cross-sectional view showing a capacitor according to an eleventh embodiment of the present disclosure. [Figure 15A] 13A to 13C are diagrams illustrating a method for manufacturing a capacitor according to an eleventh embodiment of the present disclosure. [Figure 15B] 13A to 13C are diagrams illustrating a method for manufacturing a capacitor according to an eleventh embodiment of the present disclosure. [Figure 15C] 13A to 13C are diagrams illustrating a method for manufacturing a capacitor according to an eleventh embodiment of the present disclosure. [Figure 16] FIG. 23 is a schematic cross-sectional view showing a capacitor according to a twelfth embodiment of the present disclosure. [Figure 17] FIG. 22 is a schematic cross-sectional view showing a capacitor according to a thirteenth embodiment of the present disclosure. [Figure 18A] 22A to 22D are diagrams illustrating a method for manufacturing a capacitor according to a thirteenth embodiment of the present [Figure 18B] 22A to 22D are diagrams illustrating a method for manufacturing a capacitor according to a thirteenth embodiment of the present disclosure. [Figure 18C] 22A to 22D are diagrams illustrating a method for manufacturing a capacitor according to a thirteenth embodiment of the present disclosure. [Figure 18D] 22A to 22D are diagrams illustrating a method for manufacturing a capacitor according to a thirteenth embodiment of the present [Figure 18E] 22A to 22D are diagrams illustrating a method for manufacturing a capacitor according to a thirteenth embodiment of the present disclosure. [Figure 18F] 22A to 22D are diagrams illustrating a method for manufacturing a capacitor according to a thirteenth embodiment of the present disclosure. [Figure 19] FIG. 23 is a diagram illustrating the positional relationship of capacitors according to a thirteenth embodiment of the present disclosure. [Figure 20A] 5A to 5C are diagrams illustrating another method for manufacturing a capacitor according to the first embodiment of the present disclosure. [Figure 20B] 5A to 5C are diagrams illustrating another method for manufacturing a capacitor according to the first embodiment of the present disclosure. [Figure 20C] 5A to 5C are diagrams illustrating another method for manufacturing a capacitor according to the first embodiment of the present disclosure. [Figure 20D] 5A to 5C are diagrams illustrating another method for manufacturing a capacitor according to the first embodiment of the present disclosure. [Figure 20E] 5A to 5C are diagrams illustrating another method for manufacturing a capacitor according to the first embodiment of the present disclosure. [Figure 21A] FIG. 23 is a schematic plan view showing an interposer according to a fourteenth embodiment of the present disclosure. [Figure 21B] 21B is a schematic cross-sectional view (cross-sectional view taken along line CC in FIG. 21A) showing a ring-shaped conductive layer 29 included in an interposer according to a fourteenth embodiment of the present disclosure. FIG. [Figure 22A] FIG. 22 is a schematic plan view showing a capacitor according to a fifteenth embodiment of the present disclosure. [Figure 22B] FIG. 22 is a schematic plan view showing a capacitor according to a sixteenth embodiment of the present disclosure. [Figure 23] FIG. 22 is a schematic plan view showing a capacitor according to a seventeenth embodiment of the present disclosure. [Figure 24A] FIG. 22 is a schematic plan view showing a capacitor according to an eighteenth embodiment of the present disclosure. [Figure 24B] FIG. 22 is a schematic plan view showing a capacitor according to a nineteenth embodiment of the present disclosure. [Figure 25A] FIG. 20 is a schematic plan view showing the positional relationship between a first conductive layer and a first insulating layer of a capacitor according to a twentieth embodiment of the present disclosure. [Figure 25B]FIG. 21 is a schematic plan view showing the positional relationship between a first conductive layer and a first insulating layer of a capacitor according to a twenty-first embodiment of the present disclosure. [Figure 25C] FIG. 22 is a schematic plan view showing the positional relationship between a first conductive layer and a first insulating layer of a capacitor according to a twenty-second embodiment of the present disclosure. [Figure 26A] FIG. 2 is a schematic cross-sectional view of capacitors according to the first embodiment of the present disclosure arranged adjacent to each other. [Figure 26B] FIG. 20 is a schematic cross-sectional view illustrating an example of the arrangement of a second conductive layer of a capacitor according to a twentieth embodiment of the present disclosure. [Figure 26C] FIG. 20 is a schematic cross-sectional view illustrating another example of the arrangement of the second conductive layer of the capacitor according to the twentieth embodiment of the present disclosure. [Figure 27] FIG. 23 is a schematic cross-sectional view of a capacitor according to a twenty-third embodiment of the present disclosure. [Figure 28] FIG. 24 is a schematic plan view showing a capacitor and an inductor included in an interposer according to a twenty-fourth embodiment of the present disclosure. [Figure 29] FIG. 28 is a schematic cross-sectional view (cross-sectional view taken along line DD in FIG. 28) showing an interposer according to a twenty-fourth embodiment of the present disclosure. [Figure 30] FIG. 25 is a schematic plan view showing a capacitor according to a twenty-fifth embodiment of the present disclosure. [Figure 31] FIG. 26 is a diagram illustrating a semiconductor device according to a twenty-sixth embodiment of the present disclosure. [Figure 32] FIG. 26 is a diagram showing another example of a semiconductor device according to the twenty-sixth embodiment of the present disclosure. [Figure 33] FIG. 26 is a diagram showing yet another example of a semiconductor device according to the twenty-sixth embodiment of the present disclosure. [Figure 34] FIG. 26 is a diagram illustrating an example of an electronic device using a semiconductor device according to a twenty-sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] An embodiment of the present disclosure will be described below with reference to the drawings. Note that each embodiment described below is an example of an embodiment of the present invention, and the present invention should not be construed as being limited to these embodiments. In the drawings referred to in this embodiment, identical parts or parts having similar functions are designated by the same or similar symbols (symbols consisting of only a number followed by A, B, etc.), and repeated explanations may be omitted. Furthermore, for the sake of convenience, the dimensional ratios of the drawings may differ from the actual ratios, and some components may be omitted from the drawings. In the drawings attached to this specification, for the sake of convenience and ease of illustration, the scale and aspect ratios may be appropriately changed and exaggerated from those of the actual objects, and some components may be omitted from the drawings.

[0014] In this specification and the like, a numerical range expressed using "to" means that the range includes the numerical values ​​written before and after "to" as the lower and upper limits, respectively. For example, 10 to 30 means 10 or more and 30 or less.

[0015] First Embodiment An interposer according to an embodiment of the present disclosure has a structure in which an insulating layer is sandwiched between conductive layers containing metal or the like. FIG. 1 is a schematic plan view illustrating an interposer 10 according to a first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view (cross-sectional view along line AA in FIG. 1 ) illustrating the interposer 10 according to the first embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view (cross-sectional view along line BB in FIG. 1 ) illustrating a capacitor 100 included in the interposer 10 according to the first embodiment of the present disclosure. Note that some components are omitted in FIGS. 1 and 3 to facilitate understanding of the positional relationship between the substrate 11, first conductive layer 12, first insulating layer 13, and second conductive layer 14. The interposer 10 has, for example, a metal-insulator-metal (MIM) structure in which an insulating layer is sandwiched between metals. Hereinafter, the MIM structure will be described as a capacitor 100 in which an insulating layer, which is a dielectric layer, is sandwiched between an upper electrode and a lower electrode. In this case, the first conductive layer 12 is used as a lower electrode, the first insulating layer 13 is used as a dielectric layer, and the second conductive layer 14 is used as an upper electrode.

[0016] The interposer 10 includes a substrate 11 having a first surface 11a and a second surface 11b opposite the first surface 11a, a first conductive layer 12 disposed on the first surface 11a of the substrate 11, a first insulating layer 13 disposed on the first conductive layer 12, and a second conductive layer 14 disposed on the first insulating layer 13. In this example, an underlayer 17 is further disposed between the first conductive layer 12 and the substrate 11. The underlayer 17 may be disposed directly on the first surface 11a of the substrate 11, or may be disposed on the first surface 11a of the substrate 11 via at least one conductive or insulating layer. For example, by disposing an insulating resin selected from epoxy, polyimide, polybenzoxazole, polyamide, etc. on the first surface 11a of the substrate 11, stress generated by the difference in thermal expansion coefficient between the first conductive layer 12 and the substrate 11 can be alleviated, thereby suppressing cracks from occurring in the substrate in a subsequent process including heating.

[0017] The substrate 11 has a through hole 15 penetrating the first surface 11a and the second surface 11b. The first conductive layer 12 is electrically connected to a third conductive layer 21 disposed on the second surface 11b via a through electrode 20 formed in the through hole 15. A base layer 17 is also disposed between the through electrode 20 and the substrate 11 and between the third conductive layer 21 and the substrate 11. The shape of the through hole 15 is not limited to that shown in the figure, and the through hole 15 may have a shape whose width decreases from the first surface 11a and the second surface 11b of the substrate 11 toward the center in the thickness direction of the substrate 11. The sidewall of the through hole 15 may widen in the normal direction to the first surface 11a of the substrate 11 or may narrow in the normal direction to the first surface 11a of the substrate 11. Furthermore, the sidewall may have a partially curved shape. The through holes 15 are formed in the substrate 11 by etching, laser processing, a combination of laser processing and etching, sandblasting, electrical discharge machining, drilling, or the like. The through electrodes 20 are not limited to a configuration in which a conductive material is disposed along the side of the through holes 15 as shown in FIG. 2 , but may also be a configuration in which a conductive material is filled inside the through holes 15. The first conductive layer 12, the through electrodes 20, and the third conductive layer may be integrally formed. In the interposer 10 shown in FIG. 2 , the first conductive layer 12, the through electrodes 20, and the third conductive layer 21 have the same configuration. An example of the same configuration is a configuration in which they are made of the same material. The first conductive layer 12 on the first surface 11a of the substrate 11 and the third conductive layer 21 on the second surface 11b of the substrate 11 may be made of the same material and have substantially the same thickness. In such a case, when electrically connected, differences in resistance are unlikely to occur at the connection, reducing signal transmission loss.

[0018] The opening width of through hole 15 is preferably 40 μm to 110 μm. Here, the opening width of through hole 15 refers to the maximum distance between any two points on the outer edge of the figure formed by the outer edge of through hole 15 when first surface 11a or second surface 11b of substrate 11 is viewed in plan view. If the figure formed by the outer edge is circular, the above-mentioned width refers to the diameter of the circle.

[0019] An insulating resin layer 22 is formed on the first surface 11a side and the second surface 11b side of the substrate 11. Via holes 23 are formed in the resin layer 22 at positions corresponding to the first conductive layer 12, the second conductive layer 14, and the third conductive layer 21. A connection portion 24 made of a conductive material is disposed in each of the via holes 23. The connection portion 24 is electrically connected to the conductive layer disposed at the bottom of the via hole 23.

[0020] The interposer 10 is electrically connected to the semiconductor chip 50 via the connection portions 24. The interposer 10 is also connected to the wiring substrate 40 via the connection portions 24 and solder balls 25. The semiconductor chip 50 may also be connected to the connection portions 24 via the solder balls 25. This configuration provides a semiconductor device including the interposer 10, the semiconductor chip 50 disposed on the first surface 11a of the substrate 11 and electrically connected to the through electrodes 20, and the wiring substrate 40 disposed on the second surface 11b of the substrate 11 and electrically connected to the through electrodes 20. The interposer 10 of this embodiment simplifies the mounting of the semiconductor chip 50 with a narrow terminal pitch on the large wiring substrate 40. The wiring substrate 40 may be, for example, a motherboard. The connection to the semiconductor chip 50 may be made via the large wiring substrate 40 rather than via the connection portions 42. In this case, the through electrode substrate of the present invention is considered a passive element rather than an interposer.

[0021] The substrate 11 may be a glass substrate, a glass ceramic substrate, a quartz substrate, a sapphire substrate, a resin substrate, a glass epoxy substrate, a silicon substrate, an SOI (Silicon on Insulator) substrate, an SOS (Silicon on Sapphire) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconium oxide (ZrO2) substrate, or a substrate in which these are laminated. It is preferable that the insulating material has insulating properties, and at least the surface thereof has insulating properties.

[0022] Preferably, the substrate 11 is a glass substrate. Generally, the closer to the edge of an interposer, the greater the displacement due to thermal deformation. An interposer using a glass substrate has the advantage that it can be designed to minimize the difference in thermal expansion coefficient between this region and a semiconductor chip or the like using a silicon substrate placed on the interposer. Furthermore, by using glass for the substrate 11, there is no need to worry about leakage current between conductive layers formed on the surface of the substrate 11 due to its high insulating properties.

[0023] More preferably, alkali-free glass is used for the substrate 11. Unlike soda glass, alkali-free glass does not contain alkali components such as Na and K, so alkali components do not precipitate on the glass surface. Therefore, this embodiment has the advantage that, in principle, it does not cause reliability degradation factors that corrode the terminals of the semiconductor chip to be connected to the interposer. In addition, alkali-free glass has a thermal expansion coefficient similar to that of silicon, and is well matched in terms of thermal expansion coefficient with the semiconductor chip to be connected.

[0024] The thickness of the substrate 11 is preferably, for example, 50 μm to 700 μm. The surface roughness (arithmetic mean roughness Ra) of the first surface 11a of the substrate 11 is preferably small, and is preferably 0.1 nm to 10 nm, from the viewpoint of preventing transmission loss of high-frequency signals in the first conductive layer 12 formed on the first surface 11a of the substrate 11 and the third conductive layer 21 formed on the second surface 11b. The arithmetic mean roughness Ra here follows the definition in JIS standard JIS B 0601:2001.

[0025] The first conductive layer 12 and the second conductive layer 14 are made of conductive materials such as gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd), ruthenium (Ru), and tungsten (W). Among these, Cu is preferred because of its high conductivity and low material cost. The thickness of the first conductive layer 12 is preferably 0.5 μm to 20 μm, and the thickness of the second conductive layer 14 is preferably 0.5 μm to 5 μm. The wiring pattern can be formed by subtractive etching of a metal foil, or by additive methods such as applying a conductive paste or plating. Examples of the metal foil include Cu. Examples of the conductive paste include metal nanopaste.

[0026] The underlayer 17 may include one or more layers. For example, the underlayer 17 includes at least one of an adhesion layer and a seed layer. In this example, the underlayer 17 is described as being composed of an adhesion layer and a seed layer. The adhesion layer is a layer that prevents the substrate 11 from peeling off the first conductive layer 12 and the second conductive layer 14, or the substrate 11 from the seed layer. The seed layer is a layer that passes current to form a plating film when the first conductive layer 12 and the second conductive layer 14 are formed by electroplating. Therefore, if their functions overlap, the adhesion layer and the seed layer may be the same. The adhesion layer is, for example, an adhesion layer containing zinc oxide (ZnO). The adhesion layer containing zinc oxide can be formed by, for example, a sol-gel method. The seed layer can be made of Ti, Cr, Cu, or the like. The seed layer containing Ti, Cr, or Cu can be formed by, for example, sputtering. Furthermore, when the first conductive layer 12 and the through electrode 20 are simultaneously formed, it is preferable from the viewpoint of adhesion to have the underlayer 17 cover the entire surface of the through hole 15, which has a depth in the thickness direction relative to the surface of the substrate 11. Therefore, the thickness of the underlayer 17 on the surface of the substrate 11 is preferably 20 nm to 300 nm. The underlayer 17 may be used with the thickness at the time of formation. However, if the underlayer 17 is sufficiently covered on the surface of the through hole 15, the underlayer 17 formed on the substrate 11 may be excessively thick. As a result, the underlayer 17 may be selectively damaged by chemicals, plasma, or the like in subsequent processes, or the conductive layer formed on the underlayer may peel off due to the brittleness of the underlayer 17 itself. To prevent this, the underlayer may be etched in advance after formation to reduce its thickness. For example, the thickness of the underlayer may be reduced until a layer of approximately 1 to 10 nm remains on the substrate surface.

[0027] For example, an inorganic material can be used as the first insulating layer 13, and more specifically, silicon nitride (Si x N y ), silicon dioxide (SiO2), silicon oxynitride (SiO x N y ), thiamin pentoxide Ta2O5, aluminum oxide (Al2O3), aluminum nitride (AlN), hafnium oxide (HfO2), or hafnium oxide doped with aluminum can be used. The first insulating layer 13 desirably has a higher dielectric constant than the insulating layer (e.g., resin layer 22) present around the capacitor 100. The dielectric constant of the first insulating layer 13 is, for example, in the range of 2.0 to 9.0, more preferably 5.0 to 8.0. Among these, silicon nitride (Si) is preferred from the viewpoint of dielectric constant and breakdown voltage. x N y ), silicon oxynitride (SiO x N y ) can be suitably used. The thickness of the first insulating layer 13 (T1 described later) may be 50 nm to 800 nm.

[0028] In the embodiment of the present disclosure, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or the like can be used as the film formation process for the first conductive layer 12, the second conductive layer 14, and the first insulating layer 13. Examples of chemical vapor deposition include plasma-enhanced CVD and atomic layer deposition (ALD). Examples of physical vapor deposition include sputtering and evaporation. Photolithography can be used to form patterns of the conductive layer and the insulating layer. Examples of planarization processes for the conductive layer and the insulating layer include etch-back and chemical mechanical polishing (CMP).

[0029] Next, the structure of the capacitor 100 of this embodiment will be described. As shown in FIG. 1, the first insulating layer 13 is formed on the upper surface 12a of the first conductive layer 12 at a position where the second conductive layer 14 will be disposed. As shown in FIG. 3, the first insulating layer 13 has a first portion 13a, a second portion 13b, and a third portion 13c. The first portion 13a is disposed between the first conductive layer 12 and the second conductive layer 14. The second portion 13b extends continuously from the first portion 13a and covers at least a portion of the side surface 12b of the first conductive layer 12 and at least a portion of the side surface 17a of the base layer 17. The third portion 13c extends continuously from the second portion 13b and covers at least a portion of the first surface 11a of the substrate 11. In this embodiment, the first portion 13a, the second portion 13b, and the third portion 13c are formed of the same material.

[0030] In this embodiment, the second portion 13b of the first insulating layer 13 covers the side surface 12b of the first conductive layer 12 and the side surface 17a of the base layer 17, and the third portion 13c of the first insulating layer 13 covers a portion of the first surface 11a of the substrate 11. For example, if the first insulating layer 13 were composed only of the first portion 13a, a short circuit would likely occur between the first conductive layer 12 and the second conductive layer 14 at the position indicated by the dotted circle in FIG. 3. Furthermore, if the end of the first insulating layer 13 is located inside the end of the second conductive layer 14, a region where the first insulating layer 13 is not present would be created between the first conductive layer 12 and the second conductive layer 14. If a space is formed in this region, the first conductive layer 12 and the second conductive layer 14 may come into contact due to pressure or the like, causing a short circuit. Furthermore, if resin layer 22 flows into this space, resin layer 22, which has a lower relative dielectric constant than first insulating layer 13, becomes a factor that reduces the capacitance of capacitor 100.

[0031] In contrast, in this embodiment, the second portion 13b of the first insulating layer 13 extends continuously from the first portion 13a to cover the side surface 12b of the first conductive layer 12, thereby preventing a short circuit between the first conductive layer 12 and the second conductive layer 14. Although the position of the second conductive layer 14 may be shifted to the left or right in FIG. 3 depending on the patterning accuracy, the first insulating layer 13 covers the side surface 12b of the first conductive layer 12 and the side surface 17a of the base layer 17 with the second portion 13b, and also covers the first surface 11a of the substrate 11 with the third portion 13c. Therefore, even if the position of the second conductive layer 14 is shifted, the first conductive layer 12 and the base layer 17 can be prevented from shorting with the second conductive layer 14. Furthermore, the third portion 13c of the first insulating layer 13 contacts the first surface 11a of the substrate 11, thereby increasing the resistance of the first insulating layer 13 to peeling.

[0032] In order for the second portion 13b of the first insulating layer 13 to effectively function as an insulating film, the thickness T2 of the second portion 13b of the first insulating layer 13 is preferably at least one-quarter of the thickness T1 of the first portion 13a of the first insulating layer 13. There is no particular upper limit to the thickness T2 of the second portion 13b of the first insulating layer 13, but it may be, for example, not greater than the thickness T1 of the first portion 13a of the first insulating layer 13, or may be not greater than one-half of the thickness T1. In addition, the thickness T2 of the second portion 13b of the first insulating layer 13 is preferably at least 25 nm. In consideration of the above, the thickness T1 of the first portion 13a of the first insulating layer 13 is preferably 50 nm to 400 nm, and the thickness T2 of the second portion 13b of the first insulating layer 13 is preferably 25 nm to 200 nm. Furthermore, the length L1 of the third portion 13c of the first insulating layer 13 (the distance from the first conductive layer 12 to the end of the third portion 13c) is preferably 10 μm to 200 μm, and the thickness T3 of the third portion 13c of the first insulating layer 13 is preferably 50 nm to 200 nm.

[0033] Furthermore, the surface roughness (arithmetic mean roughness Ra) of the upper surface 12a of the first conductive layer 12 is preferably small from the viewpoint of the yield of the capacitor 100, and is preferably 0.5 nm to 100 nm. Furthermore, the side surface 12b of the first conductive layer 12 may be a rough surface having a certain degree of roughness as long as it is a portion that does not function as the capacitor 100. For example, the surface roughness (arithmetic mean roughness Ra) of the side surface 12b of the first conductive layer 12 may be 20 nm to 200 nm. Such surface roughness improves the adhesion between the first conductive layer 12 (side surface 12b) and the first insulating layer 13.

[0034] Next, a method for manufacturing the interposer 10, particularly an example of forming the capacitor 100 (first conductive layer 12, first insulating layer 13, and second conductive layer 14), will be described. Figures 4A to 4F are diagrams illustrating a method for manufacturing the interposer 10 according to the first embodiment of the present disclosure. Below, an example will be described in which, simultaneously with the first conductive layer 12, a through electrode 20 electrically connected to the first conductive layer 12 and a third conductive layer 21 electrically connected to the first conductive layer 12 via the through electrode 20 are formed.

[0035] A substrate 11 is prepared, having a first surface 11a and a second surface 11b, and a through-hole 15 penetrating the first surface 11a and the second surface 11b. Then, as shown in FIG. 4A, an underlayer 17 is formed on the first surface 11a, the second surface 11b, and the sidewall 15a of the through-hole 15 of the substrate 11. The following describes an example in which the underlayer 17 is composed of an adhesion layer and a seed layer. First, the adhesion layer is formed by a physical film formation method such as evaporation or sputtering. Next, a seed layer is formed on the adhesion layer, also by the physical film formation method. After that, a step of annealing the adhesion layer and the seed layer may be performed.

[0036] The method for forming the adhesion layer and the seed layer is not limited to the above-described method. For example, an adhesion layer containing zinc oxide (ZnO) or the like may be formed, and then a seed layer may be formed on the adhesion layer by electroless plating. The adhesion layer containing zinc oxide may be formed by a sol-gel method, for example. As described above, both the adhesion layer and the seed layer may be formed by a physical film formation method such as vapor deposition or sputtering, or a combination of the sol-gel method, electroless plating, and physical film formation methods may be used.

[0037] 4B, a first resist layer 31 is formed partially on the underlayer 17. Subsequently, a plating layer is formed by electrolytic plating on the underlayer 17 that is not covered by the first resist layer 31. The plating layer can form the first conductive layer 12 on the first surface 11a of the substrate 11, the through electrodes 20 of the through holes 15, and the third conductive layer 21 on the second surface 11b of the substrate 11. As described above, the underlayer 17 is disposed between the substrate 11 (first surface 11a) and the first conductive layer 12, between the substrate 11 (sidewalls 15a of the through holes 15) and the through electrodes 20, and between the substrate 11 (second surface 11b) and the third conductive layer 21.

[0038] Thereafter, as shown in FIG. 4C , the first resist layer 31 is removed. Furthermore, the portion of the base layer 17 that was covered with the first resist layer 31 (the portion where the first conductive layer 12 is not formed) is removed by, for example, wet etching. This makes it possible to form an inductor including the first conductive layer 12 on the first surface 11a of the substrate 11, the through electrodes 20 in the through holes 15, and the third conductive layer 21 on the second surface 11b of the substrate 11. The inductor will be described in detail in the 24th embodiment. Note that a step of annealing the conductive layer may be performed. Furthermore, when forming through electrodes filled with a conductive material, the conductive material may be filled into the through holes 15 by further performing electrolytic plating.

[0039] Next, a surface treatment step is carried out in which the surface of the first conductive layer 12 is exposed to plasma such as NH3 plasma. This can remove oxides on the surface of the first conductive layer 12. This can improve the adhesion between the first conductive layer 12 and the first insulating layer 13.

[0040] Next, the first insulating layer 13 is formed. First, a resist layer (not shown) is partially formed on the first conductive layer 12 and the first surface 11a of the substrate 11. Next, the first insulating layer 13 is formed on the portions of the first conductive layer 12 and the first surface 11a of the substrate 11 that are not covered with the resist layer and the portions that are covered with the resist layer. At this time, the first insulating layer 13 is formed so as to cover the upper surface 12a of the first conductive layer 12, the side surface 12b of the first conductive layer 12, the side surface 17a of the base layer 17, and the first surface 11a of the substrate 11. As a result, the first insulating layer 13 having the above-mentioned first portion 13a, second portion 13b, and third portion 13c is formed.

[0041] The first insulating layer 13 can be formed by, for example, plasma CVD or sputtering. Sputtering is highly directional, which can make it difficult to form the first insulating layer 13 on the side surface 12b of the first conductive layer 12. Therefore, plasma CVD is preferred. After the first insulating layer 13 is formed, the resist layer is removed, for example, by wet etching. At this time, the first insulating layer 13 formed on the resist layer is removed by lift-off. FIG. 4D shows the state after the resist layer is removed. Alternatively, the first insulating layer 13 may be formed before the resist layer is formed, and then a resist layer may be formed only on the portion of the first insulating layer 13 where the first insulating layer 13 is to remain, so that the first insulating layer 13 is etched away. Alternatively, the first insulating layer 13 may be formed by photolithography, as shown in FIG. 4D.

[0042] Next, as shown in FIG. 4E, a second conductive layer 14 is formed on the first insulating layer 13. This results in a capacitor including the first conductive layer 12, the first insulating layer 13 on the first conductive layer 12, and the second conductive layer 14 on the first insulating layer 13. The process of forming the second conductive layer 14 is similar to the process of forming the first conductive layer 12, for example, a plating layer, and therefore will not be described here. Here, when the second conductive layer 14 is formed of a plating layer, a seed layer or the like may be formed between the second conductive layer 14 and the first insulating layer 13. Note that the second conductive layer 14 may be formed by etching a metal foil or by applying a conductive paste, as described above.

[0043] Subsequently, resin layer 22 is formed, via holes 23 are formed, and connection portions 24 are formed, thereby achieving the configuration shown in FIG. 2 . The thickness of resin layer 22 (in the example of FIG. 2 , the distance from first surface 11a of substrate 11 to the surface of resin layer 22) is preferably greater than or equal to the total thickness of base layer 17, first conductive layer 12, first insulating layer 13, and second conductive layer 14, but not greater than twice the total thickness, in order to flatten the surface irregularities of capacitor 100 and the like. A capacitance component occurs between first conductive layer 12 and connection portion 24 near capacitor 100, but this capacitance should be minimized as much as possible in terms of design. Therefore, it is desirable to form a thick resin layer 22 between first conductive layer 12 and connection portion 24, which has a lower dielectric constant than first insulating layer 13. When the thickness of resin layer 22 is defined as the distance from the surface of first insulating layer 13 to the surface of resin layer 22, it is desirable that the thickness be, for example, at least 10 times the thickness of first insulating layer 13.

[0044] FIG. 4F is a diagram illustrating another example of a method for manufacturing an interposer 10 according to the first embodiment of the present disclosure. While FIG. 4E illustrates an example in which the first insulating layer 13 is not formed around the through hole 15, the first insulating layer 13 may be formed to extend to the through electrode 20 in the through hole 15. As illustrated in FIG. 4F, the first insulating layer 13 may be formed to extend from the first surface 11a of the substrate 11 and cover at least a portion of the through electrode 20. In the example of FIG. 4F, the first insulating layer 13 has a portion 13h that extends continuously from the first portion 13a and covers at least a portion of the through electrode 20. With this configuration, for example, when removing the seed layer by etching after forming the first insulating layer 13, the first insulating layer 13 protects a portion of the through electrode 20 and the conductive layer at the corner of the through hole 15 (the portion at the boundary between the first conductive layer 12 and the through electrode 20). This prevents the through electrode 20 and the surrounding conductive layer from being thinned by etching. The seed layer that is removed by etching after the formation of the first insulating layer 13 is, for example, the seed layer that was used when the second conductive layer 14 was formed by plating.

[0045] Second Embodiment 5 is a schematic cross-sectional view showing a capacitor 100A according to a second embodiment of the present disclosure. In this embodiment, the third portion 13Ac of the first insulating layer 13A does not extend over the first surface 11a of the substrate 11 but covers the side surface 17a of the foundation layer 17. With this configuration, the second portion 13b of the first insulating layer 13A covers the side surface 12b of the first conductive layer 12 and the side surface 17a of the foundation layer 17, and extends from the second portion 13b to the third portion 13Ac of the first insulating layer 13A until it contacts the substrate 11. This prevents the first conductive layer 12 and the foundation layer 17 from shorting out with the second conductive layer 14.

[0046] <Third embodiment> FIG. 6 is a schematic cross-sectional view showing a capacitor 100B according to a third embodiment of the present disclosure. In this embodiment, the second portion 13Bb of the first insulating layer 13B extends from the first portion 13a to a position between the upper end 12c and the lower end 12d of the side surface 12b of the first conductive layer 12. As described above, the second portion 13b of the first insulating layer 13B does not need to cover the entire side surface 12b of the first conductive layer 12; it is sufficient that the second portion 13Bb covers at least a portion of the side surface 12b of the first conductive layer 12. With this configuration, the second portion 13Bb of the first insulating layer 13B extends continuously from the first portion 13a and covers a portion of the side surface 12b of the first conductive layer 12. This prevents the first conductive layer 12 from shorting with the second conductive layer 14.

[0047] 6 can be formed by, for example, lift-off using a resist layer. For example, a resist layer thinner than the first conductive layer 12 is formed on the portion other than the first conductive layer 12, and the first insulating layer 13B is formed on the first conductive layer 12 and the resist layer. Thereafter, the resist layer is removed to form the second portion 13Bb of the first insulating layer 13B that covers part of the side surface 12b.

[0048] <Fourth embodiment> FIG. 7 is a schematic cross-sectional view showing a capacitor 100C according to a fourth embodiment of the present disclosure. In this embodiment, the planar size of the base layer 17C is larger than the planar size of the first conductive layer 12. That is, the base layer 17C extends outward from the side surface 12b of the first conductive layer 12 by a distance D1, and the side surface 17Ca of the base layer 17C is located outward from the side surface 12b of the first conductive layer 12. That is, an upper surface 17Cf that is not covered by the first conductive layer 12 appears at the end of the base layer 17C. The second portion 13Cb of the first insulating layer 13C covers the side surface 12b of the first conductive layer 12 and the upper surface 17Cf and side surface 17Ca of a portion (end) of the base layer 17, and extends from the second portion 12Cb to the third portion 13Cc of the first insulating layer 13C until it contacts the substrate 11. This prevents the first conductive layer 12 and the base layer 17C from shorting with the second conductive layer 14. The distance D1 is preferably 20 nm to 1000 nm.

[0049] Fifth Embodiment FIG. 8 is a schematic cross-sectional view showing a capacitor 100D according to a fifth embodiment of the present disclosure. In this embodiment, the planar size of the base layer 17D is smaller than the planar size of the first conductive layer 12. That is, the base layer 17D has a side surface 17Da that is recessed a distance D2 inward from the side surface 12b of the first conductive layer 12. As a result, a recess portion 17Db is formed by the first conductive layer 12, the substrate 11, and the base layer 17D. This recess portion 17Db and the first insulating layer 13 form a space 18 below the first conductive layer 12. The second portion 13b and the third portion 13c of the first insulating layer 13 are arranged to leave at least a portion of the space 18. Thus, even when at least a portion of the space 18 remains as a void, the insulating effect of the third portion 13c of the first insulating layer 13 prevents the first conductive layer 12 and the base layer 17 from shorting with the second conductive layer 14.

[0050] Sixth Embodiment FIG. 9 is a schematic cross-sectional view showing a capacitor 100E according to a sixth embodiment of the present disclosure. In this embodiment, the second portion 13Eb and the third portion 13Ec of the first insulating layer 13E are disposed so as to fill the recessed portion 17Db (see FIG. 8). With this configuration, the second portion 13Eb and the third portion 13Ec of the first insulating layer 13E fill the recessed portion 17Db below the first conductive layer 12. Therefore, compared to the configuration of FIG. 8, it is possible to more effectively prevent the first conductive layer 12 and the base layer 17D from shorting with the second conductive layer 14. Furthermore, because the first insulating layer 13E penetrates into the recessed portion 17Db, adhesion between the first conductive layer 12 and the base layer 17D is also improved. From the viewpoint of preventing such short circuits and improving adhesion, the size of the recessed portion 17Db of the underlayer 17D, that is, the distance D2 from the first insulating layer 13 to the side surface 17Da of the underlayer 17, is preferably 20 nm to 1000 nm.

[0051] Seventh Embodiment FIG. 10 is a schematic cross-sectional view showing a capacitor 100F according to a seventh embodiment of the present disclosure. In this embodiment, in the configuration shown in FIG. 9, a second conductive layer 14F is disposed across the first portion 13a, the second portion 13Eb, and the third portion 13Ec of the first insulating layer 13E. This configuration provides a large contact area between the second conductive layer 14F and the first insulating layer 13E, resulting in good adhesion. Furthermore, this configuration reduces the distance between the second conductive layer 14F and the first conductive layer 12 and the base layer 17D. However, because the second portion 13Eb and the third portion 13Ec of the first insulating layer 13E fill the recessed portion 17Db below the first conductive layer 12, it is possible to prevent the first conductive layer 12 and the base layer 17D from shorting with the second conductive layer 14F.

[0052] Eighth Embodiment FIG. 11 is a schematic cross-sectional view showing a capacitor 100G according to an eighth embodiment of the present disclosure. This embodiment corresponds to the capacitor 100 of the first embodiment shown in FIG. 3, except that a first conductive layer 12G is formed without using an underlayer 17. With this configuration, the first insulating layer 13 covers the side surface 12Gb of the first conductive layer 12G with the second portion 13b and extends to the first surface 11a of the substrate 11 with the third portion 13c. Therefore, even if the second conductive layer 14 is misaligned, a short circuit between the first conductive layer 12G and the second conductive layer 14 can be prevented. Furthermore, since the third portion 13c of the first insulating layer 13 is in contact with the first surface 11a of the substrate 11, the resistance of the first insulating layer 13 to peeling is increased.

[0053] Ninth Embodiment FIG. 12 is a schematic cross-sectional view showing a capacitor 100H according to a ninth embodiment of the present disclosure. This embodiment corresponds to the capacitor 100A according to the second embodiment shown in FIG. 5, except that the first conductive layer 12G is formed without the base layer 17. That is, the second portion 13b of the first insulating layer 13A covers the entire side surface 12Gb of the first conductive layer 12G between the upper end 12Gc and the lower end 12Gd. With this configuration, the second portion 13b of the first insulating layer 13A extends continuously from the first portion 13a to entirely cover the side surface 12Gb of the first conductive layer 12G. This prevents the first conductive layer 12G from being shorted with the second conductive layer 14.

[0054] Tenth Embodiment FIG. 13 is a schematic cross-sectional view showing a capacitor 100I according to a tenth embodiment of the present disclosure. This embodiment corresponds to the capacitor 100B according to the third embodiment shown in FIG. 6, except that the first conductive layer 12G is formed without the base layer 17. That is, the second portion 13Bb of the first insulating layer 13B covers the side surface 12Gb of the first conductive layer 12G up to a position between the upper end 12Gc and the lower end 12Gd. With this configuration, the second portion 13Bb of the first insulating layer 13B extends continuously from the first portion 13a to cover a portion of the side surface 12Gb of the first conductive layer 12G. This prevents the first conductive layer 12G from being shorted with the second conductive layer 14.

[0055] Eleventh Embodiment FIG. 14 is a schematic cross-sectional view showing a capacitor 100J according to an eleventh embodiment of the present disclosure. Like the capacitor 100J, the insulating layer covering the side surface 12b of the first conductive layer 12 and the side surface 17a of the underlayer 17 may be formed of a second insulating layer 19 made of a material different from that of the first insulating layer 13. In this embodiment, the first insulating layer 13J is composed of a first portion 13a disposed between the first conductive layer 12 and the second conductive layer 14. That is, the first insulating layer 13J is disposed only on the upper surface 12a of the first conductive layer 12. The second insulating layer 19 has a first portion 19a, a second portion 19b, and a third portion 19c. The first portion 19a is disposed on the first insulating layer 13J. The second portion 19b extends continuously from the first portion 19a to cover the side surface 12b of the first conductive layer 12 and the side surface 17a of the underlayer 17. The third portion 19c extends continuously from the second portion 19b and covers at least a part of the first surface 11a of the substrate 11.

[0056] The second insulating layer 19 can be made of an organic or inorganic material. When a recess 17Db is present as in the sixth embodiment shown in FIG. 9 , the second insulating layer 19 can be made of resin, thereby filling the recess 17Db below the first conductive layer 12 by utilizing the deformation of the resin. More preferably, the second insulating layer 19 is a photosensitive resin that can be patterned with light, such as a photosensitive polyimide. Alternatively, the second insulating layer 19 may be a resin that can form an opening with a laser, such as an epoxy resin. This configuration allows the second insulating layer 19 to cover the side surface 12b of the first conductive layer 12, the side surface 17a of the base layer 17, and the first surface 11a of the substrate 11, thereby preventing the first conductive layer 12 and the base layer 17 from shorting with the second conductive layer 14. In this embodiment, the thickness of the second portion 19b of the second insulating layer 19 is defined as T2, and the thickness of the third portion 19c is defined as T3. The thicknesses of the above-described embodiments can be applied.

[0057] 15A to 15C are diagrams illustrating a method for manufacturing a capacitor according to an eleventh embodiment of the present disclosure. This method can be performed in accordance with the process shown in FIG. 4D in the first embodiment. First, as shown in FIG. 15A, a first insulating layer 13J is formed on the upper surface 12a of the first conductive layer 12. Next, as shown in FIG. 15B, a dry film-like photosensitive resin is formed by vacuum lamination so as to cover the first insulating layer 13J, the side surface 12b of the first conductive layer 12, and a portion of the first surface 11a of the substrate 11. Here, for example, a photosensitive polyimide can be used as the photosensitive resin. This results in a second insulating layer 19 having a first portion 19a disposed on the first insulating layer 13J, a second portion 19b covering the side surface 12b of the first conductive layer 12, and a third portion 19c covering at least a portion of the first surface 11a of the substrate 11. The laminated photosensitive resin is then placed under atmospheric pressure. As a result, in the fifth embodiment in which the space 18 is formed as shown in FIG. 8, the internal pressure of the space 18 is the pressure during lamination molding. Therefore, when placed under atmospheric pressure, the space 18 collapses due to the pressure difference, and as a result, the photosensitive resin penetrates into the recess portion 17Db below the first conductive layer 12, as in the sixth embodiment shown in FIG. 9. Next, as shown in FIG. 15C, a portion of the first portion 19a and a portion of the third portion 19c of the second insulating layer 19 are removed by photolithography. The portion of the first portion 19a is the portion where the second conductive layer 14 is formed on the first insulating layer 13J. By removing this portion, the first portion 13a of the first insulating layer 13J is exposed. The portion of the third portion 19c is the portion that is separated from the second portion 19b by a predetermined distance. Alternatively, a dry film-like non-photosensitive resin may be formed by vacuum lamination to cover the first insulating layer 13, the side surface 12b of the first conductive layer 12, and a portion of the first surface 11a of the substrate 11, and then a portion of the first portion 19a and a portion of the third portion 19c of the second insulating layer 19 described above may be removed by irradiating with a UV laser, a carbon dioxide laser, or an excimer laser. The dry film-like non-photosensitive resin may be, for example, an epoxy resin. Next, as shown in FIG. 14 , a second conductive layer 14 is formed in the portion of the second insulating layer 19 where the first insulating layer 13J is exposed.At this time, the second conductive layer 14 is also formed on a part of the second insulating layer 19 .

[0058] The method shown in FIGS. 15A to 15C is advantageous in a configuration in which an insulating layer is disposed in a recessed portion 17Db formed below the first conductive layer 12, as in the sixth embodiment shown in FIG. 9. After laminating a photosensitive or non-photosensitive resin under a first pressure, the substrate is placed under a second pressure higher than the first pressure applied during lamination. This facilitates penetration of the photosensitive or non-photosensitive resin into the recessed portion 17Db below the first conductive layer 12, thereby facilitating filling of the recessed portion 17Db with resin. In the above example, the first pressure is vacuum and the second pressure is atmospheric pressure, but this is not a limitation. The second pressure may be higher than the first pressure. Furthermore, in a configuration in which the recessed portion 17Db is not present or in which a space 18 may remain in the recessed portion 17Db, the second pressure may be lower than or equal to the first pressure.

[0059] <Twelfth embodiment> FIG. 16 is a schematic cross-sectional view showing a capacitor 100K according to a twelfth embodiment of the present disclosure. Like the capacitor 100K, it may be divided into multiple regions. For example, in FIG. 16, capacitors 100K-1, 100K-2, and 100K-3 are arranged on a substrate 11. While FIG. 16 shows a case where there are three multiple regions, the number of multiple regions is not limited to three. A space SP1 is arranged between the capacitors 100K-1 and 100K-2. A space SP2 is arranged between the capacitors 100K-2 and 100K-3. That is, the capacitor 100K-2 is arranged between the capacitors 100K-1 and 100K-3.

[0060] Capacitor 100K-1 has an underlayer 17K-1, a first conductive layer 12K-1, a first insulating layer 13K-1, and a second conductive layer 14K-1. Capacitor 100K-2 has an underlayer 17K-2, a first conductive layer 12K-2, a first insulating layer 13K-2, and a second conductive layer 14K-2. Capacitor 100K-3 has an underlayer 17K-3, a first conductive layer 12K-3, a first insulating layer 13K-3, and a second conductive layer 14K-3. Note that underlayers 17K-1, 17K-2, and 17K-3 do not necessarily have to be formed.

[0061] When the gap SP1 between the first conductive layer 12K-1 and the first conductive layer 12K-2 is narrow, i.e., when the first conductive layer 12K-1 and the first conductive layer 12K-2 are close to each other, the insulating layer is less likely to be deposited in the region facing the gap SP1. As a result, the first insulating layers 13K-1 and 13K-2 are not formed on a portion of the side surfaces of the first conductive layer 12K-1 and the first conductive layer 12K-2 that face the gap SP1. Similarly, the first insulating layers 13K-2 and 13K-3 are not formed on a portion of the side surfaces of the first conductive layer 12K-2 and the first conductive layer 12K-3 that face the gap SP2. Even with this configuration, the second conductive layer is less likely to be formed in the gaps SP1 and SP2, and the first conductive layers 12K-1, 12K-2, and 12K-3 and the base layers 17K-1, 17K-2, and 17K-3 can be prevented from shorting out with the second conductive layers 14K-1, 14K-2, and 14K-3.

[0062] <Thirteenth embodiment> FIG. 17 is a schematic cross-sectional view showing a capacitor 100L according to a thirteenth embodiment of the present disclosure. The capacitor 100L of this embodiment further includes an intermediate layer 26 between the first conductive layer 12L and the first insulating layer 13L. The intermediate layer 26 is preferably made of a conductive material for improving adhesion between the first conductive layer 12L and the first insulating layer 13L, and examples of such a conductive material include titanium (Ti), titanium nitride (TiN), nickel (Ni), and a nickel-gold alloy (Ni—Au). The thickness of the intermediate layer 26 is preferably 20 nm to 200 nm. The intermediate layer 26 may be omitted. By using a conductive material for improving adhesion as the intermediate layer 26, the first insulating layer 13L is less likely to peel off when the second resist layer 32 (see FIG. 18E) is removed by lift-off, as described below.

[0063] In this embodiment, the first portion 13a of the first insulating layer 13L is disposed between the intermediate layer 26 and the first conductive layer 12L. The first portion 13a of the first insulating layer 13L covers the upper surface 26a of the intermediate layer 26, the second portion 13b of the first insulating layer 13L covers the side surface 26b of the intermediate layer 26 and the side surface 12b of the first conductive layer 12L, and further, the third portion 13c of the first insulating layer 13L covers the first surface 11a of the substrate 11. In this embodiment, the thickness T4 of the third portion 13c is preferably 50 nm to 200 nm.

[0064] The first insulating layer 13L also has a fourth portion 13d connected to the third portion 13c and extending in a direction intersecting the first surface 11a of the substrate 11. In other words, the fourth portion 13d extends outward relative to the substrate 11. In the example of FIG. 17, the fourth portion 13d extends continuously from the third portion 13c and rises from the first surface 11a of the substrate 11. The fourth portion 13d has a tapered shape such that the width of its top is smaller than the width of its bottom. The height H1 of the fourth portion 13d is preferably 25 μm or greater. This embodiment has the following advantages. For example, in a structure such as the second conductive layer 14F of the seventh embodiment shown in FIG. 10, the second conductive layer 14F is blocked by the fourth portion 13d, thereby further improving insulation against adjacent MIM structures, such as capacitors.

[0065] In this embodiment, the length L2 of the third portion 13c (the distance from the first conductive layer 12L to the end of the third portion 13c) is preferably 20 μm or more. By setting the length L2 of the third portion 13c within the above range, the first insulating layer 13 is less likely to peel off when the second resist layer 32 (see FIG. 18E) is removed by lift-off, which will be described below.

[0066] 18A to 18F are views illustrating a method for manufacturing a capacitor 100L according to a thirteenth embodiment of the present disclosure. 18A to 18F show steps after a first conductive layer 12L is formed on the first surface 11a of a substrate 11. Fig. 18A is an enlarged view of the first surface 11a side in the state of Fig. 4B.

[0067] As shown in FIG. 18A, a first conductive layer 12L is formed on the first surface 11a of the substrate 11. Next, as shown in FIG. 18B, a layer of a conductive material (corresponding to the intermediate layer 26), such as titanium, is formed by physical vapor deposition (PVD) or the like to cover the upper surface 12a of the first conductive layer 12L and the upper surface 31a of the first resist layer 31. Here, examples of physical vapor deposition include sputtering and evaporation. Next, as shown in FIG. 18C, the first resist layer 31 is removed by lift-off. Lift-off is a method of peeling off the resist and leaving only the desired pattern. During this lift-off, the layer of conductive material formed on the upper surface of the first resist layer 31 is removed together with the first resist layer 31. As a result, the intermediate layer 26 is formed on the upper surface 12a of the first conductive layer 12L. Then, portions of the base layer 17 that were covered by the first resist layer 31 (portions where the first conductive layer 12L is not formed) are removed by, for example, wet etching. After removing the first resist layer 31, a process of removing resist residue by dry surface treatment may be performed, which can improve the adhesion of the first insulating layer 13L formed in the next step.

[0068] Next, as shown in FIG. 18D, a second resist layer 32 is formed around the first conductive layer 12L at a predetermined distance (corresponding to the distance L2 described above) from the first conductive layer 12L. Next, as shown in FIG. 18E, a first insulating layer 13L is formed to cover the upper surface 26a and side surface 26b of the intermediate layer 26, the side surface 12b of the first conductive layer 12L, the first surface 11a of the substrate 11, and the upper surface 32a and side surface 32b of the second resist layer 32. Next, as shown in FIG. 18F, the second resist layer 32 is removed by lift-off. In this embodiment, the second resist layer 32 is removed by lift-off so as to leave at least a portion of the first insulating layer 13L formed on the side surface 32b of the second resist layer 32. During this lift-off, the first insulating layer 13L formed on the upper surface 32a of the second resist layer 32 is removed together with the second resist layer 32. During the lift-off, the second resist layer 32 is removed by being pulled upward, forming a tapered (thin-tapered) fourth portion 13d. This results in the formation of a first insulating layer 13L having a first portion 13a disposed on the intermediate layer 26, a second portion 13b covering the side surface 26b of the intermediate layer 26 and the side surface 12b of the first conductive layer 12L, a third portion 13c covering at least a portion of the first surface 11a of the substrate 11, and a fourth portion 13d formed to rise from the first surface 11a of the substrate 11. Thereafter, as shown in FIG. 17, a second conductive layer 14 is formed on the first insulating layer 13L at a position corresponding to the intermediate layer 26.

[0069] 18A to 18F, the number of steps can be reduced by performing the conductive layer formation step and resist peeling (i.e., lift-off) without using etching as much as possible. Furthermore, when a transparent substrate such as a glass substrate is used as substrate 11, the transparency of the glass substrate is maintained more than when etching is used extensively, which is advantageous when optical elements that are affected by the transparency of the glass substrate are located near an MIM structure such as a capacitor.

[0070] 19 is a diagram illustrating the positional relationship of a capacitor 100L according to a thirteenth embodiment of the present disclosure. In an MIM structure such as a capacitor manufactured using lift-off, the distance L3 between adjacent MIM structures (the distance from the edge of the first insulating layer 13L of one MIM structure to the edge of the first insulating layer 13L of the adjacent MIM structure) is preferably 10 μm to 1 mm. The above-mentioned range of L3 can be set by adjusting the width of the second resist layer 32 in FIG. 18D. Setting L3 within the above-mentioned range can shorten the time required for the lift-off process, resulting in a structure suitable for lift-off.

[0071] <Fourteenth embodiment> 20A to 20E are diagrams illustrating another method for manufacturing the capacitor 100 according to the first embodiment. Because the manufacturing method is different, this is shown as the fourteenth embodiment. FIG. 20A is an enlarged view of the first surface 11a side in the state of FIG. 4C. As shown in FIG. 20A, a first conductive layer 12 is formed on the first surface 11a of the substrate 11. Next, as shown in FIG. 20B, a first insulating layer 13 is formed on the upper surface 12a and side surface 12b of the first conductive layer 12 and on the first surface 11a of the substrate 11. Next, as shown in FIG. 20C, a second conductive layer 14 is formed on a portion of the first insulating layer 13 corresponding to the upper surface 12a of the first conductive layer 12. Next, as shown in FIG. 20D, a resist layer 33 is formed to cover the second conductive layer 14 and to cover a portion of the third portion 13c extending from the second portion 13b of the first insulating layer 13 onto the first surface 11a of the substrate 11 (i.e., the base portion of the first insulating layer 13). Next, as shown in FIG. 20E, the first insulating layer 13 not covered with the resist layer 33 is removed by etching or milling. Thereafter, the resist layer 33 is removed. This completes the manufacture of the capacitor 100 shown in FIG. 3. Here, the etching may be, for example, reactive ion etching (RIE). The milling may be, for example, Ar milling.

[0072] FIG. 21A is a schematic plan view showing an interposer 10 according to a fourteenth embodiment of the present disclosure. More specifically, FIG. 21A is a schematic plan view of an interposer 10 including a capacitor 100 manufactured by the method of FIGS. 20A to 20E described above. For simplicity of explanation, many components are omitted from FIG. 21A, and only a portion of the first insulating layer 13 and second conductive layer 14 formed on the first surface 11a of the substrate 11 is shown for the capacitor 100. A resin layer 22 is formed on the first surface 11a of the substrate 11 so as to cover the capacitor 100 (MIM structure). Around the area where the capacitor 100 is disposed, a ring-shaped conductive layer 29 and a first insulating layer 13 are formed along the edge of the resin layer 22.

[0073] FIG. 21B is a schematic cross-sectional view (cross-sectional view along line CC in FIG. 21A ) showing a ring-shaped conductive layer 29 included in an interposer according to a fourteenth embodiment of the present disclosure. The conductive layer 29 is disposed on a first insulating layer 13, which is also formed in a ring shape. Preferably, the width of the first insulating layer 13 is greater than the width of the conductive layer 29. The conductive layer 29 can be formed during the manufacturing method shown in FIG. 20C . For example, the conductive layer 29 is formed simultaneously with the step of forming the second conductive layer 14. When forming the second conductive layer 14 in the step shown in FIG. 20C , the ring-shaped conductive layer 29 is also formed on the first insulating layer 13 along the position where the end of the resin layer 22 is to be formed. Thereafter, in the step shown in FIG. 20D , a resist layer 33 is formed with a width greater than the width of the conductive layer 29, as indicated by the two-dot chain line in FIG. 21B . As a result, even after the step of removing the first insulating layer 13, a first insulating layer 13 wider than the conductive layer 29 remains. According to this configuration, a first insulating layer 13 that is wider than the conductive layer 29 is arranged between the conductive layer 29 and the substrate 11 at the end position of the resin layer 22, and therefore the first insulating layer 13 improves adhesion at the end of the resin layer 22.

[0074] <Fifteenth to nineteenth embodiments> Next, the configurations of the capacitors (first conductive layer, first insulating layer, and second conductive layer) according to the fifteenth to nineteenth embodiments will be described with reference to Figures 22 to 24. The configurations described in these figures are applicable to the capacitor configurations in all of the above-mentioned embodiments.

[0075] FIG. 22A is a schematic plan view showing a capacitor 100M1 according to a fifteenth embodiment of the present disclosure. FIG. 22B is a schematic plan view showing a capacitor 100M2 according to a sixteenth embodiment of the present disclosure. These schematic plan views are plan views of the first surface 11a of the substrate 11 as viewed from above. At least one of the multiple corners 13e of the first insulating layer 13M may have a rounded shape. As shown in FIG. 22A, preferably, all four corners 13e of the first insulating layer 13M have a rounded shape. Preferably, the radius of curvature of the corners 13e is 5 μm or more. This configuration reduces stress concentration at the corners 13e, thereby preventing peeling of the first insulating layer 13M.

[0076] As shown in FIG. 22B, at least one of the multiple corners 12e of the first conductive layer 12M may have a rounded shape. Preferably, all four corners 12e of the first conductive layer 12M have a rounded shape. Also, at least one of the multiple corners 14e of the second conductive layer 14M may have a rounded shape. Preferably, all four corners 14e of the second conductive layer 14M have a rounded shape. This configuration can reduce stress on the corners of both the first conductive layer 12M and the second conductive layer 14M, thereby improving the resistance to peeling of the entire capacitor (MIM structure). Note that if at least one corner of the first conductive layer 12M or the second conductive layer 14M is rounded, the aforementioned effect of resistance to peeling can be obtained. The radius of curvature of the corners of the first conductive layer 12M and the second conductive layer 14M is preferably 5 μm or more.

[0077] FIG. 23 is a schematic plan view showing a capacitor 100N according to a seventeenth embodiment of the present disclosure. This schematic plan view shows the first surface 11a of the substrate 11 as viewed from above. The configuration for preventing peeling is not limited to a rounded shape. For example, multiple corner portions 13e of the first insulating layer 13N may have reinforcing portions 13f. In the example shown in FIG. 23, the corner portions 13e have reinforcing portions 13f that are rectangular in plan view. Reinforcing the corner portions 13e, which are usually pointed, with wide reinforcing portions 13f can prevent peeling from the corner portions 13e. The shape of the reinforcing portions 13f is not limited to a rectangular shape and may be any other shape that contributes to preventing peeling. For example, other shapes may be those that extend from the corner portions 13e and are surrounded by straight lines as exemplified in this embodiment, or may be surrounded by curved lines such as a circle, or may be surrounded by a combination of straight lines and curved lines.

[0078] FIG. 24A is a schematic plan view showing a capacitor 100P according to an eighteenth embodiment of the present disclosure. FIG. 24B is a schematic plan view showing a capacitor 100Q according to a nineteenth embodiment of the present disclosure. These schematic plan views are plan views of the first surface 11a of the substrate 11 as viewed from above. A plurality of second conductive layers 14P may be formed (patterned) independently of one another on the first insulating layer 13P. In the example of FIG. 24A, the second conductive layer 14P on the first insulating layer 13P is composed of four conductive portions. As shown in the figure, the corners of each of the four conductive portions may have a rounded shape.

[0079] 24B, the second conductive layer 14Q may have a slit 14g formed to extend inward from the corner 14e. As illustrated in the configurations of FIGS. 24A and 24B, the pattern of the second conductive layer 14 can be appropriately changed to improve design freedom. For example, this improves design freedom when connecting the second conductive layer 14 to a conductive layer of an adjacent capacitor (MIM structure) and when connecting the second conductive layer 14 to a semiconductor chip 50 or a wiring substrate 40.

[0080] <20th to 22nd Embodiments> Next, a configuration in which multiple capacitors (MIM structures) are arranged adjacent to each other will be described. The configuration described below is applicable to all of the above-mentioned embodiments. FIG. 25A is a schematic plan view showing the positional relationship between first conductive layers 12-1 and 12-2 and a first insulating layer 13R of a capacitor 100R according to a twentieth embodiment of the present disclosure. FIG. 25B is a schematic plan view showing the positional relationship between first conductive layers 12-1 and 12-2 and a first insulating layer 13S of a capacitor 100S according to a twenty-first embodiment of the present disclosure. FIG. 25C is a schematic plan view showing the positional relationship between first conductive layers 12-1 and 12-2 and a first insulating layer 13T of a capacitor 100T according to a twenty-second embodiment of the present disclosure. These schematic plan views are views of the first surface 11a of the substrate 11 as viewed from above. The second conductive layer 14 is omitted from FIGS. 25A to 25C.

[0081] As in the capacitor 100R shown in FIG. 25A, the first insulating layer 13R may be disposed across the adjacent first conductive layers 12-1 and 12-2. That is, the first insulating layer 13R includes a portion covering each of the adjacent first conductive layers 12-1 and 12-2, and a third portion 13Rc on the first surface 11a of the substrate 11 that connects these portions. Thus, the third portion 13Rc is formed to connect the adjacent first conductive layers 12-1 and 12-2. In this example, the first insulating layer 13R is rectangular in plan view. In the manufacturing process of the interposer 10, if the distance between adjacent capacitors (MIM structure) (more specifically, the distance D3 between the first conductive layers 12-1 and 12-2) becomes small, the resolution limit of the resist may be reached, resulting in an unstable film shape or the generation of foreign matter. These may be sources of film peeling. In particular, when first conductive layers 12-1 and 12-2 are formed together with through-hole electrode 20, they are formed much thicker than the thickness required to function as a capacitor. Therefore, when distance D3 is reduced, the aspect ratio of the slit formed between first conductive layers 12-1 and 12-2 increases, making it difficult to control the thickness of the resist in the slit. As a result, it becomes difficult to control the shape of first insulating layer 13R.

[0082] By connecting the first insulating layer 13R between adjacent first conductive layers 12-1 and 12-2 without separating them for each capacitor, design freedom is improved without having to worry about the resolution limit of the resist. Furthermore, the film shape is stabilized and the generation of foreign matter can be prevented. Furthermore, since the above-mentioned manufacturing process issues can be resolved, the distance between adjacent first conductive layers 12-1 and 12-2 can be made smaller than when adjacent first conductive layers 12-1 and 12-2 are each covered with a separate first insulating layer 13. Therefore, higher wiring density is possible.

[0083] In the above-described configuration, the distance D3 is preferably 10 μm to 100 μm.

[0084] Other shapes may be adopted for the shape of the first insulating layer 13R. As in the capacitor 100S shown in FIG. 25B, the first insulating layer 13S on adjacent first conductive layers 12-1 and 12-2 may be formed so as to be partially connected. That is, the third portion 13Sc of the first insulating layer 13S on the first surface 11a of the substrate 11 may be formed so as to narrow its width between adjacent first conductive layers 12-1 and 12-2, thereby connecting the adjacent first conductive layers 12-1 and 12-2. Furthermore, as in the capacitor 100T shown in FIG. 25C, the third portion 13Tc of the first insulating layer 13 on the first surface 11a of the substrate 11 may have a slit portion 13g.

[0085] 25A to 25C show an example in which first insulating layers 13R, 13S, and 13T are formed across two adjacent first conductive layers 12-1 and 12-2, but first insulating layers 13R, 13S, and 13T may be arranged across three or more first conductive layers 12 in shapes similar to those shown in Figures 25A to 25C (third portions 13Rc, 13Sc, and 13Tc between each first conductive layer). Furthermore, although the periphery of first insulating layers 13R, 13S, and 13T is formed by straight lines in a plan view, the periphery may be formed by curves in consideration of design freedom, resist resolution, and adhesion to first surface 11a.

[0086] FIG. 26A is a schematic cross-sectional view of adjacently arranged capacitors 100 according to the first embodiment of the present disclosure. FIG. 26B is a schematic cross-sectional view illustrating an example of the arrangement of the second conductive layer 14 of a capacitor 100R according to the twentieth embodiment of the present disclosure. FIG. 26C is a schematic cross-sectional view illustrating another example of the arrangement of the second conductive layer 14R of a capacitor 100R according to the twentieth embodiment of the present disclosure. These schematic cross-sectional views are schematic cross-sectional views of adjacent capacitors (MIM structure). FIG. 26A illustrates a configuration in which adjacently arranged capacitors 100 according to the first embodiment of the present disclosure are arranged. Specifically, a first insulating layer 13-1 covers a portion of the first conductive layer 12-1 and a portion of the first surface 11a of the substrate 11, and a second conductive layer 14-1 is formed on the first insulating layer 13-1. A first insulating layer 13-2 covers a portion of the first conductive layer 12-2 and a portion of the first surface 11a of the substrate 11, and a second conductive layer 14-2 is formed on the first insulating layer 13-2.

[0087] FIG. 26B is an example of the configuration shown in FIGS. 25A to 25C. Here, a case where FIG. 26B applies to the example of FIG. 25A will be described. As described above, first insulating layer 13R is formed across adjacent first conductive layers 12-1 and 12-2. First insulating layer 13R has third portion 13Rc disposed on first surface 11a of substrate 11 between adjacent first conductive layers 12-1 and 12-2, and is formed so as to connect first insulating layer 13R on first conductive layer 12-1 with first insulating layer 13R on first conductive layer 12-2. Second conductive layer 14-1 is formed on a portion of first insulating layer 13R corresponding to first conductive layer 12-1, and second conductive layer 14-2 is formed on a portion of first insulating layer 13R corresponding to first conductive layer 12-2.

[0088] FIG. 26C shows another example of the configuration shown in FIGS. 25A to 25C. Here, a case where FIG. 26C applies to the example of FIG. 25A will be described. First insulating layer 13R is formed across adjacent first conductive layers 12-1 and 12-2. Second conductive layer 14R is formed similarly. Specifically, second conductive layer 14R is formed across a portion of first insulating layer 13R corresponding to first conductive layer 12-1, a third portion 13Rc of first insulating layer 13R between adjacent first conductive layers 12-1 and 12-2, and a portion of first insulating layer 13R corresponding to first conductive layer 12-2.

[0089] <Twenty-third embodiment> FIG. 27 is a schematic cross-sectional view of a capacitor 100P according to the 23rd embodiment of the present disclosure, arranged adjacent to one another. This example illustrates a modification of the configuration of FIG. 24A. The second conductive layer 14P-1 on the first insulating layer 13P-1 may be composed of a plurality of conductive portions (a first conductive portion 14P-1a and a second conductive portion 14P-1b) that are separated from one another. The second conductive layer 14P-2 on the first insulating layer 13P-2 may be composed of a plurality of conductive portions (a first conductive portion 14P-2a and a second conductive portion 14P-2b). In such a configuration, a portion of the second conductive layer 14P-1 and a portion of the second conductive layer 14P-2 may be electrically connected. In the example of FIG. 27, the second conductive portion 14P-1b of the second conductive layer 14P-1 and the first conductive portion 14P-2a of the second conductive layer 14P-2 are connected via a connection portion 24.

[0090] <Twenty-fourth embodiment> Figure 28 is a schematic plan view showing a capacitor 100U and an inductor 27 included in an interposer 10U according to a 24th embodiment of the present disclosure. This schematic plan view is a plan view showing a first conductive layer 12U on the first surface 11a side of a substrate 11. Some components such as a connection portion 24 are omitted from Figure 28. Figure 29 is a schematic cross-sectional view (cross-sectional view along line DD in Figure 28) showing an interposer according to the 24th embodiment of the present disclosure.

[0091] 28, the interposer 10U may include at least an inductor 27 and a capacitor 100U. The interposer 10U may include at least a through electrode 20a electrically connected to the first conductive layer 12U and a plurality of through electrodes 20b constituting the inductor 27. The through electrode 20a is formed in a through hole 15-1 between the inductor 27 and the capacitor 100U (the first conductive layer 12U, the first insulating layer 13U, and the second conductive layer 14U). Furthermore, the plurality of through electrodes 20b are formed in the plurality of through holes 15-2 within the area of ​​the inductor 27 surrounded by the dotted line.

[0092] 29, a portion of first conductive layer 12U on the first surface 11a side of substrate 11 constitutes inductor 27, and another portion of first conductive layer 12U constitutes the lower electrode of capacitor 100U. On the first surface 11a side of substrate 11, thickness Th1 of first conductive layer 12U that constitutes inductor 27 may be substantially the same as thickness Th2 of first conductive layer 12U that constitutes the lower electrode of capacitor 100U. Note that the two thicknesses can be considered to be substantially the same if they satisfy the following relationship: -10% ≦ (Th1-Th2) / Th1≦ +10%

[0093] The thickness of first conductive layer 12U may be 0.5 μm to 20 μm as described above, but more preferably 5 μm to 20 μm, because this improves the performance of inductor 27. The thickness of through electrodes 20a, 20b may be 50% to 100% of the thickness of first conductive layer 12U on first surface 11a of substrate 11.

[0094] <Twenty-fifth embodiment> FIG. 30 is a schematic plan view showing a capacitor 100V according to a 25th embodiment of the present disclosure. This embodiment illustrates an example in which the second conductive layer 14 of the capacitor 100 according to the first embodiment also serves as the connection portion 24. The via hole 23V formed in the resin layer 22 is provided separately from the via hole 23 for exposing a conductive layer such as the first conductive layer 12, e.g., the via hole 23 shown in FIG. 2, and is formed so as to expose the first portion 13a of the first insulating layer 13. In this example, the via hole 23V is also formed when the via hole 23 is formed. Furthermore, when the connection portion 24 corresponding to the via hole 23 is formed, the connection portion 24V is also formed in the via hole 23V. The via hole 23 and the via hole 23V may be formed separately. Furthermore, the connection portion 24 and the connection portion 24V may also be formed separately. Even with this structure, the lower portion 14V of the connection portion 24V functions in the same manner as the second conductive layer 14 according to the first embodiment. The lower portion 14V includes a portion in contact with the first insulating layer 13.

[0095] <Twenty-sixth embodiment> In the twenty-sixth embodiment, a semiconductor device manufactured using the interposer 10 in the first embodiment will be described.

[0096] 31 is a diagram showing a semiconductor device according to a twenty-sixth embodiment of the present disclosure. The semiconductor device 1000 includes three stacked interposers 10 (10-1, 10-2, and 10-3) and is connected to an LSI substrate 70. The interposer 10-1 includes a semiconductor element such as a DRAM, and also includes connection terminals 81-1 and 82-1 formed by connection portions 24 and the like. These interposers 10 (10-1, 10-2, and 10-3) do not necessarily have to use glass substrates; some interposers 10 may use substrates made of a different material from the other interposers 10. The connection terminal 81-1 is connected to the connection terminal 80 of the LSI substrate 70 via a bump 90-1. The connection terminal 82-1 is connected to the connection terminal 81-2 of the interposer 10-2 via a bump 90-2. The connection terminal 82-2 of the interposer 10-2 and the connection terminal 83-1 of the interposer 10-3 are also connected via a bump 90-3. The bumps 90 (90-1, 90-2, 90-3) are made of a metal such as indium, copper, or gold.

[0097] When stacking interposers 10, the number of layers is not limited to three, but may be two, or even four or more. Furthermore, the connection between interposer 10 and other substrates is not limited to bumps, and other bonding techniques such as eutectic bonding may be used. Furthermore, interposer 10 and other substrates may be bonded by applying and baking polyimide, epoxy resin, or the like.

[0098] Fig. 32 is a diagram showing another example of a semiconductor device according to the twenty-sixth embodiment of the present disclosure. The semiconductor device 1000 shown in Fig. 32 has a stacked structure in which semiconductor circuit substrates (semiconductor chips) 71-1 and 71-2, such as MEMS devices, a CPU, and a memory, and an interposer 10 are stacked, and is connected to an LSI substrate 70.

[0099] The interposer 10 is disposed between the semiconductor circuit substrates 71-1 and 71-2 and is connected to them via bumps 90-1 and 90-2. The semiconductor circuit substrate 71-1 is placed on the LSI substrate 70. The LSI substrate 70 and the semiconductor circuit substrate 71-2 are connected by wires 95. In this example, the interposer 10 is used as an interposer for stacking multiple semiconductor circuit substrates for three-dimensional mounting. By connecting the interposer 10 to multiple semiconductor circuit substrates each with different functions, a multi-functional semiconductor device can be realized. For example, by configuring the semiconductor circuit substrate 71-1 as a three-axis acceleration sensor and the semiconductor circuit substrate 71-2 as a two-axis magnetic sensor, a semiconductor device can be realized that implements a five-axis motion sensor in a single module.

[0100] If the semiconductor circuit substrate is a sensor formed by a MEMS device, the sensing result may be output as an analog signal. In this case, a low-pass filter, an amplifier, etc. may also be formed on the semiconductor circuit substrate or the interposer 10.

[0101] Fig. 33 is a diagram showing yet another example of a semiconductor device according to the twenty-sixth embodiment of the present disclosure. While the above two examples (Figs. 31 and 32) were three-dimensional implementations, this example is an example applied to 2.5-dimensional implementation. In the example shown in Fig. 33, six interposers 10 (10-1 to 10-6) are stacked and connected to an LSI substrate 70. However, not only are all the interposers 10 stacked, but they are also arranged side by side in the in-plane direction of the substrate.

[0102] In the example of Fig. 33, interposers 10-1 and 10-5 are connected onto an LSI substrate 70, interposers 10-2 and 10-4 are connected onto interposer 10-1, interposer 10-3 is connected onto interposer 10-2, and interposer 10-6 is connected onto interposer 10-5. Note that, as in the example shown in Fig. 33, such 2.5-dimensional mounting is also possible when interposer 10 is used as an interposer for connecting multiple semiconductor circuit substrates. For example, interposers 10-3, 10-4, 10-6, etc. may be replaced with semiconductor circuit substrates.

[0103] The semiconductor device 1000 manufactured as described above is mounted in various electronic devices, such as mobile terminals, information processing devices, and home appliances. More specific examples of mobile terminals include mobile phones, smartphones, and notebook personal computers. More specific examples of information processing devices include desktop personal computers, servers, and car navigation systems. Examples of electronic devices include wireless local area network (LAN) devices, set-top boxes, music players, video players, entertainment units, navigation devices, communication devices, personal digital assistants (PDAs), and fixed location data units.

[0104] FIG. 34 is a diagram illustrating an example of an electronic device using the semiconductor device according to the twenty-sixth embodiment of the present disclosure.

[0105] A smartphone 500 and a notebook personal computer 600 are shown as examples of electronic devices equipped with the semiconductor device 1000. These electronic devices have a control unit 1100 configured with a CPU or the like that executes application programs to realize various functions. The various functions include a function that uses an output signal from the semiconductor device 1000. Note that the semiconductor device 1000 may have the functions of the control unit 1100.

[0106] <Modification> The present disclosure is not limited to the above-described embodiments and includes various other modifications. For example, the above-described embodiments have been described in detail to clearly explain the present disclosure, and are not necessarily limited to those including all of the described configurations. Furthermore, part of the configuration of one embodiment may be replaced with the configuration of another embodiment, or the configuration of another embodiment may be added to the configuration of one embodiment. Furthermore, part of the configuration of each embodiment may be added to, deleted from, or replaced with another configuration. Some modifications will be described below.

[0107] (1) The substrate 11 on which the through electrode 20 is formed has been described as being used as an interposer disposed between a wiring substrate and a semiconductor chip or the like, but is not limited to this. That is, the substrate 11 on which the through electrode 20 is formed can be used as a through electrode substrate. Here, the through electrode substrate includes not only an interposer disposed between a wiring substrate and a semiconductor chip or the like, but also an IPD (Integrated Passive Device) or the like on which a semiconductor chip or the like is not mounted. In this case, one of the upper and lower wiring substrates is present so as to be electrically connected to the through electrode. On the other hand, the semiconductor chip or the like may be disposed at a position on the wiring substrate different from the through electrode substrate and electrically connected to the wiring substrate.

[0108] (2) In the capacitors of the above-described embodiments, for example, in the capacitor 100, the first insulating layer 13 is illustrated as being symmetrically disposed on the side surface 12b of the first conductive layer 12, but this is not limiting. For example, the left side surface 12b of the first conductive layer 12 and the first surface 11a of the substrate 11 are covered with the second portion 13b and the third portion 13c of the first insulating layer 13, as in the capacitor 100 of the first embodiment shown in FIG. 3. Meanwhile, the right side surface 12b of the first conductive layer 12 may be covered with the first insulating layer 13A, as in the second embodiment shown in FIG. 5, or may be covered with the first insulating layer 13B, as in the third embodiment shown in FIG. 6.

[0109] (3) In the capacitors of each of the above-described embodiments, layers not shown may be formed between the substrate 11 and the first conductive layer 12, between the first conductive layer 12 and the first insulating layer 13, and between the first insulating layer 13 and the second conductive layer 14.

[0110] (4) According to the present disclosure, the following through-hole electrode substrate can also be provided.

[0111] According to the present disclosure, there is provided a through electrode substrate comprising: a substrate having a first surface and a second surface opposite to the first surface; a through electrode penetrating the substrate; a first conductive layer disposed on the first surface of the substrate and electrically connected to the through electrode; an insulating layer disposed on the first conductive layer; and a second conductive layer disposed on the insulating layer, wherein the insulating layer has a first portion disposed between the first conductive layer and the second conductive layer and a second portion covering at least a portion of a side surface of the first conductive layer.

[0112] According to the present disclosure, there is provided a through hole electrode substrate, in which the first portion of the insulating layer has a thickness of 200 nm to 400 nm, and the second portion of the insulating layer has a thickness of 50 nm to 100 nm.

[0113] According to the present disclosure, there is provided a through electrode substrate, wherein the insulating layer further has a third portion extending from the second portion and covering at least a portion of the first surface of the substrate.

[0114] According to the present disclosure, there is provided a through hole electrode substrate, wherein the third portion of the insulating layer has a thickness of 50 nm to 200 nm.

[0115] According to the present disclosure, a through electrode substrate is provided, further comprising an underlayer disposed between the substrate and the first conductive layer, the underlayer having a recess portion extending inward beyond the side surface of the first conductive layer.

[0116] According to the present disclosure, there is provided a through electrode substrate, wherein the third portion of the insulating layer is disposed so as to fill the recessed portion.

[0117] According to the present disclosure, there is provided a through electrode substrate, in which the third portion of the insulating layer is disposed so as to leave a space in the recessed portion.

[0118] According to the present disclosure, there is provided a through electrode substrate, wherein the insulating layer further has a fourth portion connected to the third portion and extending in a direction intersecting the first surface of the substrate.

[0119] According to the present disclosure, there is provided a through electrode substrate further comprising an intermediate layer between the first conductive layer and the insulating layer.

[0120] According to the present disclosure, there is provided a through electrode substrate, wherein the third portion has a length of 20 μm or more.

[0121] According to the present disclosure, there is provided a through electrode substrate, wherein the height of the fourth portion is 25 μm or more.

[0122] According to the present disclosure, there is provided a through hole electrode substrate, in which at least one of the first conductive layer, the insulating layer, and the second conductive layer has a corner portion that is rounded in plan view.

[0123] According to the present disclosure, there is provided a through electrode substrate, wherein the second portion of the insulating layer is formed of a material different from the first portion.

[0124] According to the present disclosure, there is provided a through electrode substrate, wherein the material of the second portion is an insulating resin.

[0125] According to the present disclosure, there is provided a through electrode substrate further having a resin layer disposed on the first surface, an annular conductive layer formed along an end of the resin layer, and an annular insulating layer disposed between the annular conductive layer and the first surface and having a width wider than the annular conductive layer.

[0126] According to the present disclosure, there is provided a method for manufacturing a through electrode substrate, the method including the steps of: providing a substrate having a first surface and a second surface opposite the first surface, and having a through hole penetrating the first surface and the second surface; forming a through electrode in the through hole of the substrate, which connects the first surface and the second surface, and a first conductive layer electrically connected to the through electrode on the first surface of the substrate; forming a first insulating layer on an upper surface of the first conductive layer; forming a second insulating layer so as to cover at least a portion of a side surface of the first conductive layer and the first insulating layer; removing a portion of the second insulating layer located above the first conductive layer; and forming a second conductive layer in the portion of the second insulating layer from which the second insulating layer has been removed.

[0127] According to the present disclosure, there is provided a method for manufacturing a through hole electrode substrate, in which the second insulating layer is a photosensitive resin, and the removing step is performed by photolithography.

[0128] According to the present disclosure, there is provided a method for manufacturing a through-hole electrode substrate, wherein in the step of forming the second insulating layer, the method includes applying the second insulating layer under a first pressure and then placing the substrate under a second pressure higher than the first pressure.

[0129] According to the present disclosure, there is provided a method for manufacturing a through electrode substrate, the method including the steps of: providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a through hole penetrating the first surface and the second surface; forming a first resist on the first surface; forming a through electrode in the through hole of the substrate, the through electrode connecting the first surface and the second surface, and a first conductive layer on the first surface of the substrate, the first conductive layer being electrically connected to the through electrode; forming an intermediate layer on the first conductive layer; removing the first resist by lift-off; forming a second resist around the first conductive layer; forming a first insulating layer on an upper surface and a side surface of the intermediate layer, the side surface of the first conductive layer, the first surface, and the upper surface and a side surface of the second resist; removing the second resist by lift-off so as to leave at least a portion of the first insulating layer formed on the side surface of the second resist; and forming a second conductive layer on the first insulating layer corresponding to the position of the intermediate layer.

[0130] According to the present disclosure, there is provided a method for manufacturing a through electrode substrate, the method including the steps of: providing a substrate having a first surface and a second surface opposite the first surface, the substrate having a through hole penetrating the first surface and the second surface; forming a first resist on the first surface; forming a through electrode in the through hole of the substrate, the through electrode connecting the first surface and the second surface; and forming a first conductive layer on the first surface of the substrate, the first conductive layer being electrically connected to the through electrode; forming a first insulating layer on an upper surface and a side surface of the first conductive layer and on the first surface; forming a second conductive layer on the first insulating layer corresponding to the position of the upper surface of the first conductive layer; forming a second resist layer to cover the second conductive layer and a portion of the first insulating layer on the first surface; removing a portion of the first insulating layer that is not covered by the second resist layer; and removing the second resist layer.

[0131] According to the present disclosure, there is provided a method for manufacturing a through electrode substrate, further comprising the step of forming a resin layer on the first surface, wherein the step of forming the second conductive layer comprises forming a ring-shaped conductive layer on the first insulating layer along a position where an end of the resin layer is to be formed, and the step of forming the second resist layer comprises forming the second resist layer with a width wider than a width of the ring-shaped conductive layer.

[0132] The through electrode substrate can also be used as an interposer. [Explanation of symbols]

[0133] 10, 10U...interposer, 11...substrate, 12, 12G, 12K, 12L, 12M, 12U...first conductive layer, 13, 13A, 13B, 13C, 13E, 13J, 13K, 13L, 13M, 13N, 13P, 13R, 13S, 13T, 13U...first insulating layer, 14, 14F, 14K, 14M, 14P, 14Q, 14R, 14U...second conductive layer, 15...through hole, 17...underlying layer, 18...space, 19...second insulating layer, 20...through electrode, 21...third conductive layer, 22...resin layer, 23, 23V...via hole, 24, 24V...connection portion, 25...ball solder, 26...intermediate layer, 27...inductor, 29...conductive layer, 31...first level Resist layer, 32... second resist layer, 33... resist layer, 40... wiring board, 50... semiconductor chip, 70... substrate, 71... semiconductor circuit board, 80, 81, 82, 83... connection terminal, 90... bump, 95... wire, 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M1, 100M2, 100N, 100P, 100Q, 100R, 100S, 100T, 100U... capacitor, 100V... capacitor, 500... smartphone, 600... notebook personal computer, 1000... semiconductor device, 1100... control unit

Claims

1. A substrate; an underlayer on the substrate; a first conductive layer on the underlayer; a first insulating layer having a first material on the first conductive layer; a second insulating layer on the first insulating layer, the second insulating layer having a second material different from the first material; the second insulating layer has a first portion on the first insulating layer and a second portion in contact with at least a part of a side surface of the first conductive layer; the thickness of the second portion of the second insulating layer is thinner than the thickness of the first portion of the second insulating layer; Partial structure.

2. the first material is an inorganic material; the second material is an organic material; The partial structure according to claim 1 .

3. The substructure according to claim 1 , wherein the second portion covers at least a part of a side surface of the underlayer.

4. The substructure according to claim 1 , wherein the thickness of the second portion of the second insulating layer is equal to or greater than ¼ and equal to or less than ½ of the thickness of the first portion of the second insulating layer.

5. The substructure of claim 1 , wherein the second portion of the second insulating layer is spaced apart from the substrate.

6. The substructure according to claim 1 , wherein the second portion of the second insulating layer covers an upper surface of a portion of the underlayer.

7. The partial structure according to claim 1; a capacitor adjacent to the substructure, The capacitor is an interposer having the substrate, the base layer, the first conductive layer, the first insulating layer, the second insulating layer, and a second conductive layer on the first insulating layer and the second insulating layer.

8. The interposer of claim 7 , wherein the second insulating layer has a fourth portion between the second conductive layer and the first insulating layer and a fifth portion covering at least a portion of the side surface of the first conductive layer.

9. The interposer of claim 8 , wherein the thickness of the fourth portion of the second insulating layer is greater than or equal to ¼ and less than or equal to ½ of the thickness of the fifth portion of the second insulating layer.

10. The interposer of claim 7 , wherein the substructure and the capacitor are connected.

11. a second capacitor adjacent to the capacitor, the second capacitor has the substrate, a second underlayer on the substrate, a third conductive layer on the second underlayer, a third insulating layer on the third conductive layer, a fourth insulating layer on the third insulating layer, and a fifth conductive layer on the third insulating layer and the fourth insulating layer; The interposer of claim 7 , wherein the fourth insulating layer is separate from the second insulating layer.

12. a through electrode penetrating the substrate, The interposer according to claim 7 , wherein the through electrode is electrically connected to the capacitor.

13. The interposer of claim 7 , wherein the substrate is a glass substrate.

14. The interposer according to claim 12 , wherein the second insulating layer has a portion that is connected to the first portion and covers at least a portion of the through electrode.

15. an inductor electrically connected to the capacitor, The interposer according to claim 12 , wherein the inductor is configured to include one or more of the through electrodes.

16. the thickness of the first conductive layer is 0.5 μm to 20 μm; 16. The interposer according to claim 15, wherein the through electrode constituting the inductor has a thickness of 0.5 μm to 20 μm.

17. Further comprising a resin layer covering the capacitor; The interposer according to claim 7 , wherein the first insulating layer has a higher dielectric constant than the resin layer.

18. An interposer according to claim 12; a semiconductor chip disposed on a first upper surface side of the substrate of the interposer and electrically connected to the through electrodes; a wiring substrate disposed on a second upper surface side of the substrate and electrically connected to the through electrode, the first upper surface faces the second upper surface, The semiconductor device, wherein the capacitor is disposed on the first upper surface side of the substrate.

19. An interposer according to claim 12; a semiconductor chip disposed on a first upper surface side of the substrate of the interposer and electrically connected to the through electrodes; a wiring substrate disposed on a second upper surface side of the substrate and electrically connected to the through electrode.

20. An interposer according to claim 12; a wiring board disposed on a second upper surface side of the substrate and electrically connected to the through electrodes; a semiconductor chip disposed on the wiring substrate at a position different from the interposer and electrically connected to the wiring substrate.

Images