SUBSTRATE PROCESSING SYSTEM, CONTROL DEVICE, AND SUBSTRATE TRANSPORTATION AND PROCESSING METHOD

Abstract

To provide a technology that can efficiently convey a plurality of substrates while avoiding a fact that conveyance timings of the plurality of substrates are prevented from overlapping in a conveyance module.SOLUTION: A substrate processing system comprises: one or more conveyance modules that convey a substrate; a plurality of process modules that perform substrate processing for the substrate conveyed by the one or more conveyance modules; and a control apparatus that controls the one or more conveyance modules and the plurality of process modules. The control apparatus performs in order the steps of: (A) calculating a supply interval of the substrate for supplying the substrate not to overlap between conveyance periods of a plurality of substrates, for the one or more conveyance modules; and (B) leveling the plurality of time intervals that exist among the conveyance periods of the plurality of substrates so that the conveyance periods of the plurality of substrates are apart from each other, on the basis of the calculated supply interval of the substrate.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a substrate processing system, a control device, and a substrate transfer and processing method. [Background technology]

[0002] Patent Documents 1 and 2 disclose a substrate processing system in which substrates are sequentially transported to a plurality of process modules via a plurality of transfer modules and subjected to substrate processing. In this type of substrate processing system, a single cycle time is set to equalize the thermal history of the substrates, and substrate transport processing by each transfer module and substrate processing by each process module are performed in units of the cycle time.

[0003] However, if a processing delay occurs in a module, the transport device of the transport module will not be able to transport the substrates in time, causing confusion in the transport of substrates by the transport module. Therefore, the substrate processing system absorbs the processing delay by providing a waiting time within the cycle time to allow for processing delays. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-52165 [Patent Document 2] Japanese Patent Publication No. 2022-76547 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides a technique that can efficiently transport a plurality of substrates while avoiding overlapping transport timings of the substrates in a transport module. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, there is provided a substrate processing system including one or more transfer modules that transfer substrates, a plurality of process modules that perform substrate processing on the substrates transferred by the one or more transfer modules, and a control device that controls the one or more transfer modules and the plurality of process modules, wherein the control device performs the following steps: (A) calculating a substrate supply interval for the one or more transfer modules so that transfer periods of the plurality of substrates do not overlap; A time interval is set for each of the transport periods of the adjacent substrates, and in the step (A), Based on the calculated supply intervals of the substrates, the transport periods of the plurality of substrates are determined to be mutually equal. Non-overlapping and multiple number of The leveled Time interval calculation and a substrate processing system for performing the steps of: [Effects of the Invention]

[0007] According to one aspect, it is possible to efficiently transport a plurality of substrates while avoiding overlapping transport timings of the plurality of substrates in the transport module. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view schematically showing a substrate processing system according to a first configuration example of the present embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the hardware configuration of a control device of the substrate processing system. [Figure 3] FIG. 10 is a plan view schematically showing a substrate processing system according to a second configuration example of the present embodiment. [Figure 4] Fig. 4(A) is a flowchart showing a processing flow of a substrate transport processing method, and Fig. 4(B) is a diagram for explaining wafer supply intervals. [Figure 5] FIG. 10 is a diagram showing a first transfer period, a second transfer period, a first TM use interval, and a second TM use interval included in a wafer supply interval. [Figure 6]Fig. 6(A) is an enlarged plan view showing the fourth transfer module and its surrounding configuration of the substrate processing system according to the second configuration example, and Fig. 6(B) is a diagram showing the intervals at which wafers are supplied to the fourth transfer module. [Figure 7] Fig. 7(A) is a diagram showing pattern 0 in the fourth transfer module, and Fig. 7(B) is a diagram showing pattern 1 in the fourth transfer module. [Figure 8] Fig. 8(A) is a diagram for explaining the formula (3), and Fig. 8(B) is a diagram showing an example in which the condition in the formula (3) is not satisfied. [Figure 9] Fig. 9(A) is a diagram for explaining formula (4), Fig. 9(B) is a diagram for explaining an example where the conditions in formula (4) are not satisfied, and Fig. 9(C) is a diagram for explaining formula (5). [Figure 10] FIG. 10 is a diagram showing a plurality of patterns in a third transfer module. [Figure 11] Fig. 11(A) is a diagram for explaining formula (7), Fig. 11(B) is a diagram for explaining formula (8), and Fig. 11(C) is a diagram showing a fourth transfer module side period incorporated in the third transfer module. [Figure 12] Fig. 12(A) is a diagram for explaining formula (9), Fig. 12(B) is a diagram for explaining formula (10), and Fig. 12(C) is a diagram for explaining formula (11). [Figure 13] Fig. 13(A) is a diagram for explaining formula (12). Fig. 13(B) is a diagram for explaining formula (13). Fig. 13(C) is a diagram for explaining formula (15). Fig. 13(D) is a diagram for explaining formula (16). [Figure 14] Fig. 14(A) is a diagram for explaining an example in which the wafer supply interval is longer than the actual period of the process recipe. Fig. 14(B) is a diagram for explaining formula (17). Fig. 14(C) is a diagram for explaining formula (18). Fig. 14(D) is a diagram for explaining formula (19). [Figure 15]15A is a diagram for explaining the leveling of the intervals at which the transfer modules are used, and FIG. 15B is a diagram for explaining the leveling of the intervals at which the transfer modules are used corresponding to the immediate unloading process modules. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] 1 is a plan view schematically illustrating a substrate processing system 1A according to a first configuration example of the present embodiment. As shown in FIG. 1, the substrate processing system 1A is configured as a multi-chamber type having multiple process modules PM. The substrate processing system 1A is used in one process of semiconductor manufacturing, and multiple transfer modules TM sequentially transfer substrates to each process module PM, where appropriate substrate processing is performed.

[0011] Examples of substrates that are subjected to substrate processing include silicon semiconductor wafers, compound semiconductor wafers, and oxide semiconductor wafers (hereinafter, the substrates are also referred to as wafers W). The wafers W may have recess patterns such as trenches and vias. Examples of substrate processing performed by the process modules PM include film formation processing, etching processing, ashing processing, and cleaning processing.

[0012] The substrate processing system 1A transfers a wafer W from an atmospheric atmosphere to a vacuum atmosphere, performs substrate processing on the wafer W in each transfer module TM and each process module PM in the vacuum atmosphere, and then transfers the wafer W from the vacuum atmosphere to the atmospheric atmosphere after the substrate processing. To this end, the substrate processing system 1A includes a front module FM (e.g., an Equipment Front End Module (EFEM)) that transfers the substrate in the atmospheric atmosphere, and a load lock module LLM that switches between the atmospheric atmosphere and the vacuum atmosphere. The substrate processing system 1A also includes a controller 80 that controls the front module FM, the load lock module LLM, each process module PM, and each transfer module TM.

[0013] The front module FM includes a plurality of load ports 11, one loader 12 adjacent to each load port 11, and an alignment device 13 (orienter) provided adjacent to the loader 12. Each load port 11 is set with a FOUP (Front Opening Unified Pod) that stores a plurality of wafers W after the previous manufacturing process, and an empty FOUP that stores wafers W that have been subjected to substrate processing in the substrate processing system 1A.

[0014] The loader 12 is formed in a rectangular box shape having a clean space inside. The front module FM includes an atmospheric transfer device 14 inside the loader 12.

[0015] The atmospheric transfer device 14 removes the wafer W from the FOUP set in each load port 11 and transfers the wafer W to the alignment device 13 via the clean space in the loader 12. The atmospheric transfer device 14 also transfers the wafer W removed from the alignment device 13 into the load lock module LLM. The atmospheric transfer device 14 then removes the processed wafer W from the load lock module LLM and places the wafer W in the FOUP via the clean space in the loader 12.

[0016] The alignment device 13 measures the eccentricity of the wafer W by detecting the position of the outer edge while rotating the wafer W. Based on the measured eccentricity, the alignment device 13 and the atmospheric transfer device 14 adjust the circumferential position of the wafer W and the supporting attitude of the wafer W by the atmospheric transfer device 14.

[0017] Two load lock modules LLM are provided between the front module FM and the transfer module TM. Each load lock module LLM has a load lock container 21 capable of temporarily accommodating a wafer W. A gate 22 equipped with a valve (not shown) for airtightly closing the load lock container 21 is provided between each load lock module LLM and the front module FM. In addition, a gate 23 equipped with a valve (not shown) for airtightly closing the load lock container 21 is provided between the load lock module LLM and the transfer module TM.

[0018] For example, one of the two load lock modules LLM (left side in FIG. 1) accommodates a wafer W transferred from the front module FM in an atmospheric atmosphere and then depressurizes it to a vacuum atmosphere, thereby enabling the wafer W to be transferred to the transfer module TM. The other of the two load lock modules LLM (right side in FIG. 1) accommodates a wafer W transferred from the transfer module TM in a vacuum atmosphere and then increases the pressure to an atmospheric atmosphere, thereby enabling the wafer W to be transferred to the front module FM. The substrate processing system 1A may be configured to include only one load lock module LLM (load lock container 21). In this case, the load lock container 21 may be configured such that a space for loading from the front module FM to the transfer module TM and a space for unloading from the transfer module TM to the front module FM are separated in the up-down direction (vertical direction).

[0019] The substrate processing system 1A according to this embodiment has a plurality of (four) transfer modules TM arranged in the Y-axis direction, and a plurality of (eight) process modules PM installed adjacent to each transfer module TM. Hereinafter, the plurality of transfer modules TM will be referred to as a first transfer module TM1, a second transfer module TM2, a third transfer module TM3, and a fourth transfer module TM4 in that order in the positive direction of the Y-axis.

[0020] Meanwhile, the multiple process modules PM are installed on the left side (negative X-axis direction) of the transport module group, four of which correspond to the four transport modules TM, and on the right side (positive X-axis direction) of the transport module group. Hereinafter, using FIG. 1 as an example, the process modules PM installed on the left side of each transport module TM will be referred to as the left-row process module group, and the process modules PM installed on the right side of each transport module TM will be referred to as the right-row process module group. The left-row process module group and the right-row process module group extend parallel to the transport module groups.

[0021] The left-hand process module group includes, in order along the positive Y-axis, a first process module PM1, a third process module PM3, a fifth process module PM5, and a seventh process module PM7. The right-hand process module group includes, in order along the positive Y-axis, a second process module PM2, a fourth process module PM4, a sixth process module PM6, and an eighth process module PM8.

[0022] The first process module PM1 is disposed on the left side of and between the first transfer module TM1 and the second transfer module TM2 and is connected to the first transfer module TM1 and the second transfer module TM2, while the second process module PM2 is disposed on the right side of and between the first transfer module TM1 and the second transfer module TM2 and is connected to the first transfer module TM1 and the second transfer module TM2.

[0023] The third process module PM3 is disposed between the second and third transfer modules TM2 and TM3 and is connected to them, while the fourth process module PM4 is disposed between the second and third transfer modules TM2 and TM3 and is connected to them.

[0024] The fifth process module PM5 is disposed between the third and fourth transfer modules TM3 and TM4 and is connected to the third and fourth transfer modules TM3 and TM4, and the sixth process module PM6 is disposed between the third and fourth transfer modules TM3 and TM4 and is connected to the third and fourth transfer modules TM3 and TM4.

[0025] The seventh process module PM7 is disposed on the left side of the fourth transfer module TM4 and is connected to the fourth transfer module TM4, and the eighth process module PM8 is disposed on the right side of the fourth transfer module TM4 and is connected to the fourth transfer module TM4.

[0026] Each transfer module TM includes a transfer container 31 that can be decompressed to a vacuum atmosphere, and a transfer robot 32A installed inside the transfer container 31. The transfer container 31 is formed as a hexagonal box in a plan view. Two load lock modules LLM, a first process module PM1, and a second process module PM2 are connected to predetermined sides of the transfer container 31 of the first transfer module TM1. The first process module PM1 to the fourth process module PM4 are connected to predetermined sides of the transfer container 31 of the second transfer module TM2. The third process module PM3 to the sixth process module PM6 are connected to predetermined sides of the transfer container 31 of the third transfer module TM3. The fifth process module PM5 to the eighth process module PM8 are connected to predetermined sides of the transfer container 31 of the fourth transfer module TM4.

[0027] The transfer robot 32A is configured to be movable horizontally and vertically within the transfer container 31 and to rotate by θ in the horizontal direction. The transfer robot 32A has a pick (end effector) formed of a two-pronged fork and holds the wafer W horizontally. The transfer robots 32A provided in each of the first transfer module TM1 to the fourth transfer module TM4 can operate independently of each other under the control of the control device 80. The transfer robot 32A delivers and receives the wafer W by moving toward and away from the modules adjacent to the transfer container 31 (two load lock modules LLM, and first process module PM1 to eighth process module PM8).

[0028] On the other hand, each of the process modules PM has a processing vessel 41 that accommodates a wafer W therein and performs substrate processing. The processing vessel 41 is formed in a polygonal shape (pentagonal) in a plan view. Gates 42 are provided between the transfer vessel 31 and each processing vessel 41, respectively, to communicate with the spaces between the transfer vessel 31 and each processing vessel 41 and allow the wafer W to pass through. A valve (not shown) is provided inside each gate 42 to open and close the processing vessel 41.

[0029] Each process module PM also includes a stage (not shown) on which a wafer W can be placed inside the processing chamber 41. The stage includes a plurality of lift pins (not shown), and receives and delivers the wafer W from and to the transfer robot 32A based on the elevation and lowering of the lift pins.

[0030] The substrate processing performed by each process module PM may be any of the above-mentioned film formation processing, etching processing, ashing processing, cleaning processing, etc. The substrate processing system 1A may be configured so that the first to eighth process modules PM1 to PM8 each perform a different substrate processing, or may be configured so that the same substrate processing is performed.

[0031] The above-described substrate processing system 1A can be used, for example, to manufacture a stacked film (MTJ film) used in MRAM (Magnetoresistive Random Access Memory). The manufacture of an MTJ film involves a number of substrate processes, such as pre-cleaning, film formation, oxidation, heating, and cooling, and each of these processes is performed in the first to eighth process modules PM1 to PM8. Note that one or more of the first to eighth process modules PM1 to PM8 may be standby modules for storing wafers W.

[0032] Fig. 2 is a block diagram showing an example of the hardware configuration of the control device 80 of the substrate processing system 1A. As shown in Fig. 2, the control device 80 of the substrate processing system 1A includes a main control unit 81, an input device 82, an output device 83, a display device 84, a storage device 85, an external interface 86, and a bus 87 connecting these devices to each other. The input device 82 is a keyboard, a mouse, a touch panel, etc. The output device 83 is a printer, etc. The display device 84 is a display (including a touch panel), etc.

[0033] The main control unit 81 has a CPU (Central Processing Unit) 811, a RAM (Random Access Memory) 812, and a ROM (Read Only Memory) 813. The storage device 85 has a storage medium from which information can be read, such as an HDD (Hard Disk Drive), and stores programs necessary for control and information such as recipes for processing wafers W. The CPU 811 uses the RAM 812 as a working area to execute programs stored in the ROM 813 or the storage device 85, whereby the substrate processing system 1A performs various processes on wafers W.

[0034] Returning to FIG. 1 , the control device 80 of the substrate processing system 1A can be configured to serially transfer wafers W in a U-shape in each transfer module TM and each process module PM for substrate processing. That is, the wafer W is transferred from the left load lock module LLM to the first process module PM1 by the first transfer module TM1, where it undergoes substrate processing. After the substrate processing in the first process module PM1, the wafer W is transferred from the first process module PM1 to the third process module PM3 by the second transfer module TM2, where it undergoes substrate processing in the third process module PM3. After the substrate processing in the third process module PM3, the wafer W is transferred from the third process module PM3 to the fifth process module PM5 by the third transfer module TM3, where it undergoes substrate processing in the fifth process module PM5. After the substrate processing in the fifth process module PM5, the wafer W is transferred from the fifth process module PM5 to the seventh process module PM7 by the fourth transfer module TM4, where it undergoes substrate processing in the seventh process module PM7.

[0035] After the substrate processing in the seventh process module PM7, the wafer W is transferred from the seventh process module PM7 to the eighth process module PM8 by the fourth transfer module TM4, where it is subjected to substrate processing in the eighth process module PM8. After the substrate processing in the eighth process module PM8, the wafer W is transferred from the eighth process module PM8 to the sixth process module PM6 by the fourth transfer module TM4, where it is subjected to substrate processing in the sixth process module PM6. After the substrate processing in the sixth process module PM6, the wafer W is transferred from the sixth process module PM6 to the fourth process module PM4 by the third transfer module TM3, where it is subjected to substrate processing in the fourth process module PM4. After the substrate processing in the fourth process module PM4, the wafer W is transferred from the fourth process module PM4 to the second process module PM2 by the second transfer module TM2, where it is subjected to substrate processing in the second process module PM2. After the substrate processing in the second process module PM2, the wafer W is transferred from the second process module PM2 to the right load lock module LLM by the first transfer module TM1.

[0036] As a result, the substrate processing system 1A can sequentially perform eight substrate processing operations on a wafer W. However, the substrate processing system 1A does not wait to process the next wafer W until eight substrate processing operations have been completed for one wafer W. The wafers W are transported to each of the multiple process modules PM, and substrate processing is performed on the wafers W in each process module PM. Therefore, in the substrate processing system 1A, the processing of the wafers W in each process module PM and each transport module TM is basically performed synchronously.

[0037] The substrate processing system 1A is not limited to the first configuration example described above, and various other configuration examples are possible. Next, a substrate processing system 1B according to a second configuration example will be described with reference to Fig. 3. Fig. 3 is a plan view schematically showing the substrate processing system 1B according to the second configuration example of this embodiment.

[0038] Similar to the substrate processing system 1A, the substrate processing system 1B includes a front module FM, a load lock module LLM, process modules PM, transfer modules TM, and a controller 80. The transfer modules TM are aligned along the Y-axis to form a transfer module group. The first process module PM1, the third process module PM3, the fifth process module PM5, and the seventh process module PM7 are located on the left side of the transfer module group and form a left-row process module group. The second process module PM2, the fourth process module PM4, the sixth process module PM6, and the eighth process module PM8 are located on the right side of the transfer module group and form a right-row process module group. In the following description of the substrate processing system 1B, components similar to or having similar functions to those in the substrate processing system 1A are denoted by the same reference numerals, and their description will be omitted.

[0039] The substrate processing system 1B differs from the substrate processing system 1A of FIG. 1 in that it includes a plurality of storage modules SM, a plurality of passing modules PASS, and a plurality of evacuation modules UM in addition to a plurality of process modules PM.

[0040] Furthermore, the transfer robot 32B provided in each transfer module TM has two picks (end effectors) capable of holding a wafer W. This allows the transfer robot 32B to exchange (deliver and receive) a wafer W with the process module PM, the load lock module LLM, the storage module SM, the passing module PASS, the evacuation module UM, etc. For example, the transfer robot 32B can receive a wafer W with one pick and deliver a wafer W from another pick to each storage module SM.

[0041] The substrate processing system 1B has one passing module PASS and one evacuation module UM arranged between two adjacent transfer modules TM in the Y-axis direction. The passing module PASS and the evacuation module UM are arranged side by side in the X-axis direction on one side of the hexagonal transfer module TM.

[0042] The pass-through module PASS has a cylindrical container 51 and a stage (not shown) provided within the container 51. This pass-through module PASS has two transfer modules TM adjacent in the Y-axis direction, each of which has an openable and closable gate valve (not shown). Hereinafter, the module between the first transfer module TM1 and the second transfer module TM2 will be referred to as the first pass-through module PASS1, the module between the second transfer module TM2 and the third transfer module TM3 will be referred to as the second pass-through module PASS2, the module between the third transfer module TM3 and the fourth transfer module TM4 will be referred to as the third pass-through module PASS3, and the module on the positive side of the fourth transfer module TM4 in the Y-axis direction will be referred to as the fourth pass-through module PASS4. Note that the fourth pass-through module PASS4 is used when another transfer module (a fifth transfer module) is applied to the fourth transfer module TM4, and is not used in this embodiment.

[0043] The evacuating module UM has a cylindrical container 61 and a stage (not shown) provided within the container 61. This evacuating module UM is equipped with a gate valve (not shown) that can be opened and closed relative to the transfer module TM that is in contact with the negative direction of the Y axis, while being closed relative to the transfer module TM that is in contact with the positive direction of the Y axis. Hereinafter, the module between the first transfer module TM1 and the second transfer module TM2 will be referred to as the first evacuating module UM1, the module between the second transfer module TM2 and the third transfer module TM3 will be referred to as the second evacuating module UM2, the module between the third transfer module TM3 and the fourth transfer module TM4 will be referred to as the third evacuating module UM3, and the module on the positive side of the fourth transfer module TM4 in the Y axis direction will be referred to as the fourth evacuating module UM4. The first evacuation module UM1 is capable of loading and unloading wafers W into and from the first transfer module TM1, the second evacuation module UM2 is capable of loading and unloading wafers W into and from the second transfer module TM2, the third evacuation module UM3 is capable of loading and unloading wafers W into and from the third transfer module TM3, and the fourth evacuation module UM4 is capable of loading and unloading wafers W into and from the fourth transfer module TM4.

[0044] On the other hand, the storage modules SM are connected to the left and right sides of the first transfer module TM1, to which the first process module PM1 and the second process module PM2 are not connected. The storage module SM has a rectangular parallelepiped housing 71 and multiple shelves (not shown) arranged vertically within the housing 71, and is capable of storing multiple wafers W in the vertical direction. The storage module SM stores unprocessed wafers W, processed wafers W, and wafers W in the middle of processing in the substrate processing system 1B. Hereinafter, the module on the left of the first transfer module TM1 will be referred to as the first storage module SM1, and the module on the right of the first transfer module TM1 will be referred to as the second storage module SM2.

[0045] After a wafer W is loaded, each storage module SM, each passing module PASS, and each evacuation module UM simply places the wafer W thereon and allows the wafer W to be removed by a predetermined transfer robot 32B. However, each storage module SM, each passing module PASS, and each evacuation module UM is not limited to having a simple placement function, and may be configured to perform predetermined substrate processing on the stored wafer W. For example, the substrate processing may include a process for adjusting the temperature of the wafer W (heating, cooling, or keeping warm), a process for oxidizing the wafer W, a process for cleaning the wafer W, etc.

[0046] Similarly to the substrate processing system 1A, the substrate processing system 1B controls the front module FM, the load lock module LLM, the process modules PM, the transfer modules TM, the storage modules SM, the passing modules PASS, and the evacuation module UM by a control device 80. In particular, unlike the substrate processing system 1A, the substrate processing system 1B does not transfer wafers W serially in a U-shape, but allows the user to arbitrarily set the transfer path of the wafers W depending on the type of substrate processing in each process module PM, the duration of stay, etc.

[0047] For example, in the example shown in FIG. 3, a wafer W loaded from load lock module LLM into first transfer module TM1 is transferred sequentially through first storage module SM1, first evacuation module UM1, and first process module PM1. Then, substrate processing of the wafer W is performed in first process module PM1. After substrate processing in first process module PM1, the wafer W is selectively transferred by second transfer module TM2 to third process module PM3 or fourth process module PM4 for substrate processing. That is, substrate processing system 1B is configured to perform the same type of substrate processing over a long period of time in third process module PM3 and fourth process module PM4, thereby enabling selective transfer (hereinafter also referred to as OR transfer). After substrate processing in third process module PM3 or fourth process module PM4, the wafer W is transferred by third transfer module TM3 to fifth process module PM5 for substrate processing. After the substrate processing in the fifth process module PM5, the wafer W is temporarily evacuated to the fourth evacuation module UM4 by the fourth transfer module TM4, and then selectively transferred again to the seventh process module PM7 or the eighth process module PM8 for substrate processing.

[0048] After substrate processing in the seventh process module PM7 or the eighth process module PM8, the wafer W is transferred by the fourth transfer module TM4 to the third pass module PASS3. The wafer W is then transferred by the third transfer module TM3 from the third pass module PASS3 to the third evacuation module UM3 and then to the sixth process module PM6 for substrate processing. After substrate processing in the sixth process module PM6, the wafer W is transferred by the third transfer module TM3 to the second pass module PASS2. The wafer W is then transferred by the second transfer module TM2 from the second pass module PASS2 to the first pass module PASS1 via the second evacuation module UM2. The wafer W is then transferred by the first transfer module TM1 to the second storage module SM2, and then from the second storage module SM2 to the second process module PM2 for substrate processing. After substrate processing in the second process module PM2, the wafer W is again transferred by the first transfer module TM1 to the load lock module LLM.

[0049] The substrate processing system 1B sequentially loads and unloads multiple wafers W from the atmospheric side to the vacuum side, transports each wafer W along the above-mentioned transport path, and performs substrate processing in each process module PM. In the processing of each wafer W (transfer processing, substrate processing), the control device 80 must control the transfer periods of multiple wafers W so that they do not overlap. Therefore, in the substrate transfer processing method, the control device 80 sets a schedule for the transfer processing and substrate processing by performing a period calculation step (S1) and an allocation step (S2) in this order, as shown in FIG. 4(A). Then, the control device 80 executes the transfer processing and substrate processing based on the set schedule.

[0050] In the period calculation step (S1), a supply interval of wafers W (substrates) is calculated so that the transfer periods of multiple wafers W do not overlap in the same transfer module TM (transfer robot 32B). In this specification, the "supply interval of wafers W (substrates)" refers to the total period during which all transfer processes (transfer of wafers W along a transfer path) performed by a specific transfer module TM are performed once at time intervals. The next wafer W is supplied to the specific transfer module TM according to this wafer W supply interval. The wafer W supply interval is also the cycle time that is periodically repeated by the specific transfer module TM. The control device 80 operates the transfer robots 32A and 32B in each transfer module TM according to the set wafer W supply interval and repeats this wafer W supply interval, thereby realizing sequential transfer of wafers W throughout the entire system.

[0051] For example, the wafer W supply interval will be described with reference to FIG. 4B using the first transfer module TM1 (see FIG. 1) of the substrate processing system 1A as an example. The first transfer module TM1 has a first transfer period T0 during which the wafer W is transferred from the load lock module LLM to the first process module PM1, and a second transfer period T1 during which the wafer W is transferred from the second process module PM2 to the load lock module LLM. Furthermore, the first transfer module TM1 is involved in the time interval between the first transfer period T0 and the second transfer period T1 (first TM use interval P0) and the time interval between the second transfer period T1 and the first transfer period T0 (second TM use interval P1). However, the transfer robot 32A of the first transfer module TM1 may be in a standby state during the first TM use interval and the second TM use interval. The TM use interval is determined by the transfer periods of other transfer modules TM and the stay periods of multiple process modules PM.

[0052] In summary, the first transfer module TM1 of the substrate processing system 1A must take into account the first transfer period T0, the first TM use interval P0, the second transfer period T1, and the second TM use interval P1, and the sum of these is the wafer W supply interval (cycle time) of the first transfer module TM1. However, the first TM use interval P0 and the second TM use interval P1 are not related to the operation of the transfer robot 32A of the first transfer module TM1, and can be used as a slack period for the transfer robot 32A. In this case, the control device 80 simply calculates a wafer W supply interval that is longer than the first TM use interval P0 and the second TM use interval P1 and that does not overlap the first transfer period T0 and the second transfer period T1.

[0053] Specifically, the control device 80 sets a constraint condition for each transfer module TM that prevents overlapping of the transfer periods of the wafers W, and, based on this constraint condition, uses the supply interval of the wafers W and the residence period of the wafers W in each process module PM as variables. Then, the control device 80 solves a linear programming problem to find the supply interval of the wafers W that will provide the best throughput (highest processing efficiency) in each transfer module TM.

[0054] That is, the control device 80 formulates a constraint condition that the transfer periods do not overlap for combinations of multiple types of transfer paths executed in each transfer module TM. However, there are an infinite number of solution candidates that satisfy the constraint condition. The control device 80 uses throughput as an objective function and solves a mixed integer programming problem to find a combination that provides the best throughput, thereby obtaining the supply interval of wafers W.

[0055] In addition, in the allocation step (S2), the allocation of the multiple transfer periods is calculated based on the supply intervals of the wafers W calculated in the period calculation step (S1), and each transfer period is scheduled so as to be tolerant to delays in the stay periods of the process modules PM. "Tolerant to delays in the stay periods of the process modules PM" means, for example, that even if the substrate processing time in the process modules PM becomes longer, the wafers W can be transferred without overlapping with each other in the multiple transfer periods.

[0056] The allocation of the multiple transfer periods will be described below with reference to Fig. 5, taking the first transfer module TM1 (see Fig. 1) of the substrate processing system 1A as an example. As described above, the interval between supplying wafers W to the first transfer module TM1 includes two transfer periods (first transfer period T0 and second transfer period T1).

[0057] Here, consider the case where the end of the second transfer period T1 is close to the start of the first transfer period T0 (when the second transfer period T1 is close to the end of the wafer W supply interval), as shown in the left diagram of FIG. 5. In this case, the second TM use interval P1 becomes shorter, and the first transfer period T0, which is the start of the wafer W supply interval, is implemented after this second TM use interval P1. If the substrate processing in the first process module PM1 is delayed and the first TM use interval P0 becomes longer, the second transfer period T1 may be delayed and overlap with the first transfer period T0. In other words, when multiple transfer periods are close to each other in the wafer W supply interval, it can be said that the system is vulnerable to delays in the residence time of the process module PM.

[0058] In contrast, in the allocation of the two transfer periods shown in the right diagram of FIG. 5, the start and end of the second transfer period T1 are spaced apart in time from the start and end of the first transfer period T0. In this case, even if the stay period or transfer period of each process module PM on the path is delayed, the possibility of the first transfer period T0 and the second transfer period T1 overlapping can be sufficiently reduced. In other words, if the multiple transfer periods are spaced apart (spacing out) in the supply interval of wafers W, it can be said that the system is tolerant to delays in the stay period of the process modules PM. Therefore, the control device 80 only needs to allocate the multiple transfer periods so that the multiple transfer periods are spaced apart in the supply interval of wafers W.

[0059] Specifically, the transfer timing chart obtained as a result of solving the period calculation step (S1) is not limited to one, and multiple charts that satisfy the constraints may be obtained. The control device 80 ultimately selects one solution from the multiple candidate solutions that is most tolerant to substrate processing delays. For example, the control device 80 sets an objective function to equalize the time intervals (use intervals, described below) between multiple transfer periods using the transfer module TM. The control device 80 then adds another constraint to the constraint that maximizes throughput solved in the period calculation step (S1), and solves this objective function and constraint using a linear programming problem (mixed integer programming problem). This enables the control device 80 to select a solution that separates (levels) the multiple transfer periods of the transfer module TM from each other.

[0060] By performing the above-described period calculation step (S1) and allocation step (S2), the control device 80 can obtain the wafer W supply interval and multiple transfer periods that maximize throughput. Moreover, within the calculated wafer W supply interval, the transfer periods of the wafers W do not overlap, and two conditions are met that are highly tolerant to delays in the residence period of the process module PM.

[0061] In addition, in the allocation step (S2), the control device 80 preferably performs scheduling by taking into account additional conditions that should be eliminated in practice, so as to avoid including weak solutions that will fail even with a slight delay. One example of an additional condition is that the waiting period of the process module PM is scheduled to be 0 seconds. To address this, the control device 80 may be configured to specify a minimum waiting period using a parameter so that the waiting period does not become 0 seconds. Another example of an additional condition is that the interval between uses of the transport module TM (TM use interval) is scheduled to be 0 seconds. To address this, the control device 80 may be configured to specify a minimum transport period using a parameter so that the transport period does not become 0 seconds.

[0062] The wafer W scheduling (substrate transfer processing method) by the control device 80 will now be described in more detail. In the period calculation step (S1), when the supply interval of the wafers W is formulated as a mixed integer programming problem, the objective function is as follows: Objective function: Minimization of the supply interval of wafers W

[0063] The constraints are the following (A) and (B). Constraints: (A) Multiple transport periods of the transport module TM do not overlap. (B) The stay period of each process module PM is set within a range not exceeding the interval between wafer W supply, and also satisfies requests for wafer W replacement and immediate removal of wafers W. In addition, the reason why the residence time of each process module PM must not exceed the supply interval of wafers W in constraint condition (B) is that if the residence time exceeds the supply interval of wafers W, the process module PM will cause a blockage in the transport of wafers W.

[0064] In addition, the variables of a mixed integer programming problem include the following (a) to (c). Variable: (a) Wafer W supply interval (b) Duration of stay of PMs in each process module (c) Temporary variables to represent logical conditions

[0065] The substrate transfer and processing method according to this embodiment will be described in detail below, taking the substrate processing system 1B of the second configuration example as an example. Figure 6(A) is an enlarged plan view showing the fourth transfer module TM4 and its surrounding configuration of the substrate processing system 1B of the second configuration example. First, the fourth transfer module TM4 of the substrate processing system 1B will be described.

[0066] 6A, the fourth transfer module TM4 of the substrate processing system 1B has three opportunities to transfer a wafer W. The first transfer period T0 is the period during which the transfer robot 32B of the fourth transfer module TM4 transfers the wafer W from the fifth process module PM5 to the fourth evacuation module UM4. The second transfer period T1 is the period during which the wafer W is transferred from the fourth evacuation module UM4 to the seventh process module PM7. The third transfer period T2 is the period during which the wafer W is transferred from the seventh process module PM7 to the third pass-through module PASS3.

[0067] In the fourth transfer module TM4, as shown in FIG. 6B, multiple wafers W are transferred at a constant rhythm (wafer W supply interval). For example, the transfer of the second wafer W begins during the residence period in the seventh process module PM7 after the first wafer W has been transferred thereto. In this case, the transfer of the third wafer W also begins during the residence period in the seventh process module PM7 after the second wafer W has been transferred thereto. By overlapping the transfer of these wafers W into one cycle, a single wafer W supply interval including a first transfer period T0, a second transfer period T1, and a third transfer period T2 can be obtained, as shown in the lower diagram of FIG. 6B.

[0068] The fourth transfer module TM4 transfers wafers W in two patterns (pattern 0 and pattern 1) as shown in Figures 7(A) and 7(B). Figure 7(A) shows pattern 0 in the fourth transfer module TM4. Figure 7(B) shows pattern 1 in the fourth transfer module TM4.

[0069] 7A is a transfer pattern in which the order is first transfer period T0, second transfer period T1, and third transfer period T2. In this pattern 0, the first stay period P0 of the fourth evacuation module UM4 (the interval between transfer modules TM) and the second stay period P1 of the seventh process module PM7 (the interval between transfer modules TM) are shortened. That is, by using the constraint of "stay period of each process module PM≦wafer W supply interval−transfer period using process module PM," the stay period of each process module PM can be reduced. Therefore, the first stay period P0 of the fourth evacuation module UM4 and the second stay period P1 of the seventh process module PM7 are always short.

[0070] 7B is a transfer pattern in which the first transfer period T0, the third transfer period T2, and the second transfer period T1 are performed. In the case of this pattern 1, there is a possibility that the first stay period P0 in the fourth evacuation module UM4 or the second stay period P1 in the seventh process module PM7 may be long.

[0071] If the transfer periods of the fourth transfer module TM4 do not overlap in either Pattern 0 or Pattern 1, the desired values ​​will be the supply intervals of wafers W and the stay periods in each module. Therefore, the condition under which the transfer periods of the fourth transfer module TM4 do not overlap in Pattern 0 and Pattern 1 is expressed by the following formula.

[0072] (A) In pattern 0, the formula for the second transport period T1 being carried out after the first transport period T0 is T0≦T0+P0 (P0=stay period of the fourth evacuation module UM4) ... (1) Note that, when formula (1) is rearranged, it becomes 0≦P0. Since the stay period of the fourth evacuation module UM4 is 0 seconds or more, this formula is always satisfied.

[0073] (a) In pattern 0, the formula for the third transport period T2 being carried out after the second transport period T1 is T0+P0+T1≦T0+P0+T1+P1 (P1=stay period in the seventh process module PM7) ... (2) Note that, when formula (2) is transformed, it becomes 0≦P1. Since the stay period in the seventh process module PM7 is 0 seconds or more, this formula is always satisfied.

[0074] (c) The formula for the fact that the third transfer period T2 is performed before the wafer W supply interval in pattern 0 is T0+P0+T1+P1+T2≦wafer W supply interval … (3) The left side of this equation (3) corresponds to the range from the first transfer period T0 to the third transfer period T2 shown in Figure 8(A). On the other hand, the right side of equation (3) corresponds to the range (the supply interval of wafers W) shown in Figure 8(A). For example, if the timing of the third transfer period T2 is delayed, and multiple wafers W are being sequentially transferred in the fourth transfer module TM4, the first transfer period T0 of the subsequent wafer W will overlap with the third transfer period T2, as shown in Figure 8(B), and the condition will no longer be satisfied.

[0075] (D) In ​​pattern 1, the formula for the third transport period T2 being carried out after the first transport period T0 is T0≦T0+P0+T1+P1−wafer W supply interval … (4) The left side of equation (4) corresponds to the range of the first transfer period T0 shown in Figure 9(A). The right side of equation (4) corresponds to the range of the first transfer period T0 and the first residence period P0 of the fourth evacuation module UM4 shown in Figure 9(A). For example, if the timing of the third transfer period T2 is delayed and multiple wafers W are being transferred sequentially in the fourth transfer module TM4, the third transfer period T2 of the subsequent wafer W will overlap with the first transfer period T0, as shown in Figure 9(B), and the condition will no longer be satisfied.

[0076] (E) In pattern 1, the formula for the second transport period T1 being carried out after the third transport period T2 is T0+P0+T1+P1+T2≦T0+P0+wafer W supply interval … (5) The left side of equation (5) corresponds to the range of the first transfer period T0, the second transfer period T1, and the third transfer period T2 shown in Fig. 9(C), and the right side of equation (5) corresponds to the range (the supply interval of wafers W) shown in Fig. 9(C).

[0077] (F) The formula for the first transfer period T0 in pattern 1 being performed before the wafer W supply interval T0+P0+T1≦wafer W supply interval … (6)

[0078] The control device 80 can prevent multiple transfer periods from overlapping in the fourth transfer module TM4 if the constraint conditions are satisfied in either the transfer pattern of Pattern 0 or Pattern 1. For example, by using the big-M method, the control device 80 can formulate either Pattern 0 or Pattern 1 as the following constraint conditions. Formula (1)+M×BoolPatternTM4_0 Formula (2)+M×BoolPatternTM4_0 Formula (3)+M×BoolPatternTM4_0 Formula (4)+M×BoolPatternTM4_1 Formula (5)+M×BoolPatternTM4_1 Formula (6)+M×BoolPatternTM4_1 BoolPatternTM4_0 = 0 or 1 (variable that is 0 if pattern 0 is selected, and 1 if it is not selected) BoolPatternTM4_1 = 0 or 1 (variable that is 0 if pattern 1 is selected, and 1 if it is not selected) BoolPatternTM4_0+BoolPatternTM4_1=1 (Constraint to satisfy either pattern 0 or pattern 1)

[0079] Next, the third transfer module TM3 of the substrate processing system 1B will be considered. The third transfer module TM3 has four opportunities to transfer a wafer W (see FIG. 3). The first transfer period T0 is the period during which the transfer robot 32B of the third transfer module TM3 transfers the wafer W from the third process module PM3 to the fifth process module PM5. The second transfer period T1 is the period during which the wafer W is transferred from the third pass module PASS3 to the third evacuation module UM3. The third transfer period T2 is the period during which the wafer W is transferred from the third evacuation module UM3 to the sixth process module PM6. The fourth transfer period T3 is the period during which the wafer W is transferred from the sixth process module PM6 to the second pass module PASS2.

[0080] The third transfer module TM3 also transfers multiple wafers W at a constant rhythm. Six transfer patterns (patterns 0 to 5) can be considered for the third transfer module TM3, as shown in FIG. 10 . Pattern 0 is a transfer pattern in which the first transfer period T0, the second transfer period T1, the third transfer period T2, and the fourth transfer period T3 are arranged in this order. Pattern 1 is a transfer pattern in which the first transfer period T0, the second transfer period T1, the fourth transfer period T3, and the third transfer period T2 are arranged in this order. Pattern 2 is a transfer pattern in which the first transfer period T0, the third transfer period T2, the second transfer period T1, and the fourth transfer period T3 are arranged in this order. Pattern 3 is a transfer pattern in which the first transfer period T0, the third transfer period T2, the fourth transfer period T3, and the second transfer period T1 are arranged in this order. Pattern 4 is a transfer pattern in which the first transfer period T0, the fourth transfer period T3, the second transfer period T1, and the third transfer period T2 are arranged in this order. Pattern 5 is a transport pattern in which the first transport period T0, the fourth transport period T3, the third transport period T2, and the second transport period T1 are arranged in this order.

[0081] In any of these transfer patterns, if the multiple transfer periods of the third transfer module TM3 do not overlap, the supply interval of wafers W and the stay period in each process module PM at that time will be the desired values. In the following, the condition for multiple transfer periods not to overlap in pattern 5 of the third transfer module TM3 will be expressed by the following formula as a representative example, and explanations for other patterns will be omitted.

[0082] (G) The second transfer period T1 is carried out before the wafer W supply interval. First transfer period T0 + (stay period P0 in the fifth process module PM5 + first transfer period T0 in the fourth transfer module TM4 + first stay period P0 in the fourth withdrawal module UM4 + second transfer period T1 in the fourth transfer module TM4 + second stay period P1 in the seventh process module PM7 + third transfer period T2 in the fourth transfer module TM4 + third stay period P2 in the third pass-through module PASS3) + second transfer period T1 ≦ wafer W supply interval × (N + 1) ... (7) 11A and 11C, the number in parentheses in equation (7) indicates the "fourth transfer module side period" from the stay period P0 in the fifth process module PM5 to the third stay period P2 in the third pass-through module PASS3 by the fourth transfer module TM4. The left side of equation (7) includes the fourth transfer module side period in addition to the first transfer period T0 and the second transfer period T1, and the right side of equation (7) indicates that the supply period of wafer W from the third transfer module TM3 is longer than the left side.

[0083] (H) Regarding the variable N used in the formula for the second transfer period T1 being carried out before the wafer W supply interval: N is defined as an integer variable indicating "the magnification of the start point of the first transfer returning from the fourth transfer module TM4 relative to the supply interval of wafers W, when the start point of the first transfer using the third transfer module TM3 is taken as the start point." In this case, it can be expressed by the following equation (8). Wafer W supply interval × N ≦ first transfer period T0 + (fourth transfer module side period) ≦ wafer W supply interval × (N + 1) (8) The left side of equation (8) is a predetermined range between the first transfer period T0 and the second transfer period T1, as shown in Figure 11(B). The middle side of equation (8) is a range including the fourth transfer module side period from the start of the first transfer period T0 to just before the second transfer period T1 (see also Figure 11(C)). The right side of equation (8) is a range from the start of the first transfer period T0 to beyond the second transfer period T1.

[0084] (i) The formula for the fourth transport period T3 being carried out after the first transport period T0 First transfer period T0≦First transfer period T0+(Fourth transfer module side period)+Second transfer period T1+Stay period P1 in third retreat module UM3+Third transfer period T2+Stay period P2 in sixth process module PM6−Supply interval of wafer W×(N+2) (9) 12A, the left side of equation (9) corresponds to the range of the first transfer period T0, while the right side of equation (9) corresponds to the range from the first transfer period T0 to the fourth transfer period T3 of the subsequent wafer W.

[0085] (K) The formula for the third transport period T2 being carried out after the fourth transport period T3 First transfer period T0 + (period on the side of the fourth transfer module) + second transfer period T1 + residence period P1 in the third evacuation module UM3 + third transfer period T2 + residence period P2 in the sixth process module PM6 + fourth transfer period T3 ≦ first transfer period T0 + (period on the side of the fourth transfer module) + second transfer period T1 + residence period P1 in the third evacuation module UM3 + wafer W supply interval ... (10) 12(B), the left side of equation (10) corresponds to the range from the start of the first transfer period T0 to the end of the fourth transfer period T3. On the other hand, the right side of equation (10) corresponds to the range from the start of the first transfer period T0 to the start of the third transfer period T2 of the subsequent wafer W. The supply interval of wafers W corresponds to the time from the start of the third transfer period T2 of the first wafer W to the start of the third transfer period T2 of the subsequent wafer W.

[0086] (K) The formula for the second transport period T1 being carried out after the third transport period T2 First transfer period T0 + (period on the side of the fourth transfer module) + second transfer period T1 + residence period P1 in the third evacuation module UM3 + third transfer period T2 ≦ first transfer period T0 + (period on the side of the fourth transfer module) + supply interval of wafers W ... (11) 12(C), the left side of equation (11) corresponds to the range from the start of the first transfer period T0 to the end of the third transfer period T2. On the other hand, the right side of equation (11) corresponds to the range from the start of the first transfer period T0 to the start of the second transfer period T1 of the subsequent wafer W. The supply interval of wafers W corresponds to the time from the start of the second transfer period T1 of the preceding wafer W to the start of the second transfer period T1 of the subsequent wafer W.

[0087] The control device 80 can formulate an equation that indicates that multiple transfer periods in the third transfer module TM3 do not overlap for patterns 0 to 4, similarly to pattern 5 above. If the constraint conditions are satisfied for any of these transfer patterns from pattern 0 to pattern 5, multiple transfer periods in the third transfer module TM3 can be prevented from overlapping. For example, by using the big-M method, the control device 80 can similarly formulate any of patterns 0 to 5 as constraint conditions for the fourth transfer module TM4.

[0088] Next, we will explain the formulation of OR transfer by the transfer module TM of the substrate processing system 1B. In OR transfer, a wafer W is transferred to one of two process modules PM. The same concept can be applied to the case where a wafer W is transferred to one of three or more process modules PM. Specifically, in OR transfer between two process modules PM, the stay period of the wafer W in the process module PM can be selected within a range of two cycles in the supply interval between wafers W. The calculation in this case involves the following two steps. Step 1: A tentative stay period that fits within one cycle of the wafer W supply interval is prepared and the equation is solved. Step 2: The determined tentative stay period is adjusted so that it falls within a range of two cycles of the supply interval of wafers W, and the final stay period is determined.

[0089] First, in step 1, the control device 80 calculates a tentative stay period so that it can be calculated within the range of the supply interval of the wafer W. However, there are cases where the process module PM performing the OR transfer is an immediate unloading process module PM. "Immediate unloading" refers to unloading the wafer W from the process module PM after substrate processing is performed in that process module PM.

[0090] When the OR transfer process module PM is an immediate unloading process module PM and the actual period of the process recipe is less than or equal to the wafer W supply interval (i.e., when the actual period of the process recipe is short), the following equation (12) can be used as the tentative stay period. This concept can be illustrated by a time bar graph as shown in FIG. 13(A). Temporary residence time of process module PM = Actual period of process recipe ... (12)

[0091] On the other hand, when the process module PM for OR transfer is an immediate unloading process module PM and the actual period of the process recipe is greater than the wafer W supply interval (i.e., when the actual period of the process recipe is long), the following equation (13) can be used as the tentative stay period. This concept can also be represented by a time bar graph as shown in FIG. 13(B). Temporary residence time of process module PM = Actual period of process recipe - Supply interval of wafer W ... (13)

[0092] Furthermore, there is a case where the process module PM that performs the OR transfer is the process module PM that replaces (carries in and out) the wafer W. In this case, the following equation (14) can be used as the tentative stay period. Temporary residence time in process module PM = wafer W supply interval - wafer W unloading time from process module PM - wafer W loading time into process module PM ... (14)

[0093] Furthermore, the process module PM that performs the OR transfer may be a process module PM that is carried in from one transfer module TM and carried out to another transfer module TM (however, this does not include a process module PM that is immediately carried out). Hereinafter, this process module PM will also be referred to as the sending process module PM.

[0094] In the case of a feed process module PM, where the actual period of the process recipe is less than or equal to the interval between wafers W (i.e., when the actual period of the process recipe is short), the following equation (15) can be used as the tentative residence time. This concept can be illustrated by a time bar graph as shown in FIG. 13(C). 0≦temporary residence time in process module PM≦wafer W supply interval−transfer time from process module PM−transfer time to process module PM (15)

[0095] On the other hand, in the case of a sending process module PM, where the actual period of the process recipe is greater than the interval between wafers W (i.e., when the actual period of the process recipe is long), the following equation (16) can be used as the tentative residence time. This concept can be illustrated by a time bar graph as shown in FIG. 13(D). Actual period of process recipe - supply interval of wafers W≦temporary residence period of process module PM≦supply interval of wafers W−unloading period from process module PM−loading period to process module PM (16)

[0096] In step 1, the control device 80 calculates the tentative stay period for each of the above-mentioned multiple patterns, and then calculates the final stay period in step 2. The equation for calculating the final stay period can be divided into two cases, one where the actual period of the process recipe is less than or equal to the supply interval of wafers W and the other where the actual period of the process recipe is greater than or equal to the supply interval of wafers W, as shown in FIG.

[0097] Furthermore, if the actual period of the process recipe is less than the supply interval of wafers W and the tentative residence period in the process module PM is less than the actual period of the process recipe, the following equation (17) can be used. This concept can be represented by a bar graph of time as shown in FIG. 14(B). Stay period of process module PM=temporary stay period of process module PM+supply interval of wafer W... (17)

[0098] On the other hand, if the actual period of the process recipe is smaller than the supply interval of wafers W and the tentative residence time in the process module PM is equal to or larger than the actual period of the process recipe, the following equation (18) can be used. This concept can be represented by a bar graph of time as shown in FIG. 14(C). Duration of stay of process module PM = provisional duration of stay of process module PM … (18)

[0099] If the actual period of the process recipe is greater than the supply interval of wafers W, the following equation (19) can be used: This concept can be illustrated by a bar graph of time as shown in FIG. Stay period of process module PM=temporary stay period of process module PM+supply interval of wafer W... (19)

[0100] Furthermore, the stay period of a process module PM other than the OR transfer process module PM that is immediately unloaded is expressed by the following formula (20). Process module PM stay period = process recipe performance period … (20)

[0101] Furthermore, in the process modules PM other than the OR transfer, the stay period of the process module PM that exchanges (unloads and loads) the wafer W is expressed by the following formula (21). That is, in the case of the process module PM that exchanges the wafer W, the process recipe only needs to end at the timing when the wafer W is supplied. Duration of stay in process module PM = supply interval of wafer W - unloading period from process module PM - loading period into process module PM ... (21)

[0102] Furthermore, among the process modules PM other than the OR transport, the stay period of the sending process module PM is expressed by the following formula (22). Actual period of process recipe≦stay period in process module PM≦supply interval of wafer W−transfer period from process module PM−transfer period to process module PM (22)

[0103] When determining the optimal wafer W supply interval, constraint equations are formulated for all of the first through fourth transfer modules TM1 through TM4, dividing them into the above-described patterns. That is, equations are formulated that the transfer periods of the fourth transfer module TM4 do not overlap, that the transfer periods of the third transfer module TM3 do not overlap, that the transfer periods of the second transfer module TM2 do not overlap, and that the transfer periods of the first transfer module TM1 do not overlap. Furthermore, equations are formulated that indicate that the residence time of each process module PM is appropriate.

[0104] As described above, the objective function for maximizing the throughput is minimizing the interval between supplying wafers W, and the variables for this are the interval between supplying wafers W, the residence time of the wafers W in the process module PM, and temporary and auxiliary variables for expressing logical conditions.

[0105] Next, the allocation step (S2) in the wafer W scheduling (substrate transfer processing method) will be described. As mentioned above, if the intervals between the transfer periods during which the transfer modules TM operate are close to each other, even a slight delay will disrupt the transfer (see also the left diagram in FIG. 5). For this reason, based on the supply intervals between wafers W calculated in the period calculation step (S1), the allocation step (S2) calculates the residence periods of the process modules PM so that the intervals between each transfer period of the transfer module TM are increased.

[0106] However, the calculation in the allocation step (S2) is similar to the calculation in the period calculation step (S1). The differences are that the objective function is the leveling of the use intervals of the transfer modules TM (the intervals between transfer periods), the constraint conditions include auxiliary equations for leveling the use intervals of each transfer module TM, and the variables include additional variables for leveling the use intervals of the transfer modules TM. Note that in the allocation step (S2), the supply interval of the wafers W is a constant rather than a variable.

[0107] The auxiliary equation for leveling the usage intervals of each transport module TM determines the usage intervals of the transport modules TM. For example, in the case of the fourth transport module TM4, the usage intervals are the time interval between the first transport period T0 and the second transport period T1, the time interval between the second transport period T1 and the third transport period T2, and the time interval between the third transport period T2 and the first transport period T0, as shown in FIG.

[0108] The interval between the use of the transport modules TM can be calculated by "subtracting the left side from the right side" based on the above "conditions for preventing simultaneous transport of transport modules TM." For example, equation (5) for the implementation of the second transport period T1 after the third transport period T2 in pattern 1 of the fourth transport module TM4 is expressed as the following equation (23). Note that in equation (23), the time difference between the third transport period T2 and the second transport period T1 in pattern 1 of the fourth transport module TM4 is expressed as "IntervalTM4P1_T2_T1." In other words, "IntervalTMxPy_Tv_Tw" represents the time difference between Tv and Tw in pattern y of a specific transport module TM. IntervalTM4P1_T2_T1=(T0+P0+wafer W supply interval)-(T0+P0+T1+P1+T2) ... (23)

[0109] The usage interval of the fourth transfer module TM4 from the first transfer period T0 to the third transfer period T2 of pattern 1 is given by the following equation (24). IntervalTM4P1_T0_T2=(T0+P0+T1+P1-wafer W supply interval)-T0 ... (24)

[0110] Similarly, the usage interval from the third transfer period T2 to the second transfer period T1 of pattern 1 of the fourth transfer module TM4 is given by the following formula (25). IntervalTM4P1_T2_T1=(T0+P0+wafer W supply interval)-(T0+P0+T1+P1+T2) ... (25)

[0111] The usage interval from the second transfer period T1 to the first transfer period T0 of pattern 1 of the fourth transfer module TM4 is given by the following equation (26). IntervalTM4P1_T1_T0=wafer W supply interval−(T0+P0+T1) … (26)

[0112] The use intervals of the transport modules TM are shared by each other, as shown in FIG. 15(A). For example, if the total use interval is 60 seconds, the 60 seconds are shared among them. Because of this condition, the use intervals are leveled out by preventing any use intervals from being extremely long. For example, as shown in the left diagram of FIG. 15(A), there is a long interval of 40 seconds, so this is reduced and leveled out as shown in the right diagram of FIG. 15(A). Note that other methods of leveling out are also possible, such as increasing the minimum use interval.

[0113] Furthermore, in leveling the usage interval, a constraint equation using a new variable Z_TMx is added to prevent the usage interval of each transport module TM from becoming too long. For example, the equation for restricting the usage interval of the fourth transport module TM4 to not become too long is as follows:

[0114] For pattern 0 IntervalTM4P0_T0_T1-M×BoolPatternTM4_0≦Z_TM4 IntervalTM4P0_T1_T2-M×BoolPatternTM4_0≦Z_TM4 IntervalTM4P0_T2_T0-M×BoolPatternTM4_0≦Z_TM4 For pattern 1 IntervalTM4P1_T0_T2-M×BoolPatternTM4_1≦Z_TM4 IntervalTM4P1_T2_T1-M×BoolPatternTM4_1≦Z_TM4 IntervalTM4P1_T1_T0-M×BoolPatternTM4_1≦Z_TM4 The constraint equation using this new variable Z_TMx is similarly applied to the first transfer module TM1 to the third transfer module TM3.

[0115] Here, the constraint added in the "Formula for Preventing the Individual Use Interval of Each Transfer Module TM from Becoming Too Long" above will level out the TM use intervals to some extent. However, if there is an immediate unloading process module PM, there will be some portions where the use interval will not change, and if that is the maximum value, other use intervals may not be leveled out. For example, if the use interval between the first transfer period T0 and the second transfer period T1 in the left diagram of Figure 15(B) is fixed at 40 seconds due to immediate unloading, the above formula will not level out the use interval between the third transfer period T2 and the second transfer period T1, or the use interval between the second transfer period T1 and the first transfer period T0.

[0116] Therefore, the control device 80 limits the sum of each use interval to level out use intervals other than the maximum value. By limiting the sum, the effect of leveling is achieved in areas other than the maximum value. As a result, as shown in the right diagram of Figure 15(B), the use interval between the third transfer period T2 and the second transfer period T1, which are not fixed, and the use interval between the second transfer period T1 and the first transfer period T0 are leveled out. Specifically, a constraint equation using a new variable Zpair_TMx is added to the constraint conditions so that the sum of the use intervals does not become too large. For example, the equation for limiting the use interval of the fourth transfer module TM4 so that it does not become too large is as follows.

[0117] For pattern 0 IntervalTM4P0_T0_T1+IntervalTM4P0_T1_T2-M×BoolPatternTM4_0≦Zpair_TMx IntervalTM4P0_T0_T1+IntervalTM4P0_T2_T0-M×BoolPatternTM4_0≦Zpair_TMx IntervalTM4P0_T1_T2+IntervalTM4P0_T2_T0-M×BoolPatternTM4_0≦Zpair_TMx For pattern 1 IntervalTM4P1_T0_T2+IntervalTM4P1_T2_T1-M×BoolPatternTM4_1≦Zpair_TMx IntervalTM4P1_T0_T2+IntervalTM4P1_T1_T0-M×BoolPatternTM4_1≦Zpair_TMx IntervalTM4P1_T2_T1+IntervalTM4P1_T1_T0-M×BoolPatternTM4_1≦Zpair_TMx

[0118] The constraint equations using the new variable Zpair_TMx described above can be similarly applied to the first to third transfer modules TM1 to TM3.

[0119] In the allocation step (S2), the objective function for finding the optimal stay period of the process module PM is "leveling out the use interval of the transport module TM." This is achieved by preventing the use interval from becoming extremely long. Therefore, the objective function is set to the following equation (27) so that the sum of Z_TMx and Zpair_TMx becomes small. Objective function: Minimize ΣZ_TMx+ΣZpair_TMx …(27)

[0120] When determining the optimum residence time of the process module PM, the above-mentioned constraint equations are formulated for all of the first to fourth transfer modules TM1 to TM4. That is, the control device 80 formulates an equation for limiting the usage time of the fourth transfer module TM4 so that it does not become too long, an equation for limiting the usage time of the third transfer module TM3 so that it does not become too long, an equation for limiting the usage time of the second transfer module TM2 so that it does not become too long, and an equation for limiting the usage time of the first transfer module TM1 so that it does not become too long.

[0121] As mentioned above, the above equation (27) can be applied as an objective function for leveling the residence time of the process module PM. The variables are the supply interval of the wafer W, the residence time of the process module PM, temporary variables and auxiliary variables for expressing logical conditions, and additional variables (Z_TMx, Zpair_TMx) for leveling the use interval of the transfer module TM.

[0122] By performing the above-described allocation step (S2), the substrate transfer processing method can obtain stay periods in the process modules PM where the transfer periods in each transfer module TM do not overlap and are spaced apart from one another.

[0123] The substrate processing systems 1A, 1B, the control device 80, and the substrate transfer and processing method according to the present embodiment are not limited to the above embodiment, and various modifications are possible. For example, the substrate processing systems 1A, 1B have four transfer modules TM, but the number of transfer modules TM may be one, two, three, or five or more.

[0124] The technical ideas and effects of the present disclosure explained in the above embodiments will be described below.

[0125] A first aspect of the present disclosure is a substrate processing system 1A, 1B comprising one or more transfer modules TM for transporting substrates (wafers W), a plurality of process modules PM for performing substrate processing on the substrates transported by the one or more transfer modules TM, and a control device 80 for controlling the one or more transfer modules TM and the plurality of process modules PM, in which the control device 80 performs the following steps in order: (A) calculating a substrate supply interval for one or more transfer modules TM to supply substrates so that the transport periods of the plurality of substrates do not overlap; and (B) leveling out, based on the calculated substrate supply intervals, a plurality of time intervals (usage intervals) between the transport periods of the plurality of substrates so that the transport periods of the plurality of substrates are spaced apart from each other.

[0126] As described above, the substrate processing systems 1A and 1B can appropriately allocate the transfer periods for the multiple substrates while minimizing the intervals between substrate supply, even when the substrates (wafers W) are set on multiple complex transfer paths in one or more transfer modules TM. As a result, the substrate processing systems 1A and 1B can efficiently transfer the multiple substrates while avoiding overlapping transfer timings of the multiple substrates in the transfer module TM.

[0127] In step (A), the substrate supply intervals are calculated by a linear programming problem using a constraint that formulates an equation expressing that the transfer periods of multiple substrates do not overlap in all of one or more transfer modules TM, with minimizing the substrate (wafer W) supply interval as an objective function. This enables the substrate processing systems 1A and 1B to more appropriately calculate substrate supply intervals that allow multiple substrates to be efficiently transported while avoiding overlapping transfer timings of the multiple substrates in the transfer modules TM.

[0128] Furthermore, the constraints for a specific transfer module TM among the one or more transfer modules TM use, as variables, the substrate (wafer W) supply interval and the stay period of the process module PM connected to the specific transfer module TM. This allows the substrate processing systems 1A and 1B to easily calculate the substrate supply interval using a linear programming problem.

[0129] Furthermore, the constraints of a specific transfer module TM among one or more transfer modules TM include all of the multiple types of transfer paths for substrates (wafers W) in the specific transfer module TM, as well as multiple patterns in which the order of the multiple types of transfer paths is changed. This allows the substrate processing systems 1A and 1B to effectively formulate constraints that cover the multiple types of transfer paths in the specific transfer module TM.

[0130] In step (B), the objective function is to minimize the plurality of time intervals and / or the sum of the plurality of time intervals, and the plurality of time intervals are smoothed by a linear programming problem using a constraint condition formulated as an equation that indicates that the plurality of time intervals should not become large in all of one or more transfer modules TM. In this way, by using the linear programming problem, the substrate processing systems 1A, 1B can obtain a plurality of time intervals that are tolerant to delays in the residence time of the process modules PM.

[0131] Furthermore, the constraints for a specific transfer module TM among the one or more transfer modules TM are variables, such as the residence time of the process module PM connected to the specific transfer module TM and an additional variable for leveling out multiple time intervals, and the substrate (wafer W) supply interval is a constant. This allows the substrate processing systems 1A and 1B to easily calculate multiple time intervals using a linear programming problem.

[0132] Furthermore, the constraints for a specific transfer module TM among the one or more transfer modules TM include all of the multiple types of transfer paths for substrates (wafers W) in the specific transfer module TM, multiple patterns in which the order of the multiple types of transfer paths is changed, and an equation expressing that the multiple time intervals and / or the sum of the multiple time intervals in the specific transfer module TM do not become large. This allows the substrate processing systems 1A and 1B to effectively formulate the constraints for determining the multiple time intervals.

[0133] Furthermore, between adjacent transfer modules TM among the one or more transfer modules TM, a passing module PASS is provided that allows passage through the boundary between the adjacent transfer modules TM, and the control device 80 calculates the substrate supply interval and multiple time intervals so as to include the transfer period when the substrate (wafer W) passes through the passing module PASS. This allows the substrate processing systems 1A, 1B to schedule substrate transfer taking into account the transfer period for transferring the substrate to the passing module PASS.

[0134] Furthermore, at least one of the one or more transfer modules TM is connected to an evacuation module UM capable of temporarily storing a substrate (wafer W), and the control device 80 calculates the substrate supply interval and multiple time intervals to include the transfer period when transferring the substrate to and from the evacuation module UM. This enables the substrate processing systems 1A, 1B to transfer the wafer W by effectively utilizing the evacuation module UM.

[0135] Furthermore, one transfer module TM connected to multiple process modules PM among one or more transfer modules TM can select one of the multiple process modules PM to transfer a substrate (wafer W), and the control device 80 selects the residence time of the process module PM at a cycle of substrate supply intervals corresponding to the number of multiple process modules PM. This allows the substrate processing systems 1A, 1B to effectively perform OR transfer, which selectively transfers substrates to multiple process modules PM.

[0136] Furthermore, a second aspect of the present disclosure is a control device 80 of a substrate processing system 1A, 1B that transports substrates (wafers W) to multiple process modules PM using one or more transport modules TM to perform substrate processing, and the control device 80 controls, in this order: (A) a process of calculating a substrate supply interval for one or more transport modules TM to supply substrates so that the transport periods of multiple substrates do not overlap; and (B) a process of leveling out multiple time intervals (usage intervals) between the transport periods of multiple substrates so that the transport periods of multiple substrates are spaced apart from each other based on the calculated substrate supply intervals.

[0137] Furthermore, a third aspect of the present disclosure is a substrate transfer and processing method for transferring substrates (wafers W) to multiple process modules PM by one or more transfer modules TM for substrate processing, which includes the steps of: (A) calculating a substrate supply interval for one or more transfer modules TM to supply substrates so that the transfer periods of the multiple substrates do not overlap; and (B) leveling out multiple time intervals between the transfer periods of the multiple substrates based on the calculated substrate supply intervals so that the transfer periods of the multiple substrates are spaced apart from one another. In the second and third aspects described above, multiple substrates can be efficiently transferred while avoiding overlapping transfer timings of the multiple substrates in the transfer module TM.

[0138] The substrate processing systems 1A, 1B, the control device 80, and the substrate transfer and processing method according to the presently disclosed embodiments are illustrative in all respects and are not limiting. The embodiments can be modified and improved in various ways without departing from the spirit and scope of the appended claims. The features described in the above embodiments can be configured in other ways and can be combined together without conflict. [Explanation of symbols]

[0139] 1A, 1B Substrate Processing System 80 Control device PM Process Module TM Transfer Module W wafer (substrate)

Claims

1. one or more transfer modules for transferring substrates; a plurality of process modules for performing substrate processing on the substrates transferred by the one or more transfer modules; a control device for controlling the one or more transfer modules and the plurality of process modules, The control device (A) calculating a substrate supply interval for the one or more transfer modules so that transfer periods of the plurality of substrates do not overlap with each other; (B) setting a time interval for each of the transport periods of the adjacent substrates, and calculating a plurality of equalized time intervals based on the substrate supply intervals calculated in the step (A) so that the transport periods of the plurality of substrates do not overlap with each other; Substrate processing system.

2. In the step (A), the substrate supply interval is calculated by a linear programming problem using a constraint condition in which the objective function is to minimize the substrate supply interval and an equation is formulated that indicates that the transport periods of the plurality of substrates do not overlap in all of the one or more transport modules. The substrate processing system of claim 1 .

3. the constraint condition for a predetermined transfer module among the one or more transfer modules uses as variables a supply interval between the substrates and a stay period of the process module connected to the predetermined transfer module; The substrate processing system of claim 2 .

4. the constraints of a predetermined transfer module among the one or more transfer modules include all of a plurality of types of transfer paths for the substrate in the predetermined transfer module, and also include a plurality of patterns in which the order of the plurality of types of transfer paths is changed. The substrate processing system of claim 2 .

5. In the step (B), the objective function is to minimize the plurality of time intervals, and the plurality of time intervals are averaged by a linear programming problem using constraint conditions formulated as equations that represent that the plurality of time intervals are reduced for all of the one or more transport modules. The substrate processing system of claim 1 .

6. the constraint condition for a predetermined transfer module among the one or more transfer modules has variables including a stay period of the process module connected to the predetermined transfer module and an additional variable for leveling the plurality of time intervals, and a constant including a substrate supply interval; The substrate processing system according to claim 5 .

7. the constraint condition of a predetermined transport module among the one or more transport modules includes all of a plurality of types of transport paths for the substrate in the predetermined transport module, and also includes a plurality of patterns in which the order of the plurality of types of transport paths is changed; and including an equation expressing that the plurality of time intervals in the predetermined transport module become smaller. The substrate processing system according to claim 5 .

8. a passing module that can pass through a boundary between the adjacent transport modules is provided between the one or more transport modules; the control device calculates the supply interval of the substrate and the plurality of time intervals so as to include a transport period when the substrate passes through the passing module. The substrate processing system according to claim 1 .

9. a retreat module capable of temporarily storing the substrate is connected to at least one of the one or more transfer modules; the control device calculates the substrate supply interval and the plurality of time intervals so as to include a transport period when transporting the substrate between the evacuation module and the evacuation module. The substrate processing system according to claim 1 .

10. one transfer module connected to the plurality of process modules among the one or more transfer modules is capable of selecting any one of the plurality of process modules to transfer the substrate; the control device selects a stay period of the process module at a cycle of the substrate supply interval corresponding to the number of the plurality of process modules. The substrate processing system according to claim 1 .

11. A control device for a substrate processing system that transports substrates to a plurality of process modules by one or more transport modules and performs substrate processing, The control device (A) calculating a substrate supply interval for the one or more transfer modules so that transfer periods of the plurality of substrates do not overlap with each other; (B) setting one time interval for each of the transport periods of the adjacent substrates, and calculating a plurality of equalized time intervals based on the substrate supply intervals calculated in the step (A) so that the transport periods of the plurality of substrates do not overlap with each other, and Control device.

12. A substrate transport and processing method for transporting substrates to a plurality of process modules by one or more transport modules and performing substrate processing, comprising: (A) calculating a substrate supply interval for the one or more transfer modules so that transfer periods of the plurality of substrates do not overlap with each other; (B) setting one time interval for each of the transport periods of the adjacent substrates, and calculating a plurality of equalized time intervals based on the substrate supply intervals calculated in the step (A) so that the transport periods of the plurality of substrates do not overlap with each other; A substrate transport and processing method.

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