Semiconductor Devices

Abstract

To provide a semiconductor device with excellent electrical characteristics, a semiconductor device with stable electrical characteristics, and a display device with high reliability.SOLUTION: A semiconductor device includes a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. The first insulating layer is in contact with an upper surface of the first conductive layer. The semiconductor layer is in contact with an upper surface of the first insulating layer. The pair of second conductive layers are in contact with an upper surface of the semiconductor layer. The pair of second conductive layers are apart from each other in a region overlapping with the first conductive layer. The semiconductor layer contains indium and oxygen. A triangular diagram expressing the atomic number ratio of indium, an element M, and zinc has a composition in the range of connecting a first coordinate (1:0:0), a second coordinate (2:1:0), a third coordinate (14:7:1), a fourth coordinate (7:2:2), a fifth coordinate (14:4:21), a sixth coordinate (2:0:3), and the first coordinate with a line in this order. The element M is one or more of gallium, aluminum, yttrium, and tin.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have attracted attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field-effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Non-Patent Documents 1 and 2 disclose an oxide semiconductor material of InGaO3(ZnO)m (m: natural number).

[0005] Metal oxides that can be used for semiconductor layers can be formed by sputtering or the like, and therefore can be used for the semiconductor layers of transistors that constitute large display devices. Furthermore, since it is possible to use a part of the production equipment for transistors that use polycrystalline silicon or amorphous silicon by modifying it, capital investment can be reduced. Furthermore, transistors that use metal oxides have higher field-effect mobility than transistors that use amorphous silicon, and therefore high-performance display devices equipped with driver circuits can be realized. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 [Non-patent literature]

[0007] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-patent document 2] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable display device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. The first insulating layer is in contact with a top surface of the first conductive layer, the semiconductor layer is in contact with a top surface of the first insulating layer, the pair of second conductive layers are in contact with a top surface of the semiconductor layer, and the pair of second conductive layers are separated by a region overlapping with the first conductive layer. The semiconductor layer contains indium and oxygen, and has a composition within a range connecting the first coordinate (1:0:0), the second coordinate (2:1:0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), the sixth coordinate (2:0:3), and the first coordinate, in this order, by straight lines in a ternary diagram showing the atomic ratio of indium, element M, and zinc. The element M is at least one of gallium, aluminum, yttrium, and tin.

[0011] One embodiment of the present invention is a semiconductor device including a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers, in which the first insulating layer is in contact with a top surface of the first conductive layer, the semiconductor layer is in contact with a top surface of the first insulating layer, the pair of second conductive layers are in contact with a top surface of the semiconductor layer, and the pair of second conductive layers are separated by a region overlapping with the first conductive layer. The semiconductor layer contains indium and oxygen, and has a composition within a range connecting the first coordinate (7:1:0), the second coordinate (2:1:0), the third coordinate (14:7:1), the fourth coordinate (7:2:2), the fifth coordinate (14:4:21), the sixth coordinate (2:0:3), the seventh coordinate (7:0:1), and the first coordinate in this order in a ternary diagram showing the atomic ratio of indium, element M, and zinc. The element M is one or more of gallium, aluminum, yttrium, and tin.

[0012] One embodiment of the present invention is a semiconductor device including a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. The first insulating layer is in contact with a top surface of the first conductive layer, the semiconductor layer is in contact with a top surface of the first insulating layer, the pair of second conductive layers are in contact with a top surface of the semiconductor layer, and the pair of second conductive layers are separated by a region overlapping with the first conductive layer. The semiconductor layer contains indium, zinc, and oxygen, and has a composition within a range connecting the first coordinate (44:11:10), the second coordinate (4:1:6), the third coordinate (2:0:3), the fourth coordinate (11:0:2), and the first coordinate in this order by straight lines in a ternary diagram showing the atomic ratio of indium, the element M, and zinc. The element M is at least one of gallium, aluminum, yttrium, and tin.

[0013] One embodiment of the present invention is a semiconductor device including a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. The first insulating layer is in contact with a top surface of the first conductive layer, the semiconductor layer is in contact with a top surface of the first insulating layer, the pair of second conductive layers are in contact with a top surface of the semiconductor layer, and the pair of second conductive layers are separated by a region overlapping with the first conductive layer. The semiconductor layer contains indium, zinc, and oxygen, and has a composition within a range connecting a first coordinate (44:11:10), a second coordinate (4:1:4), a third coordinate (1:0:1), a fourth coordinate (11:0:2), and the first coordinate in this order by straight lines in a ternary diagram showing the atomic ratio of indium, element M, and zinc. The element M is at least one of gallium, aluminum, yttrium, and tin.

[0014] In the above-described semiconductor device, the semiconductor layer preferably has a stacked structure of a first metal oxide film and a second metal oxide film over the first metal oxide film, and the first metal oxide film preferably has lower crystallinity than the second metal oxide film.

[0015] In the semiconductor device described above, the second conductive layer preferably has a stacked structure of a first conductive film, a second conductive film on the first conductive film, and a third conductive film on the second conductive film. The second conductive film preferably contains copper, silver, gold, or aluminum. The first conductive film and the third conductive film preferably contain an element different from that of the second conductive film, and each of the first conductive film and the third conductive film preferably independently contains any of titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, and ruthenium.

[0016] The semiconductor device preferably further includes a second insulating layer in contact with the top surface of the semiconductor layer and the top and side surfaces of the second conductive layer, and the second insulating layer preferably contains oxygen.

[0017] The semiconductor device preferably further comprises a third insulating layer, the third insulating layer being in contact with an upper surface of the second insulating layer, and the third insulating layer preferably contains nitrogen.

[0018] In the above-described semiconductor device, the second insulating layer preferably contains silicon oxide, and the third insulating layer preferably contains silicon nitride. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics, a highly reliable semiconductor device, a semiconductor device with stable electrical characteristics, or a highly reliable display device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0021] [Figure 1]1A and 1B are diagrams illustrating the composition of metal oxides. [Figure 2] 2A and 2B are diagrams illustrating the composition of metal oxides. [Figure 3] 3A and 3B are diagrams illustrating the composition of metal oxides. [Figure 4] FIG. 4 is a diagram illustrating the composition of metal oxides. [Figure 5] Figure 5A is a diagram illustrating the classification of IGZO crystal structures, Figure 5B is a diagram illustrating the XRD spectrum of silica glass, and Figure 5C is a diagram illustrating the XRD spectrum of crystalline IGZO. [Figure 6] 6A and 6B are cross-sectional views showing examples of the configuration of a transistor. [Figure 7] 7A and 7B are cross-sectional views showing examples of the configuration of a transistor. [Figure 8] 8A is a top view illustrating an example of the structure of a transistor, and FIGS. 8B and 8C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 9] 9A, 9B, and 9C are cross-sectional views showing examples of the configuration of a transistor. [Figure 10] 10A is a top view illustrating an example of the structure of a transistor, and FIGS. 10B and 10C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 11] 11A and 11B are cross-sectional views showing examples of the configuration of a transistor. [Figure 12] 12A and 12B are cross-sectional views showing examples of the configuration of a transistor. [Figure 13] 13A, 13B, and 13C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 14] 14A and 14B are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 15] 15A and 15B are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 16] 16A and 16B are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 17] 17A to 17C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 18] 18A and 18B are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 19] 19A and 19B are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 20] 20A and 20B are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 21] 21A, 21B, 21C, and 21D are cross-sectional views showing examples of the configuration of a transistor. [Figure 22] 22A is a top view illustrating an example of the structure of a transistor, and FIGS. 22B and 22C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 23] 23A is a top view illustrating an example of the structure of a transistor, and FIGS. 23B and 23C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 24] 24A is a top view illustrating an example of the structure of a transistor, and FIGS. 24B and 24C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 25] 25A, 25B, 25C, 25D, and 25E show examples of transistor configurations. [Figure 26] 26A, 26B and 26C are top views of the display device. [Figure 27] FIG. 27 is a cross-sectional view of the display device. [Figure 28] FIG. 28 is a cross-sectional view of the display device. [Figure 29] FIG. 29 is a cross-sectional view of the display device. [Figure 30] FIG. 30 is a cross-sectional view of the display device. [Figure 31] FIG. 31 is a cross-sectional view of the display device. [Figure 32] Fig. 32A is a block diagram of a display device, and Fig. 32B and Fig. 32C are circuit diagrams of the display device. [Figure 33]Figures 33A, 33C and 33D are circuit diagrams of the display device, and Figure 33B is a timing chart of the display device. [Figure 34] 34A and 34B show examples of the configuration of a display module. [Figure 35] 35A and 35B show configuration examples of electronic devices. [Figure 36] 36A, 36B, 36C, and 36D show configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0023] In each figure described herein, the size, layer thickness, or area of ​​each component may be exaggerated for clarity.

[0024] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and are not intended to limit the number.

[0025] In this specification, terms indicating position, such as "above" and "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0026] In this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. Therefore, the terms source and drain can be used interchangeably.

[0027] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to the direction perpendicular to the channel length direction. Note that, depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0028] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements with various functions.

[0029] In this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0030] In this specification, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state) when a voltage V between the gate and source of an n-channel transistor is applied. gs is the threshold voltage V th (For p-channel transistors, V th This refers to a state of being (higher than)

[0031] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) images etc. on a display surface, and therefore the display panel is one aspect of an output device.

[0032] In this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0033] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0034] A touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. A touch panel can have a configuration including a display panel and a touch sensor panel. Alternatively, the touch panel can have a touch sensor function inside or on the surface of the display panel.

[0035] In this specification, a touch panel substrate on which a connector and an IC are mounted may be called a touch panel module, a display module, or simply a touch panel.

[0036] (Embodiment 1) In this embodiment, a metal oxide that can be suitably used in a semiconductor device according to one embodiment of the present invention will be described.

[0037] A semiconductor device according to one embodiment of the present invention includes a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor in a channel formation region. The use of a metal oxide is preferable because the transistor has good switching characteristics and an extremely low off-state current compared to a semiconductor such as silicon.

[0038] Here, the composition of the metal oxide significantly affects the electrical characteristics and reliability of the transistor. The metal oxide preferably contains indium. Furthermore, the metal oxide preferably has a high indium content. By increasing the indium content of the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a transistor using a metal oxide with a high indium content in its channel formation region has high field-effect mobility and can pass a large current. Furthermore, a semiconductor device using such a transistor can be driven at high speed. Therefore, in a display device including such a semiconductor device, a transistor used in a pixel portion and a transistor used in a driver circuit portion can be formed on the same substrate. Furthermore, by using such a transistor in the pixel portion, high-quality images can be provided.

[0039] The metal oxide preferably contains element M in addition to indium. Element M preferably has a high bond energy with oxygen. In particular, element M preferably has a higher bond energy with oxygen than indium. By containing element M, which has a higher bond energy with oxygen than indium, oxygen vacancies are less likely to form in the metal oxide. As element M, one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium can be used. In particular, as element M, one or more of gallium, aluminum, yttrium, and tin can be used. Furthermore, element M has the function of increasing the energy gap of the metal oxide.

[0040] Gallium is particularly suitable as the element M. The metal oxide contains gallium, which has a higher bond energy with oxygen than indium, making it less likely for oxygen vacancies to form in the metal oxide. The presence of many oxygen vacancies in the metal oxide used in the channel formation region leads to a decrease in the electrical characteristics and reliability of the transistor. Therefore, by using a metal oxide containing indium and gallium, a transistor with high field-effect mobility and high reliability can be realized.

[0041] The metal oxide preferably contains zinc in addition to indium. Alternatively, the metal oxide preferably contains indium, the element M, and zinc. Zinc has the function of increasing the crystallinity of the metal oxide. A crystalline metal oxide can be suitably used for the channel formation region. For example, a metal oxide having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystal (nc) structure, or the like, which will be described later, can be used for the channel formation region. By using a crystalline metal oxide for the channel formation region, the defect level density in the channel formation region can be reduced, resulting in a highly reliable transistor.

[0042] The higher the crystallinity of a metal oxide, the lower the density of defect states in the film. On the other hand, by using a metal oxide with low crystallinity for the channel formation region, a transistor capable of passing a large current can be realized.

[0043] <Metal oxide composition> The composition of the metal oxide will be specifically described below, which shows the atomic ratio of indium, element M, and zinc in the metal oxide.

[0044] Preferred ranges of the atomic ratio of indium, element M, and zinc in the metal oxide are shown in Figures 1A, 1B, 2A, and 2B. Figures 1A, 1B, 2A, and 2B show the atomic ratio of indium, element M, and zinc using an equilateral triangle with indium, element M, and zinc as vertices, and are also called triangular diagrams, triangular coordinate diagrams, or ternary diagrams. Note that Figures 1A, 1B, 2A, and 2B do not show the atomic ratio of oxygen.

[0045] First, the atomic ratio of each element will be explained using Figures 3A, 3B, and 4. Figures 3A, 3B, and 4 respectively show examples of metal oxides having element X, element Y, and element Z. The ternary diagrams shown in Figures 3A, 3B, and 4 show an equilateral triangle with points X, Y, and Z as vertices, and a coordinate point W (α:β:γ) as an example of the composition of the metal oxide.

[0046] The coordinate point W (α:β:γ) indicates that the atomic ratio of elements X, Y, and Z is X:Y:Z = α:β:γ. The closer to each vertex, the higher the atomic ratio of each element, and the farther away, the lower the atomic ratio. Here, point X has coordinates (1:0:0), which indicates that the atomic ratio of elements X, Y, and Z is X:Y:Z = 1:0:0, meaning that the metal oxide contains element X and neither element Y nor element Z. Point Y has coordinates (0:1:0), which indicates that the atomic ratio of elements X, Y, and Z is X:Y:Z = 0:1:0, meaning that the metal oxide contains element Y and neither element X nor element Z. Point Z has coordinates (0:0:1), which indicates that the atomic ratio of elements X, Y, and Z is X:Y:Z = 0:0:1, meaning that the metal oxide contains element Z and neither element X nor element Y.

[0047] In this specification and the like, the atomic ratio of element X, element Y, and element Z may be expressed as X:Y:Z. Also, the ratio of the total number of atoms of element X and element Y to the number of atoms of element Z may be expressed as (X+Y):Z. Other combinations of elements may also be expressed in the same manner.

[0048] FIG. 3A shows lines LNx, LNy, and LNz. Line LNx is a line connecting point X and point Dx (0:β:γ), which divides the length of side YZ by γ:β. Line LNx can also be considered a set of points where the atomic ratio of element Y to element Z satisfies Y:Z = β:γ. Line LNy is a line connecting point Y and point Dy (α:0:γ), which divides the length of side XZ by γ:α. Line LNy can also be considered a set of points where the atomic ratio of element X to element Z satisfies X:Z = α:γ. Line LNz is a line connecting point Z and point Dz (α:β:0), which divides the length of side XY by β:α. Line LNz can also be considered a set of points where the atomic ratio of element X to element Y satisfies X:Y = α:β. Moreover, the lines LNx, LNy, and LNz all intersect with the coordinate point W(α:β:γ).

[0049] In this specification, the term "a straight line connecting point A and point B" can be replaced with "a line segment connecting point A and point B."

[0050] Here, the coordinate point W(α:β:γ) can also be said to be the intersection of the line LNx and the line LNy. The coordinate point W(α:β:γ) can also be said to be the intersection of the line LNy and the line LNz. The coordinate point W(α:β:γ) can also be said to be the intersection of the line LNx and the line LNz.

[0051] Note that side XY is a set of points where the ratio of the total number of atoms of element X and element Y to the number of atoms of element Z satisfies (X + Y):Z = 1:0. In other words, side XY indicates that the metal oxide contains at least one of element X or element Y, but does not contain element Z. Side YZ is a set of points where the ratio of the total number of atoms of element X to element Y and element Z satisfies X:(Y + Z) = 0:1. In other words, side YZ indicates that the metal oxide contains at least one of element Y or element Z, but does not contain element X. Side XZ is a set of points where the ratio of the total number of atoms of element Y to element X and element Z satisfies (X + Z):Y = 1:0. In other words, side XZ indicates that the metal oxide contains at least one of element X or element Z, but does not contain element Y.

[0052] As a specific example, we will explain the case where coordinate point W is (5:1:3). When coordinate point W is (5:1:3), the ratio of the length of line segment XDz to the length of line segment DzY is 1:5. The ratio of the length of line segment YDx to the length of line segment DxZ is 3:1. The ratio of the length of line segment XDy to the length of line segment DyZ is 3:5. Furthermore, line LNx is a set of points where the atomic ratio of element Y to element Z satisfies Y:Z = 1:3. Line LNy is a set of points where the atomic ratio of element X to element Z satisfies X:Z = 5:3. Line LNz is a set of points where the atomic ratio of element X to element Y satisfies X:Y = 5:1.

[0053] FIG. 3B shows lines PEx, PEy, and PEz. Line PEx is a perpendicular line drawn from coordinate point W (α:β:γ) to side YZ. Line PEy is a perpendicular line drawn from coordinate point W (α:β:γ) to side XZ. Line PEz is a perpendicular line drawn from coordinate point W (α:β:γ) to side XY. Here, the ratio of the lengths of line PEx, line PEy, and line PEz is α:β:γ.

[0054] As a specific example, a case where the coordinate point W is (5:1:3) will be described. When the coordinate point W is (5:1:3), the ratio of the length of the line PEx to the length of the line PEy and the length of the line PEz is 5:1:3.

[0055] FIG. 4A shows lines PAx, PAy, and PAz. Line PAx is a line parallel to side YZ and intersects with coordinate point W(α:β:γ). Line PAy is a line parallel to side XZ and intersects with coordinate point W(α:β:γ). Line PAz is a line parallel to side XY and intersects with coordinate point W(α:β:γ). Line PAx can also be considered a set of points where the ratio of the total number of atoms of element X to the total number of atoms of element Y and element Z satisfies X:(Y+Z)=α:(β+γ). Line PAy can also be considered a set of points where the ratio of the total number of atoms of element X and element Z to the number of atoms of element Y satisfies (X+Z):Y=(α+γ):β. Line PAz can also be considered a set of points where the ratio of the total number of atoms of element X and element Y to the number of atoms of element Z satisfies (X+Y):Z=(α+β):γ).

[0056] As a specific example, the case where coordinate point W is (5:1:3) will be described. When coordinate point W is (5:1:3), line PAx is a set of points where the ratio of the number of atoms of element X to the total number of atoms of elements Y and Z satisfies X:(Y+Z)=5:4. Line PAy is a set of points where the ratio of the number of atoms of element Y to the total number of atoms of elements X and Z satisfies (X+Z):Y=8:1. Line PAz is a set of points where the ratio of the number of atoms of element X to the total number of atoms of element Z satisfies (X+Y):Z=2:1.

[0057] The composition of a metal oxide that can be suitably used for a channel formation region of a transistor will be specifically described below.

[0058] [Metal oxide composition 1] The metal oxide preferably contains indium and oxygen. The metal oxide may further contain one or more of the elements M and zinc. The composition of a metal oxide suitable for use in a channel formation region of a transistor is shown in FIG. 1A. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably within range 11 in the ternary diagram shown in FIG. 1A. Range 11 is within a polygon formed by connecting coordinate points A (1:0:0), B (2:1:0), C (14:7:1), D (7:2:2), E (14:4:21), F (2:0:3), and A in this order with straight lines. Note that range 11 includes each of the coordinate points and each of the sides. Using a metal oxide having a composition within range 11 for the channel formation region can result in a transistor with high reliability and high field-effect mobility.

[0059] When the element M contains a plurality of elements, the ratio of the total number of atoms of these elements is used as the atomic ratio of the element M. For example, when the element M contains gallium and tin, the ratio of the total number of atoms of gallium and tin is used as the atomic ratio of the element M.

[0060] Here, coordinate point B (2:1:0) is the intersection of line L1, which is a set of points that satisfy (In+M):Zn=1:0, and line L2, which is a set of points that satisfy In:M=2:1. Coordinate point C (14:7:1) is the intersection of the aforementioned line L2 and line L3, which is a set of points that satisfy In:(M+Zn)=7:4. Coordinate point C is also the intersection of the aforementioned line L2 and line L4, which is a set of points that satisfy In:Zn=14:1. Coordinate point D (7:2:2) is the intersection of the aforementioned line L3 and line L5, which is a set of points that satisfy In:Zn=7:2. Coordinate point D is also the intersection of the aforementioned line L3 and line L6, which is a set of points that satisfy In:M=7:2. Coordinate point E (14:4:21) is the intersection of the aforementioned line L6 and line L7, which is a set of points that satisfy In:Zn=2:3. Coordinate point F(2:0:3) is the intersection of the above-mentioned line L7 and line L8, which is a set of points that satisfy (In+Zn):M=1:0.

[0061] In this specification, the ratio of the number of atoms of indium, element M, and zinc may be expressed as In:M:Zn. Also, the ratio of the total number of atoms of indium and element M to the number of atoms of zinc may be expressed as (In+M):Zn. The same applies to other combinations of elements.

[0062] Side AB is on the aforementioned line L1, side BC is on the aforementioned line L2, side CD is on the aforementioned line L3, side DE is on the aforementioned line L6, side EF is on the aforementioned line L7, and side FA is on the aforementioned line L8. In other words, range 11 can be said to be inside the polygon surrounded by lines L1, L2, L3, L6, L7, and L8.

[0063] As shown in range 11, the composition of the metal oxide preferably satisfies line L2, In:M=2:1, or has an indium content higher than In:M=2:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 2 or greater. Metal oxides with a high indium content have high carrier mobility (electron mobility), and transistors using metal oxides with a high indium content in their channel formation region have high field-effect mobility and can pass large currents.

[0064] However, a high content of element M can increase defect levels, resulting in larger threshold voltage variations during reliability testing. One indicator for evaluating transistor reliability is the GBT (Gate Bias Temperature) stress test, in which an electric field is applied to the gate. Among these tests, a test in which a positive potential is applied to the gate relative to the source and drain potentials and the device is held at high temperatures is called a PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential is applied to the gate and the device is held at high temperatures is called an NBTS (Negative Bias Temperature Stress) test. Furthermore, the PBTS and NBTS tests conducted under illumination with light such as white LED light are called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0065] In particular, in n-type transistors using metal oxides, a positive potential is applied to the gate when the transistor is in the on state (current is flowing), so the amount of variation in threshold voltage in the PBTS test is one of the important items to pay attention to as an index of transistor reliability.

[0066] Here, by using a metal oxide that does not contain element M or has a low content of element M, it is possible to reduce the amount of variation in threshold voltage in the PBTS test. Furthermore, when element M is contained, it is preferable that the content of element M is lower than the content of indium in the metal oxide composition. Furthermore, it is preferable that the ratio In / M of the number of indium atoms to the number of atoms of element M is 2 or more. This makes it possible to realize a highly reliable transistor.

[0067] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. However, the generation of these defect levels can be suppressed by reducing the content of element M in the part of the semiconductor layer that contacts the gate insulating layer.

[0068] The following are some possible reasons why PBTS degradation can be suppressed by eliminating element M or by reducing the content of element M. Element M contained in the semiconductor layer has the property of attracting oxygen more easily than other metal elements (e.g., indium and zinc). Therefore, it is presumed that element M combines with excess oxygen in the insulating layer at the interface between a metal oxide film containing a large amount of element M and an insulating layer containing oxide, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in the threshold voltage.

[0069] Therefore, by using a metal oxide in which the ratio of the number of indium atoms to the number of atoms of element M, In / M, is 2 or more for the channel formation region, the generation of defect levels can be suppressed, resulting in a transistor with high reliability and high field-effect mobility.

[0070] As shown in range 11, the composition of the metal oxide preferably satisfies line L3, In:(M+Zn)=7:4, or has an indium content higher than In:(M+Zn)=7:4. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc, In / (M+Zn), is preferably 7 / 4 or higher. Metal oxides with a high indium content have high carrier mobility (electron mobility), and transistors using metal oxides with a high indium content in their channel formation region have high field-effect mobility and can pass large currents. Therefore, by using a metal oxide having an atomic ratio within the above range in the channel formation region, a transistor with high field-effect mobility can be obtained.

[0071] As shown in range 11, the composition of the metal oxide preferably satisfies line L6, In:M=7:2, or has an indium content higher than In:M=7:2. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 7 / 2 or greater. By using a metal oxide having an atomic ratio within the aforementioned range for the channel formation region, it is possible to suppress the generation of defect levels, resulting in a transistor with high reliability and high field-effect mobility.

[0072] As shown in range 11, the composition of the metal oxide preferably satisfies line L7, In:Zn=2:3, or has a higher indium content than In:Zn=2:3. That is, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 2 / 3 or more. A high zinc content may cause the metal oxide to become polycrystalline. Since the grain boundaries of polycrystalline metal oxides become defect levels and act as carrier traps or carrier generation sources, transistors using polycrystalline metal oxides may exhibit significant fluctuations in electrical characteristics and reduced reliability. Therefore, by setting the atomic ratio within the above range, the metal oxide can be prevented from becoming polycrystalline. Furthermore, by using such metal oxides in the channel formation region, highly reliable transistors can be obtained.

[0073] As the metal oxide, an In-M-Zn oxide having a composition falling within range 11 can be used. As the In-M-Zn oxide, for example, In:M:Zn=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or compounds close to these can be suitably used. Indium oxide can also be used as the metal oxide. In-M oxide can also be used as the metal oxide. As the In-M oxide, for example, In:M=2:1, In:M=7:2, In:M=5:1, In:M=7:1, In:M=10:1, or a similar ratio can be suitably used. In-Zn oxide can also be used as the metal oxide. As the In-Zn oxide, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, In:Zn=14:1, or a similar ratio can be suitably used.

[0074] Examples of analytical techniques for the composition of metal oxides include energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), and inductively coupled plasma-atomic emission spectroscopy (ICP-AES). Note that for elements with low content, the actual content may differ from the content obtained by analysis due to analytical inaccuracies. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0075] When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target. Here, it is preferable that the target used is polycrystalline.

[0076] [Metal oxide composition 2] The metal oxide preferably contains one or more of element M and zinc, indium, and oxygen. FIG. 1B shows the composition of a metal oxide suitable for use in a transistor channel formation region. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably within range 13 in the ternary diagram shown in FIG. 1B. Range 13 is within a polygon formed by connecting coordinate points G (7:1:0), B (2:1:0), C (14:7:1), D (7:2:2), E (14:4:21), F (2:0:3), H (7:0:1), and G in this order with straight lines. Range 13 also includes each of the coordinate points and each of the sides. Using a metal oxide having a composition within range 13 for the channel formation region can result in a transistor with high reliability and high field-effect mobility.

[0077] Here, coordinate point G (7:1:0) is the intersection of line L1, which is a set of points that satisfy (In+M):Zn=1:0, and line L9, which is a set of points that satisfy In:(M+Zn)=7:1. Coordinate point H (7:0:1) is the intersection of line L9 and line L8, which is a set of points that satisfy (In+Zn):M=1:0. The above descriptions can be referenced for coordinate points B to F, so detailed descriptions will be omitted.

[0078] Side GB is on the aforementioned line L1, side BC is on the aforementioned line L2, side CD is on the aforementioned line L3, side DE is on the aforementioned line L6, side EF is on the aforementioned line L7, side FH is on the aforementioned line L8, and side HG is on the aforementioned line L9. In other words, range 13 can be said to be inside the polygon surrounded by lines L1, L2, L3, L6, L7, L8, and L9.

[0079] As shown in range 13, the composition of the metal oxide preferably satisfies line L9, In:(M+Zn)=7:1, or has an In content lower than In:(M+Zn)=7:1. That is, the ratio of the number of indium atoms to the total number of atoms of elements M and zinc, In / (M+Zn), is preferably 7 or less. A high indium content may result in the metal oxide having a bixbite-type crystal structure. Alternatively, the metal oxide may have a crystal structure in which a bixbite-type crystal structure and a layered crystal structure coexist. When multiple crystal structures coexist, grain boundaries may be formed between the different crystal structures. Because grain boundaries act as defect levels and carrier traps or carrier generation sources, transistors using metal oxides with grain boundaries may exhibit significant fluctuations in electrical characteristics and reduced reliability. Therefore, by setting the atomic ratio within the aforementioned range, the metal oxide is prevented from having a bixbite-type crystal structure and is more likely to have a layered crystal structure. Furthermore, using such a metal oxide in a channel formation region can provide a highly reliable transistor.

[0080] As shown in range 13, the composition of the metal oxide preferably satisfies line L2, In:M=2:1, or has an indium content higher than In:M=2:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 2 or greater. By using a metal oxide having an atomic ratio within the aforementioned range for the channel formation region, it is possible to suppress the generation of defect levels, resulting in a transistor with high reliability and high field-effect mobility.

[0081] As shown in range 13, the composition of the metal oxide preferably satisfies line L3, In:(M+Zn)=7:4, or has an indium content higher than In:(M+Zn)=7:4. In other words, the ratio of the number of indium atoms to the total number of atoms of element M and zinc, In / (M+Zn), is preferably 7 / 4 or greater. By using a metal oxide having an atomic ratio within the aforementioned range for the channel formation region, a transistor with high field-effect mobility can be obtained.

[0082] As shown in range 13, the composition of the metal oxide preferably satisfies line L6, In:M=7:2, or has an indium content higher than In:M=7:2. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 7 / 2 or higher. By using a metal oxide having an atomic ratio within the aforementioned range for the channel formation region, it is possible to suppress the generation of defect levels, resulting in a transistor with high reliability and high field-effect mobility.

[0083] As shown in range 13, the composition of the metal oxide preferably satisfies line L7, In:Zn=2:3, or has a higher indium content than In:Zn=2:3. In other words, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 2 / 3 or more. By setting the atomic ratio within the above range, the metal oxide can be prevented from becoming polycrystalline. Furthermore, by using this metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0084] As the metal oxide, an In-M-Zn oxide having a composition falling within range 13 can be used. As the In-M-Zn oxide, for example, In:M:Zn=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or compounds close to these can be suitably used. Furthermore, In-M oxides can be used as the metal oxide. Examples of In-M oxides that can be suitably used include In:M=2:1, In:M=7:2, In:M=5:1, In:M=7:1, and oxides in the vicinity of these ratios. Examples of In-Zn oxides that can be suitably used include In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, and oxides in the vicinity of these ratios.

[0085] [Metal oxide composition 3] The metal oxide preferably contains indium, zinc, and oxygen. The metal oxide may further contain element M. FIG. 2A shows the composition of a metal oxide that can be suitably used for the channel formation region of a transistor. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably within range 15 in the ternary diagram shown in FIG. 2A. Range 15 is within a polygon formed by connecting coordinate points I (44:11:10), J (4:1:6), F (2:0:3), K (11:0:2), and I, in this order, with straight lines. Range 15 also includes each of the coordinate points and each of the sides. Using a metal oxide having a composition within range 15 for the channel formation region can result in a transistor with high reliability and high field-effect mobility.

[0086] Here, coordinate point I (44:11:10) is the intersection of line L10, which is a set of points that satisfy In:M = 4:1, and line L11, which is a set of points that satisfy (In + M):Zn = 11:2. Coordinate point J (4:1:6) is the intersection of the aforementioned line L7 and line L10. Coordinate point K (11:0:2) is the intersection of the aforementioned line L11 and line L8. As the above description can be referred to for coordinate point F, detailed description will be omitted.

[0087] Side IJ is on the aforementioned line L10, side JF is on the aforementioned line L7, side FK is on the aforementioned line L8, and side KI is on the aforementioned line L11. In other words, range 15 can be said to be inside the polygon surrounded by lines L10, L7, L8, and L11.

[0088] As shown in range 15, the composition of the metal oxide preferably satisfies line L10, In:M=4:1, or has an In content higher than In:M=4:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 4 or greater. By using a metal oxide having an atomic ratio within the aforementioned range for the channel formation region, it is possible to suppress the generation of defect levels, resulting in a transistor with high reliability and high field-effect mobility.

[0089] As shown in range 15, the composition of the metal oxide preferably satisfies line L7, In:Zn=2:3, or has a higher indium content than In:Zn=2:3. In other words, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 2 / 3 or more. By setting the atomic ratio within the above range, the metal oxide can be prevented from becoming polycrystalline. Furthermore, by using this metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0090] As shown in range 15, the composition of the metal oxide preferably satisfies line L11, (In+M):Zn=11:2, or has a zinc content higher than (In+M):Zn=11:2. In other words, the ratio of the total number of indium and element M atoms to the number of zinc atoms, (In+M) / Zn, is preferably 11 / 2 or less. Due to the presence of zinc, metal oxides tend to have a layered crystal structure. Furthermore, the higher the zinc content, the more crystalline the metal oxide.

[0091] As the metal oxide, an In-M-Zn oxide having a composition falling within range 15 can be used. Examples of In-M-Zn oxides that can be suitably used include In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or compositions close to these. Furthermore, In-Zn oxide can be used as the metal oxide. As the In-Zn oxide, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, or a combination close to these can be suitably used.

[0092] The metal oxide preferably has a composition within the aforementioned range and is a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a nanocrystalline oxide semiconductor (nc-OS), or a cloud-aligned composite oxide semiconductor (CAC-OS).

[0093] Here, CAC-OS and CAAC-OS, which are metal oxides that can be used in transistors, will be described.

[0094] [Constitution of Metal Oxide] CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole functions as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0095] CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0096] In the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0097] A CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, a CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in a channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0098] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0099] [Metal oxide structure] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nc-OS, amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0100] When focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of the crystal structure of oxide semiconductors will be explained using FIG. 5A. FIG. 5A is a diagram explaining the classification of the crystal structure of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0101] As shown in Figure 5A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes c-axis aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). Crystalline excludes single crystal and polycrystal, which will be described later. Crystal includes single crystal and polycrystal.

[0102] The structure within the bold frame in Figure 5A belongs to the new crystalline phase. This structure is in the boundary region between amorphous and crystalline. In other words, this structure is completely different from the energetically unstable amorphous and crystalline phases.

[0103] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) patterns. Figures 5B and 5C show the XRD spectra of silica glass and IGZO (also called crystalline IGZO), which has a crystal structure classified as Crystalline. Figure 5B shows the XRD spectrum of silica glass, and Figure 5C shows the XRD spectrum of crystalline IGZO. The composition of the crystalline IGZO shown in Figure 5C is In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the crystalline IGZO shown in Figure 5C is 500 nm.

[0104] As shown by the arrows in Figure 5B, the peaks in the XRD spectrum of silica glass are nearly symmetrical. On the other hand, as shown by the arrows in Figure 5C, the peaks in the XRD spectrum of crystalline IGZO are asymmetrical. The asymmetrical peaks in the XRD spectrum clearly indicate the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetrical, it cannot be said to be amorphous. Note that Figure 5C clearly shows nanocrystals at or near 2θ = 31°. It is presumed that the asymmetry in the peaks in the XRD spectrum is due to these nanocrystals.

[0105] Specifically, as shown in Figure 5C, crystalline IGZO has a peak at or near 2θ = 34° in the XRD spectrum. Microcrystals have a peak at or near 2θ = 31°. When an oxide semiconductor film is evaluated using an X-ray diffraction pattern, the spectrum width at lower angles than the peak at or near 2θ = 34° is broader, as shown in Figure 5C. This suggests that the oxide semiconductor film contains microcrystals with a peak at or near 2θ = 31°.

[0106] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0107] Nanocrystals are basically hexagonal, but not necessarily regular hexagonal, and may have non-regular hexagonal shapes. The strain can also result in pentagonal, heptagonal, or other lattice arrangements. In CAAC-OS, no clear grain boundaries are observed even near the strain. This indicates that the formation of grain boundaries is suppressed by the strained lattice arrangement. This is thought to be because the CAAC-OS can tolerate strain due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by the substitution of metal elements.

[0108] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially reducing the on-state current or field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0109] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, the layer can also be referred to as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, the layer can also be referred to as an (In,M) layer.

[0110] CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, because no clear grain boundaries are observed in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. Furthermore, because the crystallinity of oxide semiconductors can be reduced by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for OS transistors can increase the flexibility of the manufacturing process.

[0111] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0112] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

[0113] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0114] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0115] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0116] An oxide semiconductor having a low carrier concentration is preferably used for a transistor. In order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic or substantially highly pure intrinsic.

[0117] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0118] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0119] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0120] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0121] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0122] When an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is preferably reduced to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0123] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor tends to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, it is preferable that the nitrogen content in the oxide semiconductor be reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0124] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0125] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0126] [Metal oxide composition 4] The metal oxide preferably contains indium, zinc, and oxygen. The metal oxide may further contain element M. FIG. 2B shows the composition of a metal oxide suitable for use in a channel formation region of a transistor. The atomic ratio of indium, element M, and zinc in the metal oxide is preferably within range 17 in the ternary diagram shown in FIG. 2B. Range 17 is within a polygon formed by connecting coordinate points I (44:11:10), L (4:1:4), M (1:0:1), K (11:0:2), and I, in this order, with straight lines. Range 17 also includes each of the coordinate points and each of the sides. Using a metal oxide having a composition within range 17 for the channel formation region can result in a transistor with high reliability and high field-effect mobility.

[0127] Here, coordinate point L (4:1:4) is the intersection of the aforementioned line L10 and line L12, which is a set of points that satisfy In:Zn = 1:1. Coordinate point M (1:0:1) is the intersection of the aforementioned line L12 and line L8. Since the above descriptions can be referred to for coordinate points I and K, detailed explanations will be omitted.

[0128] Side IL is on the aforementioned line L10, side LM is on the aforementioned line L12, side MK is on the aforementioned line L8, and side KI is on the aforementioned line L11. In other words, it can be said that range 17 is inside the polygon surrounded by lines L10, L12, L8, and L11.

[0129] As shown in range 17, the composition of the metal oxide preferably satisfies line L10, In:M=4:1, or has an In content higher than In:M=4:1. In other words, the ratio In / M of the number of indium atoms to the number of atoms of element M is preferably 4 or greater. By using a metal oxide having an atomic ratio within the aforementioned range for the channel formation region, it is possible to suppress the generation of defect levels, resulting in a transistor with high reliability and high field-effect mobility.

[0130] As shown in range 17, the composition of the metal oxide preferably satisfies line L12, In:Zn=1:1, or has a higher indium content than In:Zn=1:1. In other words, the ratio of the number of indium atoms to the number of zinc atoms, In / Zn, is preferably 1 or greater. By setting the atomic ratio within the aforementioned range, the metal oxide can be prevented from becoming polycrystalline. Since the metal oxide is less likely to become polycrystalline, the margin for the metal oxide formation conditions can be expanded. Furthermore, by using this metal oxide in the channel formation region, a highly reliable transistor can be obtained.

[0131] As shown in range 17, the composition of the metal oxide preferably satisfies line L11, where (In+M):Zn=11:2, or has a zinc content higher than (In+M):Zn=11:2. In other words, the ratio of the total number of indium and element M atoms to the number of zinc atoms, (In+M) / Zn, is preferably 11 / 2 or less. Metal oxides having an atomic number within the aforementioned range have high crystallinity. Furthermore, by using such metal oxides in the channel formation region, highly reliable transistors can be obtained.

[0132] As the metal oxide, an In-M-Zn oxide having a composition falling within range 17 can be used. Examples of In-M-Zn oxides that can be suitably used include In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, and oxides in the vicinity thereof. Furthermore, as the metal oxide, an In-Zn oxide can be used. As the In-Zn oxide, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, or a combination close to these can be suitably used.

[0133] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0134] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0135] (Embodiment 2) This embodiment will describe a structural example of a semiconductor device to which the metal oxide described in Embodiment 1 is applied. Hereinafter, a transistor will be described as an example.

[0136] <Configuration example 1> [Configuration Example 1-1] FIG. 6A is a schematic cross-sectional view of a transistor 10 according to one embodiment of the present invention taken along the channel length direction.

[0137] The transistor 10 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. A region of the semiconductor layer 108 that overlaps with the conductive layer 104 functions as a channel formation region. The transistor 10 is a so-called bottom-gate transistor that has a gate electrode below the semiconductor layer 108.

[0138] An insulating layer 114, an insulating layer 116, and an insulating layer 118 are provided to cover the conductive layer 112a, the conductive layer 112b, and the semiconductor layer 108. The insulating layer 114, the insulating layer 116, and the insulating layer 118 each function as a protective layer.

[0139] It is preferable to use a conductive film containing a metal or an alloy as the conductive layer 104 because electrical resistance can be reduced. In particular, it is preferable to use a conductive material containing copper as the conductive layer 104. Note that an oxide film may also be used for the conductive layer 104.

[0140] An oxide film is preferably used as the insulating layer 106. In particular, an oxide film is preferably used in a portion in contact with the semiconductor layer 108.

[0141] The insulating layer 106 preferably has a high withstand voltage. When the insulating layer 106 has a high withstand voltage, the transistor can have high reliability.

[0142] It is preferable that the insulating layer 106 has low stress. When the insulating layer 106 has low stress, problems during the process due to stress, such as warpage of the substrate, can be suppressed.

[0143] The insulating layer 106 preferably functions as a barrier film that suppresses diffusion of impurities such as water, hydrogen, and sodium from a member (e.g., a substrate) on the surface where the insulating layer 106 is to be formed to the transistor 10. The insulating layer 106 also preferably functions as a barrier film that suppresses diffusion of components of the conductive layer 104 to the transistor 10. The insulating layer 106 functions as a barrier film that suppresses diffusion of impurities and the like, thereby enabling the transistor to exhibit favorable electrical characteristics and high reliability.

[0144] Furthermore, it is preferable that the insulating layer 106 releases little impurities such as water and hydrogen from itself. When the insulating layer 106 releases little impurities, the impurities are prevented from diffusing into the transistor 10, and the transistor can have good electrical characteristics and high reliability.

[0145] Furthermore, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing from above the insulating layer 106 to the conductive layer 104, thereby suppressing oxidation of the conductive layer 104. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0146] 6A shows a configuration in which the insulating layer 106 has a stacked structure of an insulating layer 106a and an insulating layer 106b on the insulating layer 106a. For example, a nitride film can be used for the insulating layer 106a located on the surface to be formed of the insulating layer 106, and an oxide film can be used for the insulating layer 106b in contact with the semiconductor layer 108.

[0147] The insulating layer 106a preferably has a high withstand voltage. When the insulating layer 106 has a high withstand voltage, the transistor can have high reliability.

[0148] The insulating layer 106a preferably has a low stress, which can prevent problems during the process caused by stress, such as warping of the substrate.

[0149] The insulating layer 106a preferably functions as a barrier film that suppresses diffusion of impurities such as water, hydrogen, and sodium from a member (e.g., a substrate) on the surface where the insulating layer 106 is to be formed to the transistor 10. The insulating layer 106 also preferably functions as a barrier film that suppresses diffusion of components of the conductive layer 104 to the transistor 10. The insulating layer 106 has a function of suppressing diffusion of impurities and the like, thereby enabling the transistor to exhibit favorable electrical characteristics and high reliability.

[0150] Furthermore, it is preferable that the insulating layer 106a releases little impurities such as water and hydrogen from itself. When the insulating layer 106a releases little impurities, the impurities are prevented from diffusing into the transistor 10, and the transistor can have good electrical characteristics and high reliability.

[0151] Furthermore, the insulating layer 106a preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106a has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing from above the insulating layer 106a to the conductive layer 104, thereby suppressing oxidation of the conductive layer 104. As a result, a transistor with favorable electrical characteristics and high reliability can be obtained.

[0152] The insulating layer 106a can be, for example, an oxide film such as aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, or yttrium oxynitride, or a nitride film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide. Silicon nitride is particularly suitable for use as the insulating layer 106a.

[0153] The insulating layer 106b has a region in contact with the channel formation region of the semiconductor layer 108. The insulating layer 106b preferably has a low defect density. Furthermore, the insulating layer 106b preferably releases little hydrogen-containing impurities such as water and hydrogen from itself. An oxide film such as silicon oxide or silicon oxynitride can be preferably used as the insulating layer 106b.

[0154] As shown in FIG. 6A, by forming the insulating layer 106 with a stacked structure, a transistor can be provided that exhibits favorable electrical characteristics and is highly reliable.

[0155] A nitride film may be formed as the insulating layer 106a, and then oxygen may be added to the upper part of the insulating layer 106a to form a region containing oxygen, which may serve as the insulating layer 106b. Examples of treatment for adding oxygen include heat treatment or plasma treatment in an atmosphere containing oxygen, and ion doping treatment.

[0156] In this specification and the like, an oxynitride refers to a substance whose composition contains more oxygen than nitrogen, and an oxynitride is included in the category of oxides. A nitride oxide refers to a substance whose composition contains more nitrogen than oxygen, and a nitride oxide is included in the category of nitrides.

[0157] 6A illustrates the insulating layer 106 having a two-layer structure of the insulating layer 106a and the insulating layer 106b; however, one embodiment of the present invention is not limited to this. The insulating layer 106 may have a single-layer structure or a stacked structure of three or more layers. Each of the insulating layer 106a and the insulating layer 106b may have a stacked structure of two or more layers.

[0158] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. For the semiconductor layer 108, a metal oxide having the composition described in Embodiment 1 is preferably used. By using the metal oxide for a channel formation region, a transistor with high reliability and high field-effect mobility can be obtained.

[0159] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, a metal oxide film having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a microcrystalline (nc) structure, or the like, which will be described later, can be used. By using a crystalline metal oxide film for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0160] The higher the crystallinity of the semiconductor layer 108, the more the density of defect states in the film can be reduced. On the other hand, by using a metal oxide film with low crystallinity, a transistor capable of passing a large current can be realized.

[0161] When a metal oxide film is formed by sputtering, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the metal oxide film that can be formed.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during formation (also referred to as the oxygen flow rate ratio), the higher the crystallinity of the metal oxide film that can be formed.

[0162] The semiconductor layer 108 preferably has a stacked-layer structure of a semiconductor layer 108a and a semiconductor layer 108b over the semiconductor layer 108a. The semiconductor layer 108a and the semiconductor layer 108b each preferably contain a metal oxide. Note that the boundary (interface) between the semiconductor layer 108a and the semiconductor layer 108b may not be clearly visible. Therefore, in the drawings illustrating one embodiment of the present invention, the boundary is indicated by a dashed line. The semiconductor layer 108a and the semiconductor layer 108b are preferably formed using the metal oxide film described in Embodiment 1.

[0163] The semiconductor layer 108b located on the back channel side preferably has a region with higher crystallinity than the semiconductor layer 108a located on the conductive layer 104 side. When the semiconductor layer 108b has a region with higher crystallinity, part of the semiconductor layer 108 can be prevented from being etched and lost when the conductive layers 112a and 112b are formed. Furthermore, the semiconductor layer 108 can be prevented from being damaged when the surface of the semiconductor layer 108 is subjected to cleaning treatment.

[0164] The semiconductor layers 108a and 108b can be formed differently by, for example, varying the formation conditions, for example, by varying the flow rate of oxygen gas in the deposition gas for the semiconductor layers 108a and 108b.

[0165] In this case, as a condition for forming the semiconductor layer 108a, the ratio of the oxygen gas flow rate to the total gas flow rate (also referred to as the oxygen flow rate ratio or the oxygen partial pressure) is preferably 0% or more and less than 50%, more preferably 5% or more and 30% or less, and further preferably 5% or more and 20% or less. By setting the oxygen flow rate as described above, the crystallinity of the semiconductor layer 108a can be reduced.

[0166] On the other hand, as a condition for forming the semiconductor layer 108b, the oxygen flow rate ratio is preferably 50% to 100%, more preferably 60% to 100%, further preferably 70% to 100%, and further preferably 80% to 100%. By setting the oxygen flow rate ratio as described above, the crystallinity of the semiconductor layer 108b can be increased.

[0167] When the semiconductor layer 108 has a stacked structure, it is preferable to form the metal oxide films successively in the same treatment chamber using the same sputtering target, since this can improve the interface. In particular, the conditions for forming each metal oxide film, such as pressure, temperature, and power, may be different from each other, but it is preferable to keep the conditions other than the oxygen flow rate the same, since this can shorten the time required for the formation process. Furthermore, the semiconductor layer 108 may have a stacked structure of metal oxide films with different compositions. When metal oxide films with different compositions are stacked, it is preferable to form them successively without exposing them to the air.

[0168] The substrate temperature during the formation of the semiconductor layer 108 is preferably from room temperature (25°C) to 200°C, more preferably from room temperature to 130°C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used. When the semiconductor layer 108 has a stacked structure, productivity can be improved by setting the substrate temperature of the semiconductor layer 108a and the semiconductor layer 108b to the same temperature. Furthermore, when the substrate temperatures of the semiconductor layer 108a and the semiconductor layer 108b are different, it is preferable to set the substrate temperature during the formation of the semiconductor layer 108b higher than the substrate temperature during the formation of the semiconductor layer 108a. By increasing the substrate temperature during the formation of the semiconductor layer 108b, the crystallinity of the semiconductor layer 108b can be improved compared to the crystallinity of the semiconductor layer 108a. Note that in this specification and the like, room temperature includes a temperature when the substrate is not heated.

[0169] For example, it is preferable to use a cloud-aligned composite oxide semiconductor (CAC-OS) film for the semiconductor layer 108a and a c-axis-aligned crystalline oxide semiconductor (CAAC-OS) film for the semiconductor layer 108b.

[0170] The crystallinity of the semiconductor layer 108a and the semiconductor layer 108b can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), electron diffraction (ED), or the like.

[0171] The thickness of the semiconductor layer 108a is preferably 1 nm to 50 nm, more preferably 5 nm to 30 nm, and even more preferably 5 nm to 20 nm. The thickness of the semiconductor layer 108b is preferably 1 nm to 50 nm, more preferably 5 nm to 30 nm, and even more preferably 5 nm to 20 nm.

[0172] Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0173] In particular, when the semiconductor layer 108 contains an oxide semiconductor, hydrogen contained in the oxide semiconductor reacts with oxygen that bonds with metal atoms to form water, and oxygen vacancies (V O Furthermore, defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V O Hydrogen atoms (H) function as donors and may generate electrons as carriers. Some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0174] V O H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as the "donor concentration."

[0175] From the above, when an oxide semiconductor is used for the semiconductor layer 108, V in the semiconductor layer 108 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxygen addition treatment). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0176] When an oxide semiconductor is used for the semiconductor layer 108, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited. -9 cm -3 It can be said that:

[0177] The insulating layer 114 and the insulating layer 116 function as protective films for the transistor 10. The insulating layer 114 and the insulating layer 116 also function to supply oxygen to the semiconductor layer 108.

[0178] By supplying oxygen from the insulating layer 114 and the insulating layer 116 to the semiconductor layer 108, particularly to the back channel side of the semiconductor layer 108, the V O and V O H can be reduced, and a highly reliable transistor can be realized. Other treatments for supplying oxygen to the semiconductor layer 108 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0179] The conductive layers 112a and 112b are preferably formed using a conductive film containing a metal or an alloy because the electrical resistance can be reduced. In particular, it is preferable to use a conductive material containing copper for the conductive layers 112a and 112b. Note that an oxide film may be used for the conductive layers 112a and 112b.

[0180] FIG. 6A shows an example in which the conductive layer 112a and the conductive layer 112b each have a layered structure in which a conductive layer 113a, a conductive layer 113b, and a conductive layer 113c are stacked in this order from the formation surface side.

[0181] The conductive layer 113b is preferably made of a low-resistance conductive material. The conductive layers 113a and 113c can each be made of a conductive material different from that of the conductive layer 113b. By sandwiching the conductive layer 113b between the conductive layers 113a and 113c, oxidation of the surface of the conductive layer 113b and diffusion of components of the conductive layer 113b to surrounding layers can be suppressed. With this structure, the conductive layers 112a and 112b can have extremely low resistance.

[0182] Of the conductive layers 112a and 112b, the uppermost conductive layer 113c preferably contains a material that is less likely to bond with oxygen than a conductive film containing copper, aluminum, or the like, or a material whose conductivity is less likely to be lost even when oxidized. The conductive layer 113a in contact with the semiconductor layer 108 is preferably made of a material through which oxygen in the semiconductor layer 108 does not easily diffuse. The uppermost conductive layer 113c and the conductive layer 113a in contact with the semiconductor layer can be made of a conductive material containing, for example, titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, ruthenium, or the like. The conductive layer 113a and the conductive layer 113c can be made of the same conductive material. Alternatively, the conductive layer 113a and the conductive layer 113c may be made of different conductive materials.

[0183] Cleaning treatment is preferably performed before forming the insulating layer 114 over the semiconductor layer 108. The cleaning treatment can remove water, hydrogen, organic components, and the like adsorbed on the surface of the semiconductor layer 108. Examples of the cleaning method include wet cleaning using a cleaning solution, heat treatment, and cleaning by plasma treatment using plasma. The above cleaning methods may also be combined as appropriate.

[0184] The heat treatment is preferably performed in an atmosphere containing an oxidizing gas or in a reduced pressure atmosphere. An oxidizing gas refers to a gas having oxidizing power. Examples of the oxidizing gas that can be used include oxygen-containing gases such as oxygen (O), ozone (O), nitrous oxide (NO), nitric oxide (NO), and nitrogen dioxide (NO). The heat treatment can be performed, for example, in an oxygen gas atmosphere at a temperature of 70°C or higher and 200°C or lower.

[0185] The plasma treatment is preferably performed in an atmosphere containing an oxidizing gas. By performing the plasma treatment in an atmosphere containing an oxidizing gas, organic substances on the surface of the semiconductor layer 108 can be suitably removed. Furthermore, after the plasma treatment, the insulating layer 114 is preferably formed successively without exposing the surface of the semiconductor layer 108 to the air. Forming the insulating layer 114 successively after the plasma treatment can prevent impurities from adhering to the interface between the semiconductor layer 108 and the insulating layer 114.

[0186] Note that the cleaning treatment described above may oxidize the conductive layers 112a and 112b, increasing their resistance and adversely affecting the electrical characteristics and reliability of the transistor. Therefore, it is particularly preferable to perform plasma treatment using a mixed gas containing an oxidizing gas and a reducing gas as the cleaning treatment. The above-mentioned gases can be used as the oxidizing gas. The reducing gas refers to a gas having reducing power. Examples of the reducing gas include a gas containing hydrogen, such as ammonia (NH3) or hydrogen (H2), or carbon monoxide (CO). For example, performing plasma treatment in an atmosphere of a mixed gas containing nitrous oxide, which is an oxidizing gas, and ammonia, which is a reducing gas, can prevent the conductive layers 112a and 112b from being oxidized and effectively remove water, hydrogen, organic components, and the like adsorbed on the surface of the semiconductor layer 108.

[0187] In the plasma treatment, the ratio of the flow rate of the reducing gas to the flow rate of the oxidizing gas is preferably 0.005 to 1, more preferably 0.01 to 0.9, even more preferably 0.02 to 0.8, even more preferably 0.03 to 0.6, and even more preferably 0.03 to 0.5.

[0188] As a mixed gas used in the plasma treatment, a mixed gas containing a rare gas such as argon in addition to an oxidizing gas and a reducing gas may be used.

[0189] The insulating layer 114 in contact with the semiconductor layer 108 is heated to generate nitrogen oxides (NO x It is preferable that the emission of nitrogen oxides (x is greater than 0 and equal to or less than 2) is low. Examples of nitrogen oxides include NO2 and NO.

[0190] Nitrogen oxide forms a level in the insulating layer 114 and the like. The level is located within the energy gap of the semiconductor layer 108. Therefore, when nitrogen oxide diffuses to the interface between the insulating layer 114 and the semiconductor layer 108, the level may trap electrons on the insulating layer 114 side. As a result, the trapped electrons remain near the interface between the insulating layer 114 and the semiconductor layer 108, causing the threshold voltage of the transistor to shift in the positive direction.

[0191] Here, it is preferable that the insulating layer 114 releases a large amount of ammonia. When heat is applied, nitrogen oxide reacts with ammonia and oxygen and decomposes. When heat is applied, the nitrogen oxide contained in the insulating layer 114 reacts with ammonia contained in the insulating layer 114 and the insulating layer 116, and therefore the amount of nitrogen oxide contained in the insulating layer 114 is reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating layer 114 and the semiconductor layer 108.

[0192] By using a film that releases a lot of ammonia and little nitrogen oxide as the insulating layer 114, fluctuations in the threshold voltage of the transistor can be suppressed, and fluctuations in the electrical characteristics of the transistor can be reduced.

[0193] The insulating layer 114 is preferably formed by using an oxide film such as a silicon oxide film or a silicon oxynitride film using a plasma enhanced chemical vapor deposition (PECVD) apparatus (or simply referred to as a plasma CVD) apparatus. In this case, a mixed gas containing a silicon-containing deposition gas, an oxidizing gas, and ammonia gas is preferably used as a source gas. By forming the insulating layer 114 using a mixed gas containing ammonia gas, the insulating layer 114 can emit a large amount of ammonia. Examples of the silicon-containing deposition gas that can be used include silane, disilane, trisilane, and silane fluoride. The above-mentioned gases can be used as the oxidizing gas.

[0194] The ratio of each gas in the mixed gas can be controlled by controlling the flow rate of the gas supplied to the processing chamber of the plasma enhanced chemical vapor deposition apparatus. The ratio of each gas in the mixed gas can be expressed, for example, by volume ratio, partial pressure ratio, or weight ratio. Here, the flow rate ratio of the gases supplied to the processing chamber roughly corresponds to the volume ratio and partial pressure ratio of the gases.

[0195] When plasma treatment is performed as a cleaning treatment before the formation of the insulating layer 114, the same gas can be used for the plasma treatment and for forming the insulating layer 114. A mixed gas containing a first oxidizing gas and a reducing gas is used for the plasma treatment, and a first deposition gas mixed gas containing a second oxidizing gas, ammonia gas, and silicon is used for forming the insulating layer 114. Here, by using the same type of gas for the first oxidizing gas and the second oxidizing gas and using ammonia gas as the reducing gas, the oxidizing gas and ammonia gas can be used in common for the plasma treatment and for forming the insulating layer 114. Using a common gas can reduce the number of types of gases used for manufacturing a transistor.

[0196] An example will be described in which a plasma enhanced chemical vapor deposition apparatus is used to perform plasma processing and form the insulating layer 114. The insulating layer 114 is made of silicon oxynitride.

[0197] In the plasma treatment, a mixed gas containing nitrous oxide (NO) as an oxidizing gas and ammonia as a reducing gas is used, and in the formation of the insulating layer 114, a mixed gas containing monosilane as a deposition gas, nitrous oxide (NO) as an oxidizing gas, and ammonia can be used. Here, dinitrogen monoxide (NO) and ammonia can be commonly used in both the plasma treatment and the formation of the insulating layer 114. That is, the plasma treatment is performed using dinitrogen monoxide (NO) and ammonia, and then the insulating layer 114 can be formed by flowing monosilane gas. In this way, the plasma treatment and the formation of the insulating layer 114 can be performed consecutively in the same treatment chamber, thereby reducing impurities at the interface between the semiconductor layer 108 and the insulating layer 114 and achieving a good interface.

[0198] In forming the insulating layer 114, the flow rate of the oxidizing gas relative to the flow rate of the deposition gas is preferably greater than 20 times and less than 200 times, more preferably greater than 30 times and less than 150 times, even more preferably greater than 40 times and less than 100 times, and even more preferably greater than 40 times and less than 80 times.

[0199] In forming the insulating layer 114, the flow rate of ammonia gas is preferably equal to or lower than the flow rate of the oxidizing gas. The ratio of the flow rate of ammonia gas to the flow rate of the oxidizing gas is preferably 0.01 to 1, more preferably 0.02 to 0.9, further preferably 0.03 to 0.8, further preferably 0.04 to 0.6, and further preferably 0.05 to 0.5. The above gas flow rates enable the insulating layer 114 to emit a large amount of ammonia, and the emission of nitrogen oxides from the insulating layer 114 can be reduced, thereby enabling a transistor with small fluctuation in threshold voltage. Furthermore, the above gas flow rates enable the formation of the insulating layer 114 with few defects even when the pressure in the treatment chamber is relatively high. Note that the preferable flow rate of ammonia gas relative to the flow rate of the oxidizing gas may vary depending on the conditions, such as pressure or power, used in forming the insulating layer 114.

[0200] The pressure in the treatment chamber during the formation of the insulating layer 114 is preferably equal to or less than 200 Pa, more preferably equal to or less than 150 Pa, further preferably equal to or less than 120 Pa, and further preferably equal to or less than 100 Pa. By setting the pressure within the above range, the insulating layer 114 can be formed with little nitrogen oxide emission and with few defects.

[0201] An insulating layer that releases a lot of ammonia and little nitrogen oxide is a film that releases more ammonia than nitrogen oxide in thermal desorption spectroscopy (TDS), typically when the amount of ammonia released is 1×10 18 / cm 3 5x10 or more 19 / cm 3 The amount of ammonia released is the amount released when the surface temperature of the film is in the range of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower.

[0202] The insulating layer 114 preferably has a low defect density. If the defect density in the insulating layer 114 is high, oxygen bonds to the defects, reducing the oxygen permeability of the insulating layer 114. By using the insulating layer 114 with a low defect density, a transistor can be obtained with small fluctuations in threshold voltage and excellent electrical characteristics. For example, when an insulating film containing silicon is used as the insulating layer 114, the spin density of the signal appearing at g=2.001 due to the dangling bond of silicon in ESR measurement is 3×10 17 spins / cm 3 It is preferable that:

[0203] Since the insulating layer 114 is formed over the semiconductor layer 108, it is preferable that the insulating layer 114 be formed under conditions that cause little damage to the semiconductor layer 108. For example, the insulating layer 114 can be formed under conditions that cause a sufficiently slow film formation rate. For example, when the insulating layer 114 is formed by a plasma CVD method, damage to the semiconductor layer 108 can be significantly reduced by forming the insulating layer 114 under low-power conditions.

[0204] The insulating layer 116 is preferably an oxide film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 116 has an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 116 by forming the insulating layer 116 in an oxygen atmosphere, performing heat treatment or plasma treatment on the formed insulating layer 116 in an oxygen atmosphere, or forming an oxide film on the insulating layer 116 in an oxygen atmosphere. Note that the insulating layer 116 is preferably an oxide film that releases oxygen molecules in a TDS of 1.0×10 19 molecules / cm 3 or more, preferably 3.0 × 10 20 molecules / cm 3 The aforementioned amount of released oxygen is the total amount when the temperature of the heat treatment in TDS is in the range of 50°C or more and 650°C or less, or 50°C or more and 550°C or less.

[0205] The insulating layer 116 preferably has a low defect density. Typically, the spin density of the signal appearing at g=2.001 due to the dangling bond of silicon in ESR measurement is 1.5×10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 Note that the insulating layer 116 may have a higher defect density than the insulating layer 114 because it is located farther from the semiconductor layer 108 than the insulating layer 114.

[0206] The insulating layer 114 and the insulating layer 116 can be, for example, an insulating layer including one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.

[0207] Because the insulating layers 114 and 116 can be formed using insulating films of the same material, the interface between the insulating layer 114 and the insulating layer 116 may not be clearly visible. Therefore, in this embodiment, the boundary (interface) between the insulating layer 114 and the insulating layer 116 may not be clearly visible. Therefore, in the drawings illustrating one embodiment of the present invention, the boundary is indicated by a dashed line. Note that in this embodiment, a two-layer structure of the insulating layer 114 and the insulating layer 116 has been described; however, one embodiment of the present invention is not limited thereto. For example, the insulating layer 114 may have a single-layer structure or a stacked structure of three or more layers.

[0208] After the insulating layer 114 is formed, it is preferable to form the insulating layer 116 successively without exposing the surface of the insulating layer 114 to the air. By forming the insulating layer 116 successively after the insulating layer 114 is formed, it is possible to prevent impurities from adhering to the interface between the insulating layer 114 and the insulating layer 116.

[0209] The gas used to form the insulating layer 114 and the gas used to form the insulating layer 116 may be the same gas.

[0210] The insulating layer 114 is formed using a mixed gas containing a second oxidizing gas, ammonia gas, and a first deposition gas containing silicon, and the insulating layer 116 is formed using a mixed gas containing a third oxidizing gas and a second deposition gas containing silicon. Here, by using the same type of gas for the second oxidizing gas and the third oxidizing gas and the same type of gas for the first deposition gas containing silicon and the second deposition gas containing silicon, the oxidizing gas and the deposition gas containing silicon can be commonly used in the formation of the insulating layer 114 and the formation of the insulating layer 116. Using a common gas can reduce the number of types of gases used to manufacture transistors.

[0211] An example will be described in which the insulating layer 114 and the insulating layer 116 are formed using a plasma enhanced chemical vapor deposition apparatus.

[0212] Here, both the insulating layer 114 and the insulating layer 116 are made of silicon oxynitride. The insulating layer 114 is formed using a mixed gas containing monosilane as a deposition gas, dinitrogen monoxide (NO) as an oxidizing gas, and ammonia. The insulating layer 116 is formed using a mixed gas containing monosilane as a deposition gas and dinitrogen monoxide (NO) as an oxidizing gas. Here, both the insulating layer 114 and the insulating layer 116 can be formed using monosilane and dinitrogen monoxide (NO). That is, the insulating layer 114 is formed using monosilane, dinitrogen monoxide (NO), and ammonia, and then the insulating layer 116 can be formed by stopping the supply of ammonia gas. Since the insulating layer 114 and the insulating layer 116 can be formed consecutively in the same process chamber, impurities at the interface between the insulating layer 114 and the insulating layer 116 can be reduced, resulting in a good interface.

[0213] Furthermore, when plasma treatment is performed as the cleaning treatment before the formation of the insulating layer 114, it is preferable to use a common gas for the plasma treatment, the formation of the insulating layer 114, and the formation of the insulating layer 116. Using a common gas enables the number of types of gases used in manufacturing a transistor to be reduced.

[0214] An example will be described in which a plasma enhanced chemical vapor deposition apparatus is used to perform plasma treatment, formation of the insulating layer 114, and formation of the insulating layer 116. Here, the insulating layer 114 and the insulating layer 116 are made of silicon oxynitride.

[0215] In the plasma treatment, a mixed gas containing nitrous oxide (NO) as an oxidizing gas and ammonia as a reducing gas is used. Furthermore, in the formation of the insulating layer 114, a mixed gas containing monosilane as a deposition gas, dinitrogen monoxide (NO) as an oxidizing gas, and ammonia is used. Furthermore, in the formation of the insulating layer 116, a mixed gas containing monosilane as a deposition gas and dinitrogen monoxide (NO) as an oxidizing gas is used. Here, dinitrogen monoxide (NO) as an oxidizing gas can be commonly used in the plasma treatment, the formation of the insulating layer 114, and the formation of the insulating layer 116. Furthermore, ammonia can be commonly used in the plasma treatment and the formation of the insulating layer 114. Furthermore, monosilane as a deposition gas can be commonly used in the formation of the insulating layer 114 and the insulating layer 116. That is, the insulating layer 114 can be formed by performing plasma treatment using dinitrogen monoxide (NO) and ammonia, and then flowing monosilane gas. Subsequently, the supply of ammonia gas is stopped to form the insulating layer 116. In this manner, the plasma treatment, the formation of the insulating layer 114, and the formation of the insulating layer 116 can be performed successively in the same treatment chamber, so that impurities can be reduced at the interface between the semiconductor layer 108 and the insulating layer 114 and at the interface between the insulating layer 114 and the insulating layer 116, respectively, resulting in good interfaces.

[0216] After the insulating layer 116 is formed, a plasma treatment may be performed on the surface of the insulating layer 116. The plasma treatment can reduce impurities such as water adsorbed on the surface of the insulating layer 116. When impurities such as water are adsorbed on the surface of the insulating layer 116, the impurities reach the semiconductor layer 108 and form V in the semiconductor layer 108. O , V OIn some cases, H or the like may be formed. By performing plasma treatment on the surface of the insulating layer 116 to prevent impurities such as water from being adsorbed to the surface of the insulating layer 116, a highly reliable transistor can be obtained. This is particularly preferable when the surface of the insulating layer 116 is exposed to the air between the formation of the insulating layer 116 and the formation of the insulating layer 118. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. Nitrogen is particularly preferable for use. Furthermore, it is preferable that the formation of the insulating layer 116 and the plasma treatment be performed successively without exposure to the air.

[0217] The insulating layer 118 functions as a protective film for the transistor 10. The insulating layer 118 prevents impurities such as water and hydrogen from diffusing into the transistor 10 from the outside of the transistor 10. That is, the reliability and moisture resistance of the transistor 10 can be improved, and a highly reliable semiconductor device can be provided.

[0218] The insulating layer 118 preferably functions as a barrier film that suppresses diffusion of impurities such as water and hydrogen from the outside of the transistor 10 to the transistor 10. Furthermore, the insulating layer 118 preferably releases little hydrogen-containing impurities such as water and hydrogen from itself. Furthermore, the insulating layer 118 preferably functions as a barrier film that suppresses diffusion of oxygen. The insulating layer 118 can be, for example, an oxide film such as aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, or yttrium oxynitride, or a nitride film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide. Silicon nitride is particularly suitable for use as the insulating layer 118.

[0219] Here, if heat is applied to the insulating layer 116 in an exposed state, oxygen contained in the insulating layer 114 and the insulating layer 116 might be released to the outside. If oxygen contained in the insulating layer 114 and the insulating layer 116 is released to the outside, the amount of oxygen contained in the insulating layer 114 and the insulating layer 116 might decrease, and the amount of oxygen supplied to the semiconductor layer 108 might decrease. Therefore, the temperature at which at least the insulating layer 118 starts to be formed is preferably a temperature at which oxygen contained in the insulating layer 114 and the insulating layer 116 is not released to the outside. The insulating layer 118 has a function of suppressing oxygen diffusion. Furthermore, by forming the insulating layer 118 at a temperature at which oxygen contained in the insulating layer 114 and the insulating layer 116 is not released to the outside, oxygen can be supplied to the semiconductor layer 108, and oxygen vacancies in the semiconductor layer 108 can be efficiently filled.

[0220] The insulating layer 118, which has the function of suppressing the diffusion of impurities such as water and hydrogen and the function of suppressing the diffusion of oxygen, is preferably a dense film. For example, the insulating layer 118 can be formed into a dense film by increasing the substrate temperature during formation of the insulating layer 118.

[0221] The substrate temperature when the insulating layer 118 is formed is preferably 180° C. to 400° C., more preferably 200° C. to 380° C., further preferably 220° C. to 360° C., and further preferably 240° C. to 350° C. By setting the substrate temperature in the above range, oxygen contained in the insulating layer 114 and the insulating layer 116 can be prevented from being released to the outside, and the insulating layer 118 can be made into a dense film.

[0222] With such a structure, a transistor with favorable electrical characteristics and extremely high reliability can be realized.

[0223] The above is the explanation of configuration example 1-1.

[0224] Below, a description will be given of a configuration example of a transistor that is partially different in configuration from the above-described Configuration Example 1-1. Note that, below, descriptions of parts that overlap with the above-described Configuration Example 1-1 may be omitted. Also, in the drawings shown below, parts that have the same function as the above-described Configuration Example 1-1 may be hatched with the same pattern and may not be assigned reference numerals.

[0225] [Configuration Example 1-2] 6B is a schematic cross-sectional view of a transistor 10A of one embodiment of the present invention in the channel length direction. The transistor 10A differs from the aforementioned transistor 10 mainly in the structure of the insulating layer 106a. In the transistor 10A, the insulating layer 106a has a stacked-layer structure of an insulating layer 106a1, an insulating layer 106a2 over the insulating layer 106a1, and an insulating layer 106a3 over the insulating layer 106a2.

[0226] 6B shows an example in which the insulating layer 106 has a structure in which an insulating layer 106a1, an insulating layer 106a2, an insulating layer 106a3, and an insulating layer 106b are stacked in this order from the conductive layer 104 side. The insulating layer 106a1 is in contact with the conductive layer 104. The insulating layer 106b is in contact with the semiconductor layer 108.

[0227] It is preferable that the insulating layer 106a satisfy one or more of the following, and most preferably, it satisfies all of the following: suppression of diffusion of impurities such as water, hydrogen, and sodium; suppression of diffusion of components of the conductive layer 104; low stress; high dielectric strength; and low release of impurities such as water and hydrogen.

[0228] The insulating films that can be used for the insulating layer 106a can be used for the insulating layer 106a, which is located on the conductive layer 104 side, as the insulating layers 106a1, 106a2, and 106a3. The four insulating films of the insulating layer 106 are preferably formed successively using a plasma CVD apparatus without exposure to the air.

[0229] The insulating layer 106a1 preferably functions as a barrier film that suppresses the diffusion of impurities such as water, hydrogen, and sodium from a member (e.g., a substrate) on the surface where the insulating layer 106a1 is to be formed to the transistor 10. The insulating layer 106a1 also preferably functions as a barrier film that suppresses the diffusion of components of the conductive layer 104 to the transistor 10. The insulating layer 106a2 preferably has low stress and high dielectric strength. The insulating layer 106a3 preferably releases little impurities such as water and hydrogen from itself. The insulating layer 106a3 also preferably functions as a barrier film that suppresses the diffusion of impurities such as water and hydrogen from below the insulating layer 106a2 to the transistor 10.

[0230] The insulating layers 106a1 and 106a3 are preferably dense films that can prevent diffusion of impurities from below. The insulating layers 106a1 and 106a3 can be formed using insulating films formed at a slower deposition rate than the insulating layer 106a2. On the other hand, the insulating layer 106a2 is preferably formed using an insulating film that has low stress and is formed at a faster deposition rate. The insulating layer 106a2 is preferably thicker than the insulating layers 106a1 and 106a3.

[0231] Even when the insulating layers 106a1, 106a2, and 106a3 are made of the same film type, such as a silicon nitride film formed by plasma CVD, the insulating layer 106a2 has a lower film density than the insulating layers 106a1 and 106a3. This difference can be observed as a difference in contrast in a transmission electron microscope (TEM) image of a cross section of the insulating layer 106. Note that the boundary between the insulating layers 106a1 and 106a2 and the boundary (interface) between the insulating layers 106a2 and 106a3 may not be clearly visible. Therefore, in the drawings illustrating one embodiment of the present invention, these boundaries are indicated by dashed lines.

[0232] With such a structure, a transistor with favorable electrical characteristics and extremely high reliability can be realized.

[0233] [Configuration Example 1-3] 7A is a schematic cross-sectional view of a transistor 10B according to one embodiment of the present invention, taken along the channel length direction. The transistor 10B differs from the aforementioned transistor 10 mainly in that a conductive layer 120 is provided over an insulating layer 118.

[0234] The semiconductor layer 108 is located between the conductive layer 104 and the conductive layer 120, and the conductive layer 104, the semiconductor layer 108, and the conductive layer 120 have overlapping regions. The transistor 10B is a dual-gate transistor including the conductive layer 104 functioning as a gate electrode and the conductive layer 120 functioning as a back gate electrode, above and below the semiconductor layer 108. In the transistor 10B, part of the insulating layer 106 functions as a first gate insulating layer, and parts of the insulating layers 114, 116, and 118 function as second gate insulating layers.

[0235] For example, the transistor 10B can increase the current that can flow in an on state by applying the same potential to the conductive layer 104 and the conductive layer 120. Alternatively, the transistor 10B can apply a potential to one of the conductive layer 104 and the conductive layer 120 to control the threshold voltage, and apply a potential to the other to control the on and off states of the transistor 10B.

[0236] With such a structure, a transistor with favorable electrical characteristics and extremely high reliability can be realized.

[0237] [Configuration Example 1-4] 7B is a schematic cross-sectional view of a transistor 10C of one embodiment of the present invention in the channel length direction. The transistor 10C differs from the above-described transistor 10 mainly in the structure of the insulating layer 106 and in the presence of a conductive layer 120. The transistor 10C is an example in which the conductive layer 120 illustrated in the transistor 10B illustrated in the above-described Structural Example 1-3 is applied to the transistor 10A illustrated in the above-described Structural Example 1-2.

[0238] With such a structure, a transistor with favorable electrical characteristics and extremely high reliability can be realized.

[0239] <Configuration example 2> A more specific example of the configuration of a transistor will be described below.

[0240] [Configuration Example 2-1] FIG. 8A is a top view of the transistor 100, FIG. 8B corresponds to a cross-sectional view of the section taken along dashed-dotted line A1-A2 in FIG. 8A, and FIG. 8C corresponds to a cross-sectional view of the section taken along dashed-dotted line B1-B2 in FIG. 8A. The direction of dashed-dotted line A1-A2 corresponds to the channel length direction, and the direction of dashed-dotted line B1-B2 corresponds to the channel width direction. Note that in FIG. 8A, some of the components of the transistor 100 (such as a gate insulating layer) are omitted. As with FIG. 8A, some of the components are also omitted from the top views of the transistors in the following drawings. FIG. 9A shows an enlarged cross-sectional view of the region P surrounded by the dashed-dotted line in FIG. 8B.

[0241] The transistor 100 is provided over a substrate 102 and includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The insulating layer 106 covers the conductive layer 104. The semiconductor layer 108 has an island shape and is provided over the insulating layer 106. The conductive layers 112a and 112b are in contact with a top surface of the semiconductor layer 108 and are spaced apart from each other over the semiconductor layer 108. An insulating layer 114 is provided to cover the insulating layer 106, the conductive layer 112a, the conductive layer 112b, and the semiconductor layer 108, and an insulating layer 116 is provided over the insulating layer 114.

[0242] The conductive layer 104 functions as a gate electrode. Part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. A region of the semiconductor layer 108 overlapping with the conductive layer 104 functions as a channel formation region. The transistor 100 is a so-called bottom-gate transistor in which a gate electrode is provided closer to the semiconductor layer 108 than the semiconductor layer 108. Here, the surface of the semiconductor layer 108 opposite to the conductive layer 104 side may be referred to as a back channel side surface. The transistor 100 is a transistor with a so-called channel-etched structure in which no protective layer is provided between the back channel side of the semiconductor layer 108 and the source electrode and the drain electrode.

[0243] The semiconductor layer 108 has a layered structure in which a semiconductor layer 108a and a semiconductor layer 108b are stacked in this order from the formation surface side (the substrate 102 side). The semiconductor layer 108a and the semiconductor layer 108b each preferably contain a metal oxide. The semiconductor layer 108b located on the back channel side preferably has higher crystallinity than the semiconductor layer 108a located on the conductive layer 104 side. This can prevent part of the semiconductor layer 108 from being etched and lost when the conductive layers 112a and 112b are processed.

[0244] For example, the semiconductor layer 108 is preferably formed using a metal oxide having the composition described in Embodiment 1. By using the metal oxide for the channel formation region, a transistor with high reliability and high field-effect mobility can be obtained.

[0245] The semiconductor layer 108a and the semiconductor layer 108b are preferably formed using the metal oxide film described in Embodiment 1.

[0246] The semiconductor layer 108a and the semiconductor layer 108b may have the same or substantially the same composition. By making the semiconductor layer 108a and the semiconductor layer 108b have the same or substantially the same composition, the semiconductor layer 108a and the semiconductor layer 108b can be formed using the same sputtering target, thereby reducing manufacturing costs.

[0247] The semiconductor layer 108a and the semiconductor layer 108b may be layers having different compositions, different crystallinity, or different impurity concentrations, or may have a stacked structure of three or more layers.

[0248] The conductive layer 112a and the conductive layer 112b each have a layered structure in which a conductive layer 113a, a conductive layer 113b, and a conductive layer 113c are stacked in this order from the formation surface side.

[0249] The conductive layer 113b is preferably made of a low-resistance conductive material containing copper, silver, gold, aluminum, or the like. In particular, the conductive layer 113b preferably contains copper or aluminum. The conductive layer 113b is preferably made of a conductive material having lower resistance than the conductive layers 113a and 113c. This allows the conductive layers 112a and 112b to have extremely low resistance.

[0250] The conductive layer 113a and the conductive layer 113c can each be formed using a conductive material different from that of the conductive layer 113b. For example, the conductive layer 113a and the conductive layer 113c can each be formed using a conductive material containing titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, ruthenium, or the like.

[0251] In this manner, by sandwiching the conductive layer 113b containing copper, aluminum, or the like between the conductive layer 113a and the conductive layer 113c, it is possible to prevent the surface of the conductive layer 113b from being oxidized and the elements of the conductive layer 113b from diffusing into the surrounding layers. In particular, by providing the conductive layer 113a between the semiconductor layer 108 and the conductive layer 113b, it is possible to prevent the metal elements contained in the conductive layer 113b from diffusing into the semiconductor layer 108, thereby realizing a highly reliable transistor 100.

[0252] Here, the insulating layer 114 is provided in contact with an end portion of the conductive layer 113b. As will be described later, according to one embodiment of the present invention, even when the conductive layer 113b is made of a conductive material that is easily oxidized and the insulating layer 114 including an oxide film is formed thereon, oxidation of the surface of the conductive layer 113b can be suppressed. Therefore, one of the features of one embodiment of the present invention is that a foreign layer including an oxide is not observed at the interface between the conductive layer 113b and the insulating layer 114.

[0253] The conductive layers 112a and 112b are not limited to a three-layer structure and may have a two-layer structure or a four-layer structure including a conductive layer containing copper, silver, gold, or aluminum. For example, the conductive layers 112a and 112b may have a two-layer structure in which the conductive layers 113a and 113b are stacked, or a two-layer structure in which the conductive layers 113b and 113c are stacked.

[0254] When the conductive layer 112a and the conductive layer 112b are formed, the surface of the semiconductor layer 108 may be damaged. O is formed, and further, hydrogen in the semiconductor layer 108 is converted to V O Enter V OSince a defect H may be formed, it is preferable to remove the damaged layer. By removing the damaged layer, a transistor with good electrical characteristics and high reliability can be obtained. FIG. 9B shows an example of a configuration in which the damaged layer has been removed. FIG. 9B is an enlarged cross-sectional view of a region P surrounded by a dashed line in FIG. 8B. FIG. 9B shows an example in which the thickness of a region of the semiconductor layer 108b that does not overlap with either the conductive layer 112a or the conductive layer 112b is thinner than the thickness of a region that overlaps with either the conductive layer 112a or the conductive layer 112b.

[0255] 9A and 9B show an example in which the edges of the conductive layer 113a, the conductive layer 113b, and the conductive layer 113c are aligned or substantially aligned, but this is not a limitation of one embodiment of the present invention. Any of the edges of the conductive layer 113a, the conductive layer 113b, and the conductive layer 113c may not be aligned or may not be substantially aligned.

[0256] 9C, the ends of the conductive layers 113b and 113c are preferably located inside the end of the conductive layer 113a. Furthermore, the end of the conductive layer 113c preferably coincides or roughly coincides with the end of the conductive layer 113b. This configuration improves the step coverage of the conductive layers 113a, 113b, 113c, and layers (e.g., the insulating layer 114) formed on the semiconductor layer 108, thereby preventing defects such as discontinuities and voids in the layers.

[0257] 9C shows an example in which the end of conductive layer 113b is located inside conductive layer 113a and the end of conductive layer 113c coincides with the end of conductive layer 113b. FIG. 9C is an enlarged cross-sectional view of region P surrounded by the dashed line in FIG. 8B. The configuration shown in FIG. 9C reduces the step between conductive layer 112a and conductive layer 112b, improving the step coverage of layers (e.g., insulating layer 118) formed on conductive layer 112a, conductive layer 112b, and semiconductor layer 108a, and suppressing defects such as discontinuities and voids in the layers.

[0258] 9C shows an example in which the ends of the conductive layer 113b and the conductive layer 113c are aligned or substantially aligned, but this is not a limitation of one embodiment of the present invention. The ends of the conductive layer 113b and the conductive layer 113c may not be aligned or may not be substantially aligned. If the end of the conductive layer 113b is located inside the end of the conductive layer 113c, the step coverage of the conductive layer 112a, the conductive layer 112b, and a layer (e.g., the insulating layer 118) formed over the semiconductor layer 108a may be poor, and defects such as discontinuities or voids may occur in the layer. Therefore, it is preferable that the end of the conductive layer 113c be located inside the end of the conductive layer 113b.

[0259] Any of the above-mentioned conductive materials that can be used for the conductive layers 113a and 113b can be used as appropriate for the conductive layer 104. In particular, a conductive material containing copper is preferably used.

[0260] An insulating material containing an oxide is preferably used for the insulating layer 106 and the insulating layer 114 which are in contact with the semiconductor layer 108. When the insulating layer 106 and the insulating layer 114 have a stacked structure, an insulating material containing an oxide is used for the layer in contact with the semiconductor layer 108.

[0261] The insulating layer 106 may be a nitride film such as silicon nitride or aluminum nitride. When an insulating material that does not contain oxide is used, it is preferable to form a region containing oxygen by performing a treatment to add oxygen to the upper part of the insulating layer 106. Examples of the treatment to add oxygen include heat treatment or plasma treatment in an atmosphere containing oxygen, and ion doping treatment.

[0262] The insulating layer 116 functions as a protective layer that protects the transistor 100. The insulating layer 116 can be formed using an inorganic insulating material such as silicon nitride, silicon nitride oxide, silicon oxide, silicon oxynitride, aluminum oxide, or aluminum nitride. In particular, using a material that does not easily diffuse oxygen, such as silicon nitride or aluminum oxide, for the insulating layer 116 is preferable because oxygen can be prevented from being released from the semiconductor layer 108 or the insulating layer 114 through the insulating layer 116 due to heat or the like applied during a manufacturing process.

[0263] An organic insulating material that functions as a planarization film may be used as the insulating layer 116. Alternatively, the insulating layer 116 may be a stacked film of a film containing an inorganic insulating material and a film containing an organic insulating material.

[0264] The semiconductor layer 108 may have a pair of low-resistance regions that function as a source region and a drain region and are located in contact with and near the conductive layers 112a and 112b. These regions are part of the semiconductor layer 108 and have lower resistance than the channel formation region. The low-resistance region can also be referred to as a region with a high carrier concentration or an n-type region. In addition, a region of the semiconductor layer 108 that is sandwiched between the pair of low-resistance regions and overlaps with the conductive layer 104 functions as a channel formation region.

[0265] The above is the explanation of configuration example 2-1.

[0266] [Configuration Example 2-2] Below, a description will be given of a configuration example of a transistor that is partially different in configuration from the above-described Configuration Example 2-1. Note that, below, descriptions of parts that overlap with the above-described Configuration Example 2-1 may be omitted. Also, in the drawings shown below, parts that have the same function as the above-described Configuration Example 2-1 may be hatched with the same pattern and may not be assigned reference numerals.

[0267] 10A is a top view of the transistor 100A, FIG. 10B is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 10C is a cross-sectional view of the transistor 100B in the channel width direction.

[0268] The transistor 100A differs from the transistor 100 shown in Structural example 2-1 mainly in that the transistor 100A includes a conductive layer 120a and a conductive layer 120b over the insulating layer 116.

[0269] The conductive layer 120a has a region overlapping with the semiconductor layer 108 with the insulating layer 116 and the insulating layer 114 interposed therebetween.

[0270] In the transistor 100A, the conductive layer 104 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 120a functions as a second gate electrode (also referred to as a top gate electrode). Part of the insulating layer 116 and part of the insulating layer 114 function as a second gate insulating layer.

[0271] 10C, the conductive layer 120a may be electrically connected to the conductive layer 104 through an opening 142b provided in the insulating layer 116, the insulating layer 114, and the insulating layer 106. This allows the same potential to be applied to the conductive layer 120a and the conductive layer 104, thereby realizing a transistor with high on-state current.

[0272] 10A and 10C, it is preferable that the conductive layer 104 and the conductive layer 120a protrude outward in the channel width direction from the end portions of the semiconductor layer 108. In this case, as shown in Fig. 10C, the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 104 and the conductive layer 120a.

[0273] With this structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In this case, it is particularly preferable to apply the same potential to the conductive layer 104 and the conductive layer 120a. This allows an electric field for inducing a channel in the semiconductor layer 108 to be effectively applied, thereby increasing the on-state current of the transistor 100A. This also enables miniaturization of the transistor 100A.

[0274] Note that the conductive layer 104 and the conductive layer 120a may not be connected to each other. In this case, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be applied to the other. In this case, the threshold voltage when the transistor 100A is driven by the other electrode can be controlled by the potential applied to one electrode.

[0275] The conductive layer 120b is electrically connected to the conductive layer 112b through an opening 142a formed in the insulating layer 116 and the insulating layer 114. The conductive layer 120b can be used as a wiring or an electrode. For example, when the conductive layer 120b is applied to a display device, the conductive layer 120b can function as a pixel electrode or a wiring for connecting to a pixel electrode.

[0276] The above is the explanation of configuration example 2-2.

[0277] [Configuration Example 2-3] 11A and 11B differs from the transistor 100A shown in the above-described Structural Example 2-2 mainly in that, in a cross-sectional view in the channel length direction, an end of the insulating layer 106b roughly coincides with an end of the conductive layer 112a or an end of the conductive layer 112b. Also, in the transistor 100B, in a cross-sectional view in the channel width direction, an end of the insulating layer 106b roughly coincides with an end of the semiconductor layer 108.

[0278] The insulating layer 106a has a region in contact with the insulating layer 106b in a region overlapping with the semiconductor layer 108, the conductive layer 112a, or the conductive layer 112b. The insulating layer 106a also has a region in contact with the insulating layer 114 in a region not overlapping with any of the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b.

[0279] The insulating layer 106a preferably functions as an etching stopper when the conductive layers 112a and 112b are formed. For example, when an oxide film such as silicon oxide or silicon oxynitride is used for the insulating layer 106b, an oxide film such as aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, or yttrium oxynitride, or a nitride film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can be preferably used for the insulating layer 106a.

[0280] By the insulating layer 106a functioning as an etching stopper, the steps at the ends of the conductive layers 112a and 112b are reduced, the step coverage of the layer (e.g., the insulating layer 114) formed on the conductive layers 112a and 112b is improved, and defects such as discontinuities and voids in the layer can be suppressed.

[0281] 11A and 11B show an example in which the thickness of the insulating layer 106a in a region that does not overlap with any of the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b is approximately equal to the thickness of the insulating layer 106a in a region that overlaps with the semiconductor layer 108, the conductive layer 112a, or the conductive layer 112b, but this is not limited to this embodiment. The thickness of the insulating layer 106a in a region that does not overlap with any of the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b may be thinner than the thickness of the insulating layer 106a in a region that overlaps with the semiconductor layer 108, the conductive layer 112a, or the conductive layer 112b.

[0282] The above is the explanation of configuration example 2-3.

[0283] [Configuration Example 2-4] 12A and 12B differs from the transistor 100A shown in the above-described Configuration Example 2-2 mainly in that, in a cross-sectional view in the channel length direction, an end of the insulating layer 106b roughly coincides with an end of the semiconductor layer 108. In addition, in the transistor 100B, in a cross-sectional view in the channel width direction, an end of the insulating layer 106b roughly coincides with an end of the semiconductor layer 108.

[0284] The insulating layer 106a has a region in contact with the insulating layer 106b in a region overlapping with the semiconductor layer 108. The insulating layer 106a also has a region in contact with the insulating layer 114 in a region not overlapping with any of the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b.

[0285] The insulating layer 106a preferably functions as an etching stopper when forming the semiconductor layer 108. When the insulating layer 106a functions as an etching stopper, the step at the end of the semiconductor layer 108 is reduced, the step coverage of the layers (e.g., the conductive layers 112a and 112b) formed on the semiconductor layer 108 is improved, and defects such as disconnection and voids in the layers can be suppressed.

[0286] 12A and 12B show an example in which the thickness of the insulating layer 106a in the region not overlapping with the semiconductor layer 108 is approximately equal to the thickness of the insulating layer 106a in the region overlapping with the semiconductor layer 108, but this is not a limitation of one embodiment of the present invention. The thickness of the insulating layer 106a in the region not overlapping with the semiconductor layer 108 may be thinner than the thickness of the insulating layer 106a in the region overlapping with the semiconductor layer 108.

[0287] The above is the explanation of configuration example 2-4.

[0288] <Production method example 1> A method for manufacturing a semiconductor device of one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100A described in the above-described Structure Example 2-2 will be used as an example.

[0289] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0290] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, knife coating, etc.

[0291] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0292] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0293] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet light (EUV) or X-rays can also be used as the light used for exposure. Instead of light used for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0294] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0295] 13 to 17 illustrate a method for manufacturing the transistor 100A. In each figure, a cross section in the channel length direction is shown on the left side, and a cross section in the channel width direction is shown on the right side.

[0296] [Formation of Conductive Layer 104] A conductive film is formed over the substrate 102, a resist mask is formed over the conductive film by a lithography process, and then the conductive film is etched to form the conductive layer 104 which functions as a gate electrode.

[0297] [Formation of insulating layer 106] Next, an insulating layer 106 is formed to cover the conductive layer 104 and the substrate 102 (FIG. 13A). The insulating layer 106 can be formed by, for example, a PECVD method.

[0298] Heat treatment may be performed after the insulating layer 106 is formed. By performing the heat treatment, water and hydrogen can be released from the surface of the insulating layer 106 and from the film.

[0299] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 250°C or higher and 450°C or lower, and further preferably 300°C or higher and 450°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a rare gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. By using an atmosphere with as little hydrogen, water, or the like as possible, it is possible to prevent hydrogen, water, or the like from being introduced into the insulating layer 106 as much as possible. The heat treatment can be performed in an oven, a rapid thermal annealing (RTA) apparatus, or the like. The use of an RTA apparatus can shorten the heat treatment time.

[0300] Subsequently, a process for supplying oxygen to the insulating layer 106 may be performed. For the oxygen supply process, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating layer 106 by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed on the insulating layer 106, and then oxygen may be added to the insulating layer 106 through the film. The film is preferably removed after oxygen is added. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0301] [Formation of Semiconductor Layer 108] Next, a metal oxide film 108af and a metal oxide film 108bf are stacked on the insulating layer 106 (FIG. 13B).

[0302] The metal oxide films 108af and 108bf are preferably formed by sputtering using a metal oxide target.

[0303] When forming the metal oxide films 108af and 108bf, an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) may be mixed with oxygen gas. The ratio of oxygen gas to the total deposition gas when forming the metal oxide films (hereinafter also referred to as oxygen flow ratio) can be in the range of 0% to 100%.

[0304] By lowering the oxygen flow ratio and forming a metal oxide film with relatively low crystallinity, a metal oxide film with high conductivity can be obtained, whereas by increasing the oxygen flow ratio and forming a metal oxide film with relatively high crystallinity, a metal oxide film with high etching resistance and electrical stability can be obtained.

[0305] Here, the metal oxide film 108af located on the conductive layer 104 side, which functions as a gate electrode, is a film with low crystallinity, and the metal oxide film 108bf located on the back channel side is a film with high crystallinity, thereby realizing a transistor with high reliability and high field-effect mobility.

[0306] For example, the conditions for forming the metal oxide films 108af and 108bf are such that the substrate temperature is from room temperature to 200° C., preferably from room temperature to 140° C. When the metal oxide films are formed, the substrate temperature is preferably from room temperature to less than 140° C., for example, because productivity is increased.

[0307] More specifically, the oxygen flow rate during the formation of the metal oxide film 108af is preferably 0% or more and less than 50%, more preferably 5% or more and 30% or less, even more preferably 5% or more and 20% or less, and typically 10%. The oxygen flow rate during the formation of the metal oxide film 108bf is preferably 50% or more and 100% or less, even more preferably 60% or more and 100% or less, even more preferably 70% or more and 100% or less, even more preferably 80% or more and 100% or less, and typically 100%.

[0308] The metal oxide film 108af and the metal oxide film 108bf can be films of the same or approximately the same composition. The metal oxide film 108af and the metal oxide film 108bf can be formed using the same sputtering target, thereby reducing manufacturing costs. Furthermore, when the same sputtering target is used, the metal oxide film 108af and the metal oxide film 108bf can be successively formed in a vacuum using the same film formation apparatus, thereby preventing impurities from being introduced into the interface between the semiconductor layer 108a and the semiconductor layer 108b. Although the conditions for forming the metal oxide film 108af and the metal oxide film 108bf, such as pressure, temperature, and power, may be different, it is preferable to keep the conditions other than the oxygen flow rate the same, since this shortens the time required for the formation process.

[0309] The metal oxide film 108af and the metal oxide film 108bf may be films with different compositions. In this case, when In-Ga-Zn oxide is used for both the metal oxide film 108af and the metal oxide film 108bf, it is preferable to use an oxide target for the metal oxide film 108bf that has a higher In content than the metal oxide film 108af.

[0310] After the metal oxide film 108af and the metal oxide film 108bf are formed, a resist mask is formed on the metal oxide film 108bf, and the metal oxide film 108af and the metal oxide film 108bf are processed by etching. Then, the resist mask is removed, thereby forming an island-shaped semiconductor layer 108 in which the semiconductor layer 108a and the semiconductor layer 108b are stacked (FIG. 13C).

[0311] The metal oxide films 108af and 108bf may be processed by wet etching or dry etching, or both.

[0312] When the semiconductor layer 108 is formed, the thickness of the insulating layer 106 in the region that does not overlap with the semiconductor layer 108 may be thinner than the thickness of the insulating layer 106 in the region that overlaps with the semiconductor layer 108 .

[0313] Heat treatment may be performed after the metal oxide films 108af and 108bf are formed or after they are processed into the semiconductor layer 108. By performing the heat treatment, hydrogen and water can be removed from the surface and in the metal oxide films 108af and 108bf or the semiconductor layer 108. Furthermore, by performing the heat treatment, the etching rate of the metal oxide films 108af and 108bf or the semiconductor layer 108 can be slowed down, and thus, the semiconductor layer 108 can be prevented from disappearing in a later step (for example, in the formation of the conductive layers 112a and 112b).

[0314] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 250°C or higher and 450°C or lower, and even more preferably 300°C or higher and 450°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a rare gas and nitrogen. Alternatively, after heating in the atmosphere, heating may be performed in an atmosphere containing oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, and the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. Using an atmosphere with as little hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being introduced into the semiconductor layer 108 as much as possible. The heat treatment can be performed in an oven, a rapid thermal annealing (RTA) apparatus, or the like. Using an RTA apparatus can shorten the heat treatment time.

[0315] [Formation of Conductive Layer 112a and Conductive Layer 112b] Next, a conductive film 113af, a conductive film 113bf, and a conductive film 113cf are stacked to cover the insulating layer 106 and the semiconductor layer 108.

[0316] The conductive film 113bf is a film that will later become the conductive layer 113b and preferably contains copper, silver, gold, or aluminum. The conductive film 113af and the conductive film 113cf are films that will later become the conductive layer 113a and the conductive layer 113b, respectively, and preferably contain titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, ruthenium, or the like.

[0317] The conductive films 113af, 113bf, and 113cf are preferably formed by a sputtering method, an evaporation method, a plating method, or the like.

[0318] Subsequently, a resist mask 140 is formed on the conductive film 113cf (FIG. 14A).

[0319] Next, the conductive films 113cf, 113bf, and 113af are etched using the resist mask 140 as a mask, whereby the conductive layers 112a and 112b each having a stacked structure of the conductive layer 113a, the conductive layer 113b, and the conductive layer 113c can be formed (FIG. 14B).

[0320] 14B, the conductive layers 112a and 112b are preferably processed to be spaced apart from each other over the channel formation region of the semiconductor layer 108. In other words, the conductive layers 112a and 112b are preferably processed so that opposing ends thereof overlap with both the conductive layer 104 and the semiconductor layer 108. This can increase the on-state current of the transistor.

[0321] Note that when the conductive layers 112a and 112b are formed, the thickness of the semiconductor layer 108 in a region that does not overlap with the conductive layers 112a and 112b may be thinner than the thickness of the semiconductor layer 108 in a region that overlaps with the conductive layers 112a and 112b.

[0322] When the conductive layers 112a and 112b are formed, the thickness of the insulating layer 106 in the region that does not overlap with the conductive layers 112a and 112b may be thinner than the thickness of the insulating layer 106 in the region that overlaps with the conductive layers 112a and 112b.

[0323] The conductive films 113cf, 113bf, and 113af can be etched by wet etching, dry etching, etc. The three layers may be etched together in one step, or may be etched sequentially in different steps.

[0324] [Cleaning process 1] Subsequently, it is preferable to carry out a cleaning treatment. The cleaning treatment may be wet cleaning using a cleaning solution, plasma treatment using plasma, or cleaning by heat treatment, and the above-mentioned cleaning treatments may be combined appropriately. As the cleaning treatment, wet cleaning using phosphoric acid is particularly suitable.

[0325] When the conductive films 113cf, 113bf, and 113af are formed, and when the conductive layers 112a and 112b are formed, the surface of the semiconductor layer 108 may be damaged. O is formed, and further, hydrogen in the semiconductor layer 108 is converted to V O Enter V O In some cases, H is formed. By performing cleaning treatment after the conductive layers 112a and 112b are formed, damaged layers can be removed.

[0326] By performing the cleaning treatment, metal, organic substances, and the like attached to the surface of the semiconductor layer 108 when the conductive layers 112a and 112b are formed can be removed.

[0327] 14B, cleaning treatment is preferably performed with the top surfaces of the conductive layers 112a and 112b covered with the resist mask 140. By performing cleaning treatment with the top surfaces of the conductive layers 112a and 112b covered with the resist mask 140, it is possible to prevent, for example, the conductive layer 113c from being lost. Furthermore, by performing cleaning treatment with the top surfaces of the conductive layers 112a and 112b covered with the resist mask 140, it is possible to reduce the areas of the conductive layers 112a and 112b that are exposed during the cleaning treatment, thereby preventing components of the conductive layers 112a and 112b from being attached to the semiconductor layer 108.

[0328] Subsequently, the resist mask 140 is removed (FIG. 15A).

[0329] The above-described cleaning process may be performed after the resist mask 140 is removed.

[0330] [Cleaning process 2] Next, cleaning treatment is preferably performed. The cleaning treatment may be wet cleaning using a cleaning solution or the like, plasma treatment using plasma, or cleaning by heat treatment. The cleaning treatments may be performed in combination as appropriate. Plasma treatment is preferably used as the cleaning treatment. FIG. 15B schematically illustrates the surfaces of the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, and the insulating layer 106 being exposed to plasma 130.

[0331] In particular, it is preferable to use a mixed gas containing an oxidizing gas and a reducing gas for the plasma treatment. By using an oxidizing gas and a reducing gas for the plasma treatment, oxidation of the conductive layers 112a and 112b can be suppressed and water, hydrogen, organic components, and the like adsorbed on the surface of the semiconductor layer 108 can be effectively removed. The above-mentioned gases can be used as the oxidizing gas. The above-mentioned gases can be used as the reducing gas.

[0332] The ratio of the flow rates of the oxidizing gas and the reducing gas in the plasma treatment can be set depending on the ease of oxidation of the conductive layers 113a, 113b, and 113c, but it is preferable to set the flow rate of at least the reducing gas equal to or less than the flow rate of the oxidizing gas. If the flow rate of the reducing gas relative to the flow rate of the oxidizing gas is too low, oxidation reactions on the surfaces of the conductive layers 113b and the like become dominant, making it easier for oxides to form on the surfaces. On the other hand, if the flow rate of the reducing gas relative to the flow rate of the oxidizing gas is too high, the surface of the semiconductor layer 108 may be reduced or components of the reducing gas (e.g., hydrogen) may be supplied into the semiconductor layer 108.

[0333] In the plasma treatment, the flow rate of the reducing gas relative to the flow rate of the oxidizing gas is preferably within the aforementioned range. During the plasma treatment, the surfaces of the conductive layers 113c, 113b, and 113a are also exposed to the plasma 130. However, because the gas used in the plasma treatment contains a reducing gas, even if the surfaces are oxidized, they are immediately reduced, thereby preventing the formation of oxides. As a result, even if the conductive layer 113b is made of an easily oxidizable material such as copper or aluminum, oxidation of the conductive layer 113b can be prevented, and water, hydrogen, organic components, and the like adsorbed on the surface of the semiconductor layer 108 can be effectively removed.

[0334] Here, a case where the gas used for plasma treatment does not contain a reducing gas will be described. When a reducing gas is not contained, when the conductive layer 113b is exposed to plasma, an oxide may be formed on part of the conductive layer 113b. If the conductive layer 113a or the conductive layer 113c is made of a material that is easily oxidized, an oxide may also be formed on the surface of the conductive layer 113a or the conductive layer 113c. Oxidation of one or more of the conductive layers 113a, 113b, and 113c increases resistance, which may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, some of the oxide formed on the surface of the conductive layer 113a, 113b, or 113c may scatter during plasma treatment or during subsequent formation of the insulating layer 114, contaminating the surface of the semiconductor layer 108b. The oxide attached to the semiconductor layer 108b may function as a donor or acceptor and may adversely affect the electrical characteristics and reliability of the transistor. For example, when copper elements diffuse into the semiconductor layer 108, the copper elements may function as carrier traps, which may impair electrical characteristics and reliability.

[0335] On the other hand, when a reducing gas is contained in the gas used for the plasma treatment, the surfaces of the conductive layers 113c, 113b, and 113a, especially the side surface of the conductive layer 113b, can be prevented from being oxidized even if the surfaces are exposed. Therefore, the conductive layers 112a and 112b can be prevented from being oxidized, and water, hydrogen, organic components, and the like adsorbed on the surface of the semiconductor layer 108 can be effectively removed, resulting in a highly reliable transistor.

[0336] Furthermore, it is preferable to adjust the plasma treatment time. If the plasma treatment time is long, an oxidation reaction by the oxidizing gas may progress, resulting in oxidation of the conductive layers 113a, 113b, and 113c. If the plasma treatment time is long, a reduction reaction by the second gas may progress, resulting in reduction of the surface of the semiconductor layer 108. Therefore, it is preferable to adjust the plasma treatment time to prevent oxidation of the conductive layers 113a, 113b, and 113c and reduction of the surface of the semiconductor layer 108. The plasma treatment time is preferably, for example, from 5 seconds to 180 seconds, more preferably from 10 seconds to 120 seconds, and even more preferably from 15 seconds to 60 seconds. By setting the treatment time as described above, a transistor with good electrical characteristics and high reliability can be obtained.

[0337] [Formation of insulating layer 114] Subsequently, the insulating layer 114 is formed to cover the conductive layer 112a, the conductive layer 112b, the semiconductor layer 108, and the insulating layer 106.

[0338] The insulating layer 114 is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a plasma CVD method in an atmosphere containing oxygen. This allows the insulating layer 114 to have few defects. Furthermore, the insulating layer 114 preferably releases a lot of ammonia and little nitrogen oxide. By using the insulating layer 114 that releases a lot of ammonia and little nitrogen oxide, a change in the threshold voltage of the transistor can be suppressed, and a change in the electrical characteristics of the transistor can be reduced.

[0339] The insulating layer 114 is preferably formed using an oxide film such as a silicon oxide film or a silicon oxynitride film using a plasma enhanced chemical vapor deposition (PECVD) apparatus (or simply referred to as a plasma CVD) apparatus. In this case, a mixed gas containing a deposition gas containing silicon and an oxidizing gas is preferably used as a source gas. Furthermore, the source gas preferably contains ammonia. By forming the insulating layer 114 using a mixed gas containing ammonia, the insulating layer 114 can emit a large amount of ammonia. The above-mentioned gases can be used as the deposition gas containing silicon. The above-mentioned gases can be used as the oxidizing gas.

[0340] For example, when silicon oxynitride is used as the insulating layer 114, the insulating layer 114 can be formed using a mixed gas containing monosilane, dinitrogen monoxide, and ammonia.

[0341] In forming the insulating layer 114, the ratio of the flow rate of the oxidizing gas to the flow rate of the deposition gas is preferably within the above-described range. Furthermore, the ratio of the flow rate of the ammonia gas to the flow rate of the oxidizing gas is preferably within the above-described range. By setting the flow rates within the above-described range, the insulating layer 114 can emit a large amount of ammonia, and the release of nitrogen oxides from the insulating layer 114 can be reduced, resulting in a transistor with small fluctuation in threshold voltage. Furthermore, by setting the gas flow rates within the above-described range, the insulating layer 114 can be formed with few defects even when the pressure in the treatment chamber is relatively high.

[0342] The pressure in the treatment chamber during the formation of the insulating layer 114 is preferably in the above-described range. By setting the pressure in the above-described range, the insulating layer 114 can be formed with little release of nitrogen oxides and with few defects.

[0343] The insulating layer 114 may be formed using a PECVD method using microwaves. Microwaves refer to frequencies in the range of 300 MHz to 300 GHz. Microwaves have low electron temperatures and small electron energy. Furthermore, a small proportion of the supplied power is used to accelerate electrons, and more can be used to dissociate and ionize molecules, making it possible to excite high-density plasma (high-density plasma). This allows the insulating layer 114 to be formed with fewer defects and with less plasma damage to the surface and deposits to be formed.

[0344] The insulating layer 114 is preferably formed successively after the above-described plasma treatment without exposing the substrate 102 to the air. For example, the plasma treatment is preferably performed in a deposition apparatus for the insulating layer 114. In this case, the plasma treatment is preferably performed in a treatment chamber for forming the insulating layer 114. Alternatively, after the plasma treatment is performed in a treatment chamber connected to the treatment chamber via a gate valve or the like, the substrate may be transferred under reduced pressure to the treatment chamber for the insulating layer 114 without being exposed to the air. When the plasma treatment and the formation of the insulating layer 114 are performed successively in the same treatment chamber in the same apparatus, the plasma treatment and the formation of the insulating layer 114 are preferably performed at the same temperature.

[0345] An example will be described in which a plasma enhanced chemical vapor deposition apparatus is used to perform plasma processing and form the insulating layer 114. The insulating layer 114 is made of silicon oxynitride.

[0346] In the plasma treatment, a mixed gas containing nitrous oxide (NO) as an oxidizing gas and ammonia as a reducing gas is used, and in forming the insulating layer 114, a mixed gas containing monosilane as a deposition gas, nitrous oxide (NO) as an oxidizing gas, and ammonia can be used. Here, dinitrogen monoxide (NO) and ammonia can be commonly used in both the plasma treatment and the formation of the insulating layer 114. That is, the plasma treatment is performed using dinitrogen monoxide (NO) and ammonia, and then the insulating layer 114 can be formed by flowing monosilane gas. In this way, since the plasma treatment and the formation of the insulating layer 114 can be performed consecutively in the same treatment chamber, impurities at the interface between the semiconductor layer 108 and the insulating layer 114 can be reduced, resulting in a good interface.

[0347] After the insulating layer 114 is formed, treatment for supplying oxygen to the insulating layer 114 may be performed. The treatment for supplying oxygen can be performed using a method similar to that for the insulating layer 106.

[0348] [Formation of insulating layer 116] Subsequently, insulating layer 116 is formed to cover insulating layer 114 (FIG. 16A).

[0349] The insulating layer 116 is preferably an insulating film through which oxygen, hydrogen, water, and the like are less likely to diffuse than the insulating layer 114. The insulating layer 116 has a low oxygen diffusion rate, which can prevent oxygen in the semiconductor layer 108 from being released to the outside through the insulating layer 114. The insulating layer 116 has a low hydrogen diffusion rate, which can prevent hydrogen, water, and the like from diffusing from the outside into the semiconductor layer 108 and the like.

[0350] Heat treatment is preferably performed after the insulating layer 116 is formed. By performing the heat treatment, oxygen contained in the insulating layer 114 and the insulating layer 116 diffuses into the semiconductor layer 108, and the oxygen causes oxygen vacancies (V O ) and V O Specifically, the oxygen diffused into the semiconductor layer 108 reduces the oxygen vacancy (V O) is compensated for. In addition, oxygen diffused into the semiconductor layer 108 is compensated for by V O The hydrogen is removed from H and released as a water molecule (HO), and V O H is an oxygen deficiency (V O ) Furthermore, V O Oxygen vacancies (V) formed by the loss of hydrogen from H O ) is filled by other oxygen that reaches the semiconductor layer 108. O ) and V O By reducing H, a highly reliable transistor can be obtained.

[0351] The oxygen diffused into the semiconductor layer 108 reacts with the hydrogen remaining in the semiconductor layer 108 and is released as water molecules (H2O). In other words, hydrogen can be removed from the semiconductor layer 108 (dehydration, dehydrogenation). As a result, the hydrogen remaining in the semiconductor layer 108 becomes an oxygen vacancy (V O ) and V O The generation of H can be suppressed.

[0352] The heat treatment can remove hydrogen and water contained in the insulating layers 116 and 114. Furthermore, the heat treatment can reduce defects in the insulating layers 116 and 114.

[0353] Furthermore, by performing heat treatment, nitrogen oxide contained in the insulating layers 114 and 116 reacts with ammonia contained in the insulating layer 114, thereby reducing the amount of nitrogen oxide contained in the insulating layers 114 and 116. The reduction in nitrogen oxide can suppress a change in the threshold voltage of the transistor, thereby reducing a change in the electrical characteristics of the transistor.

[0354] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 250°C or higher and 450°C or lower, and even more preferably 300°C or higher and 450°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a rare gas, nitrogen, or oxygen. Clean dry air (CDA) may be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. Using an atmosphere with as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being introduced into the insulating layer 116 or the like as much as possible. The heat treatment can be performed in an oven, a rapid thermal annealing (RTA) apparatus, or the like. Using an RTA apparatus can shorten the heat treatment time.

[0355] [Formation of insulating layer 118] Subsequently, insulating layer 118 is formed to cover insulating layer 116 (FIG. 16B).

[0356] The insulating layer 118 is preferably an insulating film through which oxygen, hydrogen, water, and the like are less likely to diffuse than the insulating layers 114 and 116. The insulating layer 118 is less likely to diffuse oxygen, which can prevent oxygen from being released from the insulating layer 116, the insulating layer 114, and the semiconductor layer 108. The insulating layer 118 is less likely to diffuse hydrogen, which can prevent hydrogen, water, and the like from diffusing from the outside into the semiconductor layer 108 and the like. Silicon nitride is particularly suitable for use as the insulating layer 118.

[0357] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, the insulating layer 118, the insulating layer 116, and a part of the insulating layer 114 are etched to form an opening 142a reaching the conductive layer 112b and an opening 142b reaching the conductive layer 104.

[0358] Subsequently, a conductive film is formed so as to cover the openings 142a and 142b, and then the conductive film is processed to form the conductive layers 120a and 120b (FIG. 17A).

[0359] Through the above steps, the transistor 100A can be manufactured.

[0360] <Production method example 2> This section describes a manufacturing method of the transistor 100A that is different from the manufacturing method of the transistor 100A described above in <Manufacturing Method Example 1>. Note that descriptions of parts that overlap with the above description will be omitted, and only differences will be described.

[0361] First, similarly to <Manufacturing Method Example 1>, the steps up to the formation of the insulating layer 116 are formed. The detailed description of the steps up to the formation of the insulating layer 116 can be referred to in the description of FIGS. 13A to 16A, and therefore detailed description thereof will be omitted. After the insulating layer 116 is formed, heat treatment is preferably performed. The detailed description of the heat treatment can be referred to in the above <Manufacturing Method Example 1>, and therefore detailed description thereof will be omitted.

[0362] A metal oxide layer 150 is then formed over the insulating layer 116 (FIG. 18A).

[0363] The metal oxide layer 150 is formed of a material that is less permeable to oxygen and hydrogen. The metal oxide layer 150 has a function of suppressing diffusion of oxygen contained in the insulating layer 114 and the insulating layer 116 to the side opposite to the semiconductor layer 108. The metal oxide layer 150 also has a function of suppressing diffusion of hydrogen and water from the outside to the insulating layer 114 and the insulating layer 116. The metal oxide layer 150 is preferably made of a material that is less permeable to oxygen and hydrogen than at least the insulating layer 114 and the insulating layer 116.

[0364] The metal oxide layer 150 may be an insulating layer or a conductive layer.

[0365] It is preferable to use an insulating material with a higher dielectric constant than silicon oxide as the metal oxide layer 150. For example, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film can be used.

[0366] The metal oxide layer 150 may be a conductive oxide such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0367] It is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 108 for the metal oxide layer 150. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. It is preferable that the sputtering target used to form the metal oxide layer 150 has an atomic ratio of In equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such sputtering targets include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5.

[0368] In-Ga-Zn oxide (IGZO) is particularly suitable for use as the metal oxide layer 150. When the semiconductor layer 108 is an In-Ga-Zn oxide, the sputtering target used to form the In-Ga-Zn oxide preferably has an atomic ratio of In equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such sputtering targets include In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, and In:Ga:Zn=5:2:5.

[0369] The metal oxide layer 150 can be a metal oxide film formed using a sputtering target having the same composition as the semiconductor layer 108. Using a sputtering target having the same composition is preferable because it allows the use of a common manufacturing device and sputtering target.

[0370] When a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 150, a material with a higher gallium content (content rate) than that of the semiconductor layer 108 can be used for the metal oxide layer 150. Using a material with a higher gallium content (content rate) for the metal oxide layer 150 is preferable because it can further improve the blocking property against oxygen. In this case, using a material with a higher indium content than that of the metal oxide layer 150 for the semiconductor layer 108 can increase the field-effect mobility of the transistor 100.

[0371] The metal oxide layer 150 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably supplied to the insulating layer 116, the insulating layer 114, or the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0372] The metal oxide layer 150 is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 116, the insulating layer 114, or the semiconductor layer 108 during the formation of the metal oxide layer 150.

[0373] When the metal oxide layer 150 is formed by a sputtering method using an oxide target containing the same metal oxide as in the case of the semiconductor layer 108, the above method can be applied.

[0374] For example, the metal oxide layer 150 may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. For example, when aluminum is used as the metal target, an aluminum oxide film can be formed.

[0375] When forming the metal oxide layer 150, the higher the ratio of the oxygen flow rate to the total flow rate of the film formation gas introduced into the treatment chamber of the film formation apparatus (oxygen flow rate ratio) or the higher the oxygen partial pressure in the treatment chamber, the more oxygen can be supplied to the insulating layer 116. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0376] By forming the metal oxide layer 150 by a sputtering method in an oxygen-containing atmosphere in this manner, oxygen can be supplied to the insulating layer 116 and oxygen can be prevented from being released from the insulating layer 116 during the formation of the metal oxide layer 150. As a result, an extremely large amount of oxygen can be trapped in the insulating layer 116. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0377] Next, heat treatment is preferably performed to supply oxygen from the insulating layer 116 to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200° C. or higher and 400° C. or lower in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas.

[0378] By performing heat treatment after the metal oxide layer 150 is formed and before the insulating layer 118 is formed, oxygen can be effectively supplied from the insulating layer to the semiconductor layer .

[0379] Next, the metal oxide layer 150 is removed (FIG. 18B). Note that the steps after removing the metal oxide layer 150 are preferably performed at a temperature equal to or lower than the temperature of the heat treatment. This can prevent oxygen from being released from the semiconductor layer 108, and can prevent oxygen vacancies from being formed in the semiconductor layer 108. This can improve the reliability of the transistor.

[0380] Although there is no particular limitation on the method for removing the metal oxide layer 150, wet etching can be suitably used. By using wet etching, it is possible to prevent the insulating layer 116 from being etched simultaneously with the metal oxide layer 150. This makes it possible to prevent the thickness of the insulating layer 116 from becoming thin, and to make the thickness of the insulating layer 116 uniform.

[0381] Subsequently, the insulating layer 118 is formed. Since the description in the above <Manufacturing Method Example 1> can be referred to for the process after the formation of the insulating layer 118, detailed description thereof will be omitted.

[0382] Through the above steps, the transistor 100A can be manufactured.

[0383] <Production method example 3> A method for manufacturing the transistor 100B shown in the above-described Configuration Example 2-3 will be described below. Note that descriptions of parts that overlap with the above description will be omitted, and only differences will be described.

[0384] First, similarly to <Manufacturing Method Example 1>, steps up to forming the resist mask 140 are performed. Since the description of FIGS. 13A to 14A can be referred to for steps up to forming the resist mask 140, detailed description thereof will be omitted.

[0385] Next, the conductive films 113cf, 113bf, and 113af are etched using the resist mask 140. During this etching, the insulating layer 106b in a region that does not overlap with either the resist mask 140 or the semiconductor layer 108 is also removed (FIG. 19A).

[0386] Subsequently, it is preferable to carry out a washing treatment. Since the description of the above-mentioned <Preparation Method Example 1> can be referred to for the washing treatment and subsequent steps, detailed description thereof will be omitted.

[0387] Through the above steps, the transistor 100B can be manufactured (FIG. 19B).

[0388] <Production Method Example 4> A method for manufacturing the transistor 100C shown in Structural Example 2-4 will be described below. Note that descriptions of parts that overlap with the above description will be omitted, and only differences will be described.

[0389] First, the metal oxide film 108af and the metal oxide film 108bf are formed in the same manner as in <Fabrication Method Example 1>. Since the description of FIGS. 13A and 13B can be referred to for the formation of the metal oxide film 108af and the metal oxide film 108bf, detailed description thereof will be omitted.

[0390] Subsequently, after the metal oxide films 108af and 108bf are formed, a resist mask is formed on the metal oxide film 108bf, and the metal oxide films 108af and 108bf are etched using the resist mask to form the semiconductor layer 108. During this etching, the insulating layer 106b in the region not overlapping with the resist mask is also removed (FIG. 20A). Then, the resist mask is removed.

[0391] Heat treatment may be performed after the metal oxide film 108af and the metal oxide film 108bf are formed or after processing into the semiconductor layer 108. For the heat treatment and subsequent steps, the description in the above <Manufacturing Method Example 1> can be referred to, and detailed description thereof will be omitted.

[0392] Through the above steps, the transistor 100C can be manufactured (FIG. 20B).

[0393] According to the method for manufacturing a transistor exemplified here, by using a film that releases a lot of ammonia and little nitrogen oxide as the insulating layer 114 in contact with the semiconductor layer 108, fluctuations in the threshold voltage of the transistor can be suppressed, and a transistor with favorable electrical characteristics and high reliability can be manufactured.

[0394] This completes the description of the example of the method for manufacturing a transistor.

[0395] <Modification of the configuration example> Below, modifications of the above-mentioned exemplary transistor configurations will be described.

[0396] [Variation 1] A transistor 100D illustrated in FIGS. 21A and 21B is different from the transistor 100 illustrated in the above-described Structure example 2-1 mainly in that the conductive layers 112a and 112b do not have a stacked structure but have a single-layer structure.

[0397] The conductive layers 112a and 112b each have a single-layer structure, which can simplify the manufacturing process and improve productivity. The conductive layers 112a and 112b are preferably made of a conductive material containing copper, silver, gold, or aluminum.

[0398] [Variation 2] The transistor 100E shown in Figures 21C and 21D differs from the transistor 100 illustrated in the above-mentioned configuration example 2-1 mainly in that not only the conductive layer 112a and the conductive layer 112b but also the semiconductor layer 108 does not have a stacked structure but has a single-layer structure.

[0399] Productivity can be further increased by forming the semiconductor layer 108 as a single layer in addition to the conductive layers 112a and 112b. In this case, the semiconductor layer 108 is preferably a crystalline metal oxide film.

[0400] [Variation 3] The transistor 100F shown in FIGS. 22A, 22B, and 22C differs from the transistor 100A illustrated in the above-described Configuration example 2-2 mainly in that the positions of the conductive layers 120a and 120b are different.

[0401] The conductive layer 120a and the conductive layer 120b are located between the insulating layer 116 and the insulating layer 118. The conductive layer 120b is electrically connected to the conductive layer 112b through an opening 142a provided in the insulating layer 114 and the insulating layer 116.

[0402] With such a structure, the distance between the conductive layer 120a and the semiconductor layer 108 can be reduced, thereby improving the electrical characteristics of the transistor 100F.

[0403] [Variation 4] The transistor 100G shown in FIGS. 23A, 23B, and 23C differs from the transistor 100 illustrated in the above-described Configuration example 2-1 mainly in that the configuration of the insulating layer 114 is different.

[0404] The insulating layer 114 is processed into an island shape that covers a channel formation region of the semiconductor layer 108. In addition, the ends of the conductive layers 112a and 112b that are located on the semiconductor layer 108 are located on the insulating layer 114. Therefore, the insulating layer 114 functions as a so-called channel protection layer and can protect the back channel side of the semiconductor layer 108 when the conductive layers 112a and 112b are etched.

[0405] At this time, by performing plasma treatment by the above-described method after etching the conductive layers 112a and 112b, the conductive layers 112a and 112b can be prevented from being oxidized and oxygen can be supplied to the insulating layer 114 and to the semiconductor layer 108 through the insulating layer 114. Alternatively, by performing heat treatment after the plasma treatment, oxygen in the insulating layer 114 can be supplied to the semiconductor layer 108.

[0406] [Variation 5] The transistor 100H shown in FIGS. 24A, 24B, and 24C differs from the transistor 100G illustrated in the fourth modification example above mainly in that the insulating layer 114 has a different configuration.

[0407] The insulating layer 114 is provided to cover the semiconductor layer 108, the insulating layer 106, etc. The insulating layer 114 has an opening 142c at a portion where the semiconductor layer 108 is connected to the conductive layer 112a or the conductive layer 112b.

[0408] With this structure, a transistor can be made smaller than when the insulating layer 114 is processed into an island shape.

[0409] According to the manufacturing method of one embodiment of the present invention, by using a film that releases a lot of ammonia and little nitrogen oxide as the insulating layer 114 in contact with the semiconductor layer 108, fluctuations in the threshold voltage of the transistor can be suppressed, and a transistor with favorable electrical characteristics and high reliability can be manufactured.

[0410] The above is a description of the modified example.

[0411] <Application example> An example in which the above transistor is applied to a pixel of a display device will be described below.

[0412] Each diagram in Figure 25 is a schematic top view showing a part of a subpixel of a display device. One subpixel has at least one transistor and a conductive layer (conductive layer 120b in this example) that functions as a pixel electrode. Note that for ease of explanation, an example of the configuration of a part of the subpixel is shown here, but other transistors, capacitors, and the like can be provided as appropriate depending on the type of display element used in the subpixel, functions to be added to the pixel, and the like.

[0413] In Figure 25A, part of the conductive layer 104 functions as a gate line (also called a scan line), part of the conductive layer 112a functions as a source line (also called a video signal line), and part of the conductive layer 112b functions as a wiring that electrically connects the transistor and the conductive layer 120b.

[0414] In FIG. 25A, the conductive layer 104 has a partially protruding top surface, and the semiconductor layer 108 is provided on this protruding portion to form a transistor.

[0415] 25B and 25C show examples in which the conductive layer 104 does not have a protruding portion. Fig. 25B shows an example in which the channel length direction of the semiconductor layer 108 and the extension direction of the conductive layer 104 are parallel, and Fig. 25C shows an example in which they are perpendicular to each other.

[0416] 25D and 25E, the conductive layer 112b has a U-shaped top view with an arc-shaped or approximately arc-shaped portion. The conductive layers 112a and 112b are disposed on the semiconductor layer 108 so that the distance between them is always equidistant. With this configuration, the channel width of the transistor can be increased, allowing a larger current to flow.

[0417] Note that the transistor of one embodiment of the present invention can be applied not only to display devices but also to various circuits and devices, such as arithmetic circuits, memory circuits, driver circuits, and interface circuits in IC chips mounted in electronic devices, display devices using liquid crystal elements, organic EL elements, and driver circuits in various sensor devices such as touch sensors, optical sensors, and biosensors.

[0418] The above is a description of the application example.

[0419] <Components of semiconductor device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0420] 〔substrate〕 Although there are no significant limitations on the material of the substrate 102, it is necessary that the substrate 102 has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102.

[0421] A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device, which is partially or entirely completed thereon, from the substrate 102 and transfer it to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0422] [Insulating layer 106] The insulating layer 106 can be formed, for example, using a single layer or a stack of an oxide insulating film or a nitride insulating film. Note that in order to improve the interface characteristics with the semiconductor layer 108, at least a region of the insulating layer 106 that is in contact with the semiconductor layer 108 is preferably formed using an oxide insulating film. Furthermore, the insulating layer 106 is preferably formed using a film that releases oxygen when heated.

[0423] The insulating layer 106 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like, and can be formed as a single layer or a stacked layer.

[0424] When a film other than an oxide film, such as a silicon nitride film, is used on the side of the insulating layer 106 that is in contact with the semiconductor layer 108, it is preferable to perform pretreatment such as oxygen plasma treatment on the surface that is in contact with the semiconductor layer 108, and oxidize the surface or the vicinity of the surface.

[0425] [Conductive film] Conductive films that constitute a semiconductor device, such as the conductive layer 104 and the conductive layer 120a that function as a gate electrode, the conductive layer 120b that functions as a wiring, the conductive layer 112a that functions as one of a source electrode and a drain electrode, and the conductive layer 112b that functions as the other of the source electrode and the drain electrode, can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, or cobalt, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements.

[0426] In particular, the conductive layer 112a functioning as one of the source electrode and the drain electrode and the conductive layer 112b functioning as the other of the source electrode and the drain electrode are preferably made of a low-resistance conductive material containing copper, silver, gold, aluminum, or the like. Copper or aluminum is particularly preferable because of its excellent mass productivity.

[0427] As the conductive film constituting the semiconductor device, oxide conductors or metal oxide films such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, and In-Ga-Zn oxide can also be used.

[0428] Here, oxide conductors (OC) will be explained. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0429] The conductive film constituting the semiconductor device may have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. The use of a conductive film containing a metal or an alloy can reduce wiring resistance. In this case, it is preferable to use a conductive film containing an oxide conductor on the side in contact with an insulating layer that functions as a gate insulating layer.

[0430] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive layer 104, the conductive layer 112a, and the conductive layer 112b. By using a Cu-X alloy film, it can be processed by a wet etching process, which reduces manufacturing costs.

[0431] [Insulating layer 114, insulating layer 116] The insulating layer 114 provided over the semiconductor layer 108 can be an insulating layer including one or more of a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film, which are formed by a PECVD method, a sputtering method, an ALD method, or the like. In particular, it is preferable to use a silicon oxide film or a silicon oxynitride film formed by a plasma CVD method. Note that the insulating layer 114 may have a stacked structure of two or more layers.

[0432] The insulating layer 116 functioning as a protective layer can be an insulating layer including one or more films such as a silicon nitride oxide film, a silicon nitride film, an aluminum nitride film, and an aluminum nitride oxide film, which are formed by a PECVD method, a sputtering method, an ALD method, etc. Note that the insulating layer 116 may have a stacked structure of two or more layers.

[0433] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of metal elements in a sputtering target used to form the In-M-Zn oxide film is, for example, In:M:Zn=5:1:1, In:M:Zn=5:1:2, In:M:Zn=5:1:3, In:M:Zn=5:1:4, In:M:Zn=5:1:5, In:M:Zn=5:1:6, In:M:Zn=10:1:1, In In:M:Zn=10:1:2, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:5, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=10:1:10, In:M:Zn=10:1:12, In:M:Zn=10:1:15, or a similar ratio thereof, can be suitably used.

[0434] When the semiconductor layer 108 is made of indium oxide, indium oxide can be used as a sputtering target for depositing the indium oxide.

[0435] When the semiconductor layer 108 is an In-M oxide, the atomic ratio of the metal elements in the sputtering target used to deposit the In-M oxide can be, for example, In:M=2:1, In:M=7:2, In:M=5:1, In:M=7:1, In:M=10:1, or a ratio close to these.

[0436] When the semiconductor layer 108 is an In-Zn oxide, the atomic ratio of the metal elements in the sputtering target used to form the In-Zn oxide film can be, for example, In:Zn=2:3, In:Zn=3:2, In:Zn=7:2, In:Zn=4:1, In:Zn=11:2, In:Zn=7:1, In:Zn=14:1, or a ratio close to these.

[0437] It is preferable to use a target containing a polycrystalline oxide as the sputtering target because it facilitates the formation of a crystalline semiconductor layer 108. Note that the atomic ratio of the semiconductor layer 108 to be formed varies within a range of ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=5:1:3 <atomic ratio>, the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=5:1:2.4 <atomic ratio>.

[0438] Metal oxides formed by sputtering using the above target at a substrate temperature of 100°C to 130°C tend to have either an nc (nano crystal) structure or a CAAC structure, or a mixture of these. On the other hand, metal oxides formed by sputtering at room temperature tend to have an nc crystal structure.

[0439] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon, the off-state current of the transistor can be reduced.

[0440] The above is a description of the components.

[0441] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0442] (Embodiment 3) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[0443] <Configuration example> 26A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 attached to each other with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided on the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0444] An FPC terminal portion 708 to which an FPC (Flexible Printed Circuit) 716 is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied by the FPC 716 to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 via the FPC terminal portion 708 and signal lines 710.

[0445] There may be a plurality of gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0446] The transistor that is a semiconductor device of one embodiment of the present invention can be used as the transistor included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706.

[0447] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element. Examples of the light-emitting element include a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Examples of the light-emitting element include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, and a display element that employs a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type.

[0448] Display device 700A shown in FIG. 26B is an example of a display device that uses a flexible resin layer 743 instead of first substrate 701 and can be used as a flexible display.

[0449] In the display device 700A, the pixel portion 702 is not rectangular, but has arc-shaped corners. Furthermore, as shown in region P1 in FIG. 26B , the pixel portion 702 and the resin layer 743 have cutouts formed by cutting out parts of the pixel portion 702 and the resin layer 743. A pair of gate driver circuit units 706 are provided on either side of the pixel portion 702. The gate driver circuit units 706 are also provided at the corners of the pixel portion 702 along the arc-shaped contour.

[0450] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. In addition, a portion of the resin layer 743, including the FPC terminal portion 708, can be folded back to the rear side in region P2 in FIG. 26B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on an electronic device with the FPC 716 disposed on the rear side of the pixel portion 702, thereby enabling space saving of the electronic device.

[0451] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 functions as, for example, a source driver circuit. In this case, the source driver circuit unit 704 in the display device 700B can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, etc.

[0452] 26C is a display device that can be suitably used in electronic devices having large screens, such as televisions, monitors, personal computers (including notebook and desktop computers), tablet terminals, and digital signage.

[0453] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0454] The plurality of source driver ICs 721 are each attached to an FPC 723. One terminal of each of the plurality of FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0455] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0456] This configuration makes it possible to realize a large-sized, high-resolution display device. For example, it can be applied to display devices with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more. It can also realize a display device with an extremely high resolution, such as 4K2K or 8K4K.

[0457] <Example of cross-sectional configuration> Below, configurations using liquid crystal elements and EL elements as display elements will be described with reference to Figs. 27 to 31. Figs. 27 to 30 are cross-sectional views taken along dashed dotted line QR in Fig. 26A. Fig. 31 is a cross-sectional view taken along dashed dotted line ST in display device 700A shown in Fig. 26B. Figs. 27 to 29 show configurations using liquid crystal elements as display elements, while Figs. 30 and 31 show configurations using EL elements.

[0458] [Explanation of common parts of the display device] 27 to 31 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. FIG. 28 shows a case where the capacitor 790 is not included.

[0459] The transistors described in Embodiment 2 can be used as the transistors 750 and 752.

[0460] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which oxygen vacancies are suppressed. The off-state current of the transistor can be reduced. Therefore, the retention time of an electric signal such as an image signal can be increased, and the interval between writing of the image signal can also be set longer. Therefore, the frequency of a refresh operation can be reduced, thereby achieving an effect of reducing power consumption.

[0461] The transistor used in this embodiment has a relatively high field-effect mobility and can therefore be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. That is, a configuration without using a driver circuit formed using a silicon wafer or the like is possible, and the number of components in the display device can be reduced. Furthermore, by using a transistor capable of high-speed driving in the pixel portion, a high-quality image can be provided.

[0462] 27, 30, and 31 includes a lower electrode formed by processing the same film as the gate electrode of the transistor 750, and an upper electrode formed by processing the same conductive film as the source or drain electrode. In addition, a part of an insulating film functioning as a gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.

[0463] A planarization insulating film 770 is provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0464] The transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the gate driver circuit portion 706 is similar to the source driver circuit portion 704.

[0465] The signal line 710 is formed using the same conductive film as the source and drain electrodes of the transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, because this reduces signal delays and enables display on a large screen.

[0466] The FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the connection electrode 760 is formed using the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752.

[0467] A flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 750 or the like.

[0468] On the second substrate 705 side, a light-shielding layer 738, a colored layer 736, and an insulating layer 734 in contact with these are provided.

[0469] [Configuration example of a display device using a liquid crystal element] The display device 700 shown in FIG. 27 includes a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over a planarization insulating film 770 and functions as a pixel electrode.

[0470] A material that transmits or reflects visible light can be used for the conductive layer 772. For example, an oxide material containing indium, zinc, tin, or the like can be used as the light-transmitting material. For example, a material containing aluminum, silver, or the like can be used as the reflective material.

[0471] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich the liquid crystal element.

[0472] 28 shows an example of a display device 700 using a horizontal field mode (e.g., FFS mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0473] 28, a storage capacitor can be formed using a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0474] 27 and 28, an alignment film may be provided in contact with the liquid crystal layer 776. In addition, optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0475] Thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. When the in-plane switching mode is adopted, liquid crystal that exhibits a blue phase without using an alignment film may also be used.

[0476] The liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0477] A scattering type liquid crystal such as a polymer dispersed liquid crystal or a polymer network liquid crystal may be used for the liquid crystal layer 776. In this case, a configuration may be adopted in which black and white display is performed without providing the colored layer 736, or a configuration may be adopted in which color display is performed by using the colored layer 736.

[0478] A time-sequential display method (also called a field-sequential driving method) that performs color display based on a time-sequential additive color mixture method may be applied as a driving method for the liquid crystal element. In this case, the coloring layer 736 may not be provided. When the time-sequential display method is used, there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue), which has the advantage of improving the pixel aperture ratio and increasing the resolution.

[0479] FIG. 29 shows an example in which a liquid crystal element 775 of a horizontal electric field type (for example, FFS mode) is used, which is different from the display device 700 shown in FIG.

[0480] 29 includes a transistor 750, a transistor 752, a liquid crystal element 775, and the like between a first substrate 701 and a second substrate 705. The first substrate 701 and the second substrate 705 are bonded to each other with a sealing layer 732.

[0481] The liquid crystal element 775 includes a conductive layer 714, a liquid crystal layer 776, and a conductive layer 713. The conductive layer 713 is provided over a first substrate 701. One or more insulating layers are provided over the conductive layer 713, and the conductive layer 714 is provided over the insulating layers. The liquid crystal layer 776 is located between the conductive layer 714 and a second substrate 705. The conductive layer 713 is electrically connected to a wiring 728 and functions as a common electrode. The conductive layer 714 is electrically connected to a transistor 750 and functions as a pixel electrode. A common potential is applied to the wiring 728.

[0482] The conductive layer 714 has a comb-like shape or a slit-like top surface. In the liquid crystal element 775, the alignment state of the liquid crystal layer 776 is controlled by an electric field generated between the conductive layer 714 and the conductive layer 713.

[0483] A capacitor 790 functioning as a storage capacitor is formed by a stacked structure of the conductive layer 714, the conductive layer 713, and one or more insulating layers sandwiched between them. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0484] A material that transmits or reflects visible light can be used for the conductive layer 714 and the conductive layer 713. As a light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As a reflective material, for example, a material containing aluminum, silver, or the like can be used.

[0485] When a reflective material is used for either or both of the conductive layer 714 and the conductive layer 713, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for both the conductive layer 714 and the conductive layer 713, the display device 700 becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich the liquid crystal element.

[0486] 29 shows an example of a transmissive liquid crystal display device. A polarizing plate 755 and a light source 757 are provided on the outer side of a first substrate 701, and a polarizing plate 756 is provided on the outer side of a second substrate 705. The light source 757 functions as a backlight.

[0487] A light-shielding layer 738 and a colored layer 736 are provided on the surface of the second substrate 705 facing the first substrate 701. An insulating layer 734 functioning as a planarizing layer is provided to cover the light-shielding layer 738 and the colored layer 736. A spacer 727 is provided on the surface of the insulating layer 734 facing the first substrate 701.

[0488] The liquid crystal layer 776 is located between an alignment film 725 that covers the conductive layer 714 and an alignment film 726 that covers the insulating layer 734. Note that the alignment films 725 and 726 do not have to be provided if they are not necessary.

[0489] 29, optical members (optical films) such as a retardation film and an anti-reflection film, a protective film, an anti-fouling film, etc. may be appropriately provided outside the second substrate 705. Examples of anti-reflection films include an AG (Anti Glare) film and an AR (Anti Reflection) film.

[0490] 29 has a structure in which an organic insulating film functioning as a planarization layer is not provided on the formation surface side of a conductive layer 714 functioning as a pixel electrode or a conductive layer 713 functioning as a common electrode. Furthermore, bottom-gate transistors, which can be manufactured in a relatively short time, are used as transistors 750 and the like included in the display device 700. This structure reduces manufacturing costs and increases manufacturing yield, making it possible to provide a highly reliable display device at low cost.

[0491] [Configuration example of a display device using light-emitting elements] 30 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0492] Examples of materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, and examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0493] 30, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element that includes a light-transmitting conductive film 788. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0494] The coloring layer 736 is provided at a position overlapping with the light-emitting element 782, and the light-shielding layer 738 is provided at a position overlapping with the insulating film 730, in the lead-out wiring portion 711, and in the source driver circuit portion 704. The coloring layer 736 and the light-shielding layer 738 are covered with an insulating layer 734. The space between the light-emitting element 782 and the insulating layer 734 is filled with a sealing layer 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when the EL layer 786 is formed by coloring, the coloring layer 736 may not be provided.

[0495] A configuration of a display device that can be suitably applied to a flexible display is shown in Fig. 31. Fig. 31 is a cross-sectional view taken along dashed line ST in display device 700A shown in Fig. 26B.

[0496] 31 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744, instead of the first substrate 701 shown in FIG. 30. A transistor 750, a capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.

[0497] The support substrate 745 is a substrate containing organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. It is preferable that the resin layer 743 is thinner than the support substrate 745.

[0498] 31 has a protective layer 740 instead of the second substrate 705 shown in FIG. 30. The protective layer 740 is bonded to the sealing layer 732. A glass substrate, a resin film, or the like can be used as the protective layer 740. Furthermore, an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are stacked may be used as the protective layer 740.

[0499] The EL layer 786 of the light-emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By forming the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using the colored layer 736. A protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably an inorganic insulating film. More preferably, the protective layer 741 has a stacked structure including at least one inorganic insulating film and at least one organic insulating film.

[0500] FIG. 31 shows a bendable region P2. In region P2, in addition to a support substrate 745 and an adhesive layer 742, there is a portion where no inorganic insulating film, such as an insulating layer 744, is provided. Furthermore, in region P2, a resin layer 746 is provided to cover the connection electrodes 760. By not providing an inorganic insulating film in the bendable region P2 and by using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are stacked, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing a support substrate 745 in region P2, a portion of the display device 700A can be bent with an extremely small radius of curvature.

[0501] [Configuration example in which an input device is provided on a display device] An input device may be provided in the display device 700 shown in Figures 27 to 30 or the display device 700A shown in Figure 31. Examples of the input device include a touch sensor.

[0502] For example, various types of sensors can be used, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, a pressure sensitive type, etc. Alternatively, two or more of these types may be used in combination.

[0503] The touch panel may be configured as a so-called in-cell touch panel in which the input device is formed inside a pair of substrates, a so-called on-cell touch panel in which the input device is formed on the display device 700, or a so-called out-cell touch panel in which the input device is attached to the display device 700.

[0504] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0505] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0506] (Fourth embodiment) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 32A to 32C.

[0507] 32A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0508] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention may also be applied to the protection circuit 506.

[0509] The pixel section 502 has a plurality of pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element.

[0510] The driver circuit unit 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may include at least a shift register. The source driver 504b may include, for example, a plurality of analog switches. Alternatively, the source driver 504b may include a shift register.

[0511] The terminal portion 507 is a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0512] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 32A is connected to various wirings, such as gate lines GL_1 to GL_X that are wirings between the gate driver 504a and the pixel circuit 501, or data lines DL_1 to DL_Y that are wirings between the source driver 504b and the pixel circuit 501. Note that in Fig. 32A, the protection circuit 506 is hatched to distinguish it from the pixel circuit 501.

[0513] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel portion 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0514] The plurality of pixel circuits 501 shown in FIG. 32A can have the configurations shown in FIGS. 32B and 32C, for example.

[0515] 32B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0516] The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Alternatively, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0517] 32C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is also connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0518] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the gate of the transistor 554, thereby controlling the luminance of light emitted from the light-emitting element 572.

[0519] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0520] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0521] (Embodiment 5) A pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described below. The transistors described in Embodiment 2 can be used as transistors for the pixel circuits described below.

[0522] <Circuit configuration> 33A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0523] The transistor M1 has a gate connected to the wiring G1, one of a source and a drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of a source and a drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0524] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but representative examples include light-emitting elements such as organic EL elements and LED elements, liquid crystal elements, and MEMS (Micro Electro Mechanical Systems) elements.

[0525] The node connecting the transistor M1 and the capacitor C1 is defined as N1, and the node connecting the transistor M2 and the circuit 401 is defined as N2.

[0526] In the pixel circuit 400, the potential of the node N1 can be maintained by turning off the transistor M1. In addition, the potential of the node N2 can be maintained by turning off the transistor M2. In addition, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is in the off state, the potential of the node N2 can be changed in accordance with the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0527] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 2, can be used as one or both of the transistors M1 and M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period for holding the potentials of the nodes is short (specifically, when the frame frequency is 30 Hz or higher), a transistor including a semiconductor such as silicon may be used.

[0528] <Driving method example> Next, an example of an operation method of pixel circuit 400 will be described with reference to Fig. 33B. Fig. 33B is a timing chart relating to the operation of pixel circuit 400. Note that, to simplify the explanation, the influence of various resistances such as wiring resistance, parasitic capacitance of transistors and wiring, and threshold voltage of transistors will not be taken into consideration.

[0529] 33B, one frame period is divided into period T1 and period T2. Period T1 is a period in which a potential is written to node N2, and period T2 is a period in which a potential is written to node N1.

[0530] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supply.

[0531] The node N1 is connected to the line S1 via the transistor M1. ref The node N2 is supplied with a first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is maintained.

[0532] [Period T2] Subsequently, in a period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be floating.

[0533] The node N1 is supplied with a second data potential V data At this time, the second data potential V data The potential of the node N2 changes by the potential dV in response to the second data potential Vw. That is, the potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401. Note that although dV is shown as a positive value in FIG. 33B, it may be a negative value. That is, the second data potential V data is the potential V ref It may be lower.

[0534] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential is close to

[0535] In this way, the pixel circuit 400 can combine two types of data signals to generate a potential to be supplied to the circuit 401 including a display element, and therefore, gray scale correction can be performed within the pixel circuit 400.

[0536] The pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Furthermore, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0537] <Application example> [Example using liquid crystal element] The pixel circuit 400LC shown in Fig. 33C includes a circuit 401LC. The circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0538] The liquid crystal element LC has one electrode connected to the node N2 and one electrode of the capacitor C2, and the other electrode connected to the potential V com2 The capacitor C2 is connected to the wiring where the other electrode is at potential V com1 Connect with the wiring given.

[0539] The capacitor C2 functions as a storage capacitor. Note that the capacitor C2 can be omitted if not required.

[0540] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, which makes it possible to, for example, achieve high-speed display by overdriving, apply a liquid crystal material with a high driving voltage, etc. Furthermore, by supplying a correction signal to the line S1 or the line S2, it is possible to correct the gradation in accordance with the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0541] [Example using light-emitting element] The pixel circuit 400EL shown in Fig. 33D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0542] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, a source and a drain connected to a wiring to which a potential VH is applied, and the other connected to one electrode of the light-emitting element EL. com The other electrode of the light-emitting element EL is connected to a wiring to which a potential V L Connect with the wiring given.

[0543] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if it is not necessary.

[0544] Although the anode side of the light-emitting element EL is connected to the transistor M3 in this example, the transistor M3 may be connected to the cathode side. H and potential V L The value of can be changed as appropriate.

[0545] In the pixel circuit 400EL, by applying a high potential to the gate of the transistor M3, a large current can flow through the light-emitting element EL, thereby realizing, for example, HDR display, etc. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0546] It should be noted that the circuits are not limited to those illustrated in FIGS. 33C and 33D, and may be configured to include additional transistors, capacitors, and the like.

[0547] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0548] (Sixth embodiment) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0549] A display module 6000 shown in FIG. 34A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0550] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0551] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0552] The display device 6006 may have a function as a touch panel.

[0553] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0554] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, etc. The power supply may be a battery 6011.

[0555] FIG. 34B is a cross-sectional schematic diagram of a display module 6000 with an optical touch sensor.

[0556] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0557] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guide portion 6017a and a light guide portion 6017b.

[0558] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and passes through light-guiding unit 6017b to reach light-receiving unit 6016. When light 6018 is blocked by a detection target such as a finger or a stylus, a touch operation can be detected.

[0559] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0560] The light-emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light-receiving unit 6016 may be a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode that can receive infrared light may be used.

[0561] The light guiding portions 6017a and 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0562] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0563] (Embodiment 7) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0564] Electronic device 6500 shown in FIG. 35A is a portable information terminal that can be used as a smartphone.

[0565] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0566] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0567] FIG. 35B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0568] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0569] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0570] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0571] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0572] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0573] (Embodiment 8) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described.

[0574] The electronic devices exemplified below each include a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices can achieve high resolution. Furthermore, the electronic devices can also have both high resolution and a large screen.

[0575] The display portion of the electronic device of one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0576] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0577] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0578] 36A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0579] 36A can be operated using operation switches provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0580] The television device 7100 may also include a television broadcast receiver and a communication device for network connection.

[0581] 36B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0582] 36C and 36D show an example of digital signage.

[0583] 36C includes a housing 7301, a display unit 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0584] 36D shows a digital signage 7400 attached to a cylindrical pole 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pole 7401.

[0585] The larger the display unit 7500, the more information can be provided at one time, and the larger the display unit 7500 is, the more easily it will catch people's attention, which will have the effect of increasing the advertising effectiveness of advertisements, for example.

[0586] It is preferable to use a touch panel for the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes but also for providing users with information they require, such as route information, traffic information, and commercial facility guidance information.

[0587] 36C and 36D, it is preferable that the digital signage 7300 or the digital signage 7400 can wirelessly connect to an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0588] A game using the information terminal device 7311 as an operation means (controller) can also be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0589] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 36A to 36D.

[0590] Although the electronic devices in this embodiment have a display portion, one embodiment of the present invention can also be applied to electronic devices that do not have a display portion.

[0591] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0592] 10, 10A, 10B, 10C: transistors, 11, 13, 15, 17: ranges, 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H: transistors, 102: substrate, 104: conductive layer, 106, 106a, 106a1, 106a2, 106a3, 106b: insulating layer, 108, 108a, 108b: semiconductor layer, 108af , 108bf: metal oxide film, 112: gate electrode, 112a, 112b, 113, 113a, 113b, 113c: conductive layer, 113af, 113bf, 113cf: conductive film, 114, 116, 118: insulating layer, 120, 120a, 120b: conductive layer, 130: plasma, 140: resist mask, 142a, 142b, 142c: opening, 150: metal oxide layer

Claims

1. a first conductive layer, a first insulating layer, a semiconductor layer, a second conductive layer, and a second insulating layer; the first conductive layer functions as a gate electrode of a transistor; the first insulating layer has a region that forms an upper surface of the first conductive layer; the semiconductor layer has a region in contact with an upper surface of the first insulating layer and a channel formation region of the transistor; the second conductive layer has a region in contact with a top surface of the semiconductor layer and functions as one of a source electrode and a drain electrode of the transistor; the semiconductor layer comprises indium and oxygen; the semiconductor layer has a composition within a range connecting a first coordinate (1:0:0), a second coordinate (2:1:0), a third coordinate (14:7:1), a fourth coordinate (7:2:2), a fifth coordinate (14:4:21), a sixth coordinate (2:0:3), and the first coordinate in this order with straight lines in a ternary diagram showing the atomic ratio of indium, an element M, and zinc; the element M is at least one of gallium, aluminum, yttrium, and tin; the second conductive layer has a stacked structure of a first conductive film, a second conductive film having a region located above the first conductive film, and a third conductive film having a region located above the second conductive film; the second insulating layer has a region in contact with an upper surface of the semiconductor layer, a region in contact with an upper surface of the first conductive film, a region in contact with a side surface of the first conductive film, a region in contact with a side surface of the second conductive film, a region in contact with a side surface of the third conductive film, and a region in contact with an upper surface of the third conductive film.

2. a first conductive layer, a first insulating layer, a semiconductor layer, a second conductive layer, and a second insulating layer; the first conductive layer functions as a gate electrode of a transistor; the first insulating layer has a region that forms an upper surface of the first conductive layer; the semiconductor layer has a region in contact with an upper surface of the first insulating layer and a channel formation region of the transistor; the second conductive layer has a region in contact with a top surface of the semiconductor layer and functions as one of a source electrode and a drain electrode of the transistor; the semiconductor layer comprises indium and oxygen; the semiconductor layer has a composition within a range connecting a first coordinate (1:0:0), a second coordinate (2:1:0), a third coordinate (14:7:1), a fourth coordinate (7:2:2), a fifth coordinate (14:4:21), a sixth coordinate (2:0:3), and the first coordinate in this order with straight lines in a ternary diagram showing the atomic ratio of indium, an element M, and zinc; the element M is at least one of gallium, aluminum, yttrium, and tin; the second conductive layer has a stacked structure of a first conductive film, a second conductive film having a region located above the first conductive film, and a third conductive film having a region located above the second conductive film; the second conductive film includes copper, silver, gold, or aluminum; the first conductive film and the third conductive film each contain an element different from that of the second conductive film; the first conductive film and the third conductive film each independently contain any one of titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, and ruthenium; the second insulating layer has a region in contact with an upper surface of the semiconductor layer, a region in contact with an upper surface of the first conductive film, a region in contact with a side surface of the first conductive film, a region in contact with a side surface of the second conductive film, a region in contact with a side surface of the third conductive film, and a region in contact with an upper surface of the third conductive film.

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