Semiconductor Devices

Abstract

To provide a semiconductor device having favorable electrical characteristics. To provide a semiconductor device having high reliability.SOLUTION: A semiconductor device comprises a semiconductor layer, a first insulating layer over the semiconductor layer, and a conductive layer over the first insulating layer. The semiconductor layer comprises a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second regions sandwich the first region, the third regions sandwich the first region and the second regions, and the fourth regions sandwich the first region, the second regions, and the third regions. The first region comprises a region overlapping with the first insulating layer and the conductive layer. The second regions and the third regions each comprise a region overlapping with the first insulating layer and not overlapping with the conductive layer. The fourth regions overlap with neither the first insulating layer nor the conductive layer. A thickness of the first insulating layer in regions overlapping with the second regions is substantially equal to a thickness of the first insulating layer in a region overlapping with the first region. A thickness of the first insulating layer in regions overlapping with the third regions is smaller than the thickness of the first insulating layer in the regions overlapping with the second regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a display device, and a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have attracted attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing the field-effect mobility (sometimes simply referred to as mobility, or μFE).

[0004] Metal oxides that can be used for semiconductor layers can be formed by sputtering or other methods, and therefore can be used for the semiconductor layers of transistors that constitute large display devices. Furthermore, since it is possible to use a part of the production equipment for transistors that use polycrystalline silicon or amorphous silicon by modifying it, capital investment can be reduced. Furthermore, transistors that use metal oxides have higher field-effect mobility than transistors that use amorphous silicon, and therefore high-performance display devices equipped with driver circuits can be realized.

[0005] Display devices are becoming larger in screen size, with development underway to screen sizes of 60 inches or more, and even 120 inches or more. In addition, screen resolution is also trending higher, from full high definition (1920 x 1080 pixels, also known as "2K"), ultra high definition (3840 x 2160 pixels, also known as "4K"), and super high definition (7680 x 4320 pixels, also known as "8K").

[0006] Larger screen sizes and higher definitions tend to increase the wiring resistance within the display unit. Patent Document 2 discloses a technology for forming a low-resistance wiring layer using copper (Cu) in order to suppress the increase in wiring resistance in a liquid crystal display device using amorphous silicon transistors. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-163901 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first insulating layer over the semiconductor layer, and a conductive layer over the first insulating layer. The semiconductor layer includes a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second region sandwiches the first region, the third region sandwiches the first and second regions, and the fourth region sandwiches the first, second, and third regions. The first region has a region overlapping with the first insulating layer and the conductive layer, and the second and third regions each have a region overlapping with the first insulating layer but not overlapping with the conductive layer, and the fourth region overlaps with neither the first insulating layer nor the conductive layer. The thickness of the first insulating layer in the region overlapping with the second region is approximately equal to the thickness of the first insulating layer in the region overlapping with the first region. The thickness of the first insulating layer in the region overlapping with the third region is thinner than the thickness of the first insulating layer in the region overlapping with the second region.

[0011] Preferably, the aforementioned semiconductor device further comprises a second insulating layer, the second insulating layer being in contact with the upper surface and side surfaces of the first insulating layer and the upper surface of the fourth region.

[0012] In the above-described semiconductor device, the first insulating layer preferably includes an oxide or an oxynitride, and the second insulating layer preferably includes an oxide or an oxynitride.

[0013] In the above-described semiconductor device, the first insulating layer preferably contains an oxide or an oxynitride, and the second insulating layer preferably contains a nitride or an oxynitride.

[0014] In the semiconductor device described above, the third region and the fourth region each preferably contain a first element. The concentration of the first element in the third region is preferably higher than the concentration of the first element in the second region, and the concentration of the first element in the fourth region is preferably higher than the concentration of the first element in the third region. The first element is preferably one or more of hydrogen, boron, nitrogen, and phosphorus.

[0015] In the above-mentioned semiconductor device, it is preferable that the resistance of the second region is lower than the resistance of the first region, the resistance of the third region is lower than the resistance of the second region, and the resistance of the fourth region is lower than the resistance of the third region.

[0016] In the semiconductor device described above, the resistance of the third region is at least twice the resistance of the second region, 1×10 3 It is preferable that the ratio is 1:1 or less.

[0017] In the semiconductor device described above, the thickness of the first insulating layer in the portion overlapping with the third region is preferably 0.2 to 0.9 times the thickness of the first insulating layer in the portion overlapping with the second region.

[0018] In the above-described semiconductor device, the width of the second region and the width of the third region are preferably not less than 50 nm and not more than 1 μm.

[0019] In the above-described semiconductor device, the semiconductor layer preferably contains indium, an element M, and zinc, and the element M is preferably one or more of aluminum, gallium, yttrium, and tin.

[0020] One embodiment of the present invention is a method for manufacturing a semiconductor device, including the steps of: forming an island-shaped semiconductor layer, forming an insulating film over the semiconductor layer, forming a conductive film over the insulating film, forming a first resist mask over the conductive film, the edge of which is located inside an edge of the semiconductor layer, etching the conductive film using the first resist mask to form a conductive layer whose edge is located inside an edge of the first resist mask, etching the insulating film using the first resist mask to form a first insulating layer, shrinking the first resist mask to form a second resist mask whose edge is located outside an edge of the conductive layer, etching part of an upper portion of the first insulating layer using the second resist mask to form a second insulating layer, removing the second resist mask, forming a third insulating layer over the conductive layer, the second insulating layer, and the semiconductor layer, and supplying a first element to the semiconductor layer through the second insulating layer and the third insulating layer, where the first element is one or more of hydrogen, boron, nitrogen, and phosphorus.

[0021] In the above-described method for manufacturing a semiconductor device, the step of supplying the first element is preferably performed successively after the step of forming the third insulating layer without exposure to the atmosphere.

[0022] In the above-described method for manufacturing a semiconductor device, it is preferable that the step of forming the conductive layer is performed by wet etching, and the step of forming the first insulating layer and the step of forming the second insulating layer are each performed by dry etching. [Effects of the Invention]

[0023] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a method for manufacturing a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a method for manufacturing a highly reliable semiconductor device can be provided. Alternatively, a novel method for manufacturing a semiconductor device can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0025] [Figure 1] 1A, 1B, and 1C are diagrams showing configuration examples of a semiconductor device. [Figure 2] 2A, 2B, and 2C are diagrams showing configuration examples of a semiconductor device. [Figure 3] 3A and 3B are diagrams showing configuration examples of a semiconductor device. [Figure 4] 4A and 4B are diagrams showing configuration examples of a semiconductor device. [Figure 5] Fig. 5A is a top view of the semiconductor device, and Fig. 5B and Fig. 5C are cross-sectional views of the semiconductor device. [Figure 6] 6A and 6B are cross-sectional views of the semiconductor device. [Figure 7] Fig. 7A is a top view of the semiconductor device, and Fig. 7B and Fig. 7C are cross-sectional views of the semiconductor device. [Figure 8] 8A, 8B, and 8C are cross-sectional views of the semiconductor device. [Figure 9] 9A is a top view of the semiconductor device, and FIGS. 9B and 9C are cross-sectional views of the semiconductor device. [Figure 10] 10A and 10B are cross-sectional views of the semiconductor device. [Figure 11] 11A, 11B, and 11C are cross-sectional views of the semiconductor device. [Figure 12] FIG. 12 is a cross-sectional view of the semiconductor device. [Figure 13] Fig. 13A is a top view of the semiconductor device, and Fig. 13B and Fig. 13C are cross-sectional views of the semiconductor device. [Figure 14] FIG. 14 is a cross-sectional view of the semiconductor device. [Figure 15] 15A, 15B, 15C, and 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 16] 16A, 16B, and 16C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 17] 17A, 17B, and 17C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 18] 18A, 18B, and 18C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 19] 19A, 19B, 19C, and 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 20] 20A, 20B, and 20C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 21] 21A to 21C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 22] 22A, 22B, and 22C are top views of the display device. [Figure 23] FIG. 23 is a cross-sectional view of the display device. [Figure 24] FIG. 24 is a cross-sectional view of the display device. [Figure 25] FIG. 25 is a cross-sectional view of the display device. [Figure 26] FIG. 26 is a cross-sectional view of the display device. [Figure 27] Figure 27A is a block diagram of the display device, and Figures 27B and 27C are circuit diagrams of the display device. [Figure 28] 28A, 28C, and 28D are circuit diagrams of the display device, and Fig. 28B is a timing chart of the display device. [Figure 29] Fig. 29A is a diagram showing an example of the configuration of a display module, and Fig. 29B is a schematic cross-sectional view of the display module. [Figure 30] Fig. 30A is a diagram showing a configuration example of an electronic device, and Fig. 30B is a schematic cross-sectional view of the electronic device. [Figure 31] 31A, 31B, 31C, 31D, and 31E are diagrams showing configuration examples of electronic devices. [Figure 32]32A, 32B, 32C, 32D, 32E, 32F, and 32G are diagrams showing configuration examples of electronic devices. [Figure 33] 33A, 33B, 33C, and 33D are diagrams showing configuration examples of electronic devices. [Figure 34] 34A and 34B are cross-sectional STEM images. [Figure 35] 35A and 35B are cross-sectional STEM images. [Figure 36] 36A and 36B are cross-sectional STEM images. [Figure 37] 37A and 37B are diagrams showing the resistance of metal oxide films. [Figure 38] 38A and 38B are diagrams showing the resistance of metal oxide films. [Figure 39] 39A and 39B are diagrams showing the resistance of metal oxide films. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0027] In each figure described herein, the size of each component, layer thickness, or area may be exaggerated for clarity.

[0028] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion of components and are not intended to limit the number.

[0029] In this specification, terms indicating position, such as "above" and "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0030] In this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. Therefore, the terms source and drain can be used interchangeably.

[0031] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to the direction perpendicular to the channel length direction. Note that, depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0032] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements with various functions.

[0033] In this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0034] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the edge of the upper layer may be located inside the edge of the lower layer, or the edge of the upper layer may be located outside the edge of the lower layer. In these cases, the phrase "top surface shapes generally match" also applies.

[0035] In this specification, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state) when a voltage V between the gate and source of an n-channel transistor is applied. gs is the threshold voltage V th (For p-channel transistors, V th This refers to a state of being (higher than)

[0036] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) images etc. on a display surface, and therefore the display panel is one aspect of an output device.

[0037] In this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0038] In this specification and the like, a touch panel, which is one aspect of a display device, has a function of displaying an image or the like on a display surface and a function as a touch sensor that detects that a detectable object such as a finger or a stylus touches, presses, or approaches the display surface. Thus, the touch panel is one aspect of an input / output device.

[0039] A touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function. A touch panel can have a configuration including a display panel and a touch sensor panel. Alternatively, the touch panel can have a touch sensor function inside or on the surface of the display panel.

[0040] In this specification, a touch panel substrate on which a connector and an IC are mounted may be called a touch panel module, a display module, or simply a touch panel.

[0041] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. As an example of the semiconductor device, a structure example of a transistor including an oxide semiconductor in a channel formation region and a manufacturing method thereof will be described below.

[0042] <Configuration example 1> [Configuration Example 1-1] A schematic cross-sectional view of transistor 10 taken along the channel length is shown in FIG. 1A.

[0043] The transistor 10 includes a semiconductor layer 108, an insulating layer 110, and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode. The transistor 10 is a so-called top-gate transistor in which the gate electrode is provided over the semiconductor layer 108.

[0044] The semiconductor layer 108 includes a region 108C, a pair of regions 108L1, a pair of regions 108L2, and a pair of regions 108N. The region 108C overlaps with the conductive layer 112 and the insulating layer 110 and functions as a channel formation region. The pair of regions 108L1 are provided to sandwich the region 108C. The pair of regions 108L2 are provided to sandwich the region 108C and the pair of regions 108L1. The regions 108L1 and 108L2 include regions that do not overlap with the conductive layer 112 and overlap with the insulating layer 110. The pair of regions 108N are provided to sandwich the region 108C, the pair of regions 108L1, and the pair of regions 108L2. The region 108N does not overlap with either the conductive layer 112 or the insulating layer 110.

[0045] Region 108N has a lower resistance than region 108C and functions as a source region and a drain region. Regions 108L1 and 108L2 preferably have a lower resistance than region 108C and a higher resistance than region 108N. Regions 108L1 and 108L2 function as buffer regions for alleviating the drain electric field. Regions 108L1 and 108L2 function as so-called LDD (Lightly Doped Drain) regions.

[0046] By providing the regions 108L1 and 108L2 that function as LDD regions between the region 108C that functions as a channel formation region and the region 108N that functions as a source region or drain region, the electric field in the drain region can be alleviated, thereby reducing fluctuations in the threshold voltage of the transistor caused by the electric field in the drain region.

[0047] The lower the electrical resistance of the region 108N, the more preferable. For example, the sheet resistance of the region 108N is 1 Ω / □ or more and 1×10 3 Preferably less than Ω / □, more preferably 1Ω / □ or more and 8×10 2 Ω / □ or less is preferable.

[0048] The higher the electrical resistance of the region 108C in a state where no channel is formed, the more preferable. For example, the sheet resistance of the region 108C is 1×10 7 Ω / □ or more is preferable, and 1×10 8 Ω / □ or more is preferable, and 1×10 9 Ω / □ or higher is preferable.

[0049] The sheet resistance values ​​of the regions 108L1 and 108L2 are, for example, 1×10 3 Ω / □ or more 1×10 9 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 8 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 7 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 6 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 5 Ω / □ or less is preferable. By setting the resistance within the above range, a transistor with good electrical characteristics and high reliability can be obtained. The sheet resistance can be calculated from the resistance value. By providing the regions 108L1 and 108L2 having the resistance within the above range between the regions 108N and 108C, the source-drain breakdown voltage of the transistor 100 can be increased.

[0050] The electrical resistance of region 108C in a state where no channel is formed is 1×10 times that of region 108N. 6 1×10 times more 12 times or less is preferable, and even more preferably 1 × 10 6 1×10 times more 11 times or less is preferable, and even more preferably 1 × 10 6 1×10 times more 10 Preferably, it is less than twice the normal value.

[0051] The electrical resistance of the region 108C in a state where no channel is formed is 1×10 times the electrical resistance of each of the regions 108L1 and 108L2. 0 1×10 times more9 times or less is preferable, and even more preferably 1 × 10 1 1×10 times more 8 times or less is preferable, and even more preferably 1 × 10 2 1×10 times more 7 Preferably, it is less than twice the normal value.

[0052] The electrical resistance of the region 108L1 and the region 108L2 is 1×10 times that of the region 108N. 0 1×10 times more 9 times or less is preferable, and even more preferably 1 × 10 1 1×10 times more 8 times or less is preferable, and even more preferably 1 × 10 1 1×10 times more 7 Preferably, it is less than twice the normal value.

[0053] It is preferable that the carrier concentration in the semiconductor layer 108 be lowest in the region 108C and highest in the region 108N. By providing the regions 108L1 and 108L2 between the regions 108C and 108N, the carrier concentration in the region 108C can be kept extremely low even if impurities such as hydrogen diffuse from the region 108N during the manufacturing process, for example.

[0054] The carrier concentration in the region 108C functioning as a channel forming region is preferably as low as possible, and is preferably 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 More preferably, it is 1×10 or less. 13 cm -3 More preferably, it is 1×10 or less. 12 cm -3 The lower limit of the carrier concentration of the region 108C is not particularly limited, but is preferably 1×10 -9 cm -3 It can be said that:

[0055] On the other hand, the carrier concentration in the region 108N is, for example, 5×10 18 cm -3 or more, preferably 1 × 10 19 cm -3 More preferably, 5 × 10 19 cm -3 The upper limit of the carrier concentration in the region 108N is not particularly limited, but may be, for example, 5×10 21 cm -3 , or 1 × 10 22 cm -3 etc.

[0056] The carrier concentrations in the regions 108L1 and 108L2 can be between the values ​​in the regions 108C and 108N. For example, 1×10 14 cm -3 More than 1×10 20 cm -3 It is sufficient to set the value in the range below.

[0057] The carrier concentrations in the regions 108L1 and 108L2 may not be uniform, and may have a gradient such that the carrier concentration decreases from the region 108N side to the region 108C side. Also, the hydrogen concentrations in the regions 108L1 and 108L2 may have a gradient such that the hydrogen concentration decreases from the region 108N side to the region 108C side.

[0058] It is more preferable that region 108L2 has a lower resistance than region 108L1. That is, it is preferable that the resistance of semiconductor layer 108 decreases stepwise from region 108C toward region 108N. By decreasing the resistance in the order of region 108C, region 108L1, region 108L2, and region 108N, the electric field in the drain region can be effectively alleviated, and fluctuations in the threshold voltage of the transistor can be further reduced.

[0059] In addition to the region 108L1 being more resistive than the region 108L2, the sheet resistance value of the region 108L1 is, for example, 1×10 4 Ω / □ or more 1×10 9Ω / □ or less is preferable, and 1×10 4 Ω / □ or more 1×10 8 Ω / □ or less is preferable, and 1×10 4 Ω / □ or more 1×10 7 Ω / □ or less is preferable, and 1×10 4 Ω / □ or more 1×10 6 Ω / □ or less is preferable, and 1×10 4 Ω / □ or more 1×10 5 The sheet resistance of the region 108L2 is preferably 1×10 3 Ω / □ or more 1×10 8 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 7 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 6 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 5 Ω / □ or less is preferable, and 1×10 3 Ω / □ or more 1×10 4 Ω / □ or less is preferable.

[0060] The resistance of the region 108L1 is more than twice as large as the resistance of the region 108L2, 1×10 3 times or less is preferable, and more preferably 3 times or more, 1×10 2 Preferably, the resistance is 4 to 10 times greater than the resistance of the transistor 100. By providing the regions 108L1 and 108L2 having the resistance in the above range between the regions 108N and 108C, the source-drain breakdown voltage of the transistor 100 can be increased.

[0061] Regions 108L1, 108L2, and 108N each include a first element. Examples of the first element include one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, helium, neon, argon, krypton, and xenon. The first element is preferably one or more of hydrogen, boron, nitrogen, and phosphorus. Regions 108L1, 108L2, and 108N may each include a plurality of first elements.

[0062] The concentration of the first element in the semiconductor layer 108 preferably increases in the order of region 108C, region 108L1, region 108L2, and region 108N. The concentration of the first element in the semiconductor layer 108 can be analyzed by, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side with XPS analysis. Note that when the concentration of the first element is low, the first element may not be detected in the analysis or may be below the detection limit. In particular, since the concentration of the first element in region 108C is low, the first element may not be detected in the analysis or may be below the detection limit. Similarly, the first element may not be detected in the analysis of region 108L1 or may be below the detection limit.

[0063] The thickness of the insulating layer 110 in the region overlapping with the region 108L1 is preferably approximately equal to the thickness of the insulating layer 110 in the region overlapping with the region 108C. Furthermore, the thickness of the insulating layer 110 in the region overlapping with the region 108L2 is preferably thinner than the thickness of the insulating layer 110 in the region overlapping with the region 108L1. In other words, the thickness of the insulating layer 110 is preferably in a stepped shape (hereinafter also referred to as a stepped shape) that gradually becomes thinner from the region 108C side toward the region 108N side.

[0064] The stepped shape of insulating layer 110 makes it possible to control the amount of the first element added to regions 108C, 108L1, 108L2, and 108N, and to decrease the resistance of semiconductor layer 108 in the order of regions 108C, 108L1, 108L2, and 108N. Furthermore, the stepped shape of insulating layer 110 improves the coverage of a layer (e.g., insulating layer 118) formed on insulating layer 110, and can prevent defects such as discontinuities and voids from occurring in the layer.

[0065] In this specification, the film thickness of A being approximately equal to the film thickness of B means that the ratio of the film thickness of B to the film thickness of A is 0.8 or more and 1.2 or less.

[0066] 1A, an end of the insulating layer 110 is located inside an end of the semiconductor layer 108. The insulating layer 110 has a first side surface 110S1 and a second side surface 110S2. In a cross-sectional view in the channel length direction, the first side surface 110S1 and the second side surface 110S2 are each located on the semiconductor layer 108. In a cross-sectional view in the channel length direction, the first side surface 110S1 is located outside an end of the conductive layer 112, and the second side surface 110S2 is located outside the first side surface 110S1.

[0067] The insulating layer 110 in contact with the semiconductor layer 108 preferably contains an oxide or an oxynitride. The insulating layer 110 preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film capable of releasing oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment in an oxygen atmosphere after the formation of the insulating layer 110, performing plasma treatment or the like in an oxygen atmosphere after the formation of the insulating layer 110, or forming an oxide film or an oxynitride film on the insulating layer 110 in an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (such as nitrous oxide or ozone) may be used instead of or in addition to oxygen.

[0068] The insulating layer 110 can be formed by, for example, sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. CVD methods include plasma enhanced CVD (PECVD), thermal CVD, etc.

[0069] In particular, it is preferable that the insulating layer 110 be formed by PECVD (plasma enhanced chemical vapor deposition).

[0070] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. The semiconductor layer 108 preferably contains at least indium and oxygen. When the semiconductor layer 108 contains an oxide of indium, carrier mobility can be increased. For example, a transistor that can pass a larger current than a transistor using amorphous silicon can be realized.

[0071] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0072] The semiconductor layer 108 preferably contains a metal oxide. Alternatively, the semiconductor layer 108 may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single-crystal silicon).

[0073] When a metal oxide is used for the semiconductor layer 108, it is preferable that the semiconductor layer 108 contains, for example, indium, an element M (M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, it is preferable that the element M is one or more of aluminum, gallium, yttrium, and tin. It is more preferable that the element M contains either or both of gallium and tin.

[0074] For example, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (hereinafter also referred to as IGZO) can be suitably used for the semiconductor layer 108. For example, an oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 or a ratio close to that can be suitably used for the semiconductor layer 108.

[0075] In addition to indium, gallium, and zinc, an oxide containing one or more of aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium can also be used for the semiconductor layer 108. In particular, it is preferable to use an oxide containing tin, aluminum, or silicon in addition to indium, gallium, and zinc for the semiconductor layer because a transistor with high field-effect mobility can be achieved.

[0076] When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used to deposit the In-M-Zn oxide preferably has an atomic ratio of In to element M of 1 or more. Examples of atomic ratios of metal elements in such sputtering targets include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=10:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5. In the above, when two or more types of elements are contained as the element M, the proportion of the element M in the atomic ratio corresponds to the sum of the numbers of atoms of the two or more metal elements.

[0077] A sputtering target containing a polycrystalline oxide is preferred because it facilitates the formation of a crystalline semiconductor layer. The atomic ratio of the semiconductor layer to be formed can vary by ±40% from the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer is In:M:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer to be formed may be close to In:M:Zn=4:2:3 [atomic ratio].

[0078] When describing an atomic ratio of In:M:Zn=4:2:3 or thereabout, this includes a case where, when In is taken as 4, the element M is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When describing an atomic ratio of In:M:Zn=5:1:6 or thereabout, this includes a case where, when In is taken as 5, M is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. When describing an atomic ratio of In:M:Zn=1:1:1 or thereabout, this includes a case where, when In is taken as 1, the element M is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0079] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 preferably contains a metal oxide containing at least indium and oxygen. The semiconductor layer 108 may also contain zinc in addition to these elements. The semiconductor layer 108 may also contain gallium.

[0080] The composition of the semiconductor layer 108 significantly affects the electrical characteristics and reliability of the transistor 10. For example, increasing the indium content in the semiconductor layer 108 improves carrier mobility, enabling a transistor with high field-effect mobility to be realized.

[0081] One of the indicators for evaluating transistor reliability is the gate bias stress test (GBT), in which an electric field is applied to the gate and the test is held at high temperature. Among these tests, a test in which a positive potential is applied to the gate relative to the source and drain potentials and the test is held at high temperature is called a PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential is applied to the gate and the test is held at high temperature is called an NBTS (Negative Bias Temperature Stress) test. Furthermore, the PBTS and NBTS tests, which are conducted under illumination with light such as white LED light, are called PBTIS (Positive Bias Temperature Illumination Stress) and NBTIS (Negative Bias Temperature Illumination Stress), respectively.

[0082] In particular, in an n-type transistor using an oxide semiconductor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows), so the amount of change in threshold voltage in the PBTS test is one of the important items to focus on as an index of transistor reliability.

[0083] Here, by using a metal oxide film that does not contain gallium or has a low gallium content as the composition of the semiconductor layer 108, the amount of variation in threshold voltage in the PBTS test can be reduced. Furthermore, when gallium is contained, it is preferable that the gallium content be smaller than the indium content in the composition of the semiconductor layer 108. This makes it possible to realize a highly reliable transistor.

[0084] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the more significant the degradation in the PBTS test. The generation of these defect levels can be suppressed by reducing the gallium content in the part of the semiconductor layer that contacts the gate insulating layer.

[0085] The following is a possible reason why PBTS degradation can be suppressed by eliminating or reducing the gallium content. Gallium contained in the semiconductor layer 108 has the property of attracting oxygen more easily than other metal elements (e.g., indium and zinc). Therefore, it is presumed that at the interface between the metal oxide film containing a large amount of gallium and the insulating layer 110 containing oxide, gallium bonds with excess oxygen in the insulating layer 110, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause a fluctuation in the threshold voltage.

[0086] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, a metal oxide film in which the atomic ratio of In is higher than the atomic ratio of Ga can be used for the semiconductor layer 108. It is more preferable to use a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of Ga. In other words, it is preferable to use a metal oxide film in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 108.

[0087] For example, the semiconductor layer 108 can be a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=10:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, or a ratio close to these.

[0088] When a metal oxide film containing indium and gallium is used as the semiconductor layer 108, the ratio of the number of gallium atoms to the number of atoms of the metal element contained in the metal oxide (atomic ratio) can be set to be greater than 0 and less than 50%, preferably 0.05% or more and 30% or less, more preferably 0.1% or more and 15% or less, and more preferably 0.1% or more and 5% or less. Note that by including gallium in the semiconductor layer 108, oxygen deficiency (hereinafter referred to as V O This has the effect of making it less likely for the following to occur:

[0089] A metal oxide film containing no gallium may be used for the semiconductor layer 108. For example, In-Zn oxide may be used for the semiconductor layer 108. In this case, increasing the atomic ratio of In to the atomic number of metal elements contained in the metal oxide film can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of Zn to the atomic number of metal elements contained in the metal oxide film results in a metal oxide film with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide film containing no gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108. Using a metal oxide film containing no gallium at all can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0090] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide film having an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these can be used.

[0091] In particular, it is preferable to use a metal oxide film in which the atomic ratio of In is higher than the atomic ratio of the element M for the semiconductor layer 108. It is also preferable to use a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of the element M.

[0092] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, a metal oxide film having a c-axis aligned crystal (CAAC) structure, a nanocrystal (nc) structure, a polycrystalline structure, a microcrystalline structure, or the like, which will be described later, can be used. By using a crystalline metal oxide film for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0093] The higher the crystallinity of the semiconductor layer 108, the more the density of defect states in the film can be reduced. On the other hand, by using a metal oxide film with low crystallinity, a transistor capable of passing a large current can be realized.

[0094] The semiconductor layer 108 may have a stacked structure in which layers with different compositions, layers with different crystallinity, or layers with different impurity concentrations are stacked.

[0095] When a metal oxide film is formed by sputtering, the higher the substrate temperature (stage temperature) during film formation, the higher the crystallinity of the formed metal oxide film. Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during film formation (also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide film. Thus, the crystallinity of the formed metal oxide film can be controlled by the substrate temperature and the oxygen flow rate ratio in the film formation gas.

[0096] The conductive layer 112 is preferably formed using a low-resistance material. By using a low-resistance material for the conductive layer 112, parasitic resistance can be reduced, and a transistor with high on-state current can be obtained, thereby enabling a semiconductor device with high on-state current. For example, it is preferable to use a conductive film containing a metal or an alloy as the conductive layer 112 because electrical resistance can be reduced. Note that a conductive film containing an oxide may also be used for the conductive layer 112. Furthermore, by reducing wiring resistance in a large display device or a high-resolution display device, signal delay can be suppressed and high-speed driving can be achieved. Copper, silver, gold, aluminum, aluminum, or the like can be used for the conductive layer 112. In particular, copper is preferable because it has low resistance and is suitable for mass production.

[0097] The conductive layer 112 may have a stacked structure. When the conductive layer 112 has a stacked structure, a second conductive layer is provided on or under, or both of, the first conductive layer having low resistance. The second conductive layer is preferably made of a conductive material that is less susceptible to oxidation (has oxidation resistance) than the first conductive layer. In addition, the second conductive layer is preferably made of a material that suppresses the diffusion of components of the first conductive layer. For example, the second conductive layer can be made of a metal oxide such as indium oxide, indium zinc oxide, indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO), or zinc oxide, or a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, or tungsten nitride.

[0098] The transistor 10 preferably further includes an insulating layer 118. The insulating layer 118 functions as a protective layer to protect the transistor 10. The insulating layer 118 can be formed using an inorganic insulating material such as oxide, oxynitride, nitride oxide, or nitride. More specifically, an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used. The insulating layer 118 may have a stacked structure of two or more layers.

[0099] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0100] Furthermore, in this specification, when an oxynitride and a nitride oxide containing the same element are described, the oxynitride includes a material that satisfies either or both of the following: a higher oxygen content and a lower nitrogen content than the nitride oxide. Similarly, the nitride oxide includes a material that satisfies either or both of the following: a lower oxygen content and a higher nitrogen content than the oxynitride. For example, when silicon oxynitride and silicon nitride oxide are described, the silicon oxynitride includes a material that has a higher oxygen content and a lower nitrogen content than the silicon nitride oxide. Similarly, the silicon nitride oxide includes a material that has a lower oxygen content and a higher nitrogen content than the silicon oxynitride.

[0101] The insulating layer 118 may function as a supply source of the first element to the regions 108L1, 108L2, and 108N. For example, the insulating layer 118 can function as a supply source of hydrogen to the regions 108L1, 108L2, and 108N. The regions 108L1, 108L2, and 108N are each located at a different distance from the insulating layer 118, which allows the amounts of hydrogen supplied from the insulating layer 118 to vary. Specifically, the distance from the insulating layer 118 to the regions 108L1, 108L2, and 108N decreases in this order, allowing the amounts of hydrogen added to increase in this order. In other words, the resistance of the regions 108L1, 108L2, and 108N decreases in this order. The insulating layer 118 also contacts the region 108N of the semiconductor layer 108. Providing the insulating layer 118 in contact with the region 108N can reduce the resistance of the region 108N in particular. Note that the region 108C has the conductive layer 112 and the insulating layer 110 between it and the insulating layer 118, so hydrogen is less likely to be added, and it is possible to prevent the resistance of the region 108C from decreasing.

[0102] When hydrogen is used as the first element, the insulating layer 118 may be formed using a mixed gas containing a gas containing hydrogen. This allows hydrogen to be effectively supplied to the exposed region 108N when the insulating layer 118 is formed, thereby further reducing the resistance of the region 108N. Examples of the hydrogen-containing gas that can be used include hydrogen (H2), ammonia (NH3), and silane (SiH4).

[0103] The transistor 10 of one embodiment of the present invention includes the regions 108L1 and 108L2 between the regions 108C and 108N, so that the transistor 10 can have both a high drain withstand voltage and a high on-state current and can be highly reliable.

[0104] [Configuration Example 1-2] 1B shows an example of a configuration different from the aforementioned transistor 10. FIG. 1B is a schematic cross-sectional view of a transistor 10A in the channel length direction. The transistor 10A differs from the transistor 10 mainly in that the transistor 10A has a conductive layer 106.

[0105] The conductive layer 106 has a region overlapping with the semiconductor layer 108, the insulating layer 110, and the conductive layer 112 with the insulating layer 103 interposed therebetween. The conductive layer 106 functions as a first gate electrode (also referred to as a back gate electrode). The insulating layer 103 functions as a first gate insulating layer. In this case, the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode), and the insulating layer 110 functions as a second gate insulating layer.

[0106] For example, the transistor 10A can increase the current that can flow in an on state by applying the same potential to the conductive layer 112 and the conductive layer 106. Alternatively, the transistor 10A can apply a potential to one of the conductive layer 112 and the conductive layer 106 to control the threshold voltage, and apply a potential to the other to control the on and off states of the transistor 10A. Furthermore, the electrical characteristics of the transistor 10A can be stabilized by electrically connecting one of the conductive layer 112 and the conductive layer 106 to the source.

[0107] The insulating layer 103 functioning as the second gate insulating layer preferably functions as a barrier layer that suppresses diffusion of impurities from the surface where the insulating layer 103 is to be formed to the semiconductor layer 108 or the like. Examples of the impurities include metal components contained in the conductive layer 106. The insulating layer 103 preferably satisfies one or more of the following, and more preferably all of them: high withstand voltage, low film stress, difficulty in releasing hydrogen or water, difficulty in diffusing hydrogen or water, and few defects. The insulating layer 103 can be formed using the insulating film that can be used for the insulating layer 110.

[0108] The conductive layer 106 can be formed using the same conductive film as the conductive layer 112 .

[0109] 1B shows an example in which the edge of the conductive layer 106 is approximately aligned with the edge of the conductive layer 112; however, one embodiment of the present invention is not limited to this. The edge of the conductive layer 106 may be located outside the edge of the conductive layer 112. Alternatively, the edge of the conductive layer 106 may be located inside the edge of the conductive layer 112. In this specification and the like, the phrase "edges approximately aligned" means that at least part of the contours of stacked layers overlap. For example, this also includes a case in which an upper layer and a lower layer are processed using the same mask pattern or a case in which a part of the upper layer is processed using the same mask pattern. However, strictly speaking, the contours may not overlap, and the edge of the upper layer may be located inside the edge of the lower layer or outside the edge of the lower layer. In this case, the phrase "edges approximately aligned" is also used.

[0110] [Configuration Example 1-3] An example of a configuration different from that of the above-described transistor 10A is shown in Fig. 1C. Fig. 1C is a schematic cross-sectional view of a transistor 10B in the channel length direction. The transistor 10B differs from the transistor 10A mainly in that the insulating layer 103 has a stacked structure.

[0111] 1C shows an example of a configuration in which the insulating layer 103 has a three-layer structure in which an insulating layer 103a, an insulating layer 103b, and an insulating layer 103c are stacked in this order from the conductive layer 106 side. The insulating layer 103a is in contact with the conductive layer 106. The insulating layer 103c is in contact with the semiconductor layer 108.

[0112] Of the three insulating films included in the insulating layer 103, an insulating film containing nitrogen is preferably used for the insulating layer 103a located on the surface to be formed of the insulating layer 103. On the other hand, an insulating film containing oxygen is preferably used for the insulating layer 103c in contact with the semiconductor layer 108. Furthermore, the three insulating films included in the insulating layer 103 are preferably formed successively without exposure to the air using a plasma CVD apparatus.

[0113] The insulating layer 103a is preferably a dense film that can prevent diffusion of impurities from below. The insulating layer 103a is preferably a film that can block metal elements, hydrogen, water, and the like contained in a member (such as a substrate) on the surface where the insulating layer 103a is to be formed. Therefore, the insulating layer 103a can be an insulating film formed at a lower deposition rate than the insulating layer 103b.

[0114] The insulating layer 103a can be made of an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film. It is particularly preferable to use a dense silicon nitride film formed using a plasma CVD apparatus as the insulating layer 103a. By using such an insulating film containing nitrogen, even if the insulating layer is thin, it is possible to effectively prevent impurities from diffusing from the surface on which the insulating layer is to be formed.

[0115] The insulating layer 103c in contact with the semiconductor layer 108 is preferably formed using an insulating film containing oxide or oxynitride. In particular, an oxide film or an oxynitride film is preferably used for the insulating layer 103c. Furthermore, the insulating layer 103c is preferably formed using a dense insulating film whose surface is less likely to adsorb impurities such as water. Furthermore, it is preferable to use an insulating film with as few defects as possible and in which impurities such as water and hydrogen are reduced.

[0116] The insulating layer 103c preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 103c is preferably an insulating film that can release oxygen by heating. For example, oxygen can be supplied to the insulating layer 103c by forming the insulating layer 103c in an oxygen atmosphere, performing heat treatment on the formed insulating layer 103c in an oxygen atmosphere, performing plasma treatment or the like in an oxygen atmosphere after the formation of the insulating layer 103c, or forming an oxide film or an oxynitride film on the insulating layer 103c in an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (e.g., nitrous oxide or ozone) may be used instead of or in addition to oxygen. Alternatively, oxygen may be supplied to the insulating layer 103c from an insulating film that can release oxygen by heating formed on the insulating layer 103c and then performing heat treatment.

[0117] Furthermore, oxygen can be supplied to the insulating layer 103c when the metal oxide film to be the semiconductor layer 108 is formed by a sputtering method in an oxygen-containing atmosphere. After the metal oxide film to be the semiconductor layer is formed, heat treatment is performed to supply oxygen in the insulating layer 103c to the metal oxide film, thereby reducing oxygen vacancies (V O ) can be reduced.

[0118] The insulating layer 103c can be, for example, an insulating layer including one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. In particular, it is preferable to use a silicon oxide film or a silicon oxynitride film as the insulating layer 103c.

[0119] The insulating layer 103b located between the insulating layer 103a and the insulating layer 103c is preferably an insulating film that has low stress and is deposited at a high deposition rate. For example, the insulating layer 103b is preferably a film that has lower stress than the insulating layer 103a and the insulating layer 103c. Furthermore, the insulating layer 103b is preferably a film that is deposited at a higher deposition rate than the insulating layer 103a and the insulating layer 103c.

[0120] The insulating layer 103b is preferably an insulating film that releases as little hydrogen and water as possible. By using such an insulating film, it is possible to prevent hydrogen and water from diffusing from the insulating layer 103b through the insulating layer 103c to the semiconductor layer 108 due to heat applied during heat treatment or other processes, thereby reducing the carrier concentration in the region 108C.

[0121] Furthermore, the insulating layer 103b is preferably made of an insulating film that does not easily absorb oxygen. In other words, it is preferable to use an insulating film through which oxygen does not easily diffuse. This can prevent a decrease in the amount of oxygen supplied to the semiconductor layer 108 due to diffusion of oxygen from the insulating layer 103c toward the insulating layer 103b when heat treatment is performed to supply oxygen from the insulating layer 103c to the semiconductor layer 108 (or a metal oxide film that will become the semiconductor layer 108).

[0122] The insulating layer 103b can be, for example, an insulating layer including one or more of a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an aluminum nitride film, and a hafnium nitride film. In particular, it is preferable to use a silicon nitride oxide film or a silicon nitride film as the insulating layer 103b.

[0123] Of insulating layers 103a, 103b, and 103c constituting insulating layer 103, insulating layer 103b is preferably the thickest. The thickness (total thickness) of insulating layer 103 can be determined based on the relative dielectric constant value and thickness of each insulating film, taking into consideration the relative dielectric constant value required for insulating layer 103 and the dielectric strength voltage performance required for insulating layer 103. In other words, the thicknesses of the insulating films can be adjusted relative to one another within a range that satisfies the above requirements.

[0124] In particular, the insulating layer 103b is preferably thicker than the insulating layer 103a. By making the insulating layer 103b thicker than the insulating layer 103a, even when a film that easily releases hydrogen by heating is used as the insulating layer 103a, the amount of hydrogen that can reach the insulating layer 103c can be reduced. Furthermore, by making the insulating layer 103a thinner than the insulating layer 103b, the volume of the insulating layer 103a can be relatively small, and therefore the amount of hydrogen that the insulating layer 103a can release can be reduced.

[0125] Furthermore, the insulating layer 103b is preferably thicker than the insulating layer 103c. If the insulating layer 103c is too thick, when a process for supplying oxygen into the insulating layer 103c is performed, the amount of oxygen remaining in the insulating layer 103c without being released by heating increases, which may result in a decrease in the amount of oxygen that can be supplied to the semiconductor layer 108 (or the metal oxide film that will become the semiconductor layer 108). Therefore, by making the insulating layer 103c thinner (reducing its volume) than the insulating layer 103b, the amount of oxygen remaining in the insulating layer 103c after heating can be reduced. As a result, the proportion of oxygen supplied to the semiconductor layer 108 out of the oxygen supplied to the insulating layer 103c can be increased, which can effectively increase the amount of oxygen supplied to the semiconductor layer 108.

[0126] Furthermore, by forming the thickest insulating layer 103b under conditions of a high film formation rate and forming thinner insulating layers 103a and 103c to be dense films under conditions of a low film formation rate, the film formation time of the insulating layer 103 can be shortened without impairing reliability, and productivity can be increased.

[0127] Here, the insulating layer 103a is preferably an insulating film containing at least silicon and nitrogen, typically a silicon nitride film or a silicon nitride oxide film. The insulating layer 103b is preferably an insulating film containing at least silicon, nitrogen, and oxygen, typically a silicon nitride oxide film or a silicon oxynitride film. The insulating layer 103c is preferably an insulating film containing at least silicon and oxygen, typically a silicon oxide film or a silicon oxynitride film. The amount of oxygen contained in the insulating layer 103b is preferably greater than that of the insulating layer 103a and less than that of the insulating layer 103c. The amount of nitrogen contained in the insulating layer 103b is preferably less than that of the insulating layer 103a and more than that of the insulating layer 103c.

[0128] The oxygen and nitrogen contents in the insulating layers 103a, 103b, and 103c can be analyzed by secondary ion mass spectroscopy (SIMS), X-ray photoelectron spectroscopy (XPS), or other analytical methods. 3 or more than 1 atoms / cm 3 On the other hand, when the content of the target element in the film is low (for example, 0.5 atoms / cm or more), XPS is suitable. 3 or less than 1 atoms / cm 3 SIMS is suitable in the following cases. When comparing the element contents in films, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0129] When the film densities of insulating layer 103a, insulating layer 103b, and insulating layer 103c are different, they may be distinguishable from each other by being observed as differences in contrast in a transmission electron microscope (TEM) image of a cross section of insulating layer 103. However, when the compositions and film densities are similar, the boundaries between them may be unclear.

[0130] The insulating layer 103 may be two layers or four or more layers. For example, the insulating layer 103 may have a two-layer structure of an insulating layer 103a and an insulating layer 103c.

[0131] [Configuration Example 1-4] 2A shows an example of a configuration different from that of the aforementioned transistor 10. Fig. 2A is a schematic cross-sectional view of a transistor 10C in the channel length direction. The transistor 10C differs from the transistor 10 mainly in that the insulating layer 110 has a stacked structure.

[0132] FIG. 2A shows an example in which the insulating layer 110 has a three-layer structure in which an insulating layer 110a, an insulating layer 110b, and an insulating layer 110c are stacked in this order from the semiconductor layer 108 side.

[0133] The insulating layer 110a has regions in contact with the regions 108C, 108L1, and 108L2. The insulating layer 110c has a region in contact with the conductive layer 112. The insulating layer 110b is located between the insulating layer 110a and the insulating layer 110c.

[0134] The insulating layers 110a, 110b, and 110c are preferably insulating films containing oxide or oxynitride. The insulating layers 110a, 110b, and 110c are preferably successively formed using the same film formation apparatus without exposure to the air. By successively forming the insulating layers 110a, 110b, and 110c, it is possible to prevent impurities such as water from adhering to the interfaces of the insulating layers 110a, 110b, and 110c.

[0135] The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be, for example, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.

[0136] The insulating layers 110a, 110b, and 110c can be formed by, for example, sputtering, CVD, vacuum deposition, PLD, ALD, etc. Examples of CVD include plasma CVD and thermal CVD.

[0137] In particular, it is preferable that the insulating layers 110a, 110b, and 110c are formed by plasma CVD.

[0138] The insulating layer 110a is preferably formed under conditions that minimize damage to the semiconductor layer 108 because it is formed over the semiconductor layer 108. For example, the insulating layer 110a can be formed under conditions that minimize damage to the semiconductor layer 108. By forming the insulating layer 110a under conditions that minimize damage to the semiconductor layer 108, the density of defect states at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, thereby providing a highly reliable transistor 10C.

[0139] For example, when a silicon oxynitride film is formed as the insulating layer 110a by a plasma CVD method, damage to the semiconductor layer 108 can be made extremely small by forming the film under low power conditions.

[0140] The deposition gas used to form a silicon oxynitride film can be a source gas containing a deposition gas containing silicon, such as silane or disilane, and an oxidizing gas, such as oxygen, ozone, nitrous oxide, or nitrogen dioxide. In addition to the source gas, a dilution gas, such as argon, helium, or nitrogen, can also be used.

[0141] For example, by reducing the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter simply referred to as the flow rate ratio), the film-forming rate can be reduced, and a dense film with few defects can be formed.

[0142] The insulating layer 110b is preferably formed under conditions that allow for a higher film formation rate than the insulating layer 110a, thereby improving productivity.

[0143] For example, the insulating layer 110b can be formed under conditions in which the flow rate of the deposition gas is higher than that of the insulating layer 110a, thereby increasing the film formation rate.

[0144] The insulating layer 110c is preferably an extremely dense film with reduced surface defects and low adsorption of impurities such as water contained in the atmosphere. For example, similar to the insulating layer 110a, the insulating layer 110c can be formed under conditions where the film formation rate is sufficiently low.

[0145] Furthermore, since the insulating layer 110c is formed on the insulating layer 110b, the insulating layer 110c has less influence on the semiconductor layer 108 during its formation than the insulating layer 110a. Therefore, the insulating layer 110c can be formed under higher power conditions than the insulating layer 110a. By reducing the flow rate ratio of the deposition gas and forming the insulating layer 110c at relatively high power, a dense film with reduced surface defects can be obtained.

[0146] That is, a stacked film formed under conditions in which the film formation rate is fastest for insulating layer 110b, followed by insulating layer 110a and insulating layer 110c, can be used for insulating layer 110. Furthermore, for insulating layer 110, the etching rate under the same wet etching or dry etching conditions is fastest for insulating layer 110b, followed by insulating layer 110a and insulating layer 110c, in that order.

[0147] The insulating layer 110b is preferably formed thicker than the insulating layer 110a and the insulating layer 110c. By forming the insulating layer 110b, which has the fastest deposition rate, thick, the time required for the deposition process of the insulating layer 110 can be shortened.

[0148] Note that because insulating layers 110a, 110b, and 110c can be made of insulating films of the same material, the boundaries between insulating layers 110a and 110b and between insulating layers 110b and 110c may not be clearly visible. Therefore, in Figure 2A and other figures, these boundaries are indicated by dashed lines. Note that insulating layers 110a and 110b have different film densities, so their boundaries may be observed as differences in contrast in transmission electron microscope (TEM) images of a cross section of insulating layer 110. Similarly, the boundary between insulating layers 110b and 110c may also be observed as differences in contrast.

[0149] 2A illustrates a configuration in which the insulating layer 110 in the region in contact with the region 108C and the insulating layer 110 in the region in contact with the region 108L1 each have a stacked structure of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110 in the region overlapping with the region 108L2 has a stacked structure of the insulating layer 110a and the insulating layer 110b, but this embodiment of the present invention is not limited to this. As in the transistor 10D illustrated in FIG. 2B, the insulating layer 110 in the region overlapping with the region 108L2 may have a stacked structure of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c. As in the transistor 10E illustrated in FIG. 2C, the insulating layer 110 in the region overlapping with the region 108L2 may have a single-layer structure of the insulating layer 110a.

[0150] The insulating layer 110 may have a two-layer structure of an insulating layer 110a and an insulating layer 110c on the insulating layer 110a. Alternatively, the insulating layer 110 may have a single-layer structure. The insulating layer 110 may be any one of the insulating layers 110a, 110b, and 110c described above, selected as appropriate depending on the purpose.

[0151] [Configuration Example 1-5] 3A shows an example of a configuration different from the aforementioned transistor 10. Fig. 3A is a schematic cross-sectional view of a transistor 10F in the channel length direction. The transistor 10F differs from the transistor 10 mainly in that it has a metal oxide layer 114 between the insulating layer 110 and the conductive layer 112.

[0152] The metal oxide layer 114 has a function of supplying oxygen to the insulating layer 110. When a conductive film containing a metal or alloy that is easily oxidized is used for the conductive layer 112, the metal oxide layer 114 functions as a barrier layer that prevents the conductive layer 112 from being oxidized by oxygen in the insulating layer 110.

[0153] The metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing toward the insulating layer 110. The metal oxide layer 114 can be made of a material that is less permeable to oxygen and hydrogen than the insulating layer 110, for example.

[0154] The metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Furthermore, even when the conductive layer 112 contains hydrogen, the metal oxide layer 114 can prevent hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 via the insulating layer 110. As a result, the carrier concentration in the region 108C can be made extremely low.

[0155] An insulating material or a conductive material can be used for the metal oxide layer 114. When the metal oxide layer 114 has insulating properties, the metal oxide layer 114 functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, the metal oxide layer 114 functions as a part of the gate electrode.

[0156] An insulating material having a higher dielectric constant than silicon oxide is preferably used for the metal oxide layer 114. In particular, an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferably used because the driving voltage can be reduced.

[0157] The metal oxide layer 114 can be made of a metal oxide. For example, an oxide containing indium, such as indium oxide, indium zinc oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO), can be used. Conductive oxides containing indium are preferable because of their high conductivity. Furthermore, ITSO is less likely to crystallize due to the silicon it contains, and has high flatness, which increases the adhesion to a film formed on the ITSO. The metal oxide layer 114 can be made of a metal oxide such as zinc oxide or zinc oxide containing gallium. Alternatively, the metal oxide layer 114 may have a stacked structure of these oxides.

[0158] The metal oxide layer 114 is preferably formed using an oxide material containing one or more of the same elements as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 as the metal oxide layer 114, because this allows the use of common equipment.

[0159] Alternatively, when a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 114, it is preferable to use a material with a higher gallium content (content ratio) than the semiconductor layer 108 because the blocking property against oxygen can be further improved. In this case, by using a material with a higher indium content than the metal oxide layer 114 for the semiconductor layer 108, the field-effect mobility of the transistor 100 can be increased.

[0160] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0161] Note that in the case where the metal oxide layer 114 is formed for the purpose of supplying oxygen to the insulating layer 110, the metal oxide layer 114 may be removed after the metal oxide film that becomes the metal oxide layer 114 is formed. If unnecessary, the metal oxide layer 114 does not have to be provided.

[0162] [Configuration Example 1-6] An example of a configuration different from the aforementioned transistor 10 is shown in Figure 3B. Figure 3B is a schematic cross-sectional view of a transistor 10G in the channel length direction. The transistor 10G differs from the transistor 10 mainly in that it has a region 108L3 between the region 108N and the region 108L2.

[0163] The semiconductor layer 108 has a region 108C, a pair of regions 108L1, a pair of regions 108L2, a pair of regions 108L3, and a pair of regions 108N. The region 108L3 is provided between the region 108C, the pair of regions 108L1, and the pair of regions 108L2. The region 108L3 does not overlap with the conductive layer 112 and overlaps with the insulating layer 110. The above descriptions can be referred to for the region 108C, the region 108L1, and the region 108L2, and detailed description thereof will be omitted.

[0164] Regions 108L1, 108L2, and 108L3 preferably have a lower resistance than region 108C and a higher resistance than region 108N. Regions 108L1, 108L2, and 108L3 function as LDD regions.

[0165] It is more preferable that region 108L3 has a lower resistance than region 108L2. The order of decreasing resistance is region 108C, region 108L1, region 108L2, region 108L3, and region 108N, which effectively relaxes the electric field in the drain region and further reduces fluctuations in the threshold voltage of the transistor.

[0166] The thickness of the insulating layer 110 in the region overlapping with the region 108L3 is preferably thinner than the thickness of the insulating layer 110 in the region overlapping with the region 108L2. That is, the insulating layer 110 preferably has a stepped shape in which the thickness thereof gradually decreases from the region 108C side toward the region 108N side. By having the insulating layer 110 have a stepped shape, the resistance of the semiconductor layer 108 can be made lower in the order of the region 108C, the region 108L1, the region 108L2, the region 108L3, and the region 108N.

[0167] 3B, the insulating layer 110 has a first side surface 110S1, a second side surface 110S2, and a third side surface 110S3. In a cross-sectional view in the channel length direction, the first side surface 110S1, the second side surface 110S2, and the third side surface 110S3 are each located on the semiconductor layer 108. In addition, in a cross-sectional view in the channel length direction, the first side surface 110S1 is located outside an end of the conductive layer 112, the second side surface 110S2 is located outside the first side surface 110S1, and the third side surface 110S3 is located outside the second side surface 110S2.

[0168] [Configuration Example 1-7] 1A to 1C, 2A to 2C, and 3A show a configuration having two LDD regions (regions 108L1 and 108L2) between region 108C and region 108N, and FIG. 3B shows a configuration having three LDD regions (regions 108L1, 108L2, and 108L3), but one embodiment of the present invention is not limited to this. A configuration having p (p is 2 or more) LDD regions between region 108C and region 108N is also possible.

[0169] 4A is a schematic cross-sectional view of a transistor 10H in the channel length direction. The transistor 10H has regions 108L1 to 108Lp between a region 108C and a region 108N.

[0170] 4A, the insulating layer 110 has a first side surface 110S1 to a p-th side surface 110Sp. In a cross-sectional view in the channel length direction, the first side surface 110S1 to the p-th side surface 110Sp are each located on the semiconductor layer 108. In addition, in a cross-sectional view in the channel length direction, the first side surface 110S1 is located outside an end of the conductive layer 112, the second side surface 110S2 is located outside the first side surface 110S1, and the p-th side surface 110Sp is located outside the p-1-th side surface 110Sp-1.

[0171] Note that the insulating layer 110 may not have a stepped shape, and the thickness of the insulating layer 110 may continuously decrease from the region 108C side to the region 108N side. FIG. 4B is a schematic cross-sectional view of the transistor 10I in the channel length direction. As shown in FIG. 4B, the side surface 110S of the insulating layer 110 may have a sloped shape. Furthermore, the transistor 10I has a configuration in which the thickness of the insulating layer 110 continuously decreases from the region 108C side to the region 108N side, and the resistance continuously decreases from the region 108L1 to the region 108Lp.

[0172] <Configuration example 2> A more specific example of the configuration of a transistor will be described below.

[0173] [Configuration Example 2-1] FIG. 5A is a top view of the transistor 100, FIG. 5B corresponds to a cross-sectional view of the section taken along dashed-dotted line A1-A2 in FIG. 5A, and FIG. 5C corresponds to a cross-sectional view of the section taken along dashed-dotted line B1-B2 in FIG. 5A. Note that in FIG. 5A, some of the components of the transistor 100 (such as a protective layer) are omitted. The direction of dashed-dotted line A1-A2 corresponds to the channel length direction, and the direction of dashed-dotted line B1-B2 corresponds to the channel width direction. As with FIG. 5A, some of the components are omitted in the top views of the transistors in the following drawings.

[0174] An enlarged view of the region P surrounded by the dashed line in Figure 5B is shown in Figure 6A. An enlarged view of the region R surrounded by the dashed line in Figure 5C is shown in Figure 6B.

[0175] The transistor 100 is provided over a substrate 102 and includes a semiconductor layer 108, an insulating layer 110, a conductive layer 112, an insulating layer 118, and the like. The island-shaped semiconductor layer 108 is provided over the substrate 102. The insulating layer 110 is provided to cover part of the top surface of the substrate 102, the side surfaces of the semiconductor layer 108, and part of the top surface of the semiconductor layer 108. The conductive layer 112 is provided over the insulating layer 110 and has a portion overlapping with the semiconductor layer 108.

[0176] The end of the conductive layer 112 is located inside the end of the insulating layer 110. In other words, the insulating layer 110 has a portion that protrudes outside the end of the conductive layer 112 at least on the semiconductor layer 108.

[0177] A portion of the end of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 has a portion that overlaps with the conductive layer 112 and functions as a gate insulating layer, and a portion that does not overlap with the conductive layer 112 (i.e., a portion that overlaps with the region 108L1 or the region 108L2).

[0178] The semiconductor layer 108 includes a region 108C, a pair of regions 108L1, a pair of regions 108L2, and a pair of regions 108N. The region 108C overlaps with the conductive layer 112 and the insulating layer 110 and functions as a channel formation region. The region 108L1 is provided to sandwich the region 108C. The region 108L2 is provided to sandwich the region 108C and the pair of regions 108L1. The regions 108L1 and 108L2 include regions that do not overlap with the conductive layer 112 and overlap with the insulating layer 110. The region 108N is provided to sandwich the region 108C, the pair of regions 108L1, and the pair of regions 108L2. The region 108N does not overlap with either the conductive layer 112 or the insulating layer 110.

[0179] Regions 108L1 and 108L2 are regions of the semiconductor layer 108 that overlap with the insulating layer 110 but do not overlap with the conductive layer 112. In Figure 6A, the width of region 108C in the channel length direction of the transistor 100 is indicated as width L0, the width of region 108L1 as width L1, and the width of region 108L2 as width L2. In addition, the thickness of the insulating layer 110 in the region overlapping with region 108C is indicated as thickness TN0, the thickness of the insulating layer 110 in the region overlapping with region 108L1 as thickness TN1, and the thickness of the insulating layer 110 in the region overlapping with region 108L2 as thickness TN2.

[0180] The thickness TN1 is preferably approximately equal to the thickness TN0. The thickness TN2 is preferably 0.2 to 0.9 times the thickness TN1, more preferably 0.3 to 0.8 times, and even more preferably 0.4 to 0.7 times. By setting the thickness within the above range, the resistance of the region 108L1 and the region 108L2 can be controlled.

[0181] As will be described later, the regions 108L1 and 108L2 can be formed in a self-aligned manner, which eliminates the need for a photomask for forming the regions 108L1 and 108L2 and reduces manufacturing costs. Furthermore, by forming the regions 108L1 and 108L2 in a self-aligned manner, relative positional deviation between the regions 108L1, 108L2, and the conductive layer 112 does not occur, so the widths of the regions 108L1 and 108L2 in the semiconductor layer 108 can be approximately the same.

[0182] Between the region 108C functioning as a channel formation region and the low-resistance region 108N, the regions 108L1 and 108L2 functioning as offset regions to which the electric field of the gate is not applied (or to which the electric field is less applied than that of the region 108C) can be formed with uniformity and stability. As a result, the source-drain breakdown voltage of the transistor can be improved, resulting in a highly reliable transistor. Furthermore, the current density at the boundary between the region 108C and the region 108N can be reduced, suppressing heat generation at the boundary between the channel and the source or drain, resulting in a highly reliable transistor and semiconductor device.

[0183] The width L1 of the region 108L1 and the width L2 of the region 108L2 are preferably 50 nm to 1 μm, more preferably 70 nm to 700 nm, and even more preferably 100 nm to 500 nm. The provision of the regions 108L1 and 108L2 reduces electric field concentration near the drain, thereby suppressing transistor degradation, particularly when the drain voltage is high. In particular, making the total width of the widths L1 and L2 greater than the thickness of the insulating layer 110 effectively suppresses electric field concentration near the drain. On the other hand, if the total width of the widths L1 and L2 is greater than 2 μm, the source-drain resistance may increase, slowing the transistor's operating speed. Setting the widths L1 and L2 within the aforementioned ranges results in a highly reliable transistor and semiconductor device with a high operating speed. The widths L1 and L2 can be determined based on the thickness of the semiconductor layer 108, the thickness of the insulating layer 110, and the magnitude of the voltage applied between the source and drain when operating the transistor 100.

[0184] Preferably, the first side surface 110S1 and the second side surface 110S2 of the insulating layer 110 each have a tapered shape. The tapered shapes of the first side surface 110S1 and the second side surface 110S2 improve the coverage of a layer (e.g., the insulating layer 118) formed on the insulating layer 110, and can prevent defects such as discontinuities and voids in the layer. In the top view shown in FIG. 5A, the end of the insulating layer 110, the first side surface 110S1, and the second side surface 110S2 are indicated by dashed lines.

[0185] Angles θ1 and θ2 shown in FIGS. 6A and 6B will be described. Angle θ1 is the angle between the first side surface 110S1 and a surface extending into the insulating layer 110 from the upper surface of the insulating layer 110, with which the lower end of the first side surface 110S1 is in contact. Angle θ2 is the angle between the bottom surface of the insulating layer 110 and the second side surface 110S2. Each of angles θ1 and θ2 is preferably 30 degrees or more and less than 90 degrees, more preferably 35 degrees or more and 85 degrees or less, even more preferably 40 degrees or more and 80 degrees or less, even more preferably 45 degrees or more and 80 degrees or less, and even more preferably 50 degrees or more and 80 degrees or less. Setting the angles within the aforementioned ranges can improve the coverage of the insulating layer 118 provided on the insulating layer 110.

[0186] In this specification, the taper angle refers to the inclination angle between the side and bottom surfaces of a target layer when the layer is observed from a direction perpendicular to the cross section (e.g., a surface perpendicular to the surface of the substrate).

[0187] The concentration of the first element in region 108N preferably has a concentration gradient such that the concentration increases closer to insulating layer 118. This reduces the total amount of the first element in region 108N compared to when the concentration is uniform throughout region 108N, thereby keeping the amount of the first element that can diffuse into region 108C due to the influence of heat during the manufacturing process low. Furthermore, since the resistance decreases toward the top of region 108N, the contact resistance with conductive layer 120a (or conductive layer 120b) can be more effectively reduced.

[0188] The process of adding the first element to the regions 108L1, 108L2, and 108N can be performed using the conductive layer 112 and the insulating layer 110 as masks, thereby allowing the regions 108L1, 108L2, and 108N to be formed in a self-aligned manner.

[0189] The region 108N has a first element concentration of 1×10 19 atoms / cm 3 That's it, 1 x 10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm3 That's it, 5 x 10 22 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 That's it, 1 x 10 22 atoms / cm 3 It is preferred to include a region in which:

[0190] When an easily oxidizable element such as boron, phosphorus, magnesium, aluminum, or silicon is used as the first element, it is preferable that the first element exists in an oxidized state in each of the regions 108L1, 108L2, and 108N. Such an easily oxidizable element can exist stably in an oxidized state by bonding with oxygen in the semiconductor layer 108, and therefore is prevented from being desorbed even when a high temperature (for example, 400° C. or higher, 600° C. or higher, or 800° C. or higher) is applied in a later process. In addition, the first element removes oxygen from the semiconductor layer 108, thereby forming oxygen vacancies (V) in the regions 108L1, 108L2, and 108N. O ) is generated. This oxygen vacancy (V O ) is a defect in which hydrogen in the film enters (hereinafter referred to as V O H) serves as a carrier supply source, and the resistance of the region 108L1, the region 108L2, and the region 108N becomes low.

[0191] Here, the semiconductor layer 108 and oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0192] Oxygen vacancies formed in the channel formation region of the semiconductor layer 108 are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies and they can become carrier sources. When a carrier source is generated in the channel formation region, the electrical characteristics of the transistor 100 change, typically resulting in a shift in threshold voltage. Therefore, it is preferable to have fewer oxygen vacancies in the channel formation region.

[0193] Therefore, in one embodiment of the present invention, an insulating film near the channel formation region of the semiconductor layer 108, specifically, the insulating layer 110 located above the channel formation region and the insulating layer 103 located below the channel formation region, includes an oxide film or an oxynitride film. By transferring oxygen from the insulating layer 103 and the insulating layer 110 to the channel formation region by heat or the like during the manufacturing process, oxygen vacancies in the channel formation region can be reduced.

[0194] The semiconductor layer 108 preferably has a region where the atomic ratio of In to the element M is greater than 1. The higher the In content, the more the field-effect mobility of the transistor can be improved.

[0195] In the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is weaker than the bonding strength between Ga and oxygen, so oxygen vacancies are likely to form in the metal oxide film when the In content is high. The same tendency occurs when element M is used instead of Ga. The presence of many oxygen vacancies in the metal oxide film leads to deterioration in the electrical characteristics and reliability of the transistor.

[0196] However, in one embodiment of the present invention, a metal oxide material with a high In content can be used because an extremely large amount of oxygen can be supplied to the channel formation region of the semiconductor layer 108 containing a metal oxide. As a result, a transistor with extremely high field-effect mobility, stable electrical characteristics, and high reliability can be realized.

[0197] For example, metal oxides in which the atomic ratio of In to element M is 1.5 or more, or 2 or more, or 3 or more, or 3.5 or more, or 4 or more can be suitably used.

[0198] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is preferably In:M:Zn=4:2:3 or approximately thereabouts. Alternatively, the atomic ratio of In, M, and Zn is preferably In:M:Zn=5:1:6 or approximately thereabouts. Furthermore, the composition of the semiconductor layer 108 may be such that the atomic ratio of In, the element M, and Zn in the semiconductor layer 108 is approximately equal. That is, the semiconductor layer 108 may contain a material in which the atomic ratio of In, the element M, and Zn is In:M:Zn=1:1:1 or approximately thereabouts.

[0199] For example, by using the transistor with high field-effect mobility in a gate driver that generates gate signals, a display device with a narrow frame width (also called a narrow frame) can be provided.Furthermore, by using the transistor with high field-effect mobility in a source driver (especially a demultiplexer connected to an output terminal of a shift register included in the source driver), a display device with a small number of wirings connected to the display device can be provided.

[0200] Even if the semiconductor layer 108 has a region where the atomic ratio of In to the element M is greater than 1, the field-effect mobility may be reduced if the semiconductor layer 108 has high crystallinity. The crystallinity of the semiconductor layer 108 can be analyzed using, for example, X-ray diffraction (XRD) or a transmission electron microscope (TEM).

[0201] Here, the channel formation region of the semiconductor layer 108 has a low impurity concentration and a low defect state density (reduced oxygen vacancies), which allows the carrier concentration in the film to be low. A transistor using such a metal oxide film for the channel formation region of the semiconductor layer rarely exhibits electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). Furthermore, a transistor using such a metal oxide film can exhibit an extremely small off-state current.

[0202] When a metal oxide film with high crystallinity is used for the semiconductor layer 108, damage during processing of the semiconductor layer 108 or during deposition of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, when a metal oxide film with relatively low crystallinity is used for the semiconductor layer 108, electrical conductivity is improved, and a transistor with high field-effect mobility can be realized.

[0203] The semiconductor layer 108 is preferably a metal oxide film having a c-axis aligned crystal (CAAC) structure, a metal oxide film having a nano crystal (nc) structure, or a metal oxide film having a mixture of the CAAC structure and the nc structure, as described below.

[0204] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0205] For example, it is possible to use a semiconductor layer 108 in which two or more metal oxide films with different compositions are stacked. For example, when an In-M-Zn oxide is used, it is preferable to use a stack of two or more films formed with a sputtering target in which the atomic ratio of In, element M, and Zn is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn=1:3:2, or a ratio close to these.

[0206] A stack of two or more metal oxide films with different crystallinity can be used for the semiconductor layer 108. In this case, it is preferable to use the same oxide target and to form the films under different film formation conditions successively without exposure to the air.

[0207] In this case, the semiconductor layer 108 may have a stacked structure of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, the semiconductor layer 108 may have a stacked structure of a metal oxide film having an nc structure and a metal oxide film having an nc structure. Note that the function or material structure of a metal oxide that can be suitably used for the metal oxide film can be based on the description of CAC (Cloud-Aligned Composite) described later.

[0208] For example, the oxygen flow rate during deposition of the first metal oxide film is set lower than the oxygen flow rate during deposition of the second metal oxide film. Alternatively, oxygen is not supplied during deposition of the first metal oxide film. This allows oxygen to be effectively supplied during deposition of the second metal oxide film. Furthermore, the first metal oxide film can be made to have lower crystallinity than the second metal oxide film and higher electrical conductivity. On the other hand, by making the second metal oxide film provided on top a film with higher crystallinity than the first metal oxide film, damage during processing of the semiconductor layer 108 and during deposition of the insulating layer 110 can be suppressed.

[0209] More specifically, the oxygen flow ratio during deposition of the first metal oxide film is set to 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The oxygen flow ratio during deposition of the second metal oxide film is set to 50% or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less, and typically 100%. Although the conditions during deposition, such as pressure, temperature, and power, may be different between the first and second metal oxide films, it is preferable to keep the conditions other than the oxygen flow ratio the same, since this shortens the time required for the deposition process.

[0210] With this structure, a transistor 100 with excellent electrical characteristics and high reliability can be realized.

[0211] 5A and 5B, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over an insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode and a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108N through an opening 141a and an opening 141b, respectively, provided in the insulating layer 118.

[0212] This concludes the description of configuration example 2-1.

[0213] Below, a description will be given of a configuration example of a transistor that is partially different in configuration from the above-mentioned configuration example 2-1. Note that, below, a description of parts that overlap with the above-mentioned configuration example 2-1 may be omitted. Also, in the drawings shown below, parts that have the same function as the above-mentioned configuration example may be hatched with the same pattern and may not be assigned a reference symbol.

[0214] [Configuration Example 2-2] Fig. 7A is a top view of the transistor 100A, Fig. 7B is a cross-sectional view of the transistor 100A in the channel length direction, and Fig. 7C is a cross-sectional view of the transistor 100A in the channel width direction. Fig. 8A shows an enlarged view of a region P surrounded by a dashed line in Fig. 7B, and Fig. 8B shows an enlarged view of a region Q. Fig. 8C shows an enlarged view of a region R surrounded by a dashed line in Fig. 7C.

[0215] The transistor 100A differs from the transistor 100 mainly in that the transistor 100A includes an insulating layer 103 and a conductive layer 106 between the substrate 102 and the semiconductor layer 108. The conductive layer 106 has a region overlapping with the region 108C.

[0216] In the transistor 100A, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode). Part of the insulating layer 103 functions as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.

[0217] A portion of the semiconductor layer 108 overlapping with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of description, the portion of the semiconductor layer 108 overlapping with the conductive layer 112 will be referred to as a channel formation region in some cases below; however, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106.

[0218] 7A and 7C, the conductive layer 106 may be electrically connected to the conductive layer 112 through the insulating layer 110 and the opening 142 provided in the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be applied with the same potential.

[0219] The conductive layer 106 can be formed using a material that can be used for the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because wiring resistance can be reduced. Furthermore, if a material containing a high-melting-point metal such as tungsten or molybdenum is used for the conductive layer 106, processing can be performed at a high temperature in a later step.

[0220] 7A and 7C, it is preferable that the conductive layer 112 and the conductive layer 106 protrude outward in the channel width direction beyond the end portions of the semiconductor layer 108. In this case, as shown in Fig. 7C, the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 via the insulating layer 110 and the insulating layer 103.

[0221] With this structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. In this case, it is particularly preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. This allows an electric field for inducing a channel in the semiconductor layer 108 to be effectively applied, thereby increasing the on-state current of the transistor 100A. This also enables miniaturization of the transistor 100A.

[0222] Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. In this case, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be applied to the other. In this case, the threshold voltage when the transistor 100A is driven by the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0223] The insulating layer 103 can have a stacked structure. 7B and 7C show an example in which the insulating layer 103 has a three-layer structure in which an insulating layer 103a, an insulating layer 103b, and an insulating layer 103c are stacked in this order from the conductive layer 106 side. The insulating layer 103a is in contact with the conductive layer 106. The insulating layer 103c is in contact with the semiconductor layer 108. The above description can be referred to for the insulating layer 103, and therefore detailed description thereof will be omitted.

[0224] Note that when a metal film or an alloy film that is difficult to diffuse into the insulating layer 103 is used as the conductive layer 106, the insulating layer 103a and the insulating layer 103b are not provided, and a single layer structure of the insulating layer 103c may be used.

[0225] The transistor 100A has a region where the insulating layer 103c and the insulating layer 118 are in contact with each other. By having a region where the insulating layer 103c and the insulating layer 118 are in contact with each other, oxygen contained in the insulating layer 118 can diffuse into the semiconductor layer 108 through the insulating layer 103c, thereby reducing oxygen defects in the semiconductor layer 108.

[0226] This concludes the description of configuration example 2-2.

[0227] [Configuration Example 2-3] 9A to 9C show structures different from those of the transistor 100A. FIG. 9A is a top view of the transistor 100B, FIG. 9B is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 9C is a cross-sectional view of the transistor 100B in the channel width direction. FIG. 10A shows an enlarged view of a region Q surrounded by a dashed line in FIG. 9B. FIG. 10B shows an enlarged view of a region R surrounded by a dashed line in FIG. 9C. FIG. 8A can be referred to for an enlarged view of a region P surrounded by a dashed line in FIG. 9B.

[0228] 10A and 10B, the transistor 100B differs from the transistor 100A mainly in that the transistor 100B has a region where the insulating layer 118 and the insulating layer 103b are in contact with each other. The region of the insulating layer 118 that does not overlap with the semiconductor layer 108 is provided in contact with the insulating layer 103c. The edge of the insulating layer 103c roughly coincides with the edge of the semiconductor layer 108. For example, when forming the insulating layer 110, a part of the insulating film that will become the insulating layer 103c is removed to form the insulating layer 103c, thereby making it possible to roughly coincide the edge of the insulating layer 103c with the edge of the semiconductor layer 108.

[0229] This concludes the description of configuration example 2-3.

[0230] [Configuration Example 2-4] 11A is a cross-sectional view of a transistor 100C, in which the cross section in the channel length direction is shown to the left of the dashed dotted line, and the cross section in the channel width direction is shown to the right of the dashed dotted line.

[0231] The transistor 100C differs from the transistor 100B mainly in that the insulating layer 118 has a stacked structure. The insulating layer 118 can have a stacked structure of two or more layers. When the insulating layer 118 has a stacked structure, it is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0232] FIG. 11A shows an example in which insulating layer 118 has a two-layer structure consisting of insulating layer 118a and insulating layer 118b on insulating layer 118a. Materials that can be used for insulating layer 118 can be used for insulating layer 118. Insulating layers 118a and 118b may be made of the same material, or different materials. Because insulating layers 118a and 118b can be made of insulating films made of the same material, the interface between insulating layers 118a and 118b may not be clearly visible. Therefore, in FIG. 11A, the interface between insulating layers 118a and 118b is indicated by a dashed line.

[0233] 11B and 11C show configurations different from transistor 100C. FIG. 11B is a cross-sectional view of transistor 100D. FIG. 11C is a cross-sectional view of transistor 100E. In each of FIGS. 11B and 11C, the cross section in the channel length direction is clearly shown to the left of the dashed dotted line, and the cross section in the channel width direction is clearly shown to the right.

[0234] The transistor 100D and the transistor 100E have a structure in which the insulating layer 118a and the insulating layer 118b are made of different materials.

[0235] The transistor 100D has a structure in which the insulating layer 118a has a higher barrier property against oxygen than the insulating layer 118b. For example, the insulating layer 118a can be formed using a nitride or a nitride oxide, and the insulating layer 118b can be formed using an oxide or an oxynitride.

[0236] The transistor 100E has a structure in which the insulating layer 118b has a higher barrier property against oxygen than the insulating layer 118a. For example, the insulating layer 118a can be formed using an oxide or an oxynitride, and the insulating layer 118b can be formed using a nitride or a nitride oxide.

[0237] When a high-temperature treatment is performed after the insulating layer 118 is formed, a large amount of oxygen may be supplied to the region 108N from the outside of the transistor or from a film in the vicinity of the region 108N, which may increase the resistance of the region 108N. Therefore, when a high-temperature treatment is performed, it is preferable to perform the treatment while the semiconductor layer 108 is covered with an insulating layer that has a high barrier property against oxygen.

[0238] This concludes the description of configuration example 2-4.

[0239] [Configuration Example 2-5] 12 is a cross-sectional view of a transistor 100F, in which the cross section in the channel length direction is shown to the left of the dashed dotted line, and the cross section in the channel width direction is shown to the right of the dashed dotted line.

[0240] The transistor 100F differs from the transistor 100C mainly in that the transistor 100F has a metal oxide layer 114 between the insulating layer 110 and the conductive layer 112. The above description can be referred to for materials that can be used for the metal oxide layer 114, and therefore detailed description thereof will be omitted.

[0241] 12 shows an example in which the end of the conductive layer 112 and the end of the metal oxide layer 114 are approximately aligned. By forming the metal oxide layer 114 when forming the conductive layer 112, the end of the conductive layer 112 and the end of the metal oxide layer 114 can be approximately aligned. Note that the end of the conductive layer 112 and the end of the metal oxide layer 114 do not necessarily have to be approximately aligned. For example, the end of the conductive layer 112 may be located more inward than the end of the metal oxide layer 114.

[0242] This concludes the description of configuration example 2-5.

[0243] [Configuration Example 2-6] 13A to 13C show structures different from those of the transistor 100B. Fig. 13A is a top view of the transistor 100G, Fig. 13B is a cross-sectional view of the transistor 100G in the channel length direction, and Fig. 13C is a cross-sectional view of the transistor 100G in the channel width direction. Fig. 14 shows an enlarged view of a region P surrounded by a dashed line in Fig. 13B.

[0244] As shown in FIGS. 13B, 13C, and 14, the transistor 100B differs mainly in that it has a region 108L3 between the region 108N and the region 108L2.

[0245] 14, the width of region 108C in the channel length direction of transistor 100G is indicated as width L0, the width of region 108L1 as width L1, the width of region 108L2 as width L2, and the width of region 108L3 as width L3. Also, the thickness of insulating layer 110 in the region overlapping with region 108C is indicated as thickness TN0, the thickness of insulating layer 110 in the region overlapping with region 108L1 as thickness TN1, the thickness of insulating layer 110 in the region overlapping with region 108L2 as thickness TN2, and the thickness of insulating layer 110 in the region overlapping with region 108L3 as thickness TN3.

[0246] It is preferable that the film thickness TN0 is approximately equal to the film thickness TN1. Furthermore, the film thickness TN2 is preferably 0.2 to 0.9 times the film thickness TN1, more preferably 0.3 to 0.8 times, and even more preferably 0.4 to 0.7 times. The film thickness TN3 is preferably 0.1 to 0.6 times the film thickness TN1, more preferably 0.15 to 0.5 times, and even more preferably 0.2 to 0.4 times. By setting the film thickness within the above range, the resistance of the regions 108L1, 108L2, and 108L3 can be controlled.

[0247] The widths L1, L2, and L3 are each preferably 50 nm to 1 μm, more preferably 70 nm to 700 nm, and even more preferably 100 nm to 500 nm. In particular, by making the total width of the widths L1, L2, and L3 greater than the thickness of the insulating layer 110, electric field concentration near the drain can be effectively suppressed. On the other hand, if the total width of the widths L1, L2, and L3 is greater than 2 μm, the source-drain resistance may increase, slowing the transistor's operating speed. By setting the widths L1, L2, and L3 within the aforementioned ranges, a highly reliable transistor and semiconductor device with a high operating speed can be obtained. The widths L1, L2, and L3 can be determined based on the thickness of the semiconductor layer 108, the thickness of the insulating layer 110, and the magnitude of the voltage applied between the source and drain when operating the transistor 100.

[0248] It is preferable that the first side surface 110S1, the second side surface 110S2, and the third side surface 110S3 of the insulating layer 110 each have a tapered shape. The tapered shapes of the first side surface 110S1, the second side surface 110S2, and the third side surface 110S3 improve the coverage of a layer (e.g., the insulating layer 118) formed on the insulating layer 110, and can prevent defects such as discontinuities and voids from occurring in the layer.

[0249] 14 shows the angle θ1 between the first side surface 110S1 and the surface to which the lower end of the first side surface 110S1 contacts, the angle θ2 between the second side surface 110S2 and the surface to which the lower end of the second side surface 110S2 contacts, and the angle θ3 between the third side surface 110S3 and the surface to which the lower end of the third side surface 110S3 contacts. The angles θ1, θ2, and θ3 are each preferably 30 degrees or greater and less than 90 degrees, more preferably 35 degrees or greater and 85 degrees or less, even more preferably 40 degrees or greater and 80 degrees or less, and even more preferably 45 degrees or greater and 75 degrees or less. Setting the angles within the above ranges can improve the coverage of the insulating layer 118 provided on the insulating layer 110.

[0250] Angles θ1, θ2, and θ3 shown in FIG. 14 will be described. Angle θ1 is the angle between the first side surface 110S1 and a plane extending into the insulating layer 110 from the upper surface of the insulating layer 110, with which the lower end of the first side surface 110S1 contacts. Angle θ2 is the angle between the second side surface 110S2 and a plane extending into the insulating layer 110 from the upper surface of the insulating layer 110, with which the lower end of the second side surface 110S2 contacts. Angle θ3 is the angle between the bottom surface of the insulating layer 110 and the third side surface 110S3. Each of angles θ1, θ2, and θ3 is preferably 30 degrees or more and less than 90 degrees, more preferably 35 degrees or more and 85 degrees or less, even more preferably 40 degrees or more and 80 degrees or less, and even more preferably 45 degrees or more and 75 degrees or less. By setting the angle in the above range, the coverage of the insulating layer 118 provided over the insulating layer 110 can be improved.

[0251] This concludes the description of configuration example 2-6.

[0252] <Production method example 1> A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings, taking the transistor 100C given as an example in the above structure example as an example.

[0253] The thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0254] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0255] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0256] There are two typical photolithography methods: One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and then the resist mask is removed. The other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into the desired shape.

[0257] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. Instead of light used for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0258] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0259] 15A to 15D, 16A to 16C, 17A to 17C, and 18A to 18C show cross sections of the transistor 100C at various stages in the manufacturing process, with the channel length direction cross section shown to the left of the central dashed line and the channel width direction cross section shown to the right of the dashed line.

[0260] [Formation of Conductive Layer 106] A conductive film is formed over the substrate 102 and processed by etching to form a conductive layer 106 that functions as a first gate electrode. At this time, it is preferable to process the conductive layer 106 so that the end portion thereof has a tapered shape. This can improve the step coverage of the insulating layer 103 to be formed next.

[0261] Furthermore, by using a conductive film containing copper as the conductive layer 106, wiring resistance can be reduced. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a display device with high resolution, a conductive film containing copper is preferably used. Even when a conductive film containing copper is used for the conductive layer 106, the insulating layer 103 prevents copper from diffusing toward the semiconductor layer 108, so that a highly reliable transistor can be realized.

[0262] [Formation of insulating layer 103] Subsequently, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 15A). The insulating layer 103 can be formed using a PECVD method, an ALD method, a sputtering method, or the like.

[0263] Here, the insulating layer 103 is formed by stacking insulating layers 103a, 103b, and 103c. In particular, it is preferable that each insulating layer constituting the insulating layer 103 is formed by a PECVD method. The formation of the insulating layer 103 can be referred to in the description of the above-mentioned Configuration Example 1, and therefore a detailed description thereof will be omitted.

[0264] After the insulating layer 103 is formed, treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method or an ion implantation method.

[0265] [Formation of Semiconductor Layer 108] Subsequently, a metal oxide film 108f that will become the semiconductor layer 108 is formed on the insulating layer 103 (FIG. 15B).

[0266] The metal oxide film 108f is preferably formed by sputtering using a metal oxide target.

[0267] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0268] When forming the metal oxide film 108f, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, resulting in a transistor with increased on-state current.

[0269] When the semiconductor layer 108 has a stacked structure, it is preferable to deposit the films successively in the same deposition chamber using the same sputtering target, since this can improve the interface. In particular, although the deposition conditions for each metal oxide film may be different, such as pressure, temperature, and power, it is preferable to keep the conditions other than the oxygen flow rate the same, since this can shorten the time required for the deposition process. Furthermore, when metal oxide films with different compositions are stacked, it is preferable to deposit the films successively without exposing them to the air.

[0270] It is preferable to set the deposition conditions so that the metal oxide film 108f becomes a metal oxide film having a CAAC structure, a metal oxide film having an nc structure, or a metal oxide film having a mixture of the CAAC structure and the nc structure. Note that the deposition conditions under which the metal oxide film to be deposited has a CAAC structure and the nc structure differ depending on the composition of the sputtering target used, and therefore, the substrate temperature, oxygen flow rate, pressure, power, and the like can be appropriately set according to the composition.

[0271] The substrate temperature during deposition of the metal oxide film 108f is preferably from room temperature to 450° C., more preferably from room temperature to 300° C., even more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, when a large glass substrate or a resin substrate is used as the substrate 102, it is preferable to set the substrate temperature to from room temperature to less than 140° C., as this increases productivity. Furthermore, by depositing the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0272] Before forming the metal oxide film 108f, it is preferable to perform a treatment for desorbing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103, and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced-pressure atmosphere. Alternatively, plasma treatment may be performed in an oxygen-containing atmosphere. By performing plasma treatment in an oxygen-containing atmosphere, such as an atmosphere containing nitrous oxide gas, oxygen can be supplied to the insulating layer 103. Furthermore, by performing plasma treatment in an atmosphere containing nitrous oxide gas, organic substances on the surface of the insulating layer 103 can be suitably removed. After such treatment, it is preferable to form the metal oxide film 108f successively without exposing the surface of the insulating layer 103 to the air.

[0273] Subsequently, the metal oxide film 108f is processed to form island-shaped semiconductor layers 108 (FIG. 15C).

[0274] The metal oxide film 108f may be processed by wet etching, dry etching, or both. At this time, a part of the insulating layer 103c that does not overlap with the semiconductor layer 108 may be etched and removed. By removing the part of the insulating layer 103c, the semiconductor layer 108 and the insulating layer 103c have roughly the same top surface shape. Furthermore, by removing the part of the insulating layer 103c, a part of the insulating layer 103b is exposed, and the insulating layer 118, which will be formed later, can be in contact with the insulating layer 103b.

[0275] After the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108, heat treatment may be performed to remove hydrogen or water from the metal oxide film or the semiconductor layer 108. The heat treatment can remove hydrogen or water contained in or adsorbed to the surface of the metal oxide film 108f or the semiconductor layer 108. The heat treatment may also improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, reduce defects, improve crystallinity, etc.).

[0276] By the heat treatment, oxygen can also be supplied from the insulating layer 103 to the metal oxide film 108f or the semiconductor layer 108. In the case where oxygen is supplied from the insulating layer 103, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108.

[0277] The temperature of the heat treatment can be typically 150° C. or higher and lower than the strain point of the substrate, or 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower. Note that the heat treatment does not necessarily have to be performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108. The heat treatment may be performed at any stage after the metal oxide film is formed. Alternatively, the heat treatment may be performed together with a later heat treatment or a step in which heat is applied.

[0278] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, heating in such an atmosphere may be performed, followed by heating in an atmosphere containing oxygen. Ultra-dry air (CDA: Clean Dry Air) may be used as the atmosphere containing nitrogen or oxygen. Note that the atmosphere for the heat treatment preferably does not contain hydrogen, water, or the like. By using a gas that has been highly purified to a dew point of −60° C. or less, preferably −100° C. or less, it is possible to prevent hydrogen, water, or the like from being taken into the semiconductor layer 108 as much as possible. The heat treatment can be performed using an electric furnace, a rapid thermal annealing (RTA) apparatus, or the like. The use of an RTA apparatus can shorten the heat treatment time.

[0279] It is preferable to form the insulating film 110f immediately after forming the semiconductor layer 108. When the surface of the semiconductor layer 108 is exposed, water may be adsorbed onto the surface of the semiconductor layer 108. If water is adsorbed onto the surface of the semiconductor layer 108, hydrogen may be diffused into the semiconductor layer 108 by a subsequent heat treatment or the like, and V O H may be formed. V O Since H can be a carrier generation source, it is preferable that the amount of adsorbed water in the semiconductor layer 108 is small.

[0280] [Formation of insulating film 110f] Subsequently, an insulating film 110f is formed to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 15D).

[0281] The insulating film 110f is a film that will later become the insulating layer 110. The insulating film 110f is preferably formed by forming an oxide film or an oxynitride film, such as a silicon oxide film or a silicon oxynitride film, using a plasma enhanced chemical vapor deposition (PECVD) apparatus. Alternatively, the insulating film 110f may be formed by a PECVD method using microwaves.

[0282] After the insulating film 110f is formed, heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas. Note that the heat treatment does not necessarily have to be performed after the insulating film 110f is formed. Furthermore, the heat treatment may be performed at any stage after the insulating film 110f is formed. Furthermore, the heat treatment may be performed in combination with a later heat treatment or a process in which heat is applied.

[0283] It is preferable to perform plasma treatment on the surface of the semiconductor layer 108 before forming the insulating film 110f. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating film 110f can be reduced, resulting in a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating film 110f. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. It is also preferable to perform the plasma treatment and the formation of the insulating film 110f consecutively without exposure to the air.

[0284] Here, after the insulating film 110f is formed, it is preferable to perform heat treatment. The heat treatment can remove hydrogen or water contained in the insulating film 110f or adsorbed on the surface thereof and can also reduce defects in the insulating film 110f.

[0285] The conditions for the heat treatment can be as described above.

[0286] After forming the insulating film 110f or after performing the heat treatment to remove hydrogen or water, a treatment to supply oxygen to the insulating film 110f may be performed. For example, a plasma treatment or a heat treatment may be performed in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating film 110f by a plasma ion doping method, an ion implantation method, or the like. For example, a PECVD apparatus can be suitably used for the plasma treatment. When the insulating film 110f is formed using a PECVD apparatus, it is preferable to perform a plasma treatment in a vacuum successively after the formation of the insulating film 110f. By performing the formation of the insulating film 110f and the plasma treatment successively in a vacuum, productivity can be improved.

[0287] When heat treatment is performed after the treatment of supplying oxygen to the insulating film 110f, it is preferable to perform the heat treatment after a film (for example, the metal oxide film 114f) is formed on the insulating film 110f. If the heat treatment is performed in an exposed state of the insulating film 110f, the oxygen supplied to the insulating film 110f may be desorbed out of the insulating film 110f. By performing the heat treatment after a film (for example, the metal oxide film 114f) is formed on the insulating film 110f, the oxygen supplied to the insulating film 110f can be prevented from being desorbed out of the insulating film 110f.

[0288] [Formation of opening 142] Subsequently, insulating layer 110 and a portion of insulating layer 103 are removed to form openings 142 that reach conductive layer 106 (FIG. 16A). This allows conductive layer 106 to be electrically connected to conductive layer 112, which will be formed later, through openings 142.

[0289] [Formation of Conductive Film 112f] Subsequently, a conductive film 112f is formed to become the conductive layer 112 (FIG. 16B). The conductive film 112f is preferably formed by sputtering using a sputtering target of a metal or alloy.

[0290] [Formation of insulating layer 110 and conductive layer 112] Subsequently, a resist mask 115 is formed on the conductive film 112f (FIG. 16B). After that, the conductive film 112f in the region not covered with the resist mask 115 is removed, and the conductive layer 112 is formed (FIG. 16C).

[0291] A wet etching method can be suitably used to form the conductive layer 112. For example, an etchant containing hydrogen peroxide can be used in the wet etching method. For example, an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid can be used. In particular, when a material containing copper is used for the conductive layer 112, an etchant containing phosphoric acid, acetic acid, and nitric acid can be suitably used.

[0292] 16C, the conductive layer 112 is processed so that the edge of the conductive layer 112 is positioned inside the outline of the resist mask 115. A wet etching method is preferably used to form the conductive layer 112. The width L0 of the region 108C can be controlled by adjusting the etching time.

[0293] The conductive layer 112 may be formed by etching at least two times using different etching conditions or techniques. For example, the conductive film 112f may be etched by anisotropic etching, and then the side surfaces of the conductive film 112f may be etched by isotropic etching to recess the end surfaces (also referred to as side etching). This allows the conductive layer 112 to be formed on the inner side of the insulating layer 110 in a plan view.

[0294] Next, the insulating film 110f is removed from the region not covered by the resist mask 115, to form the insulating layer 110A (FIG. 17A). Anisotropic etching is preferably used to form the insulating layer 110A. In particular, dry etching is preferably used. By using dry etching, the edge of the resist mask 115 and the edge of the insulating layer 110A can be made to roughly coincide with each other.

[0295] Next, the resist mask 115 is shrunk to form a resist mask 115a (FIG. 17B). In FIG. 17B, the resist mask 115 before being shrunk is indicated by a dashed line together with the resist mask 115a after being shrunk. The edge of the resist mask 115a is preferably located outside the edge of the conductive layer 112. In other words, the edge of the resist mask 115a is preferably located between the edge of the conductive layer 112 and the edge of the insulating layer 110A.

[0296] The resist mask 115a can be preferably formed by an ashing method. For example, plasma ashing may be used, in which a gas such as oxygen or ozone is converted into plasma by high frequency or the like and the plasma is used to react with the resist mask. Alternatively, photoexcited ashing may be used, in which a gas such as oxygen or ozone is irradiated with light such as ultraviolet light to promote the reaction between the gas and the resist mask. Note that the ashing method may reduce the area of ​​the resist mask 115 in a plan view and may also reduce the film thickness of the resist mask 115.

[0297] Next, a portion of the insulating layer 110A is removed in the region not covered by the resist mask 115a to form the insulating layer 110 (FIG. 17C). Anisotropic etching is preferably used to form the insulating layer 110. Dry etching is particularly suitable. At this time, it is preferable to process the exposed region of the insulating layer 110A by removing only a portion of the upper portion of the insulating layer 110A in that region (hereinafter referred to as half etching) to reduce the film thickness. In this way, the resist mask used to process the insulating layer is reduced in size, and the insulating layer is then processed again using the reduced resist mask, thereby forming the insulating layer 110 having a stepped shape. Furthermore, the width L2 of the region 108L2 can be controlled by adjusting the amount by which the resist mask is reduced.

[0298] Since half etching is used to form the insulating layer 110, it is preferable to confirm in advance the etching rate of the film that will become the insulating layer 110A and calculate the etching time required to reach the desired film thickness TN2. By performing half etching for the calculated etching time, the insulating layer 110 can be formed with high precision. Furthermore, by using dry etching to form the insulating layer 110, the film thickness TN2 can be finely adjusted, resulting in a transistor with good electrical characteristics and high reliability.

[0299] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0300] Here, cleaning may be performed to remove impurities. By performing cleaning, impurities attached to the exposed regions of the insulating layer 110 and the semiconductor layer 108 can be removed, thereby preventing deterioration in the electrical characteristics and reliability of the transistor. The impurities include, for example, components of the etching gas or etchant that are attached during etching of the insulating film 110f, components of the conductive film 112f, and components of the metal oxide film 114f.

[0301] The cleaning method can be wet cleaning using a cleaning solution or plasma treatment, or a combination of these cleaning methods. Wet cleaning can use a cleaning solution containing oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, or the like.

[0302] [Formation of insulating layer 118] Subsequently, the insulating layer 118 is formed to cover the insulating layer 103, the semiconductor layer 108, the insulating layer 110, and the conductive layer 112. Here, a structure in which the insulating layer 118 has a stacked structure of an insulating layer 118a and an insulating layer 118b will be described.

[0303] An insulating layer 118a is formed to cover the insulating layer 103, the semiconductor layer 108, the insulating layer 110 and the conductive layer 112 (FIG. 18A).

[0304] The insulating layer 118a is preferably formed by plasma CVD using a deposition gas containing hydrogen. For example, a silicon nitride film is formed using a deposition gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen can be contained in the film. Furthermore, hydrogen can be supplied to the exposed portion of the semiconductor layer 108 during film formation. By supplying hydrogen, an extremely low-resistance region 108N can be formed in the semiconductor layer 108.

[0305] Next, using the conductive layer 112 as a mask, the first element 140 is supplied (also referred to as added or injected) to the semiconductor layer 108 through the insulating layer 110 and the insulating layer 118a ( FIG. 18B ). By supplying the first element 140 to the semiconductor layer 108, the resistance of the semiconductor layer 108 in the region not covered with the conductive layer 112 is reduced, and regions 108L1, 108L2, and 108N can be formed. At this time, the total thickness of the insulating layer 118a and the insulating layer 110 provided over the regions 108L1, 108L2, and 108N decreases in the order of the region 108L1, the region 108L2, and the region 108N. Therefore, the amount of the first element 140 supplied increases in the order of the region 108L1, the region 108L2, and the region 108N, and the resistance can be decreased in this order. By adjusting the thickness of the insulating layer 110, the thickness of the insulating layer 118a, and the conditions for supplying the first element 140, the resistance of each of the regions 108L1, 108L2, and 108N can be controlled.

[0306] It is preferable to determine the conditions for supplying the first element 140 in consideration of the material and thickness of the conductive layer 112 so as to minimize the supply of the first element 140 to the region 108C of the semiconductor layer 108 that overlaps with the conductive layer 112. This makes it possible to form the region 108C with a sufficiently reduced impurity concentration in the region of the semiconductor layer 108 that overlaps with the conductive layer 112.

[0307] For elements that can be used as the first element 140, the above description can be referred to, and therefore a detailed description thereof will be omitted.

[0308] Plasma treatment can be suitably used to supply the first element 140. When using plasma treatment, plasma is generated in a gas atmosphere containing the first element 140 to be added, and the plasma treatment is performed, thereby allowing the first element 140 to be added. As an apparatus for generating plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

[0309] The supply of the first element 140 may be performed continuously after the insulating layer 118a is formed without exposing it to the atmosphere. For example, by using a plasma CVD apparatus, the supply of the first element 140 can be performed continuously after the insulating layer 118a is formed without exposing it to the atmosphere. By performing the supply of the first element 140 continuously, the productivity of the semiconductor device can be improved.

[0310] When performing plasma processing, a gas containing the first element can be used as a gas for supplying the first element 140. In particular, it is preferable to use a gas containing hydrogen, and by adding hydrogen to the region 108L1, the region 108L2, and the region 108N, the resistance of each can be controlled. As the gas containing the first element 140, for example, hydrogen (H2), ammonia (NH3), or silane (SiH4) can be suitably used.

[0311] The substrate temperature during the plasma treatment is preferably from room temperature to 450° C., more preferably from 150° C. to 400° C., and even more preferably from 200° C. to 350° C. By setting the substrate temperature within the above range, the reaction between the material constituting the semiconductor layer 108 and the first element 140 is promoted, and the resistance of the semiconductor layer 108 can be reduced.

[0312] The pressure in the processing chamber during plasma processing is preferably 50 Pa or more and 1500 Pa or less, more preferably 100 Pa or more and 1000 Pa or less, even more preferably 120 Pa or more and 500 Pa or less, and even more preferably 150 Pa or more and 300 Pa or less. By setting the pressure within the above range, plasma can be generated stably.

[0313] By appropriately selecting the conditions of the plasma treatment, the amount of the first element 140 added to the semiconductor layer 108 can be adjusted, thereby controlling the resistance value. Furthermore, since the first element 140 is added to the semiconductor layer 108 through the insulating layer 118a and the insulating layer 110, it is preferable to adjust the thickness of the insulating layer 118a and the insulating layer 110 so as to achieve a desired resistance.

[0314] Alternatively, the first element 140 may be supplied by a process utilizing thermal diffusion caused by heating using a gas containing the first element 140.

[0315] Alternatively, the first element 140 may be supplied by plasma ion doping or ion implantation. These methods allow for highly accurate control of the concentration profile in the depth direction by adjusting the ion acceleration voltage, dose, and the like. The use of plasma ion doping can improve productivity. The use of ion implantation using mass separation can increase the purity of the supplied first element. In particular, one or more of boron, phosphorus, aluminum, magnesium, and silicon can be preferably used as the first element 140.

[0316] In the supplying process of the first element 140, it is preferable to control the processing conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 110, or at a portion in the semiconductor layer 108 close to the interface, or at a portion in the insulating layer 110 close to the interface. This makes it possible to supply the first element 140 at an optimum concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0317] When using plasma ion doping or ion implantation, a gas containing the first element described above can be used as the gas supplying the first element 140. When supplying boron, B2H6 gas or BF3 gas can be typically used. When supplying phosphorus, PH3 gas can be typically used. A mixed gas obtained by diluting these source gases with a rare gas can also be used. Other examples of gases that can be used to supply the first element 140 include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to a gas; a solid or liquid vaporized by heating can also be used.

[0318] The addition of the first element 140 can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108.

[0319] For example, when adding boron by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 5 kV to 100 kV, preferably 7 kV to 70 kV, and more preferably 10 kV to 50 kV. The dose can be, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than 1 × 10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The range can be as follows:

[0320] When phosphorus ions are added by ion implantation or plasma ion doping, the acceleration voltage can be set to, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less. The dose can be set to, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than 1 × 10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Less than or equal to 1×10 15 ions / cm 2 3x10 or more 16 ions / cm 2 The range can be as follows:

[0321] In one embodiment of the present invention, the first element 140 can be supplied to the semiconductor layer 108 through the insulating layer 110 and the insulating layer 118a. Therefore, even when the semiconductor layer 108 has crystallinity, damage to the semiconductor layer 108 when the first element 140 is supplied can be reduced, and loss of crystallinity can be suppressed. Therefore, this is preferable in cases where electrical resistance increases due to a decrease in crystallinity.

[0322] Although the formation method in which the first element 140 is supplied to the semiconductor layer 108 after the insulating layer 118a is formed is described here, one embodiment of the present invention is not limited to this. The first element 140 may be supplied to the semiconductor layer 108 before the insulating layer 118a is formed. Alternatively, the first element 140 may be supplied to the semiconductor layer 108 after the insulating layer 118b is formed.

[0323] Subsequently, insulating layer 118b is formed to cover insulating layer 118a (FIG. 18C).

[0324] By using a plasma CVD apparatus for forming the insulating layer 118a, supplying the first element 140, and forming the insulating layer 118b, these processes can be performed consecutively. By performing the processes consecutively in the plasma CVD apparatus, it is possible to prevent impurities from adhering to the interface between the insulating layer 118a and the insulating layer 118b. It is also possible to improve the productivity of the semiconductor device.

[0325] When the insulating layer 118 is formed by plasma CVD, if the film formation temperature is too high, depending on the impurities contained in the region 108N, the impurities may diffuse to the surrounding area including the region 108C. As a result, the resistance of the region 108C may decrease, or the resistance of the region 108N may increase. The film formation temperature for the insulating layer 118 is preferably, for example, 150°C to 400°C, more preferably 180°C to 360°C, and even more preferably 200°C to 250°C. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0326] After the insulating layer 118 is formed, heat treatment may be performed.

[0327] [Formation of Openings 141a and 141b] Subsequently, a portion of the insulating layer 118 is removed to form an opening 141a and an opening 141b that reach the region 108N.

[0328] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed to form the conductive layers 120a and 120b (FIG. 11A).

[0329] Through the above steps, the transistor 100C can be manufactured.

[0330] <Production method example 2> The following description will be given taking as an example a configuration in which the metal oxide layer 114 is provided between the conductive layer 112 and the insulating layer 110, as exemplified in the transistor 100F.

[0331] The steps up to the formation of the insulating film 110f are the same as those in the above-described <Manufacturing Method Example 1> (see FIGS. 15A to 15D).

[0332] [Formation of Metal Oxide Film 114f] Subsequently, a metal oxide film 114f is formed to cover the insulating film 110f (FIG. 19A).

[0333] The metal oxide film 114f is a film that will later become the metal oxide layer 114. The metal oxide film 114f is preferably formed by sputtering in an atmosphere containing oxygen, for example, so that oxygen can be supplied to the insulating film 110f during the formation of the metal oxide film 114f.

[0334] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that used for the semiconductor layer 108, the above method can be applied.

[0335] The metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, an aluminum oxide film can be formed.

[0336] During the deposition of the metal oxide film 114f, the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber is preferably higher, because this increases the amount of oxygen supplied to the insulating layer 110. The oxygen flow rate ratio or oxygen partial pressure is, for example, greater than 0% and less than or equal to 100%, preferably 10% to 100%, more preferably 20% to 100%, even more preferably 30% to 100%, and still more preferably 40% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0337] By forming the metal oxide film 114f by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110f during the formation of the metal oxide film 114f and oxygen desorption from the insulating film 110f can be prevented. As a result, an extremely large amount of oxygen can be trapped in the insulating film 110f. Then, by subsequent heat treatment, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, oxygen vacancies in the channel formation region can be reduced, and a highly reliable transistor can be realized.

[0338] The substrate temperature during deposition of the metal oxide film 114f is preferably from room temperature to 450°C, more preferably from room temperature to 300°C, even more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, when a large glass substrate or a resin substrate is used as the substrate 102, it is preferable to set the substrate temperature to from room temperature to less than 140°C, as this increases productivity. Furthermore, if the substrate temperature during deposition of the metal oxide film 114f is high, the crystallinity of the metal oxide film 114f may increase, resulting in a slower etching rate. If the substrate temperature is low, the crystallinity of the metal oxide film 114f may decrease, resulting in a faster etching rate. The deposition temperature of the metal oxide film 114f may be appropriately selected to achieve a desired etching rate for the etchant used to process the metal oxide film 114f.

[0339] After the metal oxide film 114f is formed, heat treatment may be performed so that oxygen can be supplied from the insulating film 110f to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200° C. to 400° C. in an atmosphere containing one or more of nitrogen, oxygen, and a rare gas. Note that the heat treatment does not necessarily have to be performed after the metal oxide film 114f is formed. The heat treatment may be performed at any stage after the formation of the metal oxide film 114f. Alternatively, the heat treatment may be performed together with a later heat treatment or a step in which heat is applied.

[0340] [Formation of opening 142] Subsequently, the metal oxide film 114f, the insulating layer 110f, and a portion of the insulating layer 103 are removed to form an opening 142 that reaches the conductive layer 106. This allows the conductive layer 106 to be electrically connected to the conductive layer 112, which will be formed later, through the opening 142.

[0341] [Formation of Conductive Film 112f] Next, a conductive film 112f is formed to become the conductive layer 112 (FIG. 19B). The above description can be referred to for the conductive film 112f, and therefore a detailed description thereof will be omitted.

[0342] [Formation of Insulating Layer 110, Metal Oxide Layer 114, and Conductive Layer 112] Subsequently, a resist mask (not shown) is formed over the conductive film 112f, and the conductive film 112f and the metal oxide film 114f in regions not covered with the resist mask are removed to form the conductive layer 112 and the metal oxide layer 114 (FIG. 19C).

[0343] A wet etching method can be suitably used to form the conductive layer 112 and the metal oxide layer 114. The above description can be referred to for the wet etching method, and therefore detailed description thereof will be omitted.

[0344] The conductive layer 112 and the metal oxide layer 114 may be formed by etching at least two times using different etching conditions or techniques. For example, the conductive film 112f and the metal oxide film 114f may be etched by an anisotropic etching method, and then the side surfaces of the conductive film 112f and the metal oxide film 114f may be etched by an isotropic etching method to recess the end faces (also referred to as side etching). In this way, the conductive layer 112 and the metal oxide film 114 can be formed to be located inside the insulating layer 110 in a plan view.

[0345] Subsequently, the insulating film 110f is removed from the region not covered by the resist mask to form the insulating layer 110 (FIG. 19D). The above description can be referred to for the formation of the insulating layer 110, and therefore a detailed description thereof will be omitted.

[0346] After the insulating layer 110 is formed, the resist mask is removed.

[0347] Here, cleaning may be performed to remove impurities. As the above description can be referred to for the cleaning, detailed description will be omitted.

[0348] Since the description of <Manufacturing Method Example 1> can be referred to for the steps after the formation of the insulating layer 118, detailed description thereof will be omitted.

[0349] Through the above steps, the transistor 100F can be manufactured.

[0350] <Production method example 3> In the following, a configuration in which the regions 108L1, 108L2, and 108L3 are provided between the regions 108N and 108C, as exemplified in the transistor 100G, will be described as an example.

[0351] The steps up to the formation of the insulating layer 110A are the same as those in the above-described <Manufacturing Method Example 1> (see FIGS. 15A to 15D, 16A to 16C, and 17A).

[0352] [Formation of insulating layer 110] Next, the resist mask 115 is shrunk to form a resist mask 115a (FIG. 20A). In FIG. 20A, the resist mask 115 before being shrunk is indicated by a dashed line along with the resist mask 115a after being shrunk. The edge of the resist mask 115a is preferably located outside the edge of the conductive layer 112. In other words, the edge of the resist mask 115a is preferably located between the edge of the conductive layer 112 and the edge of the insulating layer 110A.

[0353] The resist mask 115a can be formed by an ashing method, which may reduce the area of ​​the resist mask 115 in a plan view and may also reduce the thickness of the resist mask 115.

[0354] Next, in the region not covered with the resist mask 115a, a portion of the upper part of the insulating layer 110A is removed to form the insulating layer 110B (FIG. 20B). The insulating layer 110B is preferably formed by anisotropic etching. In particular, dry etching is preferably used.

[0355] Next, the resist mask 115a is shrunk to form a resist mask 115b (FIG. 20C). In FIG. 20C, the resist mask 115a before being shrunk is indicated by a dashed line along with the resist mask 115b after being shrunk. The edge of the resist mask 115b is preferably located outside the edge of the conductive layer 112. In other words, the edge of the resist mask 115b is preferably located between the edge of the conductive layer 112 and the edge of the insulating layer 110B.

[0356] The resist mask 115b can be formed by an ashing method, which may reduce the area of ​​the resist mask 115a in a plan view and may also reduce the thickness of the resist mask 115a.

[0357] Subsequently, in the region not covered with the resist mask 115b, a part of the upper part of the insulating layer 110B is removed to form the insulating layer 110 (FIG. 21). It is preferable to use anisotropic etching to form the insulating layer 110. In particular, dry etching is preferably used.

[0358] By adjusting the amount by which the resist mask 115 and the resist mask 115a are reduced, the width L1 of the region 108L1, the width L2 of the region 108L2, and the width L3 of the region 108L3 can be controlled.

[0359] After the insulating layer 110 is formed, the resist mask 115b is removed.

[0360] Here, cleaning may be performed to remove impurities. As the above description can be referred to for the cleaning, detailed description will be omitted.

[0361] Since the description of <Manufacturing Method Example 1> can be referred to for the steps after the formation of the insulating layer 118, detailed description thereof will be omitted.

[0362] Through the above steps, the transistor 100G can be manufactured.

[0363] <Components of semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0364] 〔substrate〕 Although there are no significant limitations on the material of the substrate 102, it is necessary that the substrate 102 has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102.

[0365] A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device, which is partially or entirely completed thereon, from the substrate 102 and transfer it to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0366] [Insulating layer 103] The insulating layer 103 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, or the like as appropriate. The insulating layer 103 can be formed, for example, by using a single layer or a stack of an oxide insulating film, an oxynitride insulating film, a nitride oxide insulating film, or a nitride insulating film. Note that in order to improve the interface characteristics with the semiconductor layer 108, at least a region of the insulating layer 103 that is in contact with the semiconductor layer 108 is preferably formed using an oxide insulating film or an oxynitride film. Furthermore, a film that releases oxygen when heated is preferably used for the insulating layer 103.

[0367] The insulating layer 103 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like, and can be formed as a single layer or a stacked layer.

[0368] When a film other than an oxide film or an oxynitride film, such as a silicon nitride film, is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable to perform pretreatment such as oxygen plasma treatment on the surface in contact with the semiconductor layer 108 to oxidize the surface or the vicinity of the surface.

[0369] [Conductive film] The conductive layer 106, the conductive layer 120a functioning as one of the source electrode and the drain electrode, and the conductive layer 120b functioning as the other of the source electrode and the drain electrode can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, an alloy containing any of the above metal elements, an alloy combining any of the above metal elements, or the like.

[0370] The conductive layer 106, the conductive layer 120a, and the conductive layer 120b may be formed of an oxide conductor or a metal oxide film such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide.

[0371] Here, oxide conductors (OC) will be explained. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0372] The conductive layer 106 or the like may have a stacked structure of a conductive film containing the above oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. In this case, it is preferable to use a conductive film containing an oxide conductor on the side in contact with an insulating layer that functions as a gate insulating film.

[0373] The conductive layer 106, the conductive layer 120a, and the conductive layer 120b preferably contain one or more of the above-mentioned metal elements selected from titanium, tungsten, tantalum, and molybdenum. A tantalum nitride film is particularly preferable. The tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself. Therefore, the tantalum nitride film can be preferably used as a conductive film in contact with the semiconductor layer 108 or in the vicinity of the semiconductor layer 108.

[0374] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film of the transistor 100 or the like, can be formed by a PECVD method, a sputtering method, or the like. The insulating layer 110 can be an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that the insulating layer 110 may have a stacked structure of two layers or a stacked structure of three or more layers.

[0375] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film or an oxynitride film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is an insulating film that can release oxygen. For example, oxygen can be supplied to the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment on the formed insulating layer 110 in an oxygen atmosphere, performing plasma treatment or the like in an oxygen atmosphere after the formation of the insulating layer 110, or forming an oxide film or an oxynitride film over the insulating layer 110 in an oxygen atmosphere. Note that in each of the above treatments for supplying oxygen, an oxidizing gas (e.g., nitrous oxide or ozone) may be used instead of or in addition to oxygen.

[0376] A material such as hafnium oxide, which has a higher dielectric constant than silicon oxide or silicon oxynitride, can also be used for the insulating layer 110. This allows the thickness of the insulating layer 110 to be increased, thereby suppressing leakage current due to tunneling current. In particular, crystalline hafnium oxide is preferred because it has a higher dielectric constant than amorphous hafnium oxide.

[0377] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used to deposit the In-M-Zn oxide preferably has an atomic ratio of In to element M of 1 or more. Examples of atomic ratios of metal elements in such sputtering targets include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5.

[0378] It is preferable to use a sputtering target containing a polycrystalline oxide because it facilitates the formation of a crystalline semiconductor layer 108. The atomic ratio of the semiconductor layer 108 to be formed can vary by ±40% from the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0379] When describing an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when In is taken as 4, Ga is 1 to 3 and Zn is 2 to 4. When describing an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when In is taken as 5, Ga is more than 0.1 and 2 or less and Zn is 5 to 7. When describing an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when In is taken as 1, Ga is more than 0.1 and 2 or less and Zn is more than 0.1 and 2 or less.

[0380] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wider energy gap than silicon, the off-state current of the transistor can be reduced.

[0381] It is preferable to use a metal oxide with a low carrier concentration for the semiconductor layer 108. To lower the carrier concentration of a metal oxide, the impurity concentration in the metal oxide should be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0382] In particular, hydrogen contained in metal oxide reacts with oxygen bonded to metal atoms to form water, which can form oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region of a metal oxide, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies can function as donors, generating electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to exhibit normally-on characteristics.

[0383] Defects in which hydrogen has entered oxygen vacancies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0384] Therefore, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0385] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0386] The semiconductor layer 108 preferably has a non-single-crystal structure. Examples of the non-single-crystal structure include a CAAC structure, a polycrystalline structure, a microcrystalline structure, and an amorphous structure, which will be described later. Among the non-single-crystal structures, the amorphous structure has the highest density of defect states, and the CAAC structure has the lowest density of defect states.

[0387] Below, we explain about CAAC (c-axis aligned crystal), which is an example of a crystal structure.

[0388] The CAAC structure is a type of crystalline structure, such as in thin films, that contains multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm), characterized by the c-axis of each nanocrystal oriented in a specific direction, the a-axis and b-axis not being oriented, and the nanocrystals being continuously connected without forming grain boundaries. In particular, thin films with the CAAC structure are characterized by the c-axis of each nanocrystal tending to be oriented in the thickness direction of the thin film, the normal direction to the surface on which it is formed, or the normal direction to the surface of the thin film.

[0389] CAAC-OS (oxide semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, because no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. Furthermore, since the crystallinity of oxide semiconductors can be reduced by the inclusion of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable.

[0390] In crystallography, it is common to define a unit cell with a specific axis as the c-axis, out of the three axes (crystal axes) that make up the unit cell: the a-axis, the b-axis, and the c-axis. In particular, for crystals with a layered structure, it is common to define the two axes parallel to the plane of the layers as the a-axis and the b-axis, and the axis intersecting the layers as the c-axis. A typical example of a crystal with such a layered structure is graphite, which is classified as a hexagonal crystal system. The a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, InGaZnO4 crystals, which have a layered YbFe2O4-type crystal structure, can be classified as a hexagonal crystal system. The a-axis and b-axis of the unit cell are parallel to the plane of the layers, and the c-axis is perpendicular to the layers (i.e., the a-axis and b-axis).

[0391] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly visible in a TEM image. The crystal parts contained in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals with a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. Furthermore, in an nc-OS film, for example, crystal grain boundaries may not be clearly visible in a TEM image.

[0392] The nc-OS film has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS film does not exhibit regularity in the crystal orientation between different crystalline regions. Therefore, the film as a whole lacks orientation. Therefore, depending on the analytical method, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film. For example, when the nc-OS film is subjected to structural analysis using an XRD apparatus that uses X-rays with a diameter larger than that of the crystalline region, peaks indicating crystal planes are not detected by the out-of-plane analysis. Furthermore, when the nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of the crystalline region (for example, 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also known as nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to or smaller than the size of the crystalline portion, a circular (ring-shaped) region of high brightness is observed, and multiple spots may be observed within that region.

[0393] The nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film lacks regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier concentration and electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit high field-effect mobility.

[0394] The nc-OS film can be formed by lowering the oxygen flow rate during film formation compared to the CAAC-OS film. The nc-OS film can also be formed by lowering the substrate temperature during film formation compared to the CAAC-OS film. For example, the nc-OS film can be formed at a relatively low substrate temperature (for example, 130°C or lower) or without heating the substrate. This makes the nc-OS film suitable for use on large glass or resin substrates, thereby improving productivity.

[0395] An example of the crystal structure of a metal oxide will be described. Hereinafter, a metal oxide film formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) will be described as an example. Metal oxides formed by sputtering using the above target at a substrate temperature of 100°C or higher and 130°C or lower tend to have either an nc (nano crystal) structure or a CAAC structure, or a mixed structure of these. On the other hand, metal oxides formed by sputtering at a substrate temperature of room temperature (RT) tend to have an nc crystal structure. Here, room temperature (RT) includes the temperature when the substrate is not heated.

[0396] <Metal oxide composition> The structure of a cloud-aligned composite (CAC)-OS that can be used for the transistor disclosed in one embodiment of the present invention will be described below.

[0397] In this specification, etc., they may be referred to as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0398] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of allowing electrons (or holes) to flow as carriers, and the insulating function is a function of preventing the flow of electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0399] CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the above-mentioned conductive function, and the insulating regions have the above-mentioned insulating function. In addition, the conductive regions and the insulating regions may be separated at the nanoparticle level in the material. In addition, the conductive regions and the insulating regions may be unevenly distributed in the material. In addition, the conductive regions may be observed as connected in a cloud-like shape with the periphery blurred.

[0400] In the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may be dispersed in the material with sizes of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0401] CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap due to an insulating region and a component with a narrow gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow gap. Furthermore, the component with the narrow gap acts complementarily with the component with the wide gap, and carriers also flow in the component with the wide gap in conjunction with the component with the narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the transistor can achieve high current driving power in the on state, i.e., a large on-state current, and high field-effect mobility.

[0402] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0403] This concludes the description of the components.

[0404] This embodiment can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0405] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described.

[0406] <Configuration example> 22A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 attached to each other with a sealant 712. A pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided on the first substrate 701 in a region sealed by the first substrate 701, the second substrate 705, and the sealant 712. The pixel portion 702 is provided with a plurality of display elements.

[0407] An FPC terminal portion 708 to which an FPC (Flexible Printed Circuit) 716 is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals and the like are supplied by the FPC 716 to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 via the FPC terminal portion 708 and signal lines 710.

[0408] There may be multiple gate driver circuits 706. The gate driver circuits 706 and the source driver circuits 704 may each be formed separately on a semiconductor substrate or the like and may be in the form of a packaged IC chip. The IC chip can be mounted on the first substrate 701 or the FPC 716.

[0409] The transistor that is a semiconductor device of one embodiment of the present invention can be applied to the transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706.

[0410] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element. Examples of the light-emitting element include a self-luminous light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Examples of the light-emitting element include a shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) element, and a display element that employs a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type.

[0411] Display device 700A shown in FIG. 22B is an example of a display device that uses flexible resin layer 743 instead of first substrate 701 and can be used as a flexible display.

[0412] In the display device 700A, the pixel portion 702 is not rectangular, but has arc-shaped corners. Furthermore, as shown in region P1 in FIG. 22B , the pixel portion 702 and the resin layer 743 have cutouts formed by cutting out parts of the pixel portion 702 and the resin layer 743. A pair of gate driver circuit units 706 are provided on both sides of the pixel portion 702. The gate driver circuit units 706 are also provided at the corners of the pixel portion 702 along the arc-shaped contour.

[0413] The resin layer 743 has a protruding shape at a portion where the FPC terminal portion 708 is provided. In addition, a portion of the resin layer 743, including the FPC terminal portion 708, can be folded back to the rear side in region P2 in FIG. 22B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on an electronic device with the FPC 716 disposed on the rear side of the pixel portion 702, thereby enabling space saving of the electronic device.

[0414] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 functions as, for example, a source driver circuit. In this case, the source driver circuit unit 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, etc.

[0415] 22C is a display device that can be suitably used in electronic devices having large screens. Display device 700B can be suitably used in, for example, television devices, monitor devices, personal computers (including notebook and desktop computers), tablet terminals, digital signage, and the like.

[0416] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuit units 722.

[0417] The plurality of source driver ICs 721 are each attached to an FPC 723. One terminal of each of the plurality of FPCs 723 is connected to the first substrate 701, and the other terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby enabling space saving of the electronic device.

[0418] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize an electronic device with a narrow frame.

[0419] This configuration makes it possible to realize a large-sized, high-resolution display device. For example, a display device with a diagonal screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more can be realized. Also, a display device with an extremely high resolution, such as 4K2K or 8K4K, can be realized.

[0420] <Example of cross-sectional configuration> Below, a configuration using liquid crystal elements as display elements and a configuration using EL elements will be described with reference to Figs. 23 to 26. Figs. 23 to 25 are cross-sectional views taken along dashed dotted line QR in Fig. 22A. Fig. 26 is a cross-sectional view taken along dashed dotted line ST in display device 700A shown in Fig. 22B. Figs. 23 and 24 show configurations using liquid crystal elements as display elements, and Figs. 25 and 26 show configurations using EL elements.

[0421] [Explanation of common parts of the display device] 23 to 26 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. FIG. 24 shows a case where the capacitor 790 is not included.

[0422] The transistors described as examples in Embodiment 1 can be used as the transistors 750 and 752.

[0423] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which oxygen vacancies are suppressed. The off-state current of the transistor can be reduced. Therefore, the retention time of an electric signal such as an image signal can be increased, and the interval between writing of the image signal can also be set longer. Therefore, the frequency of a refresh operation can be reduced, thereby achieving an effect of reducing power consumption.

[0424] The transistor used in this embodiment has a relatively high field-effect mobility and can therefore be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed on the same substrate. That is, a configuration without using a driver circuit formed using a silicon wafer or the like is possible, and the number of components in the display device can be reduced. Furthermore, by using a transistor capable of high-speed driving in the pixel portion, a high-quality image can be provided.

[0425] The capacitor 790 shown in FIGS. 23, 25, and 26 includes a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has low resistance, similar to the source and drain regions of the transistor 750. A part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower and upper electrodes. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. The upper electrode is connected to wiring obtained by processing the same film as the source and drain electrodes of the transistor.

[0426] A planarization insulating film 770 is provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0427] The transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 may have different structures. For example, a top-gate transistor may be used for one of them, and a bottom-gate transistor may be used for the other. Note that the gate driver circuit portion 706 is similar to the source driver circuit portion 704.

[0428] The signal line 710 is formed using the same conductive film as the source and drain electrodes of the transistors 750 and 752. In this case, it is preferable to use a low-resistance material such as a material containing copper, because this reduces signal delays and enables display on a large screen.

[0429] The FPC terminal portion 708 includes a wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to a terminal of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed using the same conductive film as the source and drain electrodes of the transistors 750 and 752.

[0430] A flexible substrate such as a glass substrate or a plastic substrate can be used as the first substrate 701 and the second substrate 705. When a flexible substrate is used as the first substrate 701, an insulating layer having a barrier property against water and hydrogen is preferably provided between the first substrate 701 and the transistor 750, etc.

[0431] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0432] [Configuration example of a display device using a liquid crystal element] The display device 700 shown in FIG. 23 includes a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over the planarization insulating film 770 and functions as a pixel electrode.

[0433] A material that transmits or reflects visible light can be used for the conductive layer 772. For example, an oxide material containing indium, zinc, tin, or the like can be used as the light-transmitting material. For example, a material containing aluminum, silver, or the like can be used as the reflective material.

[0434] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates is provided to sandwich the liquid crystal element.

[0435] 24 shows an example of a display device 700 using a horizontal field mode (e.g., FFS mode) liquid crystal element 775. A conductive layer 774 functioning as a common electrode is provided over a conductive layer 772 with an insulating layer 773 interposed therebetween. The alignment state of a liquid crystal layer 776 can be controlled by an electric field generated between the conductive layer 772 and the conductive layer 774.

[0436] 24, a storage capacitor can be formed using a stacked structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitor, and the aperture ratio can be increased.

[0437] 23 and 24, an alignment film may be provided in contact with the liquid crystal layer 776. Furthermore, optical members (optical substrates) such as a polarizing member, a phase difference member, and an anti-reflection member, and light sources such as a backlight and a sidelight may be provided as appropriate.

[0438] Thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used for the liquid crystal layer 776. When the in-plane switching mode is adopted, liquid crystal that exhibits a blue phase without using an alignment film may also be used.

[0439] The liquid crystal element modes that can be used include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode.

[0440] A scattering type liquid crystal such as a polymer dispersed liquid crystal or a polymer network liquid crystal may be used for the liquid crystal layer 776. In this case, a configuration may be adopted in which black and white display is performed without providing the colored film 736, or a configuration may be adopted in which color display is performed using the colored film 736.

[0441] The liquid crystal element may be driven by a time-sequential display method (also called a field-sequential driving method) that performs color display based on a time-sequential additive color mixture method. In this case, the color film 736 may not be provided. When the time-sequential display method is used, there is no need to provide sub-pixels that exhibit the respective colors of R (red), G (green), and B (blue), which has the advantage of improving the pixel aperture ratio and increasing the resolution.

[0442] [Display device using light-emitting elements] 25 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0443] Materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, while materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0444] 25, an insulating film 730 that covers part of a conductive layer 772 is provided over a planarization insulating film 770. Here, the light-emitting element 782 is a top-emission light-emitting element that includes a light-transmitting conductive film 788. Note that the light-emitting element 782 may have a bottom-emission structure in which light is emitted to the conductive layer 772 side or a dual-emission structure in which light is emitted to both the conductive layer 772 side and the conductive film 788 side.

[0445] The colored film 736 is provided at a position overlapping the light-emitting element 782, and the light-shielding film 738 is provided at a position overlapping the insulating film 730, in the lead-out wiring portion 711, and in the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when the EL layer 786 is formed by coloring, the colored film 736 may not be provided.

[0446] A configuration of a display device that can be suitably applied to a flexible display is shown in Fig. 26. Fig. 26 is a cross-sectional view taken along dashed line ST in display device 700A shown in Fig. 22B.

[0447] 26 has a stacked structure of a supporting substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744, instead of the first substrate 701 shown in FIG. 25. A transistor 750, a capacitor 790, and the like are provided over the insulating layer 744 provided over the resin layer 743.

[0448] The support substrate 745 is a substrate containing organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing organic resin such as polyimide or acrylic. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. It is preferable that the resin layer 743 is thinner than the support substrate 745.

[0449] 26 has a protective layer 740 instead of the second substrate 705 shown in FIG. 25. The protective layer 740 is attached to a sealing film 732. The protective layer 740 may be a glass substrate, a resin film, or the like. Alternatively, the protective layer 740 may be an optical member such as a polarizing plate or a scattering plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are stacked.

[0450] The EL layer 786 of the light-emitting element 782 is provided in an island shape over the insulating film 730 and the conductive layer 772. By forming the EL layer 786 so that each subpixel emits a different light color, color display can be achieved without using the colored film 736. In addition, a protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably an inorganic insulating film. In addition, a layered structure including at least one inorganic insulating film and at least one organic insulating film is more preferably used.

[0451] FIG. 26 shows a bendable region P2. In region P2, in addition to a support substrate 745 and an adhesive layer 742, there is a portion where no inorganic insulating film, such as an insulating layer 744, is provided. Furthermore, in region P2, a resin layer 746 is provided to cover the wiring 760. By providing as little inorganic insulating film as possible in the bendable region P2 and using a configuration in which only a conductive layer containing a metal or alloy and a layer containing an organic material are stacked, it is possible to prevent cracks from occurring when the display device 700A is bent. Furthermore, by not providing a support substrate 745 in region P2, a portion of the display device 700A can be bent with an extremely small radius of curvature.

[0452] [Configuration example in which an input device is provided on a display device] An input device may be provided in the display devices shown in Figures 23 to 26. Examples of the input device include a touch sensor.

[0453] For example, the sensor may be of various types, such as a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, or a pressure-sensitive type, or may be a combination of two or more of these types.

[0454] The touch panel may have a configuration such as an in-cell type touch panel in which the input device is formed between a pair of substrates, an on-cell type touch panel in which the input device is formed on the display device, or an out-cell type touch panel in which the input device is attached to the display device.

[0455] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by combining them appropriately with other configuration examples or drawings.

[0456] This embodiment can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0457] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0458] 27A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 does not necessarily have to be provided.

[0459] The transistor of one embodiment of the present invention can be applied to the transistors included in the pixel portion 502 and the driver circuit portion 504. The transistor of one embodiment of the present invention can also be applied to the protection circuit 506.

[0460] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0461] The driver circuit unit 504 includes driver circuits such as a gate driver 504a that outputs scan signals to the gate lines GL_1 to GL_X and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y. The gate driver 504a may include at least a shift register. The source driver 504b may include, for example, a plurality of analog switches. Alternatively, the source driver 504b may include a shift register.

[0462] The terminal portion 507 is a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0463] 27A is connected to various wirings, such as gate lines GL_1 to GL_X that are wirings between the gate driver 504a and the pixel circuit 501, or data lines DL_1 to DL_Y that are wirings between the source driver 504b and the pixel circuit 501.

[0464] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel unit 502, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (for example, a drive circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0465] The plurality of pixel circuits 501 shown in FIG. 27A can have the configurations shown in FIGS. 27B and 27C, for example.

[0466] 27B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.

[0467] The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Alternatively, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

[0468] 27C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is also connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.

[0469] A high power supply potential (VDD) is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential (VSS) is applied to the other. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the gate of the transistor 554, thereby controlling the luminance of the light-emitting element 572.

[0470] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by combining them appropriately with other configuration examples or drawings.

[0471] This embodiment can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0472] (Fourth embodiment) A pixel circuit including a memory for correcting a gray scale displayed in a pixel and a display device including the pixel circuit will be described below. The transistors exemplified in Embodiment 1 can be applied to transistors used in the pixel circuits exemplified below.

[0473] <Circuit configuration> 28A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 is connected to a wiring S1, a wiring S2, a wiring G1, and a wiring G2.

[0474] The transistor M1 has a gate connected to the wiring G1, one of its source and drain connected to the wiring S1, and the other connected to one electrode of the capacitor C1. The transistor M2 has a gate connected to the wiring G2, one of its source and drain connected to the wiring S2, and the other connected to the other electrode of the capacitor C1 and the circuit 401.

[0475] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but representative examples include light-emitting elements such as organic EL elements and LED elements, liquid crystal elements, and MEMS (Micro Electro Mechanical Systems) elements.

[0476] The node connecting the transistor M1 and the capacitor C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 401 is referred to as a node N2.

[0477] The pixel circuit 400 can maintain the potential of the node N1 by turning off the transistor M1. Also, the potential of the node N2 can be maintained by turning off the transistor M2. Furthermore, by writing a predetermined potential to the node N1 via the transistor M1 while the transistor M2 is turned off, the potential of the node N2 can be changed in accordance with the change in the potential of the node N1 due to capacitive coupling via the capacitor C1.

[0478] Here, the transistor including an oxide semiconductor, as exemplified in Embodiment 1, can be used as one or both of the transistors M1 and M2. Therefore, the potentials of the nodes N1 and N2 can be held for a long period of time due to an extremely low off-state current. Note that when the period for holding the potentials of the nodes is short (specifically, when the frame frequency is 30 Hz or higher), a transistor including a semiconductor such as silicon may be used.

[0479] <Driving method example> Next, an example of an operation method of pixel circuit 400 will be described with reference to Fig. 28B. Fig. 28B is a timing chart relating to the operation of pixel circuit 400. Note that, to simplify the explanation, the influence of various resistances such as wiring resistance, parasitic capacitance of transistors and wiring, and threshold voltage of transistors will not be taken into consideration.

[0480] 28B, one frame period is divided into period T1 and period T2. Period T1 is a period in which a potential is written to node N2, and period T2 is a period in which a potential is written to node N1.

[0481] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, a fixed potential V ref is supplied to the line S2, and the first data potential V w supply.

[0482] The node N1 is connected to the line S1 via the transistor M1. ref The node N2 is supplied with a first data potential V w Therefore, the capacitance C1 has a potential difference V w -V ref is maintained.

[0483] [Period T2] Subsequently, in a period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2. data A predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.

[0484] The node N1 receives a second data potential V data At this time, the second data potential V data In other words, the potential of the node N2 changes by a potential dV in response to the first data potential V w The potential obtained by adding the second data potential V to the potential dV is input. Note that although the potential dV is shown as a positive value in FIG. 28B, it may be a negative value. That is, data is the potential V ref It may be lower.

[0485] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is equal to the second data potential V data The potential is close to

[0486] In this way, the pixel circuit 400 can generate a potential to be supplied to the circuit 401 including a display element by combining two types of data signals, and therefore, it is possible to perform gray scale correction within the pixel circuit 400.

[0487] The pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Furthermore, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0488] <Application example> [Example using liquid crystal element] 28C includes a circuit 401LC, which includes a liquid crystal element LC and a capacitor C2.

[0489] The liquid crystal element LC has one electrode connected to the other electrode of the capacitor C1, the other electrode of the source and drain of the transistor M2, and one electrode of the capacitor C2, and the other electrode connected to a potential V com2 The capacitor C2 is connected to the wiring where the other electrode is at potential V com1 Connect with the wiring given.

[0490] The capacitor C2 functions as a storage capacitor. Note that the capacitor C2 can be omitted if not required.

[0491] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, which makes it possible to, for example, achieve high-speed display by overdriving, apply a liquid crystal material with a high driving voltage, etc. Furthermore, by supplying a correction signal to the line S1 or line S2, it is possible to correct the gradation in accordance with the operating temperature, the deterioration state of the liquid crystal element LC, etc.

[0492] [Example using light-emitting element] 28D includes a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0493] The transistor M3 has a gate connected to one electrode of the capacitor C2 and a source or drain connected to a potential V H The other electrode of the capacitor C2 is connected to a wiring to which a potential V com The other electrode of the light-emitting element EL is connected to a wiring to which a potential V L Connect with the wiring given.

[0494] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a storage capacitor. The capacitor C2 can be omitted if it is not necessary.

[0495] Although the anode side of the light-emitting element EL is connected to the transistor M3 in this example, the transistor M3 may be connected to the cathode side. H and potential V L You can change the value accordingly.

[0496] In the pixel circuit 400EL, by applying a high potential to the gate of the transistor M3, a large current can flow through the light-emitting element EL, thereby realizing, for example, HDR display, etc. Also, by supplying a correction signal to the wiring S1 or wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0497] It should be noted that the circuits are not limited to those illustrated in FIGS. 28C and 28D, and may be configured to include additional transistors, capacitors, and the like.

[0498] This embodiment can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0499] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0500] A display module 6000 shown in FIG. 29A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0501] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0502] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0503] The display device 6006 may have a function as a touch panel.

[0504] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0505] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, and the like.

[0506] FIG. 29B is a cross-sectional schematic diagram of a display module 6000 with an optical touch sensor.

[0507] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0508] The display device 6006 is provided so as to overlap a printed circuit board 6010 and a battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to a light guide portion 6017a and a light guide portion 6017b.

[0509] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and then through light-guiding unit 6017b to reach light-receiving unit 6016. When light 6018 is blocked by a detection target such as a finger or a stylus, a touch operation can be detected.

[0510] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0511] The light-emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light-receiving unit 6016 may be a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode that can receive infrared light may be used.

[0512] The light guiding portions 6017a and 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0513] This embodiment can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0514] (Sixth embodiment) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0515] Electronic device 6500 shown in FIG. 30A is a portable information terminal that can be used as a smartphone.

[0516] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0517] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0518] FIG. 30B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0519] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0520] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0521] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0522] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0523] This embodiment can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0524] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described.

[0525] The electronic devices exemplified below each include a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices can achieve high resolution. Furthermore, the electronic devices can also have both high resolution and a large screen.

[0526] The display portion of the electronic device of one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0527] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0528] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a house or building, or the interior or exterior of an automobile or the like.

[0529] FIG. 31A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0530] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached thereto.

[0531] The camera 8000 may have the lens 8006 and the housing integrated together.

[0532] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0533] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0534] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0535] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0536] The button 8103 has a function such as a power button.

[0537] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0538] FIG. 31B is a diagram showing the appearance of the head mounted display 8200.

[0539] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0540] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use the information on the movements of the user's eyeballs and eyelids as an input means.

[0541] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user and capable of detecting a current that flows in accordance with the movement of the user's eyeballs. The wearing unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0542] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0543] 31C, 31D, and 31E are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0544] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0545] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has extremely high definition, and therefore, even when an image is enlarged using the lens 8305 as in FIG. 31E, pixels are not visible to a user, and more realistic images can be displayed.

[0546] The electronic device shown in Figures 32A to 32G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0547] 32A to 32G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic device are not limited to these, and the electronic device may have various other functions. The electronic device may have multiple display units. Furthermore, the electronic device may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0548] The electronic devices shown in FIGS. 32A to 32G will be described in detail below.

[0549] 32A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more.

[0550] FIG. 32B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 32B shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and the strength of antenna reception. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0551] 32C is a perspective view showing mobile information terminal 9102. Mobile information terminal 9102 has a function of displaying information on three or more sides of display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, while mobile information terminal 9102 is placed in a breast pocket of clothes, the user can check information 9053 displayed in a position that can be observed from above mobile information terminal 9102. The user can check the display without taking mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0552] FIG. 32D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and reception with another information terminal and charge itself via a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0553] 32E, 32F, and 32G are perspective views showing a foldable mobile information terminal 9201. FIG. 32E shows the mobile information terminal 9201 in an unfolded state, FIG. 32G shows it in a folded state, and FIG. 32F is a perspective view showing a state in the process of changing from one of FIG. 32E and FIG. 32G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display. A display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0554] 33A shows an example of a television device. A television device 7100 has a display unit 7500 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0555] 33A can be operated using operation switches provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0556] The television device 7100 may also include a television broadcast receiver and a communication device for network connection.

[0557] 33B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0558] 33C and 33D show an example of digital signage.

[0559] 33C includes a housing 7301, a display unit 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0560] 33D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0561] The larger the display unit 7500, the more information can be provided at one time, and the larger the display unit 7500 is, the more easily it will catch people's attention, which will have the effect of increasing the advertising effectiveness of advertisements, for example.

[0562] It is preferable to use a touch panel for the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes but also for providing users with information they require, such as route information, traffic information, and commercial facility guidance information.

[0563] 33C and 33D, it is preferable that the digital signage 7300 or the digital signage 7400 can wirelessly connect to an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, or the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0564] A game using the information terminal device 7311 as an operation means (controller) can also be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0565] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS. 33A to 33D.

[0566] Although the electronic devices in this embodiment have a display portion, one embodiment of the present invention can also be applied to electronic devices that do not have a display portion.

[0567] This embodiment can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. [Example]

[0568] In this example, a sample (sample A) simulating the shape of the transistor 100A shown in FIG. 7 and a sample (sample B) simulating the shape of the transistor 100G shown in FIG. 13 were fabricated, and their cross-sectional shapes were evaluated.

[0569] <Sample preparation> First, a titanium film having a thickness of 30 nm and a copper film having a thickness of 100 nm were formed in this order on a glass substrate by sputtering, and then processed to obtain a first gate electrode (bottom gate).

[0570] Next, a 300 nm thick silicon nitride layer and a 100 nm thick first silicon oxynitride layer were deposited in this order as a first gate insulating layer. The first gate insulating layer was deposited using a PECVD apparatus.

[0571] Next, a 25-nm-thick metal oxide film was formed on the first silicon oxynitride layer. The metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the source power was 2.5 kW, and the substrate temperature was room temperature. A mixture of oxygen gas and argon gas was used as the film formation gas, and the ratio of the oxygen gas flow rate to the total flow rate of the film formation gas (oxygen flow rate ratio) was 30%.

[0572] Subsequently, the metal oxide film was processed into islands to form a metal oxide layer.

[0573] Subsequently, the substrate was subjected to a heat treatment at 370°C for 1 hour in a nitrogen atmosphere, and then to a heat treatment at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven was used for the heat treatment.

[0574] Subsequently, a second silicon oxynitride film having a thickness of 130 nm was formed as a second gate insulating layer using a PECVD apparatus.

[0575] Subsequently, a heat treatment was carried out for 1 hour at 370° C. in a nitrogen atmosphere using an oven.

[0576] Subsequently, a molybdenum film having a thickness of 100 nm was formed on the second silicon oxynitride film by sputtering.

[0577] Next, a first resist mask was formed on the molybdenum film, and a molybdenum layer was formed. A wet etching method was used to form the molybdenum layer. An Al mixed acid etching solution was used as the etchant. The etching time was adjusted so that the edge of the molybdenum layer was located inside the edge of the first resist mask.

[0578] Subsequently, the second silicon oxynitride film was processed using the first resist mask as a mask.

[0579] Next, the first resist mask was reduced in size to form a second resist mask, which was then reduced in size by ashing.

[0580] Subsequently, the second silicon oxynitride film was processed using the second resist mask to obtain a second silicon oxynitride layer. The sample fabricated through the steps up to this point was designated as Sample A.

[0581] Next, the second resist mask was reduced to form a third resist mask for sample B. The second resist mask was reduced by ashing.

[0582] Subsequently, for sample B, the second silicon oxynitride film was processed using the third resist mask as a mask to obtain a second silicon oxynitride layer.

[0583] Through the above steps, sample A and sample B were obtained.

[0584] <Cross-section observation> Next, sample A and sample B were sliced ​​using a focused ion beam (FIB), and the cross sections were observed using a STEM.

[0585] Figure 34A shows a STEM image of the cross section of sample A, and Figure 34B shows a STEM image of the cross section of sample B. Figures 34A and 34B are transmission electron (TE) images at a magnification of 1800 times.

[0586] Figures 35A and 35B show enlarged STEM images of the vicinity of the edge of the second silicon oxynitride layer of sample A. Figures 36A and 36B show enlarged STEM images of the vicinity of the edge of the second silicon oxynitride layer of sample B. Figures 35A, 35B, 36A, and 36B are transmission electron (TE) images at a magnification of 100,000 times.

[0587] Note that Fig. 35B shows the same STEM image as Fig. 35A, and Fig. 36B shows the same STEM image as Fig. 36A. Figs. 35B and 36B respectively show locations where measurements were made of the width L1 of region 108L1, the width L2 of region 108L2, the width L3 of region 108L3, the thickness TN1 of the second silicon oxynitride layer in the region overlapping with region 108L1, the thickness TN2 of the second silicon oxynitride layer in the region overlapping with region 108L2, and the thickness TN3 of the second silicon oxynitride layer in the region overlapping with region 108L3.

[0588] 34A, 34B, 35A, 35B, 36A, and 36B, the glass substrate is referred to as Glass, the copper layer as Cu, the silicon nitride layer as SiN, the first silicon oxynitride layer as SiON-1, the metal oxide layer as OS, the second silicon oxynitride layer as SiON-2, the molybdenum layer as Mo, and the photoresist as PR.

[0589] As shown in FIGS. 34A, 34B, 35A, 35B, 36A, and 36B, it was confirmed that the second silicon oxynitride layer had a stepped shape.

[0590] The width L1 of region 108L1, the width L2 of region 108L2, the width L3 of region 108L3, the thickness TN1 of the second silicon oxynitride layer in the region overlapping with region 108L1, the thickness TN2 of the second silicon oxynitride layer in the region overlapping with region 108L2, and the thickness TN3 of the second silicon oxynitride layer in the region overlapping with region 108L3 for each of sample A and sample B are shown in Table 1. Note that in Table 1, since sample A does not have region 108L3, the values ​​of width L3 and thickness TN3 are not shown.

[0591] [Table 1]

[0592] As shown in Figures 34A, 34B, 35A, 35B, 36A, 36B, and Table 1, it was possible to confirm that sample A had a transistor shape having regions 108L1 and 108L2, and sample B had a transistor shape having regions 108L1, 108L2, and 108L3. In sample A, the ratio of film thickness TN1 to film thickness TN0 was 0.97, confirming that film thicknesses TN0 and TN1 were approximately equal. In sample B, the ratio of film thickness TN1 to film thickness TN0 was 0.99, confirming that film thicknesses TN0 and TN1 were approximately equal. [Example]

[0593] In this example, samples corresponding to the regions 108C, 108L1, 108L2, 108L3, and 108N were fabricated, and their resistances were evaluated.

[0594] <Sample preparation> First, a first silicon nitride film having a thickness of 240 nm, a second silicon nitride film having a thickness of 60 nm, and a first silicon oxynitride film having a thickness of 100 nm were formed in this order on a glass substrate.

[0595] Next, a 25-nm-thick metal oxide film was formed on the first silicon oxynitride film. The metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the source power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow rate ratio was 30%.

[0596] Subsequently, a heat treatment was carried out in a CDA atmosphere at 340° C. for 1 hour using an oven.

[0597] Subsequently, a second silicon oxynitride film was formed on the metal oxide film. The thickness of the second silicon oxynitride film was varied among the samples. The thicknesses of the second silicon oxynitride film were 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, and 140 nm. Samples without the second silicon oxynitride film were also fabricated. The second silicon oxynitride film corresponds to the insulating layer provided over the semiconductor layer 108 when the first element 140 described in Embodiment 1 is supplied. The second silicon oxynitride film corresponds to, for example, the insulating layer 110 and the insulating layer 118a shown in FIG. 18B.

[0598] Subsequently, heat treatment was performed in a CDA atmosphere at 340° C. for 1 hour. An oven was used for the heat treatment. Note that the heat treatment was not performed on samples that did not have a second silicon oxynitride film formed thereon.

[0599] Next, plasma treatment was performed using ammonia gas. The substrate temperature and treatment time during plasma treatment were varied between samples. The substrate temperatures during plasma treatment were 240°C and 350°C. The treatment times for plasma treatment were 15 seconds, 30 seconds, 60 seconds, and 90 seconds. Samples were also prepared without plasma treatment.

[0600] Next, they were heat-treated for 1 hour in a nitrogen atmosphere. An oven was used for the heat treatment. The heat treatment temperatures were varied between samples. The heat treatment temperatures were 250°C, 300°C, and 350°C. Samples were also prepared that were not heat-treated.

[0601] Subsequently, an opening reaching the metal oxide film was formed in the second silicon oxynitride film, and a terminal was provided therein.

[0602] <Sheet resistance measurement> Subsequently, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the metal oxide film.

[0603] The sheet resistance values ​​of the metal oxide films of the samples are shown in FIGS. 37A, 37B, 38A, 38B, 39A, and 39B.

[0604] In Figures 37A, 37B, 38A, and 38B, the horizontal axis represents the plasma treatment time, and the vertical axis represents the sheet resistance Rs of the metal oxide film. Note that Figure 37A shows excerpts from the results of a sample in which the substrate temperature during plasma treatment was 350°C and no post-plasma heat treatment was performed. Figure 37B shows excerpts from the results of a sample in which the substrate temperature during plasma treatment was 240°C and no post-plasma heat treatment was performed. Figure 38A shows excerpts from the results of a sample in which the substrate temperature during plasma treatment was 350°C and the post-plasma heat treatment temperature was 250°C. Figure 38B shows excerpts from the results of a sample in which the substrate temperature during plasma treatment was 240°C and the post-plasma heat treatment temperature was 250°C.

[0605] 39A and 39B, the horizontal axis represents the film thickness (SiON film thickness) of the second silicon oxynitride film, and the vertical axis represents the sheet resistance Rs of the metal oxide film. Note that FIG. 39A shows the results of a sample in which the substrate temperature during plasma treatment was 350°C and the treatment time was 60 seconds. FIG. 39B shows the results of a sample in which the substrate temperature during plasma treatment was 240°C and the treatment time was 60 seconds.

[0606] As shown in Figures 37A, 37B, 38A, and 38B, the resistance of the metal oxide film decreased with increasing plasma treatment time. Furthermore, the resistance of the metal oxide film was lower for samples treated at a substrate temperature of 350°C compared to samples treated at a substrate temperature of 240°C. As shown in Figures 39A and 39B, the resistance of the metal oxide film increased when heat treatment was performed after plasma treatment, and the resistance of the metal oxide film tended to increase with increasing heat treatment temperature. Furthermore, the resistance of the metal oxide film decreased as the thickness of the second silicon oxynitride film decreased. Note that the resistance of the metal oxide film tended to be higher for samples treated without a second silicon oxynitride film. The samples treated without a second silicon oxynitride film were treated with plasma while the metal oxide film was exposed, which likely resulted in damage to the metal oxide film, resulting in the increased resistance.

[0607] From the above results, it was found that the resistance of the metal oxide film can be controlled by adjusting the film thickness of the second silicon oxynitride film and the processing conditions of the plasma treatment. Note that in this example, a heat treatment was performed after the plasma treatment, but the heat treatment can be replaced with a process that applies heat. As shown in this example, the resistance of the metal oxide film varies depending on the temperature of the heat treatment after the plasma treatment. Therefore, it was found that the resistance of the metal oxide film can be controlled by adjusting the film thickness of the second silicon oxynitride film and the processing conditions of the plasma treatment, taking into account the temperature of the process that applies heat after the plasma treatment. [Explanation of symbols]

[0608] C1: capacitance, C2: capacitance, DL_Y: data line, DL_1: data line, G1: wiring, G2: wiring, GL_X: gate line, GL_1: gate line, M1: transistor, M2: transistor, M3: transistor, N1: node, N2: node, P1: area, P2: area, S1: wiring, S2: wiring, T1: period, T2: period, TN0: film thickness, TN1: film thickness, TN2: film thickness, TN3: film thickness, 10: transistor, 10A: transistor, 10B: transistor, 10C: transistor, 10D: transistor, 10E: transistor, 10F: transistor, 1 0G: transistor, 10H: transistor, 10I: transistor, 100: transistor, 100A: transistor, 100B: transistor, 100C: transistor, 100D: transistor, 100E: transistor, 100F: transistor, 100G: transistor, 102: substrate, 103: insulating layer, 103a: insulating layer, 103b: insulating layer, 103c: insulating layer, 106: conductive layer, 108: semiconductor layer, 108C: region, 108f: metal oxide film, 108L1: region, 108L2: region, 108L3: region, 108Lp: region, 108N: region, 110: insulating layer, 110a: insulating layer, 110A: insulating layer, 110b: insulating layer, 110B: insulating layer, 110c: insulating layer, 110f: insulating film, 110S1: first side surface, 110S2: second side surface, 110S3: third side surface, 110Sp: pth side surface, 112: conductive layer, 112f: conductive film, 114: metal oxide layer, 114f: metal oxide film, 115: resist mask, 115a: resist mask, 115b: resist mask, 118: insulating layer, 118a: insulating layer, 118b: insulating layer, 120a: conductive layer, 120b: conductive layer, 140: first element, 141a: opening section, 141b: opening, 142: opening, 400: pixel circuit, 400EL: pixel circuit, 400LC: pixel circuit, 401: circuit, 401EL: circuit, 401LC: circuit, 501: pixel circuit, 502: pixel section, 504: drive circuit section, 504a: gate driver, 504b: source driver, 506: protection circuit, 507: terminal section, 550: transistor, 552: transistor, 554: transistor, 560: capacitance element, 562: capacitance element, 570: liquid crystal element, 572: light-emitting element, 700: display device, 700A: display device, 700B: display device, 701: substrate,702: pixel section, 704: source driver circuit section, 705: substrate, 706: gate driver circuit section, 708: FPC terminal section, 710: signal line, 711: wiring section, 712: sealing material, 716: FPC, 717: IC, 721: source driver IC, 722: gate driver circuit section, 723: FPC, 724: printed circuit board, 730: insulating film, 732: sealing film, 734: insulating film, 736: colored film, 738: light-shielding film, 740: protective layer, 741: protective layer, 742: adhesive layer, 743: resin layer, 744: insulating layer, 745: supporting substrate, 746: resin layer, 750: transistor , 752: transistor, 760: wiring, 770: planarization insulating film, 772: conductive layer, 773: insulating layer, 774: conductive layer, 775: liquid crystal element, 776: liquid crystal layer, 778: spacer, 780: anisotropic conductive film, 782: light-emitting element, 786: EL layer, 788: conductive film, 790: capacitance element, 6000: display module, 6001: upper cover, 6002: lower cover, 6005: FPC, 6006: display device, 6009: frame, 6010: printed circuit board, 6011: battery, 6015: light-emitting section, 6016: light-receiving section, 6017a: light-guiding section, 6017b : Light guide section, 6018: Light, 6500: Electronic device, 6501: Housing, 6502: Display section, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7100: Television device, 7101: Housing, 7103: Stand, 7111: Remote control device, 7200: Notebook personal computer, 7 211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7500: Display unit, 8000: Camera, 8001: Housing, 8002: Display unit, 8003: Operation buttons, 8004: Shutter button, 8006: Lens, 8100: Viewfinder, 8101: Housing, 8102: Display unit, 8103: Button, 8200: Head-mounted display, 8201: Wearing part,8202: Lens, 8203: Main body, 8204: Display unit, 8205: Cable, 8206: Battery, 8300: Head mounted display, 8301: Housing, 8302: Display unit, 8304: Fixing device, 8305: Lens, 9000: Housing, 9001: Display unit, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9100: Television device, 9101: Portable information terminal, 9102: Portable information terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

1. a semiconductor layer containing indium and oxygen, a first insulating layer on the semiconductor layer, and a conductive layer on the first insulating layer; the semiconductor layer has a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions; the second region sandwiches the first region; the third region sandwiches the first region and the second region; the fourth region sandwiches the first region, the second region, and the third region; the first region has a region overlapping the first insulating layer and the conductive layer, the second region and the third region each have a region that overlaps with the first insulating layer and does not overlap with the conductive layer; the fourth region does not overlap with either the first insulating layer or the conductive layer, the first insulating layer has a stepped shape; a thickness of the first insulating layer in a region overlapping with the second region is approximately equal to a thickness of the first insulating layer in a region overlapping with the first region; a thickness of the first insulating layer in a region overlapping with the third region is thinner than a thickness of the first insulating layer in a region overlapping with the second region; the third region and the fourth region each have a first element; a concentration of the first element in the third region is higher than a concentration of the first element in the second region; a concentration of the first element in the fourth region is higher than a concentration of the first element in the third region; The semiconductor device, wherein the first element is one or more of hydrogen, boron, nitrogen, and phosphorus.

2. a semiconductor layer containing indium and oxygen, a first insulating layer on the semiconductor layer, and a conductive layer on the first insulating layer; the semiconductor layer has a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions; the second region sandwiches the first region; the third region sandwiches the first region and the second region; the fourth region sandwiches the first region, the second region, and the third region; the first region has a region overlapping the first insulating layer and the conductive layer, the second region and the third region each have a region that overlaps with the first insulating layer and does not overlap with the conductive layer; the fourth region does not overlap with either the first insulating layer or the conductive layer, the first insulating layer has a stepped shape; a thickness of the first insulating layer in a region overlapping with the second region is approximately equal to a thickness of the first insulating layer in a region overlapping with the first region; a thickness of the first insulating layer in a region overlapping with the third region is thinner than a thickness of the first insulating layer in a region overlapping with the second region; the resistance of the second region is lower than the resistance of the first region; the resistance of the third region is lower than the resistance of the second region; The semiconductor device, wherein the resistance of the fourth region is lower than the resistance of the third region.

3. In claim 1 or claim 2, Further, a second insulating layer is provided, The second insulating layer contacts the top surface and side surfaces of the first insulating layer and the top surface of the fourth region.

4. In claim 3, the first insulating layer comprises an oxide or an oxynitride; The semiconductor device, wherein the second insulating layer comprises an oxide or an oxynitride.

5. In claim 3, the first insulating layer comprises an oxide or an oxynitride; The semiconductor device, wherein the second insulating layer comprises a nitride or a nitride oxide.

6. In any one of claims 1 to 5, The resistance of the second region is at least twice the resistance of the third region (1×10 ３ Semiconductor device that is less than twice the size.

7. In any one of claims 1 to 6, a thickness of the first insulating layer in a portion overlapping with the third region that is 0.2 to 0.9 times the thickness of the first insulating layer in a portion overlapping with the second region;

8. In any one of claims 1 to 7, The semiconductor device, wherein the width of the second region and the width of the third region are each 50 nm or more and 1 μm or less.

9. In any one of claims 1 to 8, The semiconductor device, wherein the semiconductor layer has a polycrystalline structure.

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