Method for manufacturing a display device

Abstract

To build a circuit capable of high-speed operation and pixels on the same board.SOLUTION: A first metal oxide film, a first metal film, and an island-shaped first resist mask are formed on a first insulating layer. Subsequently, an island-shaped first metal layer and an island-shaped first oxide semiconductor layer are formed, and a part of the upper surface of the first insulating layer is exposed to remove the first resist mask. Subsequently, a second metal oxide film, a second metal film, and an island-shaped second resist mask are formed on the first metal layer and the first insulating layer. Subsequently, an island-shaped second metal layer and an island-shaped second oxide semiconductor layer are formed, and the second resist mask is removed. Then, the first metal layer and the second metal layer are removed.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a display device, and a manufacturing method of a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] Display device driver circuits are required to have high performance to accommodate the trend toward higher resolution and multiple grayscale levels in the display area. For this reason, display device driver circuits, particularly source drivers, use integrated circuits (ICs) (hereinafter also referred to as driver ICs) fabricated using single-crystal substrates.

[0004] A driver IC consists of a shift register, latch, level shifter, digital-to-analog conversion circuit (also known as DAC), analog buffer, etc. The shift register and latch are circuits that handle digital signals, the level shifter and DAC are circuits that convert digital signals to analog signals, and the analog buffer is a circuit that generates and outputs gradation voltages. Circuits that handle digital signals in particular are required to operate at high speeds.

[0005] Furthermore, oxide semiconductors using metal oxides have been attracting attention as semiconductor materials that can be used for transistors in display portions of display devices. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is made higher than the proportion of gallium, thereby increasing field-effect mobility.

[0006] Metal oxides can be formed using a sputtering method or the like, and therefore can be used for the semiconductor layers of transistors that constitute large display devices. Furthermore, because it is possible to use some of the production equipment for transistors that use polycrystalline silicon or amorphous silicon by modifying it, capital investment can be reduced. Furthermore, transistors that use metal oxides have higher field-effect mobility than transistors that use amorphous silicon, and therefore high-performance display devices equipped with gate drivers can be realized. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a display device including a circuit capable of high-speed operation.An object of one embodiment of the present invention is to form a pixel and a driver circuit over the same substrate.An object of one embodiment of the present invention is to form a pixel and at least a part of a source driver over the same substrate.An object of one embodiment of the present invention is to form different transistors over the same substrate.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a method for manufacturing a display device including a first transistor having a first oxide semiconductor layer and a second transistor having a second oxide semiconductor layer, the method including the following steps: forming a first insulating layer over a first substrate, depositing a first metal oxide film over the first insulating layer, depositing a first metal film over the first metal oxide film, and forming a first island-shaped resist mask over the first metal film. Subsequently, portions of the first metal film and the first metal oxide film that are not covered with the first resist mask are removed to form the island-shaped first metal layer and the island-shaped first oxide semiconductor layer, and exposing part of the top surface of the first insulating layer. Next, the first resist mask is removed, a second metal oxide film is formed on the first metal layer and the first insulating layer, a second metal film is formed on the second metal oxide film, and an island-shaped second resist mask is formed on the second metal film in an area that does not overlap with the first metal film. Next, portions of the second metal film and the second metal oxide film that are not covered by the second resist mask are removed to form an island-shaped second metal layer and an island-shaped second oxide semiconductor layer, and the second resist mask is removed. Then, the first metal layer and the second metal layer are removed.

[0011] Another embodiment of the present invention is a method for manufacturing a display device including a first transistor including a first oxide semiconductor layer and a second transistor including a second oxide semiconductor layer, the method including the following steps: forming a first insulating layer over a first substrate, depositing a first metal oxide film over the first insulating layer, depositing a first metal film over the first metal oxide film, and forming a first island-shaped resist mask over the first metal film. Next, a portion of the first metal film that is not covered with the first resist mask is removed to form an island-shaped first metal layer, and the first resist mask is removed. Next, the portion of the first metal oxide film that is not covered with the first metal film is removed to form an island-shaped first oxide semiconductor layer and expose part of the top surface of the first insulating layer. Next, a second metal oxide film is formed on the first metal layer and the first insulating layer, a second metal film is formed on the second metal oxide film, and an island-shaped second resist mask is formed on the second metal film in an area that does not overlap with the first metal film. Next, the portion of the second metal film that is not covered by the second resist mask is removed to form an island-shaped second metal layer, and the second resist mask is removed. Next, the portion of the second metal oxide film that is not covered by the second metal film is removed to form an island-shaped second oxide semiconductor layer. Then, the first metal layer and the second metal layer are removed.

[0012] In the above, it is preferable that the first metal oxide film contains indium, zinc, and gallium, the second metal oxide film contains indium, and the second metal oxide film is formed so that the ratio of the number of indium atoms to the number of atoms of the contained metal elements is higher than that of the first metal oxide film.

[0013] Alternatively, in the above, it is preferable that the second metal oxide film contains indium, zinc, and gallium, the first metal oxide film contains indium, and the first metal oxide film is formed so that the ratio of the number of indium atoms to the number of atoms of the contained metal elements is higher than that of the second metal oxide film.

[0014] In the above, the first metal film is preferably etched by dry etching, and the first metal oxide film is preferably etched by wet etching. Furthermore, the second metal film is preferably etched by dry etching, and the second metal oxide film is preferably etched by wet etching. Furthermore, the first metal layer and the second metal layer are preferably etched by wet etching.

[0015] In the above, the first metal film and the second metal film are preferably made of tungsten, molybdenum, or titanium.

[0016] Another embodiment of the present invention is a display device including a display portion over a first substrate and a first circuit outside the display portion. The display portion includes a display element and a first transistor. The first circuit includes a second transistor. The first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate electrode. The first insulating layer is provided over the first substrate. The first semiconductor layer and the second semiconductor layer are provided in contact with an upper surface of the first insulating layer. The first gate insulating layer and the second gate insulating layer are formed by processing the same film, i.e., have the same composition. The first gate electrode and the second gate electrode are formed by processing the same film, i.e., have the same composition. The first semiconductor layer and the second semiconductor layer are formed by processing different films. The first semiconductor layer contains indium, zinc, gallium, and oxygen, and the second semiconductor layer contains indium and oxygen, and the ratio of the number of indium atoms to the number of atoms of the metal elements contained in the second semiconductor layer is higher than that of the first semiconductor layer.

[0017] In the above, it is preferable that the second semiconductor layer contains zinc, and that the ratio of the number of indium atoms to the number of atoms of the contained metal elements is 50 atomic % or more.

[0018] In any of the above, the second semiconductor layer preferably further contains tin, and more preferably the second semiconductor layer further contains gallium.

[0019] In any of the above, it is preferable that the semiconductor device further includes a second circuit functioning as a gate driver and a plurality of first transistors, and in this case, the second circuit preferably includes the first transistor.

[0020] In any of the above, the first circuit preferably has a function as a source driver or a demultiplexer.

[0021] In any of the above, the display element is preferably an organic EL element. [Effects of the Invention]

[0022] According to one embodiment of the present invention, a display device including a circuit capable of high-speed operation can be provided. Alternatively, a pixel and a driver circuit can be formed over the same substrate. Alternatively, a pixel and at least a part of a source driver can be formed over the same substrate. Alternatively, different transistors can be formed over the same substrate.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0024] [Figure 1] 1A and 1B are diagrams showing a configuration example of a semiconductor device. [Figure 2] 2A and 2B are diagrams showing configuration examples of a semiconductor device. [Figure 3] 3A and 3B are diagrams showing an example of the configuration of a semiconductor device. [Figure 4]4A and 4B are diagrams showing an example of the configuration of a semiconductor device. [Figure 5] 5A to 5F are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 6] 6A to 6F are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 7] 7A to 7E are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 8] 8A and 8B are diagrams showing configuration examples of a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a display device. [Figure 10] 10(A) and 10(B) are diagrams showing configuration examples of a display device. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a display device. [Figure 12] 12A to 12C are diagrams showing configuration examples of display devices. [Figure 13] 13A to 13C are diagrams showing configuration examples of display devices. [Figure 14] FIG. 14 is a diagram showing an example of a cross-sectional configuration of a display device. [Figure 15] 15A to 15F are diagrams showing configuration examples of electronic devices. [Figure 16] 16(A) and 16(B) are diagrams showing configuration examples of a display module. [Figure 17] 17(A) and 17(B) are diagrams showing configuration examples of electronic devices. [Figure 18] 18A to 18E are diagrams showing configuration examples of electronic devices. [Figure 19] 19A to 19G are diagrams showing configuration examples of electronic devices. [Figure 20] 20A to 20D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0027] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0028] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0029] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0030] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0031] In this specification, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0032] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

[0033] Furthermore, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" may be interchangeable with the terms "conductive film" and "insulating film."

[0034] In this specification, the EL layer refers to a layer provided between a pair of electrodes of a light-emitting element and containing at least a light-emitting substance (also referred to as a light-emitting layer), or a stack including a light-emitting layer.

[0035] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting) images etc. on a display surface, and therefore the display panel is one aspect of an output device.

[0036] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel.

[0037] (Embodiment 1) In this embodiment, a structural example of a semiconductor device that can be used for a display device of one embodiment of the present invention and an example of a method for manufacturing the semiconductor device will be described.

[0038] A display device according to one embodiment of the present invention includes a display portion, a first circuit portion, and a second circuit portion. The display portion includes a display element and a pixel circuit for driving the display element. The first circuit portion includes a circuit that functions as a gate driver (also referred to as a gate line driver circuit or a scan line driver circuit). The second circuit portion includes a circuit that functions as a source driver (also referred to as a source line driver circuit or a signal line driver circuit) or a demultiplexer circuit provided between the source driver and the display portion.

[0039] The display device has at least two types of transistors (first transistor and second transistor) over a substrate. The first transistor is used as a transistor constituting a pixel circuit and a first circuit portion of a display portion. The second transistor is used as a transistor constituting the second circuit portion.

[0040] The first transistor is a transistor in which a channel is formed in a first oxide semiconductor layer. The second transistor is a transistor in which a channel is formed in a second oxide semiconductor layer. The first oxide semiconductor layer and the second oxide semiconductor layer include metal oxide films that differ in one or more of composition, thickness, crystallinity, and film quality. In particular, the first oxide semiconductor layer and the second oxide semiconductor layer preferably include metal oxide films that differ in composition.

[0041] The second transistor preferably has a higher field-effect mobility than the first transistor. This allows a source driver or demultiplexer circuit that requires high-speed switching operation to be realized. Furthermore, the pixel circuit, the first circuit, and the second circuit can be fabricated on the same substrate, i.e., an on-panel display can be realized.

[0042] On the other hand, pixel circuits and gate drivers do not require high-speed switching operations compared to source drivers or demultiplexer circuits. Therefore, if they are configured using second transistors, the transistor size must be increased (e.g., the channel length must be increased) to obtain appropriate electrical characteristics, resulting in a larger circuit area. Therefore, by configuring the pixel circuit and gate driver using first transistors with lower field-effect mobility than the second transistors, it is possible to reduce the area occupied by the pixel circuit and gate driver. Since the area occupied by the pixel circuit can be reduced, a high-resolution display device can be realized. Furthermore, since the area occupied by the gate driver can be reduced, a display device with a narrow frame can be realized.

[0043] The first oxide semiconductor layer and the second oxide semiconductor layer can be formed as follows. First, a first metal oxide film to be the first oxide semiconductor layer is formed on a first insulating layer, and a first metal film is formed thereon. Next, a first resist mask is formed on the first metal film by photolithography or the like, and portions of the first metal film and the metal oxide film not covered by the first resist mask are etched to form a stack of an island-shaped first metal layer and an island-shaped first oxide semiconductor layer, and to expose a portion of the top surface of the first insulating layer. In this case, dry etching of the first metal film is preferable because it can prevent pattern shrinkage due to etching. Wet etching of the first metal oxide film is also preferable because it can mitigate damage due to etching. The first resist mask may be removed after the island-shaped first oxide semiconductor layer is formed, or after the island-shaped first metal layer is formed but before processing the first metal oxide film.

[0044] Next, a second metal oxide film and a second metal film are stacked on the top surface of the first insulating layer, the first metal layer, and the first oxide semiconductor layer. Next, a second resist mask is formed on the second metal film in a region that does not overlap with the first metal layer, and then the second metal film and the second metal oxide film are etched in the same manner as described above to form an island-shaped second metal layer and an island-shaped second metal oxide layer. At this time, by etching the second metal oxide layer while the first metal layer is provided on the first metal oxide layer, the first metal oxide layer can be prevented from being etched by the first metal layer. Similarly to the above, the second resist mask may be removed after the island-shaped second oxide semiconductor layer is formed, or may be removed after the island-shaped second metal layer is formed and before processing the second metal oxide film.

[0045] Finally, the first metal layer and the second metal layer are removed. By removing them by wet etching, damage to the first oxide semiconductor layer and the second oxide semiconductor layer due to etching can be reduced. In particular, because these layers are used as channel formation regions of transistors, it is preferable to remove them under conditions that minimize damage.

[0046] Note that a second resist mask can also be formed directly on the second metal oxide film without forming a second metal film. In this case, the second metal oxide film that is not covered by the second resist mask is etched to form an island-shaped second oxide semiconductor layer. Since the first oxide semiconductor layer is covered by the first metal film, it can be prevented from being etched. After that, the first metal layer is removed, and then the second resist mask is removed. Alternatively, the first metal layer is removed after the second resist mask is removed.

[0047] As a result, the first oxide semiconductor layer and the second oxide semiconductor layer can be formed side by side and in contact with the top surface of the first insulating layer. By repeating the above steps, three or more types of oxide semiconductor layers can be formed in contact with each other on the same surface. Therefore, one embodiment of the present invention includes a semiconductor device, a display device, or an electronic device in which three or more types of transistors using different oxide semiconductors are formed on the same surface, and a manufacturing method thereof.

[0048] When three or more types of oxide semiconductor layers are formed in contact with each other on the same surface, the metal oxide film of the oxide semiconductor layer formed last may be processed without forming a metal film as described above.

[0049] A more specific example will be described below with reference to the drawings.

[0050] [Configuration example 1] 1A is a schematic cross-sectional view of a transistor 100 and a transistor 200 provided over a substrate 102, taken along a channel length direction. FIG. 1B is a schematic cross-sectional view of the transistor 100 and the transistor 200, taken along a channel width direction.

[0051] The transistor 100 is provided over a substrate 102 and includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, and the like. The island-shaped semiconductor layer 108 is provided on and in contact with the insulating layer 103. The insulating layer 110 is provided in contact with a top surface of the insulating layer 103 and a top surface and side surfaces of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are stacked in this order on the insulating layer 110 and have a portion overlapping with the semiconductor layer 108. The insulating layer 118 is provided to cover a top surface of the insulating layer 110, side surfaces of the metal oxide layer 114, and a top surface of the conductive layer 112.

[0052] The transistor 200 is provided over a substrate 102 and includes an insulating layer 103, a semiconductor layer 208, an insulating layer 110, a metal oxide layer 214, a conductive layer 212, an insulating layer 118, and the like. The island-shaped semiconductor layer 208 is provided on and in contact with the insulating layer 103. The insulating layer 110 is provided in contact with the top surface of the insulating layer 103 and the top surface and side surfaces of the semiconductor layer 208. The metal oxide layer 214 and the conductive layer 212 are stacked in this order on the insulating layer 110 and have a portion overlapping with the semiconductor layer 208. The insulating layer 118 is provided to cover the top surface of the insulating layer 110, the side surfaces of the metal oxide layer 214, and the top surface of the conductive layer 212.

[0053] 1A, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode and a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to a low-resistance region 108n included in the semiconductor layer 108 through an opening 141a and an opening 141b provided in the insulating layer 118 and the insulating layer 110, respectively.

[0054] The transistor 200 may also include a conductive layer 220a and a conductive layer 220b over the insulating layer 118. The conductive layer 220a and the conductive layer 220b function as a source electrode and a drain electrode. The conductive layer 220a and the conductive layer 220b are electrically connected to the low-resistance region 208n of the semiconductor layer 208 through an opening 141c and an opening 141d provided in the insulating layer 118 and the insulating layer 110, respectively.

[0055] The semiconductor layer 108 included in the transistor 100 and the semiconductor layer 208 included in the transistor 200 include metal oxide films with different compositions. The semiconductor layer 108 and the semiconductor layer 208 are formed by processing different metal oxide films.

[0056] The semiconductor layer 108 and the semiconductor layer 208 are not limited to being of the same composition, and metal oxide films that differ in one or more of thickness, crystallinity, carrier concentration, and film quality can also be used. In this case, it is preferable to make the composition, thickness, or film formation conditions different so that the field-effect mobility of the transistor 200 is higher than that of the transistor 100.

[0057] Here, the compositions of the semiconductor layer 108 and the semiconductor layer 208 will be described. When metal oxide films with different compositions are used for the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layer 108 preferably contains a metal oxide containing at least indium, gallium, zinc, and oxygen. On the other hand, the semiconductor layer 208 preferably contains a metal oxide containing at least indium and oxygen. The semiconductor layer 208 may also contain zinc in addition to these. The semiconductor layer 208 may also contain tin. The semiconductor layer 208 may also contain gallium. The semiconductor layer 108 may also contain titanium.

[0058] Indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO) or the like can be used for the semiconductor layer 108. Representative materials that can be used for the semiconductor layer 208 include indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), and indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide). Alternatively, indium tin oxide containing silicon or the like can be used.

[0059] The present invention can also be applied to a case where, instead of the gallium, an element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is used. In particular, it is preferable that M is one or more elements selected from aluminum and yttrium.

[0060] Here, the compositions of the semiconductor layer 108 and the semiconductor layer 208 greatly affect the electrical characteristics and reliability of the transistor 100 or the transistor 200. For example, by increasing the indium content in the semiconductor layer 208, carrier mobility can be improved, and a transistor with high field-effect mobility can be realized.

[0061] When an In-Zn oxide is used for the semiconductor layer 208, it is preferable to use a metal oxide film in which the atomic ratio of In is equal to or greater than the atomic ratio of Zn. For example, a metal oxide film in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1 or a similar ratio can be used.

[0062] Furthermore, when an In-Sn oxide is used for the semiconductor layer 208, it is preferable to use a metal oxide film in which the atomic ratio of In is equal to or greater than the atomic ratio of Sn. For example, a metal oxide film in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1 or a ratio close thereto can be used.

[0063] Furthermore, when an In-Sn-Zn oxide is used for the semiconductor layer 208, a metal oxide film in which the atomic ratio of In to the number of atoms of the metal elements is higher than the atomic ratios of Sn and Zn can be used. It is more preferable to use a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of Sn. In other words, it is preferable to use a metal oxide film in which the atomic ratios of metal elements satisfy In>Sn, In>Zn, and Zn>Sn for the semiconductor layer 208.

[0064] Furthermore, when an In-Ga-Zn oxide is used for the semiconductor layer 208, a metal oxide film in which the atomic ratio of In to the number of atoms of the metal elements is higher than the atomic ratio of Ga can be used. It is more preferable to use a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of Ga. In other words, it is preferable to use a metal oxide film in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 208.

[0065] For example, the semiconductor layer 208 can be a metal oxide film having an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=10:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, or a ratio close to these.

[0066] In particular, it is preferable to use a metal oxide film containing indium and zinc, in which the ratio of the number of indium atoms to the number of atoms of the contained metal elements is 50 atomic % or more, preferably 60 atomic % or more, and more preferably 70 atomic % or more, for the semiconductor layer 208.

[0067] When In-Ga-Zn oxide is used for both the semiconductor layer 108 and the semiconductor layer 208, the semiconductor layer 208 can be a metal oxide film having a larger ratio of the number of In atoms to the number of atoms of the metal elements than the semiconductor layer 108.

[0068] Similarly, when an In-Ga-Zn oxide is used for the semiconductor layer 108 and a metal oxide containing indium other than an In-Ga-Zn oxide is used for the semiconductor layer 208, a metal oxide film having a larger ratio of the number of In atoms to the number of atoms of the metal element compared to the semiconductor layer 108 can be used for the semiconductor layer 208.

[0069] Furthermore, a metal oxide containing indium other than In-Ga-Zn oxide can also be used for the semiconductor layer 108. In this case, similarly, a metal oxide film having a higher ratio of the number of In atoms to the number of metal elements compared to the semiconductor layer 108 can be used for the semiconductor layer 208.

[0070] The components of the transistor 100 and the transistor 200, other than the semiconductor layers, can be formed simultaneously in the same process, which prevents an increase in the number of processes even when two types of transistors are mixed.

[0071] That is, the metal oxide layer 114 and the metal oxide layer 214 are formed by processing the same metal oxide film. The conductive layer 112 and the conductive layer 212 are formed by processing the same conductive film. The conductive layer 120a, the conductive layer 120b, the conductive layer 220a, and the conductive layer 220b are formed by processing the same conductive film.

[0072] Part of the conductive layer 112 and part of the conductive layer 212 function as a gate electrode. Part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 and the transistor 200 are so-called top-gate transistors in which a gate electrode is provided over a semiconductor layer.

[0073] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes roughly match each other. The conductive layer 212 and the metal oxide layer 214 are also processed so that their top surface shapes roughly match each other.

[0074] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" also applies.

[0075] The following describes the metal oxide layer 114. Note that the metal oxide layer 214 also has the same functions and effects as the metal oxide layer 114, and therefore the following description can be taken into consideration.

[0076] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112. Furthermore, the metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing toward the insulating layer 110. For the metal oxide layer 114, it is preferable to use a material that is less permeable to oxygen and hydrogen than, for example, the insulating layer 110.

[0077] The metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when the conductive layer 112 is made of a metal material that easily absorbs oxygen, such as aluminum or copper. Furthermore, even when the conductive layer 112 contains hydrogen, the metal oxide layer 114 can prevent hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0078] An insulating material or a conductive material can be used for the metal oxide layer 114. When the metal oxide layer 114 has insulating properties, the metal oxide layer 114 functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, the metal oxide layer 114 functions as a part of the gate electrode.

[0079] An insulating material having a higher dielectric constant than silicon oxide is preferably used for the metal oxide layer 114. In particular, an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferably used because the driving voltage can be reduced.

[0080] Conductive oxides such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide can also be used as the metal oxide layer 114. Conductive oxides containing indium are particularly preferred because of their high conductivity.

[0081] It is preferable to use an oxide material containing one or more elements that are the same as those of the semiconductor layer 108 or the semiconductor layer 208 for the metal oxide layer 114. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108 or the semiconductor layer 208. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as that for the semiconductor layer 108 or the semiconductor layer 208 for the metal oxide layer 114, because this allows the use of common equipment.

[0082] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming the oxide film in an atmosphere containing oxygen gas.

[0083] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108n sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 functions as a channel formation region of the transistor 100. On the other hand, the pair of low-resistance regions 108n function as source and drain regions of the transistor 100. Similarly, the semiconductor layer 208 has a channel formation region overlapping with the conductive layer 212 and a pair of low-resistance regions 208n sandwiching the channel formation region.

[0084] The low-resistance region 108n and the low-resistance region 208n can also be referred to as a region with lower resistance than the channel formation region, a region with a high carrier concentration, a region with a high oxygen defect density, a region with a high impurity concentration, or an n-type region.

[0085] The low-resistance region 108n and the low-resistance region 208n are regions containing impurity elements. Examples of the impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and rare gases. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable for the low-resistance region 108n to contain boron or phosphorus. Two or more of these elements may also be contained.

[0086] As will be described later, the treatment of adding impurities to the low-resistance regions 108n and 208n can be performed through the insulating layer 110 using the conductive layer 112 or the conductive layer 212 as a mask.

[0087] The low resistance region 108n and the low resistance region 208n have an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1 x 10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than 1×10, more preferably 20 atoms / cm 3 That's it, 1 x 10 22 atoms / cm 3 It is preferred to include a region in which:

[0088] The concentration of impurities contained in the low-resistance region 108n and the low-resistance region 208n can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side with XPS analysis.

[0089] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, an inorganic insulating material such as an oxide or a nitride can be used for the insulating layer 110. More specifically, an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, or hafnium aluminate can be used.

[0090] [Configuration example 2] FIG. 2A is a cross-sectional view of the transistor 100A and the transistor 200A in the channel length direction, and FIG. 2B is a cross-sectional view of the transistor 100A and the transistor 200A in the channel width direction.

[0091] The transistor 100A differs from the transistor 100 mainly in that the transistor 100A includes a conductive layer 106 between the substrate 102 and the insulating layer 103. Similarly, the transistor 200A differs from the transistor 200 mainly in that the transistor 200A includes a conductive layer 206. The conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112, and the conductive layer 206 has a region overlapping with the semiconductor layer 208 and the conductive layer 212.

[0092] The conductive layers 112 and 212 function as second gate electrodes (also referred to as top gate electrodes), and the conductive layers 106 and 206 function as first gate electrodes (also referred to as bottom gate electrodes). Part of the insulating layer 110 functions as a second gate insulating layer of each transistor, and part of the insulating layer 103 functions as a first gate insulating layer of each transistor.

[0093] A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that for ease of explanation, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 will sometimes be referred to as a channel formation region hereinafter. However, in reality, a channel can also be formed in a portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106 (a portion including the low-resistance region 108n). The same applies to the semiconductor layer 208 of the transistor 200.

[0094] 2B, the conductive layer 106 may be electrically connected to the conductive layer 112 through an opening 142a provided in the metal oxide layer 114, the insulating layer 110, and the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to have the same potential. Similarly, in the transistor 200A, the conductive layer 206 and the conductive layer 212 are electrically connected.

[0095] The conductive layer 106 and the conductive layer 206 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because wiring resistance can be reduced.

[0096] 2(B), the conductive layer 112 and the conductive layer 106 preferably protrude outward beyond the end portions of the semiconductor layer 108 in the channel width direction. In this case, as shown in FIG. 2(B), the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 via the insulating layer 110 and the insulating layer 103. Similarly, the semiconductor layer 208 is also covered with the conductive layer 212 and the conductive layer 206.

[0097] With this structure, the semiconductor layer can be electrically surrounded by an electric field generated by the pair of gate electrodes. In this case, it is particularly preferable to apply the same potential to the pair of gate electrodes. This allows an electric field for inducing a channel in the semiconductor layer to be effectively applied, thereby increasing the on-state current of the transistor 100A and the transistor 200A. This also enables miniaturization of the transistor 100A and the transistor 200A.

[0098] Note that the pair of gate electrodes may not be connected. In this case, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100A or the transistor 200A may be applied to the other. In this case, the threshold voltage when the transistor 100A or the transistor 200A is driven by the other gate electrode can be controlled by the potential applied to one gate electrode.

[0099] Note that in the manufacturing process of the transistor 100A and the transistor 200A, the transistor 100 and the transistor 200 can be manufactured over the same substrate at the same time. Therefore, a display device including four types of transistors, namely, the transistor 100, the transistor 100A, the transistor 200, and the transistor 200A, can be realized. Alternatively, a display device including either or both of the transistor 100 and the transistor 100A and either or both of the transistor 200 and the transistor 200A can be realized.

[0100] [Configuration example 3] FIG. 3A is a cross-sectional view of the transistor 100B and the transistor 200B in the channel length direction, and FIG. 3B is a cross-sectional view of the transistor 100B and the transistor 200B in the channel width direction.

[0101] The transistor 100B and the transistor 200B are different from the transistor 100 and the transistor 200 described above mainly in that the shape of the insulating layer 110 is different.

[0102] The following describes the insulating layer 110. Although the transistor 100B will be described here, the same effects can be achieved with the transistor 200B.

[0103] The insulating layer 110 is processed so that its top surface shape is approximately the same as those of the conductive layer 112 and the metal oxide layer 114. The insulating layer 110 can be formed by processing using a resist mask for processing the conductive layer 112 and the metal oxide layer 114, for example.

[0104] The insulating layer 118 is provided in contact with the top surface and side surface of the semiconductor layer 108 that are not covered with the conductive layer 112, the metal oxide layer 114, and the insulating layer 110. The insulating layer 118 is also provided to cover the top surface of the insulating layer 103, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the top surface and side surface of the conductive layer 112.

[0105] The insulating layer 118 has a function of reducing the resistance of the low-resistance region 108n. As such an insulating layer 118, an insulating film that can supply impurities into the low-resistance region 108n by heating during or after the formation of the insulating layer 118 can be used. Alternatively, an insulating film that can generate oxygen vacancies in the low-resistance region 108n by heating during or after the formation of the insulating layer 118 can be used.

[0106] For example, the insulating layer 118 can be an insulating film that functions as a supply source for supplying impurities to the low-resistance region 108n. In this case, the insulating layer 118 is preferably a film that releases hydrogen when heated. By forming such an insulating layer 118 in contact with the semiconductor layer 108, impurities such as hydrogen can be supplied to the low-resistance region 108n, thereby reducing the resistance of the low-resistance region 108n.

[0107] The insulating layer 118 is preferably formed using a deposition gas containing an impurity element such as a hydrogen element.

[0108] For example, an insulating film containing a nitride, such as silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, or aluminum nitride oxide, can be suitably used for the insulating layer 118. In particular, silicon nitride has a blocking property against hydrogen and oxygen, and can therefore prevent both diffusion of hydrogen from the outside to the semiconductor layer and desorption of oxygen from the semiconductor layer to the outside, thereby achieving a highly reliable transistor.

[0109] Alternatively, the insulating layer 118 can be an oxide film such as silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide.

[0110] [Configuration example 4] FIG. 4A is a cross-sectional view of the transistor 100C and the transistor 200C in the channel length direction, and FIG. 4B is a cross-sectional view of the transistor 100C and the transistor 200C in the channel width direction.

[0111] The transistor 100C is an example in which the conductive layer 106 functioning as a first gate electrode, which is illustrated in Configuration Example 2, is provided in the transistor 100B illustrated in Configuration Example 3. Similarly, the transistor 200C is an example in which the conductive layer 206 is provided in the transistor 200B.

[0112] With such a structure, a transistor with high on-state current or a transistor whose threshold voltage can be controlled can be provided.

[0113] [Example of manufacturing method] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below, taking the transistor 100A and the transistor 200A described in Structure Example 2 as examples.

[0114] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0115] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0116] Furthermore, when processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0117] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0118] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as light for exposure. Instead of light for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0119] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0120] 5A to 7E show schematic cross-sectional views in the channel length direction at different stages in the manufacturing process of the transistor 100A and the transistor 200A illustrated in Configuration Example 2. FIG.

[0121] In the following, regarding matters common to components (such as conductive layers 106 and 206, conductive layers 112 and 212) that can be formed in the same process between transistor 100A and transistor 200A, only one of them may be described, assuming that they have the same functions and effects, and the description of the other may be omitted and taken into consideration.

[0122] [Formation of Conductive Layer 106 and Conductive Layer 206] A conductive film is formed over the substrate 102 and processed by etching to form a conductive layer 106 and a conductive layer 206 which function as gate electrodes (FIG. 5A).

[0123] 5A, the conductive layers 106 and 206 are preferably processed so that their end portions have a tapered shape, which can improve the step coverage of the insulating layer 103 to be formed next.

[0124] Furthermore, by using a conductive film containing copper as the conductive film to be the conductive layer 106 and the conductive layer 206, wiring resistance can be reduced. For example, when the present invention is applied to a large display device or a display device with high resolution, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used for the conductive layer 106 or the like, the insulating layer 103 prevents copper from diffusing toward the semiconductor layer 108 or the like, so that a highly reliable transistor can be realized.

[0125] [Formation of insulating layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102, the conductive layer 106, and the conductive layer 206 (FIG. 5B). The insulating layer 103 can be formed by a PECVD method, an ALD method, a sputtering method, or the like.

[0126] In particular, it is preferable that the insulating layer 103 be formed by the PECVD method.

[0127] The insulating layer 103 preferably has a stacked structure of two or more insulating films. In this case, an insulating film containing nitrogen is preferably used as the insulating film located on the conductive layer 106 side. Specifically, the insulating film located on the conductive layer 106 side can be, for example, an insulating film containing nitrogen, such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a hafnium nitride film.

[0128] On the other hand, an insulating film containing oxygen is preferably used for the insulating film in contact with the semiconductor layer 108 and the semiconductor layer 208. For example, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used.

[0129] Furthermore, it is preferable that each insulating film constituting the insulating layer 103 is successively formed using a plasma CVD apparatus without being exposed to the air.

[0130] After the insulating layer 103 is formed, treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method or an ion implantation method.

[0131] [Formation of Metal Oxide Film 108f] Subsequently, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 5(C)).

[0132] The metal oxide film 108f is preferably formed by sputtering using a metal oxide target.

[0133] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0134] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0135] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0136] The conditions for forming the metal oxide film are that the substrate temperature is from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because it increases productivity. Furthermore, by forming the metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0137] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for desorbing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103 and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C to 200°C in a reduced-pressure atmosphere. Alternatively, plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO). The plasma treatment containing nitrous oxide gas can supply oxygen while suitably removing organic substances on the surface of the insulating layer 103. After such a treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 103 to the air.

[0138] In addition, when the semiconductor layer 108 has a stacked structure in which a plurality of semiconductor layers are stacked, it is preferable to form a metal oxide film first, and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0139] [Formation of Metal Film 131f] Subsequently, a metal film 131f is formed on the metal oxide film 108f (FIG. 5(D)).

[0140] The metal film 131f can be formed by a film formation method such as sputtering, vacuum evaporation, etc. It is preferable that the metal film 131f is formed successively after the metal oxide film 108f is formed without being exposed to the air.

[0141] The metal film 131f is preferably made of a metal that is unlikely to diffuse into the oxide semiconductor that constitutes the metal oxide film 108f. This allows for a reduced carrier concentration in the subsequent semiconductor layer 108. Furthermore, the metal film 131f is preferably made of a material that has a high etching selectivity with respect to the metal oxide film 108f. In particular, since the metal film 131f is etched by both dry etching and wet etching when the metal layer 131 is subsequently removed, it is preferable to use a material that can increase the etching selectivity with respect to the metal oxide film 108f for both methods. Thus, a film of a high-melting-point metal, such as a tungsten film, a molybdenum film, or a titanium film, can be suitably used as the metal film 131f that is unlikely to diffuse into the oxide semiconductor and has a high etching selectivity.

[0142] [Formation of Metal Layer 131 and Semiconductor Layer 108] Subsequently, a resist mask 135 is formed on the metal film 131f (FIG. 5(E)).

[0143] Next, the metal film 131f in the region not covered by the resist mask 135 is removed by etching to expose a part of the upper surface of the metal oxide film 108f, thereby forming the island-shaped metal layer 131 first.

[0144] The metal film 131f is preferably etched by dry etching. In particular, it is preferable to use a highly anisotropic dry etching method. This prevents the side surfaces of the metal layer 131 from being etched, thereby preventing the pattern of the metal layer 131 from shrinking below the pattern of the resist mask 135.

[0145] Next, the metal oxide film 108f in the region not covered with the metal layer 131 is removed by etching to expose a part of the top surface of the insulating layer 103 (FIG. 5(F)). Although dry etching can be used to etch the metal oxide film 108f, wet etching is preferable because it can reduce etching damage to the semiconductor layer 108.

[0146] As a result, island-shaped metal layers 131 and island-shaped semiconductor layers 108 are formed.

[0147] Thereafter, the resist mask 135 is removed (FIG. 6(A)). The resist mask 135 can be removed by wet etching or dry etching.

[0148] Note that the resist mask 135 may be removed after the metal layer 131 is formed and before the metal oxide film 108f is etched. At this time, the metal oxide film 108f can be etched using the metal layer 131 as a mask for etching (also referred to as a hard mask). In this way, the side surfaces of the semiconductor layer 108 are not exposed to the etching of the resist mask 135, and therefore, damage to the semiconductor layer 108 can be suppressed.

[0149] [Formation of Metal Oxide Film 208f] Subsequently, a metal oxide film 208f is formed on the metal layer 131, the semiconductor layer 108, and the insulating layer 103.

[0150] The metal oxide film 208f can be formed using a sputtering target different from that for the metal oxide film 108f. For details on the formation of the metal oxide film 208f, the description of the metal oxide film 108f can be cited.

[0151] [Formation of Metal Film 132f] Subsequently, a metal film 132f is formed on the metal oxide film 208f (FIG. 6(B)).

[0152] It is preferable that the metal film 132f is formed using the same material and under the same conditions as the metal film 131f. Furthermore, it is preferable that the metal film 132f is formed to have the same thickness as the metal film 131f. This eliminates the need to separately remove the metal layer 131 and the metal layer 132 later, and allows the steps to be shared.

[0153] [Formation of Metal Layer 132 and Semiconductor Layer 208] Subsequently, a resist mask 136 is formed on the metal film 132f in an area that does not overlap with the metal layer 131 (FIG. 6(C)).

[0154] Subsequently, the metal film 132f in the region not covered by the resist mask 136 is removed by etching to expose a part of the upper surface of the metal oxide film 208f, thereby forming the island-shaped metal layer 132 first.

[0155] As with the metal film 131f, the metal film 132f is preferably etched by dry etching.

[0156] Next, the metal oxide film 208f in the region not covered with the metal layer 132 is removed by etching to expose the upper surface of the metal layer 131, the side surfaces of the semiconductor layer 108, and the upper surface of the insulating layer 103 (FIG. 6(D)). As with the above-described metal oxide film 108f, the etching of the metal oxide film 208f is preferably performed by wet etching.

[0157] In this case, the metal layer 131 functions as a protective layer to prevent the semiconductor layer 108 from being etched when the metal oxide film 208f is etched. Therefore, it is preferable to etch the metal film 132f under conditions that provide a high etching rate selectivity with respect to the metal oxide film 208f, rather than simultaneously etching the metal film 132f and the metal oxide film 208f under the same conditions, and then etch them separately. This makes it possible to use conditions for etching the metal oxide film 208f that provide a high etching rate selectivity with respect to the metal layer 131, thereby preventing the metal layer 131, which functions as a protective layer, from being etched when the metal oxide film 208f is etched.

[0158] Thereafter, the resist mask 136 is removed (FIG. 6(E)).

[0159] Note that, like the resist mask 135, the resist mask 136 may be removed after the formation of the metal layer 132 and before the etching of the metal oxide film 208f. At this time, the metal oxide film 208f can be etched using the metal layer 132 as a mask for etching (also referred to as a hard mask). In this way, the side surfaces of the semiconductor layer 208 and the semiconductor layer 108 are not exposed to the etching of the resist mask 136, and therefore, damage to the semiconductor layer 108 and the semiconductor layer 208 can be suppressed.

[0160] [Removal of Metal Layer 131 and Metal Layer 132] Subsequently, the metal layer 131 and the metal layer 132 are removed by etching (FIG. 6(F)).

[0161] By forming the metal layer 131 and the metal layer 132 under the same conditions, they can be removed simultaneously in one step.

[0162] The metal layers 131 and 132 are preferably removed by wet etching. If they are removed by dry etching, the semiconductor layers 108 and 208 may be damaged by plasma, which may cause changes in film quality. By using wet etching, a highly reliable transistor with favorable electrical characteristics can be manufactured.

[0163] Through the above steps, the semiconductor layer 108 and the semiconductor layer 208 having different compositions can be formed side by side on the same surface.

[0164] Here, the semiconductor layer 108 is formed first and then the semiconductor layer 208, but the order is not important. That is, the semiconductor layer 208 may be formed first and then the semiconductor layer 108 may be formed.

[0165] [Heat Treatment] Heat treatment is preferably performed after the formation of the semiconductor layers 108 and 208. The heat treatment can remove hydrogen or water contained in or adsorbed to the surfaces of the semiconductor layers 108 and 208. Furthermore, the heat treatment may improve the film quality of the semiconductor layers 108 and 208 (for example, reduce defects, improve crystallinity, etc.).

[0166] Furthermore, oxygen can be supplied from the insulating layer 103 to the semiconductor layer 108 and the semiconductor layer 208 by the heat treatment.

[0167] The temperature of the heat treatment can typically be 150°C or higher and lower than the strain point of the substrate, or 200°C or higher and 500°C or lower, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower.

[0168] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, after heating in the atmosphere, heating can be performed in an atmosphere containing oxygen. Alternatively, heating can be performed in a dry air atmosphere. Note that it is preferable that the atmosphere for the heat treatment contains as little hydrogen, water, or the like as possible. The heat treatment can be performed using an electric furnace, an RTA (Rapid Thermal Anneal) device, or the like. Using an RTA device can shorten the heat treatment time.

[0169] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0170] [Formation of insulating layer 110] Subsequently, the insulating layer 110 is formed to cover the insulating layer 103, the semiconductor layer 108, and the semiconductor layer 208.

[0171] The insulating layer 110 is preferably formed by the PECVD method.

[0172] Furthermore, before the insulating layer 110 is formed, it is preferable to perform plasma treatment on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interfaces between the semiconductor layer 108 and the insulating layer 110 and between the semiconductor layer 108 and the semiconductor layer 208 and between the semiconductor layer 108 and the semiconductor layer 208 and the insulating layer 110 can be reduced, thereby realizing a highly reliable transistor. This is particularly suitable when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air during the period from the formation of the semiconductor layer 108 and the semiconductor layer 208 to the formation of the insulating layer 110. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. It is preferable to perform the plasma treatment and the formation of the insulating layer 110 successively without exposure to the air.

[0173] Here, heat treatment is preferably performed after the insulating layer 110 is formed. The heat treatment can remove hydrogen or water contained in or adsorbed to the surface of the insulating layer 110. Furthermore, defects in the insulating layer 110 can be reduced.

[0174] The conditions for the heat treatment may be as described above.

[0175] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0176] [Formation of Metal Oxide Film 114f] Subsequently, on the insulating layer 110, a metal oxide film 114f is formed.

[0177] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 110 during the formation of the metal oxide film 114f. Note that oxygen may be supplied to the semiconductor layer 108 or the semiconductor layer 208 during the formation of the metal oxide film 114f.

[0178] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing a metal oxide similar to that of the semiconductor layer 108 or the semiconductor layer 208, the description of the semiconductor layer 108 can be used.

[0179] For example, the metal oxide film 114f may be formed by reactive sputtering using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, an aluminum oxide film can be formed.

[0180] During deposition of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio) or the higher the oxygen partial pressure in the deposition chamber, the more oxygen can be supplied to the insulating layer 110. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% ​​to 100%, more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to set the oxygen partial pressure in the deposition chamber as close to 100% as possible.

[0181] In this way, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f, and oxygen can be prevented from being released from the insulating layer 110. As a result, an extremely large amount of oxygen can be trapped in the insulating layer 110.

[0182] After the metal oxide film 114f is formed, heat treatment is preferably performed. By the heat treatment, oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108 and the semiconductor layer 208. By performing heat treatment while the insulating layer 110 is covered with the metal oxide film 114f, oxygen is prevented from being released from the insulating layer 110 to the outside, and a large amount of oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208. As a result, oxygen vacancies in the semiconductor layer 108 and the semiconductor layer 208 can be reduced, and a highly reliable transistor can be realized.

[0183] The conditions for the heat treatment may be as described above.

[0184] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, there are cases where a high-temperature treatment in a later step (e.g., a film formation step) can also serve as the heat treatment.

[0185] After the metal oxide film 114f is formed or after the heat treatment, the metal oxide film 114f may be removed.

[0186] [Formation of opening 142] Subsequently, the metal oxide film 114f, the insulating layer 110, and the insulating layer 103 are partially etched to form openings 142a and 142b (not shown) that reach the conductive layer 106 or the conductive layer 206. This allows the conductive layer 106 or the conductive layer 206 to be electrically connected to the conductive layer 112 or the conductive layer 212, which will be formed later, through the openings 142a and 142b.

[0187] [Formation of Conductive Layer 112, Conductive Layer 212, Metal Oxide Layer 114, and Metal Oxide Layer 214] Subsequently, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f (FIG. 7(A)).

[0188] The conductive film 112f is preferably made of a low-resistance metal or alloy material, a material that does not easily release hydrogen and from which hydrogen does not easily diffuse, and a material that does not easily oxidize.

[0189] For example, the conductive film 112f is preferably formed by a sputtering method using a sputtering target containing a metal or an alloy.

[0190] For example, the conductive film 112f is preferably a stacked film in which a conductive film that is resistant to oxidation and hydrogen diffusion and a conductive film with low resistance are stacked.

[0191] Next, the conductive film 112f and the metal oxide film 114f are partly etched to form the conductive layer 112, the conductive layer 212, the metal oxide layer 114, and the metal oxide layer 214 (FIG. 7B). The conductive film 112f and the metal oxide film 114f are preferably processed using the same resist mask. Alternatively, the metal oxide film 114f may be etched using the etched conductive layer 112 as a hard mask.

[0192] It is particularly preferable to use a wet etching method for etching the conductive film 112f and the metal oxide film 114f.

[0193] This allows the conductive layer 112 and the metal oxide layer 114, and the conductive layer 212 and the metal oxide layer 214, to be formed so that their top surface shapes are roughly the same.

[0194] In this way, by forming a structure in which the top surface and side surface of the semiconductor layer 108, the top surface and side surface of the semiconductor layer 208, and the insulating layer 103 are covered without etching the insulating layer 110, it is possible to prevent the semiconductor layer 108, the semiconductor layer 208, the insulating layer 103, and the like from being etched and thinned when the conductive film 112f and the like are etched.

[0195] [Fueling of impurity elements] Next, using the conductive layers 112 and 212 as masks, a process of supplying (also referred to as adding or injecting) the impurity element 140 to the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 110 is performed (FIG. 7C). As a result, a low-resistance region 108n can be formed in a region of the semiconductor layer 108 that is not covered with the conductive layer 112. Similarly, a low-resistance region 208n can be formed in the semiconductor layer 208. At this time, it is preferable to determine conditions for the process of supplying the impurity element 140 in consideration of the material, thickness, and the like of the conductive layers 112 and 212 that serve as masks so that the impurity element 140 is not supplied as much as possible to a region of the semiconductor layer 108 that overlaps with the conductive layer 112 and a region of the semiconductor layer 208 that overlaps with the conductive layer 212. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 112 and a region of the semiconductor layer 208 that overlaps with the conductive layer 212.

[0196] The impurity element 140 can be preferably supplied by plasma ion doping or ion implantation. These methods allow the concentration profile in the depth direction to be controlled with high precision by adjusting the ion acceleration voltage, dose, etc. The use of plasma ion doping can increase productivity. Furthermore, the use of ion implantation using mass separation can increase the purity of the supplied impurity element.

[0197] In the supplying process of the impurity element 140, it is preferable to control the processing conditions so that the concentration is highest at the interface between the semiconductor layer 108 and the insulating layer 110, or in a portion close to the interface in the semiconductor layer 108, or in a portion close to the interface in the insulating layer 110. This allows the impurity element 140 to be supplied at an optimum concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0198] Examples of the impurity element 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and rare gases. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0199] As a source gas for the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, B2H6 gas or BF3 gas can be typically used. When supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas in which these source gases are diluted with a rare gas can be used.

[0200] Other usable source gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. The ion source is not limited to gas, and a solid or liquid vaporized by heating may also be used.

[0201] The addition of the impurity element 140 can be controlled by setting conditions such as acceleration voltage or dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 110 and the semiconductor layer 108 .

[0202] For example, when adding boron or phosphorus by ion implantation or plasma ion doping, the dose is, for example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Less than 1 × 10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Less than 1×10, more preferably 15 ions / cm 2 3x10 or more 16 ions / cm 2 The range can be as follows:

[0203] The method for supplying the impurity element 140 is not limited to this, and may be, for example, a treatment using thermal diffusion by heating, a plasma treatment, or the like. In the case of the plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. The apparatus for generating the plasma may be a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like.

[0204] In one embodiment of the present invention, the impurity element 140 can be supplied to the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 110. Therefore, even when the semiconductor layer 108 or the semiconductor layer 208 has crystallinity, damage to the semiconductor layer 108 or the semiconductor layer 208 when the impurity element 140 is supplied can be reduced, and loss of crystallinity can be suppressed. Therefore, this is preferable in cases where electrical resistance increases due to a decrease in crystallinity.

[0205] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed to cover the insulating layer 110, the metal oxide layer 114, the conductive layer 112, the metal oxide layer 214, and the conductive layer 212 (FIG. 7(D)).

[0206] When the insulating layer 118 is formed by plasma CVD, if the film formation temperature is too high, impurities contained in the low-resistance region 108n and the like may diffuse into the peripheral portion including the channel formation region of the semiconductor layer 108, or the electrical resistance of the low-resistance region 108n may increase. Therefore, the film formation temperature for the insulating layer 118 may be determined taking these factors into consideration.

[0207] For example, the deposition temperature of the insulating layer 118 is preferably 150° C. to 400° C., preferably 180° C. to 360° C., more preferably 200° C. to 250° C. By depositing the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0208] After the insulating layer 118 is formed, heat treatment may be performed. The heat treatment may make the low-resistance region 108n more stable and low-resistance. For example, the heat treatment may cause the impurity element 140 to diffuse appropriately and become locally uniform, thereby forming the low-resistance region 108n having an ideal impurity element concentration gradient. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), the impurity element 140 may diffuse into the channel formation region, which may result in deterioration of the electrical characteristics and reliability of the transistor.

[0209] The conditions for the heat treatment may be as described above.

[0210] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, if there is a high-temperature treatment (e.g., a film formation step) in a later step, this heat treatment may be combined with the heat treatment.

[0211] [Formation of Openings 141a to 141d] Subsequently, the insulating layer 118 and the insulating layer 110 are partially etched to form openings 141a and 141b that reach the low-resistance region 108n, and openings 141c and 141d that reach the low-resistance region 208n.

[0212] [Formation of Conductive Layer 120a, Conductive Layer 120b, Conductive Layer 220a, and Conductive Layer 220b] Next, a conductive film is formed over the insulating layer 118 so as to cover the openings 141a to 141d, and the conductive film is processed into a desired shape to form conductive layers 120a, 120b, 220a, and 220b (FIG. 7(E)).

[0213] Through the above steps, the transistor 100A and the transistor 200A can be manufactured. For example, when the transistor 100A is used in a pixel of a display device, a subsequent step of forming one or more of a protective insulating layer, a planarization layer, a pixel electrode, and a wiring may be added.

[0214] The above is an explanation of an example of the manufacturing method.

[0215] [Modification of the manufacturing method] Although the structure in which the gate electrode is provided above the semiconductor layer has been described above, a so-called bottom-gate transistor in which the gate electrode is provided below the semiconductor layer can also be manufactured.

[0216] First, similarly to the above-described manufacturing method example, the conductive layer 106, the conductive layer 206, the insulating layer 103, the semiconductor layer 108, and the semiconductor layer 208 are formed over the substrate 102 (see FIG. 6F).

[0217] Subsequently, a conductive film is formed over the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 103. After that, the conductive film is etched in a region over the semiconductor layer 108 that overlaps with the conductive layer 106 and in a region over the semiconductor layer 208 that overlaps with the conductive layer 206, thereby forming conductive layers 130a, 130b, 230a, and 230b (FIG. 8A).

[0218] The conductive layer 130a, the conductive layer 130b, the conductive layer 230a, and the conductive layer 230b each function as a source electrode or a drain electrode of a transistor.

[0219] In this manner, the bottom-gate transistor 100D and the bottom-gate transistor 200D can be formed side by side on the same surface.

[0220] After that, the insulating layer 119 is preferably formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 130a, the conductive layer 130b, the conductive layer 230a, and the conductive layer 230b (FIG. 8B). The insulating layer 119 can be formed by a method similar to that for the insulating layer 118.

[0221] The above is a description of the modified example.

[0222] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0223] (Embodiment 2) In this embodiment, a structural example of a display panel in which the transistor described in Embodiment 1 can be used will be described.

[0224] [Configuration example] 9 shows a block diagram of the display panel 10. The display panel 10 includes a display section 11, a first drive circuit 12, and a second drive circuit 13.

[0225] A plurality of pixels PIX are arranged in a matrix on the display unit 11. Each pixel includes at least one display element and one transistor. The display element can typically be an organic EL element or a liquid crystal element.

[0226] The first driver circuit 12 includes a circuit that functions as a source driver. The first driver circuit 12 has a function of generating a gray scale signal based on a video signal input from the outside and supplying the gray scale signal to the pixels of the display unit 11.

[0227] The second driver circuit 13 includes a circuit that functions as a gate driver. The second driver circuit 13 has a function of generating a selection signal based on a signal input from the outside and supplying the selection signal to the pixels of the display unit 11.

[0228] The pixel PIX in the display unit 11 and the second driver circuit 13 can be configured using the transistor 100 or the like described in Embodiment 1. The first driver circuit 12 can be configured using the transistor 200 or the like described in Embodiment 1. Note that the pixel PIX and the second driver circuit 13 can be configured using the transistor 200 or the like, or the first driver circuit 12 can be configured using the transistor 100, as needed.

[0229] The display section 11 is also provided with a plurality of source lines SL connected to a first drive circuit 12 and a plurality of gate lines GL connected to a second drive circuit 13 .

[0230] [Configuration example of first drive circuit] A more specific example of the configuration of the first drive circuit 12 included in the display panel 10 will be described below.

[0231] The first drive circuit 12 includes a shift register circuit 31, a latch circuit section 41, a level shifter circuit section 42, a DA conversion section 43, an analog buffer circuit section 44, and the like.

[0232] The latch circuit section 41 has a plurality of latch circuits 32 and a plurality of latch circuits 33. The level shifter circuit section 42 has a plurality of level shifter circuits 34. The DA conversion section 43 has a plurality of DAC circuits 35. The analog buffer circuit section 44 has a plurality of analog buffer circuits 36.

[0233] A clock signal CLK and a start pulse signal SP are input to the shift register circuit 31. The shift register circuit 31 generates a timing signal for sequentially shifting pulses in accordance with the clock signal CLK and the start pulse signal SP, and outputs the timing signal to each latch circuit 32 in the latch circuit section 41.

[0234] The latch circuit section 41 receives the video signal S0 and the latch signal LAT.

[0235] When a timing signal is input to the latch circuits 32, the video signal S0 is sampled in accordance with the pulse signal included in the timing signal and written sequentially into each latch circuit 32. At this time, the period until the video signal S0 has been written into all of the latch circuits 32 can be called a line period.

[0236] When one line period is completed, the video signals held in each latch circuit 32 are simultaneously written into and held in each latch circuit 33 in accordance with the pulse of the latch signal LAT input to each latch circuit 33. After sending out the video signal to the latch circuit 33, the latch circuit 32 sequentially writes the next video signal in accordance with the timing signal from the shift register circuit 31 again. During this second one line period, the video signals written into and held in the latch circuit 33 are output to each level shifter circuit 34 of the level shifter circuit section 42.

[0237] The video signals input to each level shifter circuit 34 of the level shifter circuit section 42 have their voltage amplitudes amplified by the level shifter circuits 34, and are then sent to each DAC circuit 35 in the DA conversion section 43. The group of video signals input to the DAC circuits 35 are converted to analog and output as a single analog signal to the analog buffer circuit section 44. The video signals input to the analog buffer circuit section 44 are output to each source line SL via each analog buffer circuit 36.

[0238] On the other hand, the second drive circuit 13 sequentially selects each gate line GL. A video signal input from the first drive circuit 12 to the display unit 11 via the source line SL is input to each pixel PIX connected to the gate line GL selected by the second drive circuit 13.

[0239] Instead of the shift register circuit 31, other circuits capable of outputting signals in which pulses are shifted sequentially may be used.

[0240] [Modification of the first driving circuit] The first driving circuit 12 illustrated in FIG. 9 is configured to convert a digital signal into an analog signal and output it to the display unit 11, but by using an analog signal as the input signal, the configuration of the first driving circuit 12 can be further simplified.

[0241] 10A includes a shift register circuit 31, a latch circuit portion 41, and a source follower circuit portion 45. The source follower circuit portion 45 includes a plurality of source follower circuits 37.

[0242] The latch circuit 32 samples the analog video signal S0 as analog data in accordance with the timing signal from the shift register circuit 31. Furthermore, each latch circuit 32 simultaneously outputs the video signal held in each latch circuit 33 in accordance with the latch signal LAT.

[0243] The video signal held in the latch circuit 33 is output to one source line SL via a source follower circuit 37. Note that the source follower circuit 37 may be replaced by the analog buffer circuit described above.

[0244] The first driving circuit 12b shown in FIG. 10(B) includes a shift register circuit 31 and a demultiplexer circuit .

[0245] The demultiplexer circuit 46 has a plurality of sampling circuits 38. A plurality of analog video signals S0 are input to each sampling circuit 38 from a plurality of wirings, and the sampling circuits 38 simultaneously output the video signals to a plurality of source lines SL in accordance with a timing signal input from the shift register circuit 31. The shift register circuit 31 outputs a timing signal so as to sequentially select the plurality of sampling circuits 38.

[0246] For example, if the number of source lines SL connected to the display unit 11 is 2160 and the number of wirings through which the video signal S0 is supplied is 54, by providing 40 sampling circuits 38 in the demultiplexer circuit 46, one line period can be divided into 40 parts, and video signals can be output simultaneously to 54 source lines SL within each period.

[0247] This concludes the description of the first driving circuit.

[0248] [Example of display configuration] The display section 11 can be configured to have at least one display element and a plurality of pixels PIX, each having one transistor, arranged in a matrix.

[0249] Fig. 11 shows an example of a circuit diagram of a display unit 11 in which light-emitting elements are used as display elements. m (m is an integer of 2 or more) gate lines GL and n (n is an integer of 2 or more) source lines SL are connected to the display unit 11 shown in Fig. 11.

[0250] Each pixel PIX included in the display unit 11 includes a transistor 51, a transistor 52, a capacitor 53, and a light-emitting element 54. The pixel PIX is connected to a source line SL, a gate line GL, and wirings VL1 and VL2 to which a power supply potential is supplied.

[0251] The transistor 51 and the transistor 52 can be the transistor 100 or the like described in Embodiment 1. Note that the transistor 200 or the like described in Embodiment 1 may be used as one of the transistors 51 and 52 as needed.

[0252] The transistor 51 has a gate connected to the gate line GL, one of its source and drain connected to the source line SL, and the other connected to one electrode of the capacitor 53 and the gate of the transistor 52. The transistor 52 has one of its source and drain connected to one electrode of the light-emitting element 54, and the other connected to a wiring VL1. The capacitor 53 has the other electrode connected to a wiring VL1. The light-emitting element 54 has the other electrode connected to a wiring VL2.

[0253] The pixel PIX is selected by a signal supplied from the gate line GL. The luminance of the light-emitting element 54 can be controlled by controlling the current flowing through the light-emitting element 54 using a potential written from the source line SL to a node connected to the gate of the transistor 52 via the transistor 51.

[0254] An organic electroluminescence element (also referred to as an organic EL element) or the like can be typically used as the light-emitting element 54. However, the light-emitting element 54 is not limited to this, and an inorganic EL element containing an inorganic material, a light-emitting diode, or the like may also be used.

[0255] The above is a description of an example of the configuration of the display unit.

[0256] [Example of light-emitting element configuration] An example of the configuration of the display panel and the light-emitting element will be described below.

[0257] 12A shows a schematic top view of a display device 240 of one embodiment of the present invention. The display device 240 includes a plurality of red light-emitting elements 250R, a plurality of green light-emitting elements 250G, and a plurality of blue light-emitting elements 250B. In FIG. 12A, the light-emitting regions of the light-emitting elements are labeled with R, G, and B to easily distinguish the light-emitting elements from one another.

[0258] The light emitting elements 250R, 250G, and 250B are arranged in a matrix. Fig. 12(A) shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement of the light emitting elements is not limited to this, and arrangements such as a delta arrangement or a zigzag arrangement may also be used, or a pentile arrangement may also be used.

[0259] It is preferable to use EL elements such as OLEDs (Organic Light Emitting Diodes) or QLEDs (Quantum-dot Light Emitting Diodes) as light-emitting elements 250R, 250G, and 250B. Examples of light-emitting materials that the EL elements have include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (quantum dot materials, etc.).

[0260] FIG. 12(B) is a schematic cross-sectional view corresponding to the dashed dotted line A1-A2 in FIG. 12(A).

[0261] 12B shows cross sections of the light emitting element 250R, the light emitting element 250G, and the light emitting element 250B. The light emitting element 250R, the light emitting element 250G, and the light emitting element 250B are each provided on a substrate 251, and have a pixel electrode 261 and a common electrode 263.

[0262] The light-emitting element 250R has an EL layer 262R between the pixel electrode 261 and the common electrode 263. The EL layer 262R contains a light-emitting organic compound that emits light having an intensity at least in the red wavelength range. The EL layer 262G of the light-emitting element 250G contains a light-emitting organic compound that emits light having an intensity at least in the green wavelength range. The EL layer 262B of the light-emitting element 250B contains a light-emitting organic compound that emits light having an intensity at least in the blue wavelength range.

[0263] The EL layer 262R, the EL layer 262G, and the EL layer 262B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0264] The pixel electrode 261 is provided for each light-emitting element. The common electrode 263 is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the pixel electrode 261 or the common electrode 263, and a conductive film that is reflective is used for the other. By making the pixel electrode 261 transparent and the common electrode 263 reflective, a bottom-emission display device can be obtained. Conversely, by making the pixel electrode 261 reflective and the common electrode 263 transparent, a top-emission display device can be obtained. Note that by making both the pixel electrode 261 and the common electrode 263 transparent, a dual-emission display device can also be obtained.

[0265] An insulating layer 272 is provided to cover the edge of the pixel electrode 261. The edge of the insulating layer 272 is preferably tapered.

[0266] The EL layer 262R, the EL layer 262G, and the EL layer 262B each have a region in contact with the upper surface of the pixel electrode 261 and a region in contact with the surface of the insulating layer 272. In addition, the ends of the EL layer 262R, the EL layer 262G, and the EL layer 262B are located on the insulating layer 272.

[0267] As shown in Figure 12(B), a gap is provided between two EL layers between light-emitting elements of different colors. In this way, it is preferable that the EL layer 262R, the EL layer 262G, and the EL layer 262B are provided so as not to be in contact with each other. This makes it possible to preferably prevent current from flowing through two adjacent EL layers and causing unintended light emission (also known as crosstalk). This makes it possible to improve contrast and realize a display device with high display quality.

[0268] The EL layer 262R, the EL layer 262G, and the EL layer 262B can be separately fabricated by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they may be separately fabricated by photolithography. By using photolithography, it is possible to realize a high-definition display device that is difficult to achieve using a metal mask.

[0269] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0270] Furthermore, a protective layer 271 is provided on the common electrode 263 to cover the light emitting elements 250R, 250G, and 250B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above into each light emitting element.

[0271] The protective layer 271 may have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 271 may be made of a semiconductor material such as indium gallium oxide or indium gallium zinc oxide.

[0272] FIG. 12(C) shows an example different from the above.

[0273] 12C, a light-emitting element 250W that emits white light is provided. The light-emitting element 250W has an EL layer 262W that emits white light between the pixel electrode and the common electrode 263.

[0274] The EL layer 262W may be configured by stacking two or more light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.

[0275] 12(C) shows three light-emitting elements 250W lined up. A colored layer 264R is provided on the top of the left light-emitting element 250W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 250W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 250W. This allows the display device to display color images.

[0276] Here, the EL layer 262W and the common electrode 263 are separated between two adjacent light-emitting elements 250W. This effectively prevents current from flowing through the EL layer 262W between the two adjacent light-emitting elements 250W, resulting in unintended light emission. In particular, when a stacked EL layer in which a charge-generating layer is provided between two light-emitting layers is used as the EL layer 262W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using such a configuration, a display device that combines high resolution and high contrast can be realized.

[0277] The EL layer 262W and the common electrode 263 are preferably separated by photolithography, which allows the distance between the light-emitting elements to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0278] In the case of a bottom emission type light emitting element, a colored layer may be provided between the pixel electrode 261 and the substrate 251 .

[0279] The above is the description of the light emitting element.

[0280] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0281] (Embodiment 3) In this embodiment, a structural example of a display device that can be manufactured using a transistor of one embodiment of the present invention will be described.

[0282] 13A is a schematic top view of a display device 700. The display device 700 includes a flexible substrate 762. The substrate 762 is provided with a display portion 702, a pair of circuit portions 763, a circuit portion 764, wiring 704, and connection terminals 703a and 703b.

[0283] The circuit portion 763 and the circuit portion 764 have a function of driving the display portion 702. Two circuit portions 763 are provided with the display portion 702 sandwiched therebetween. The circuit portion 764 is provided between the display portion 702 and the wiring 704. The circuit portion 763 has a function as, for example, a gate driver, and the circuit portion 764 has a function as, for example, a source driver or a part thereof. For example, the circuit portion 764 may include a buffer circuit or a demultiplexer circuit.

[0284] The various display elements described above, such as a liquid crystal element or a light-emitting element, can be used as the display element provided in the display unit 702. In particular, it is preferable to use an organic EL element as the display element.

[0285] The substrate 762 has a top surface shape in which a portion where the wiring 704, the connection terminal 703a, and the connection terminal 703b are provided protrudes more than other portions. In other words, the width of the portion of the substrate 762 where the wiring 704, the connection terminal 703a, and the connection terminal 703b are provided is smaller than the width of a portion where the display portion 702 is provided.

[0286] The protruding portion of the substrate 762 has a region (curved portion 761a) that can be curved in a region overlapping with the wiring 704. The substrate 762 also has a pair of regions (curved portion 761b) that can be curved in a region where the display portion 702 is provided. As shown in FIG. 13A, the protruding shape of part of the substrate 762 allows the curved direction of the curved portion 761a and the curved direction of the curved portion 761b to intersect.

[0287] The connection terminal 703a functions as a terminal to which an FPC (Flexible Printed Circuit) is connected, and the connection terminal 703b functions as a terminal to which an IC is connected.

[0288] 13(B) and 13(C) are perspective views of the display device 700 when the substrate 762 is bent on the side opposite the display surface side at the curved portions 761a and 761b. Fig. 13(B) is a perspective view including the display surface side, and Fig. 13(C) is a perspective view including the side opposite the display surface side. Fig. 13(C) also clearly shows the FPC 706 connected to the connection terminal 703a and the IC 707 connected to the connection terminal 703b.

[0289] 13B, by bending both sides of the display portion 702, curved display portions can be provided on both sides of the electronic device when the display device 700 is incorporated into the electronic device, thereby realizing an electronic device with high functionality.

[0290] 13(B) and 13(C), the curved portion 761a allows a portion of the substrate 762 to be folded back to the side opposite the display surface side. Specifically, the protruding portion of the substrate 762 can be folded back so that the wiring 704 faces outward. This allows the connection terminals 703a and 703b to be disposed on the side opposite the display surface side, and further allows the FPC 706 to be disposed on the side opposite the display surface side. This makes it possible to reduce the area of ​​the non-display portion when the display device 700 is incorporated into an electronic device.

[0291] The substrate 762 is also provided with a notch 765. The notch 765 is a portion where, for example, a camera lens, various sensors such as an optical sensor, a lighting device, or a design element of the electronic device can be placed. By cutting out a portion of the display unit 702, an electronic device with a more sophisticated design can be realized. This also increases the occupancy rate of the screen relative to the surface of the housing.

[0292] [Cross-section example] An example of the cross-sectional configuration of the display device will be described below.

[0293] [Configuration example 1] 14 is a schematic cross-sectional view of a display device 700. FIG. 14 shows a cross section including the display portion 702, the circuit portion 763, the circuit portion 764, and the connection terminal 703a of the display device 700 shown in FIG. 13(A). The display portion 702 is provided with a transistor 750 and a capacitor 790. The circuit portion 763 is provided with a transistor 752. The circuit portion 764 is provided with a transistor 754.

[0294] The transistor 750 and the transistor 752 can be the transistor 100 or the like described in Embodiment 1. The transistor 754 can be the transistor 200 or the like described in Embodiment 1.

[0295] The transistor used in this embodiment includes a highly purified oxide semiconductor layer in which the formation of oxygen vacancies is suppressed. The off-state current of the transistor can be significantly reduced. Therefore, a pixel including such a transistor can hold an electric signal such as an image signal for a long time and can set a long interval between writing of the image signal or the like. Therefore, the frequency of a refresh operation can be reduced, leading to reduced power consumption.

[0296] Furthermore, the transistor used in this embodiment can be driven at high speed because it has relatively high field-effect mobility. For example, by using such a transistor capable of high-speed driving in a display device, a pixel switching transistor and a driver transistor used in a circuit portion can be formed over the same substrate. That is, a configuration without using a driver circuit formed using a silicon wafer or the like is possible, and the number of components in the display device can be reduced. Furthermore, by using a transistor capable of high-speed driving in a pixel, a high-quality image can be provided.

[0297] The capacitor 790 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide film as the semiconductor layer. The upper electrode has low resistance, similar to the source and drain regions of the transistor 750. A part of an insulating film functioning as the first gate insulating layer of the transistor 750 is provided between the lower and upper electrodes. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes. The upper electrode is connected to wiring obtained by processing the same film as the source and drain electrodes of the transistor 750.

[0298] An insulating layer 770 functioning as a planarization film is provided over the transistor 750, the transistor 752, the transistor 754, and the capacitor 790.

[0299] The transistor 750 in the display portion 702, the transistor 752 in the circuit portion 763, and the transistor 754 in the circuit portion 764 may have different structures. For example, a top-gate transistor may be used in one of the portions, and a bottom-gate transistor may be used in the other portion.

[0300] Note that the structures of the transistors 750, 752, and 754 can be those described in Embodiment 1.

[0301] The connection terminal 703a has a part of the wiring 704. The connection terminal 703a is electrically connected to the FPC 706 via a connection layer 780. The connection layer 780 may be made of, for example, an anisotropic conductive material.

[0302] The display device 700 includes a substrate 762 and a substrate 740, each of which functions as a support substrate. As the substrate 762 and the substrate 740, for example, a flexible substrate such as a glass substrate or a plastic substrate can be used.

[0303] The transistor 750, the transistor 752, the transistor 754, the capacitor 790, and the like are provided over an insulating layer 744. The substrate 762 and the insulating layer 744 are attached to each other with an adhesive layer 742.

[0304] The display device 700 also includes a light-emitting element 782, a colored layer 736, a light-shielding layer 738, and the like.

[0305] The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive layer 788. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is provided over the insulating layer 770 and functions as a pixel electrode. An insulating layer 730 is provided to cover an end portion of the conductive layer 772, and the EL layer 786 and the conductive layer 788 are stacked over the insulating layer 730 and the conductive layer 772.

[0306] The conductive layer 772 can be formed using a material that reflects visible light. For example, a material containing aluminum, silver, or the like can be used. The conductive layer 788 can be formed using a material that transmits visible light. For example, an oxide material containing indium, zinc, tin, or the like can be used. Therefore, the light-emitting element 782 is a top-emission light-emitting element that emits light to the opposite side from the surface where it is formed (the substrate 740 side).

[0307] The EL layer 786 includes organic compounds or inorganic compounds such as quantum dots, etc. The EL layer 786 includes a light-emitting material that emits light when a current is passed through it.

[0308] Examples of luminescent materials include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, inorganic compounds (quantum dot materials, etc.), etc. Examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, and core-type quantum dot materials.

[0309] The light-shielding layer 738 and the coloring layer 736 are provided on one surface of the insulating layer 746. The coloring layer 736 is provided at a position overlapping with the light-emitting element 782. The light-shielding layer 738 is provided in a region of the display portion 702 that does not overlap with the light-emitting element 782. The light-shielding layer 738 may also be provided to overlap with the circuit portion 763 and the like.

[0310] The substrate 740 is bonded to the other surface of the insulating layer 746 by an adhesive layer 747. The substrate 740 and the substrate 762 are bonded to each other by a sealing layer 732.

[0311] Here, a light-emitting material that emits white light is used for the EL layer 786 of the light-emitting element 782. The white light emitted by the light-emitting element 782 is colored by the coloring layer 736 and emitted to the outside. The EL layer 786 is provided across pixels that exhibit different colors. By arranging pixels, each provided with a coloring layer 736 that transmits any of red (R), green (G), and blue (B), in a matrix in the display portion 702, the display device 700 can display full colors.

[0312] Also, this example shows an example in which a part of the EL layer 786 is divided, which makes it possible to suitably suppress unintended light emission caused by a current flowing between adjacent pixels via the EL layer 786.

[0313] Alternatively, a conductive film having transparency and reflectivity may be used as the conductive layer 788. In this case, a microresonator (microcavity) structure may be realized between the conductive layer 772 and the conductive layer 788, so that light of a specific wavelength can be intensified and emitted. In this case, an optical adjustment layer for adjusting the optical distance may be disposed between the conductive layer 772 and the conductive layer 788, and the thickness of the optical adjustment layer may be made different between pixels of different colors, thereby increasing the color purity of the light emitted from each pixel.

[0314] When the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, when it is formed by coloring, the colored layer 736 and the optical adjustment layer described above may not be provided.

[0315] Here, an inorganic insulating film functioning as a barrier film with low moisture permeability is preferably used for each of the insulating layers 744 and 746. By sandwiching the light-emitting element 782, the transistor 750, and the like between the insulating layer 744 and the insulating layer 746, deterioration of the light-emitting element 782, the transistor 750, and the like can be suppressed, and a highly reliable display device can be realized.

[0316] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0317] (Fourth embodiment) In this embodiment, an example of a head-mounted display to which a display device is applied will be described as an example of an electronic device of one embodiment of the present invention.

[0318] 15(A) and 15(B) show the appearance of the head mounted display 8300.

[0319] The head mounted display 8300 includes a housing 8301, a display portion 8302, operation buttons 8303, and a band-shaped fixture 8304.

[0320] The operation button 8303 has a function of a power button, etc. In addition to the operation button 8303, other buttons may be provided.

[0321] 15(C), a lens 8305 may be provided between the display portion 8302 and the user's eyes. The lens 8305 allows the user to enlarge the display portion 8302, thereby enhancing the sense of realism. In this case, a dial 8306 may be provided to change the position of the lens for adjusting the diopter, as shown in FIG.

[0322] The display device of one embodiment of the present invention can be applied to the display portion 8302. The display device of one embodiment of the present invention has extremely high resolution; therefore, even when an image is enlarged using a lens 8305 as in FIG. 15C, pixels are not visible to a user, and more realistic images can be displayed.

[0323] 15A to 15C show an example in which one display portion 8302 is included. With such a configuration, the number of components can be reduced.

[0324] The display portion 8302 can display two images, one for the right eye and one for the left eye, side by side in two regions, left and right, respectively, thereby enabling display of a stereoscopic image using binocular parallax.

[0325] Alternatively, a single image that can be viewed with both eyes may be displayed across the entire area of ​​the display unit 8302. This allows a panoramic image to be displayed across both ends of the field of view, thereby enhancing the sense of reality.

[0326] Here, the head mounted display 8300 preferably has a mechanism for changing the curvature of the display portion 8302 to an appropriate value depending on the size of the user's head, the position of the user's eyes, etc. For example, the user may adjust the curvature of the display portion 8302 by operating a dial 8307 for adjusting the curvature of the display portion 8302. Alternatively, the housing 8301 may be provided with a sensor (for example, a camera, a contact sensor, a non-contact sensor, etc.) that detects the size of the user's head, the position of the user's eyes, etc., and the head mounted display 8300 may have a mechanism for adjusting the curvature of the display portion 8302 based on the detection data of the sensor.

[0327] When the lens 8305 is used, it is preferable to provide a mechanism for adjusting the position and angle of the lens 8305 in synchronization with the curvature of the display portion 8302. Alternatively, the dial 8306 may have a function for adjusting the angle of the lens.

[0328] 15E and 15F show an example in which a driver 8308 that controls the curvature of the display portion 8302 is provided. The driver 8308 is fixed to at least a part of the display portion 8302. The driver 8308 has a function of deforming the display portion 8302 by deforming or moving a part fixed to the display portion 8302.

[0329] 15(E) is a schematic diagram showing a case where a user 8310 with a relatively large head size is wearing the housing 8301. In this case, the shape of the display portion 8302 is adjusted by a driving portion 8308 so that the curvature is relatively small (the radius of curvature is large).

[0330] On the other hand, Fig. 15(F) shows a case where a user 8311, whose head is smaller than that of the user 8310, wears the housing 8301. The user 8311 has a smaller eye distance than the user 8310. In this case, the shape of the display unit 8302 is adjusted by the driving unit 8308 so that the curvature of the display unit 8302 is larger (the radius of curvature is smaller). In Fig. 15(F), the position and shape of the display unit 8302 in Fig. 15(E) are indicated by dashed lines.

[0331] In this way, the head mounted display 8300 has a mechanism for adjusting the curvature of the display portion 8302, and can provide an optimal display to various users, regardless of age or gender.

[0332] Furthermore, by changing the curvature of the display portion 8302 depending on the content displayed on the display portion 8302, a high sense of realism can be given to the user. For example, by vibrating the curvature of the display portion 8302, it is possible to express shaking. In this way, various effects can be produced according to the scene in the content, and a new experience can be provided to the user. Furthermore, by linking this with a vibration module provided in the housing 8301, a more realistic display can be achieved.

[0333] Note that the head mounted display 8300 may have two display portions 8302 as shown in FIG.

[0334] By having two display units 8302, the user can view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. Furthermore, the display unit 8302 is curved in an arc shape roughly centered on the user's eye. This allows the distance from the user's eye to the display surface of the display unit to be constant, allowing the user to view more natural images. Furthermore, even if the brightness and chromaticity of light from the display unit change depending on the viewing angle, this effect can be substantially ignored because the user's eyes are positioned in the normal direction to the display surface of the display unit, allowing for the display of more realistic images.

[0335] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0336] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

[0337] A display module 6000 shown in FIG. 16A includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0338] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0339] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0340] The display device 6006 may have a function as a touch panel.

[0341] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0342] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, and the like.

[0343] FIG. 16(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor.

[0344] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0345] The display device 6006 is provided so as to overlap the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide portions 6017a and 6017b.

[0346] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and reaches light-receiving unit 6016 through light-guiding unit 6017b. When light 6018 is blocked by a detectable object such as a finger or a stylus, a touch operation can be detected.

[0347] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0348] The light-emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light-receiving unit 6016 may be a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode that can receive infrared light may be used.

[0349] The light guiding portions 6017a and 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0350] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0351] (Sixth embodiment) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0352] An electronic device 6500 shown in FIG. 17A is a portable information terminal that can be used as a smartphone.

[0353] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0354] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0355] FIG. 17B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0356] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0357] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0358] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0359] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0360] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0361] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described.

[0362] The electronic devices exemplified below each include a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices can achieve high resolution. Furthermore, the electronic devices can also have both high resolution and a large screen.

[0363] One embodiment of the present invention includes a display device and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0364] The electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0365] Examples of secondary batteries include lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) that use a gel electrolyte, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0366] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0367] The display portion of the electronic device of one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0368] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0369] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a building such as a house or a building, or the interior or exterior of a car or the like.

[0370] FIG. 18A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0371] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached thereto.

[0372] The camera 8000 may have the lens 8006 and the housing integrated together.

[0373] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0374] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0375] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0376] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0377] The button 8103 has a function such as a power button.

[0378] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0379] FIG. 18B is a diagram showing the appearance of the head mounted display 8200.

[0380] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0381] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0382] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user, capable of detecting a current that flows in accordance with the movement of the user's eyeballs. The wearing unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors, such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may also have a function of displaying the user's biological information on the display unit 8204 and a function of changing the image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0383] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0384] 18(C), 18(D), and 18(E) are diagrams showing the appearance of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0385] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0386] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has extremely high definition, and therefore, even when an image is enlarged using the lens 8305 as in FIG. 18(E), pixels are not visible to a user, and a more realistic image can be displayed.

[0387] The electronic devices shown in Figures 19(A) to 19(G) include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0388] 19(A) to 19(G) have various functions. For example, they may have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing using various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function of providing a camera or the like to capture still images or videos and store them in a recording medium (external or built-in to the camera), a function of displaying the captured images on the display unit, etc.

[0389] The electronic devices shown in FIGS. 19A to 19G will be described in detail below.

[0390] 19A is a perspective view of a television set 9100. The television set 9100 can incorporate a display portion 9001 with a large screen, for example, 50 inches or more, or 100 inches or more.

[0391] FIG. 19B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text, image information, and the like on multiple surfaces thereof. FIG. 19B shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, and the like, the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and the strength of antenna reception. Alternatively, the icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0392] 19C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0393] 19(D) is a perspective view showing a wristwatch-type mobile information terminal 9200. The display surface of the display portion 9001 is curved, and a display can be displayed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and reception with another information terminal or charge the mobile information terminal 9200 through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0394] 19(E), 19(F), and 19(G) are perspective views showing a foldable mobile information terminal 9201. FIG. 19(E) shows the mobile information terminal 9201 in an unfolded state, FIG. 19(G) shows it in a folded state, and FIG. 19(F) is a perspective view showing a state in the process of changing from one of FIG. 19(E) and FIG. 19(G) to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display. A display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0395] 20A shows an example of a television set. A television set 7100 includes a display portion 7500 built in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0396] 20A can be operated using operation switches provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch panel may be applied to the display portion 7500, and the television set 7100 may be operated by touching the touch panel. The remote control 7111 may have a display portion in addition to operation buttons.

[0397] The television device 7100 may also include a television broadcast receiver or a communication device for network connection.

[0398] 20B shows a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

[0399] 20(C) and 20(D) show an example of a digital signage.

[0400] 20C includes a housing 7301, a display portion 7500, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0401] 20D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0402] The larger the display unit 7500, the more information can be provided at one time, and the larger the display unit 7500 is, the more easily it will catch people's attention, which will have the effect of increasing the advertising effectiveness of advertisements, for example.

[0403] It is preferable that a touch panel be applied to the display unit 7500 so that the user can operate it. This allows the display unit 7500 to be used not only for advertising purposes but also for providing information desired by the user, such as route information, traffic information, or guidance information for commercial facilities.

[0404] 20C and 20D, the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311. Furthermore, by operating the information terminal 7311, the display on the display unit 7500 can be switched.

[0405] Furthermore, a game using the information terminal device 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. This allows an unspecified number of users to simultaneously participate in and enjoy the game.

[0406] The display device of one embodiment of the present invention can be applied to the display portion 7500 in FIGS.

[0407] Although the electronic devices in this embodiment have a display portion, one embodiment of the present invention can also be applied to electronic devices that do not have a display portion.

[0408] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0409] 10: Display panel 11: Display unit 12, 12a, 12b: First drive circuit 13: Second drive circuit 31: Shift register circuit 32, 33: Latch circuit 34: Level shifter circuit 35: DAC circuit 36: Analog buffer circuit 37: Source follower circuit 38: Sampling circuit 41: Latch circuit unit 42: Level shifter circuit unit 43: DA conversion unit 44: Analog buffer circuit unit 45: Source follower circuit unit 46: Demultiplexer circuit 51, 52: Transistor 53: Capacitor element 54: Light-emitting element 100, 100A-D: Transistor 102: Substrate 103: Insulating layer 106: Conductive layer 108f: Metal oxide film 108n: Low resistance region 108: Semiconductor layer 110: Insulating layer 112f: Conductive film 112: Conductive layer 114f: metal oxide film 114: metal oxide layer 118: insulating layer 119: insulating layer 120a, 120b: conductive layer 130a, 130b: conductive layer 131f, 132f: metal film 131, 132: metal layer 135, 136: resist mask 140: impurity element 141a-d: opening 142a, 142b: opening 200: transistor, 200A-D: transistor 206: conductive layer 208f: metal oxide film 208n: low resistance region 208: semiconductor layer 212: conductive layer 214: metal oxide layer 220a, 220b: conductive layer 230a, 230b: conductive layer 240: display device 250W: light emitting element 251: substrate 250B: light emitting element 250G: light emitting element 250R: Light-emitting element 261: Pixel electrode 262R, 252G, 262B, 262W: EL layer 263: Common electrode 264R, 264G, 264B: Colored layer 271: Protective layer 272: Insulating layer

Claims

1. A method for manufacturing a display device including a first transistor including a first oxide semiconductor layer and a second transistor including a second oxide semiconductor layer, forming a first insulating layer on a first substrate; forming a first metal oxide film on the first insulating layer; forming a first metal film on the first metal oxide film; forming an island-shaped first resist mask on the first metal film; removing portions of the first metal film and the first metal oxide film that are not covered with the first resist mask to form an island-shaped first metal layer and an island-shaped first oxide semiconductor layer, and exposing a portion of an upper surface of the first insulating layer; removing the first resist mask; forming a second metal oxide film on the first metal layer and the first insulating layer; forming a second metal film on the second metal oxide film; forming an island-shaped second resist mask on the second metal film in a region not overlapping with the first metal film; removing portions of the second metal film and the second metal oxide film that are not covered with the second resist mask to form an island-shaped second metal layer and an island-shaped second oxide semiconductor layer; removing the second resist mask; removing the first metal layer and the second metal layer; A method for manufacturing a display device.

2. A method for manufacturing a display device including a first transistor including a first oxide semiconductor layer and a second transistor including a second oxide semiconductor layer, forming a first insulating layer on a first substrate; forming a first metal oxide film on the first insulating layer; forming a first metal film on the first metal oxide film; forming an island-shaped first resist mask on the first metal film; removing a portion of the first metal film that is not covered by the first resist mask to form an island-shaped first metal layer; removing the first resist mask; removing a portion of the first metal oxide film that is not covered with the first metal film to form the first oxide semiconductor layer in an island shape and to expose a portion of an upper surface of the first insulating layer; forming a second metal oxide film on the first metal layer and the first insulating layer; forming a second metal film on the second metal oxide film; forming an island-shaped second resist mask on the second metal film in a region not overlapping with the first metal film; removing a portion of the second metal film that is not covered by the second resist mask to form an island-shaped second metal layer; removing the second resist mask; removing a portion of the second metal oxide film that is not covered with the second metal film to form the second oxide semiconductor layer in an island shape; removing the first metal layer and the second metal layer; A method for manufacturing a display device.

3. In claim 1 or claim 2, the first metal oxide film contains indium, zinc, and gallium; the second metal oxide film contains indium; the second metal oxide film is formed so that the ratio of the number of indium atoms to the number of atoms of the contained metal element is larger than that of the first metal oxide film; A method for manufacturing a display device.

4. In claim 1 or claim 2, the second metal oxide film contains indium, zinc, and gallium; the first metal oxide film contains indium; the first metal oxide film is formed so that the ratio of the number of indium atoms to the number of atoms of the contained metal element is larger than that of the second metal oxide film; A method for manufacturing a display device.

5. In any one of claims 1 to 4, the first metal film is etched by a dry etching method, and the first metal oxide film is etched by a wet etching method; the second metal film is etched by a dry etching method, and the second metal oxide film is etched by a wet etching method; the first metal layer and the second metal layer are etched by a wet etching method; A method for manufacturing a display device.

6. In any one of claims 1 to 5, tungsten, molybdenum, or titanium is used for the first metal film and the second metal film; A method for manufacturing a display device.

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