Storage device, liquid ejection head, and liquid ejection device

Abstract

To achieve more appropriate writing of information in a storage.SOLUTION: A storage according to the present invention comprises: a memory unit that includes an anti-fuse element, and a resistance element connected in parallel to the anti-fuse element; an information writing section that writes information in the anti-fuse element by periodically adding a signal to the memory unit; and a control section that performs drive control of the information writing section. The control section changes the period of the signal output by the information writing section based on the value of current supplied to the memory unit.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates generally to storage devices. [Background technology]

[0002] Some electrical appliances are equipped with a storage device for storing product-specific information (see Patent Document 1). The storage device may use a memory element that can store information only once, a so-called OTP (One Time Programmable) memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-58130 Summary of the Invention [Problem to be solved by the invention]

[0004] As an example of an OTP memory, an anti-fuse element having a MOS structure is used, and in this case, information can be written by causing dielectric breakdown of the MOS structure. However, since differences in electrical characteristics can occur among multiple anti-fuse elements due to, for example, manufacturing variations, a technology for writing appropriate information that takes this into consideration is required.

[0005] The present invention was made in response to the inventor's recognition of the above-mentioned problems, and has an exemplary object to make it possible to realize more appropriate writing of information in a storage device. [Means for solving the problem]

[0006] One aspect of the present invention relates to a storage device, the storage device comprising: a memory unit including an antifuse element and a resistance element connected in parallel to the antifuse element; an information writing unit that writes information into the antifuse element by periodically applying a signal to the memory unit; a control unit that controls the driving of the information writing unit, The control unit changes the period of the signal output by the information writing unit based on the value of the current supplied to the memory unit. It is characterized by: [Effects of the Invention]

[0007] According to the present invention, it is possible to realize more appropriate writing of information in a storage device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram showing an example of the overall configuration of a liquid ejection device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a liquid ejection head. [Figure 3] FIG. 2 is a diagram showing an example of the configuration of a current detection unit. [Figure 4] 10 is a flowchart showing an example of a control method for an information writing unit. [Figure 5] 10 is a timing chart for writing information to a memory unit. [Figure 6] 10 shows another example of the configuration of the memory unit. [Figure 7] FIG. 2 is a diagram showing an example of the connection relationship between elements in a liquid ejection device. [Figure 8] FIG. 10 is a diagram showing another example of the connection relationship between elements in the liquid ejection device. [Figure 9] FIG. 10 is a diagram showing another example of the connection relationship between elements in the liquid ejection device. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] 1 is a schematic diagram showing an example of the overall configuration of a liquid ejection device 1 according to an embodiment. The liquid ejection device 1 includes a liquid ejection head 11, a carriage 12, and a head controller 13 for controlling the driving of these components.

[0011] The liquid ejection head 11 is provided with a plurality of nozzles (ejection ports) for ejecting liquid, and includes a head substrate on which a plurality of liquid ejection elements corresponding to the plurality of nozzles are provided. Ink is typically used as the liquid. The liquid ejection head 11 drives each liquid ejection element based on a drive signal or control signal from a head controller 13. This causes ink to be ejected from the corresponding nozzle, and desired printing is performed on a printing medium P, such as a sheet of paper. This type of printing mode may be referred to as an inkjet method.

[0012] The liquid ejection head 11 is mounted on a carriage 12, which can move back and forth in direction d1 along a guide 14 based on a drive signal or control signal from a head controller 13. The recording medium P is transported in direction d2 by a transport mechanism of the liquid ejection device 1, and during this transport, the liquid ejection head 11 can move back and forth in direction d1 by the carriage 12.

[0013] The head controller 13 controls the driving of the liquid ejection head 11 while reciprocating the carriage 12. This allows desired recording to be achieved on the recording medium P, forming, for example, characters, symbols, figures, photographs, etc.

[0014] The head controller 13 may be expressed as a head driver or the like. The liquid ejection head 11 may be expressed simply as an ejection head, or may be expressed as a recording head. In this embodiment, the liquid ejection head 11 may also be expressed as an inkjet head, a serial head, or the like. The liquid ejection device 1 may also be expressed simply as an ejection device, or may be expressed as a recording device. In this embodiment, the liquid ejection device 1 may also be expressed as an inkjet printer or the like.

[0015] 2 is a diagram showing an example of the configuration of a liquid ejection head 11. The liquid ejection head 11 includes a functional unit 2 for realizing its main function (here, a recording function), and a storage device 3 capable of storing predetermined information. The functional unit 2 and the storage device 3 may be provided on the same semiconductor substrate, or may be provided on separate semiconductor substrates, or may be partially provided on the same semiconductor substrate.

[0016] In this embodiment, the functional unit 2 includes a plurality of liquid ejection elements 21 and an element driver 22 capable of driving the liquid ejection elements individually. The liquid ejection elements 21 may be simply referred to as ejection elements, or may be referred to as recording elements or the like. The liquid ejection elements 21 are typically heater elements or electrothermal conversion elements, but other elements such as piezoelectric elements may also be used. Although not described here, the functional unit 2 may be configured to be drivable by a known method; for example, the plurality of liquid ejection elements 21 may be divided into several blocks and driven in block units (using a so-called time-division driving method).

[0017] The storage device 3 is capable of storing information specific to the liquid ejection head 11. Examples of the specific information include an identifier, a serial number, and specific parameters. The storage device 3 includes a plurality of memory units 31 and a plurality of information writing units 32. The memory unit 31 includes an anti-fuse element 311, a switch element 312, and protection elements 313a and 313b.

[0018] The antifuse element 311 is a memory element that can store information only once, i.e., it is a memory element that cannot be rewritten, and functions as a so-called OTP (One Time Programmable) memory. In this embodiment, a MOS (Metal Oxide Semiconductor) structure is used for the antifuse element 311. This MOS structure shows a state in which no information is written before dielectric breakdown, and a state in which information is written after dielectric breakdown.

[0019] A known high-voltage transistor such as a DMOS (Double-Diffused MOS) transistor may be used for the switch element 312. The switch element 312 is turned on or off based on a signal from the information writing unit 32. When the switch element 312 is turned on, a voltage VHT is supplied to the anti-fuse element 311, and when the switch element 312 is turned off, the supply is suppressed.

[0020] As will be described in detail later, the switch element 312 is periodically driven, and thereby the voltage VHT is periodically supplied to the anti-fuse element 311. This causes dielectric breakdown of the MOS structure of the anti-fuse element 311, and information is written to the anti-fuse element 311. Note that writing of information may be expressed as writing of information to the memory unit 31 or as writing of information to the storage device 3.

[0021] The protection element 313a is connected in parallel to the anti-fuse element 311, and a resistive element (e.g., 80 kΩ (kiloohms)) may be used for the protection element 313a. The protection element 313b is connected in series to the anti-fuse element 311, and a resistive element (e.g., 1 kΩ) may be used for the protection element 313b. With this configuration, if an unexpected overvoltage such as ESD (electrostatic discharge) is applied to the power supply line of the power supply voltage VHT, the overvoltage can be guided to the other protection element 313c connected to that power supply line. This makes it possible to prevent unexpected writing of information to the anti-fuse element 311 due to the overvoltage.

[0022] The information writing unit 32 is a logic circuit provided corresponding to each memory unit 31, and in this embodiment is an AND circuit. A voltage VHTM generated from the voltage VHT via a step-down circuit 39 can be supplied to the information writing unit 32.

[0023] Here, the information writing unit 32 periodically applies a signal to the memory unit 31 based on a signal from the control unit 91, thereby writing information to the anti-fuse element 311. By periodically applying a signal to the memory unit 31, a large current from the parasitic capacitance is periodically supplied to the anti-fuse element 311, thereby making it possible to relatively quickly write information to the anti-fuse element 311. More specifically, the state of the MOS structure after dielectric breakdown includes a state in which dielectric breakdown has occurred sufficiently (a so-called hard breakdown state) and a state in which dielectric breakdown has occurred partially (a so-called soft breakdown state). Then, by periodically applying a signal to the memory unit 31, the electrical energy required to change the MOS structure from a state before dielectric breakdown to a hard breakdown state via a soft breakdown state can be appropriately supplied to the MOS structure.

[0024] The information writing unit 32 may be expressed as an information writing control unit, or simply as a writing control unit, or may be expressed as an information writing execution unit, or simply as a writing execution unit.

[0025] Here, a current detection unit 90 is connected to the memory unit 31 to detect the value of the current supplied to the memory unit 31. In this embodiment, the current detection unit 90 is arranged between the power supply line of the voltage VHT and the memory unit 31.

[0026] FIG. 3 shows an example of the configuration of the current detection unit 90. The current detection unit 90 includes a resistor element 901 as a current detection element, an amplifier OP0, and comparators CP0 and CP1. The resistor element 901 is disposed between the power supply line of the voltage VHT and the protection element 313b, and has a resistance value of, for example, 1 Ω. The amplifier OP0 amplifies the potential difference generated in the resistor element 901 and outputs the resulting output voltage Vdet to each of the comparators CP0 and CP1. The comparator CP0 compares the output voltage Vdet of the amplifier OP0 with a reference voltage Vref0 and outputs the comparison result as a signal ST0. The comparator CP1 compares the output voltage Vdet of the amplifier OP0 with a reference voltage Vref1 (>Vref0) and outputs the comparison result as a signal ST1.

[0027] Here, a resistive element having a relatively high resistance value is used for the protection element 313a connected in parallel with the anti-fuse element 311. Before information is written to the anti-fuse element 311 (before dielectric breakdown of the MOS structure), the anti-fuse element 311 is in a high impedance state, so a minute current can be supplied to the memory unit 31. Therefore, the potential difference that can occur across the resistive element 901 is relatively small, and the output voltage Vdet of the amplifier OP0 is relatively small.

[0028] On the other hand, after information is written to the anti-fuse element 311 (after the dielectric breakdown of the MOS structure), the anti-fuse element 311 is in a short-circuit state, and therefore a large current may be supplied to the memory unit 31. Therefore, the potential difference that may occur across the resistance element 901 increases, and accordingly the output voltage Vdet of the amplifier OP0 increases.

[0029] For the reference voltages Vref0 and Vref1, values that can identify the state of the MOS structure of the anti-fuse element 311 (such as before or after dielectric breakdown, etc.) may be set. As an example, when VHT = 24V, Vref0 = 0.326 mV (millivolt) can be set as the reference voltage for identifying whether the MOS structure is in a state before dielectric breakdown or in a soft breakdown state. Also, Vref1 = 2.9 mV can be set as the reference voltage for identifying whether the MOS structure is in a soft breakdown state or a hard breakdown state.

[0030] According to such a configuration, between Vdet < Vref0, the signals ST0 and ST1 become the L level (low level). Between Vref0 ≤ Vdet < Vref1, the signal ST0 becomes the H level (high level) and the signal ST1 becomes the L level. Also, between Vdet ≥ Vref1, the signals ST0 and ST1 become the H level.

[0031] Referring to FIG. 2 again, the control unit 91 controls the information writing unit 32 based on the signals ST0 and ST1 obtained in this way, so that signals are periodically applied to the memory unit 31 and the period (frequency) of the signals is changed. Incidentally, the current detection unit 90 and the control unit 91 may be provided in the storage device 3, but may be provided at any part of the liquid ejection device 1, and may also be provided outside the liquid ejection head 11.

[0032] The function of the control unit 91 may be realized by a CPU and a memory, or may be realized by a semiconductor device such as an ASIC (application-specific integrated circuit), that is, it may be realized by either software or hardware. Typically, the control unit 91 includes one or more processing circuits with a memory, and its function can be realized by executing a predetermined program while expanding it on the memory.

[0033] 4 is a flowchart showing an example of a method for controlling the information writing unit 32 by the control unit 91. This flowchart is executed mainly by the control unit 91, and the outline thereof is that the period of the signal output by the information writing unit 32 is changed based on the detection result of the current detection unit 90.

[0034] In step S4000 (hereinafter simply referred to as "S4000"; the same applies to other steps described below), it is determined whether or not to execute writing of information to the storage device 3. This determination can be made, for example, based on whether or not there is a command from an external device instructing writing of information to the storage device 3. If writing of information is to be executed, the process proceeds to S4010; if not, the process returns to S4000 (or ends this flowchart).

[0035] In S4010, a memory unit 31 to be written to is selected from among the plurality of memory units 31. The memory unit 31 to be selected can be determined based on the command instructing the external device to write information to the storage device 212.

[0036] In S4020, an initial value of frequency fm is set for periodically applying a signal to memory unit 31. Two or more frequencies fm may be prepared, and here, frequency f1 is selected from two frequencies f1 and f2 (here, f1>f2), and fm=f1 is set.

[0037] In S4030, the process starts to write information to the selected memory unit 31. This step is performed by the information writing unit 32 outputting a signal of frequency fm to the memory unit 31.

[0038] In S4040, the signal level of signal ST0 is obtained as the detection result of the current detection unit 90, and it is determined whether the signal level is the L level or the H level. The fact that signal ST0 becomes the H level corresponds to the MOS structure of the anti-fuse element 311 being in the soft breakdown state. If signal ST0 is at the H level, the process proceeds to S4100; otherwise, the process returns to S4040.

[0039] In S4100, the set value of the frequency fm is changed. Here, it is assumed that fm = f2 (<f1) is set. As a result, the information writing unit 32 outputs a signal of frequency f2 to the memory unit 31.

[0040] In S4110, the signal level of signal ST1 is obtained as the detection result of the current detection unit 90, and it is determined whether the signal level is the L level or the H level. The fact that signal ST1 becomes the H level corresponds to the MOS structure of the anti-fuse element 311 being in the hard breakdown state, that is, it corresponds to the completion of writing information to the memory unit 31. If signal ST1 is at the H level, the process proceeds to S4200; otherwise, the process returns to S4110.

[0041] In S4200, it is determined whether it is necessary to write information to another memory unit 31. If it is necessary to write information to another memory unit 31, the process returns to S4010, and in the same procedure, the writing of information to the other memory unit 31 is started. If it is not necessary to write information to another memory unit 31, it is considered that the writing of information to the storage device 3 is completed, and this flowchart is terminated.

[0042] FIG. 5(a) shows a timing chart when writing information to a single memory unit 31 based on this flowchart. In the figure, the horizontal axis is the time axis, and the vertical axis shows the voltage VHT, the signal SIGwr output by the information writing unit 32, the voltage Vdet corresponding to the current value supplied to the memory unit 31, and the signals ST0 and ST1, respectively.

[0043] After the voltage VHT is supplied, in period T1, a signal pulse with a frequency f1 is supplied to the memory unit 31 as the signal SIGwr. Along with the signal ST0 becoming the H level at time t11, in period T2, a signal pulse with a frequency f2 is supplied to the memory unit 31 as the signal SIGwr. Along with the signals ST0 and ST1 becoming the H level at time t21, the supply of the signal SIGwr (frequency f2) is suppressed. Thereby, assuming that the writing of information to the memory unit 31 is completed, thereafter, the supply of the voltage VHT is suppressed.

[0044] According to such a control mode, before the current value supplied to the memory unit 31 reaches the first reference value (when Vdet < Vref0), a signal of the first period (frequency f1) is applied to the memory unit 31. After the current value supplied to the memory unit 31 reaches the first reference value (when Vref0 ≤ Vdet < Vref), a signal of a second period (frequency f2) larger than the first period is applied to the memory unit 31. And when the current value supplied to the memory unit 31 reaches a second reference value larger than the first reference value (when Vref1 ≤ Vdet), the supply of the signal to the memory unit 31 is suppressed.

[0045] According to the present embodiment, the period of the signal output by the information writing unit 32 is changed based on the current value supplied to the memory unit 31. Before the dielectric breakdown of the MOS structure of the anti-fuse element 311, the information writing unit 32 outputs a signal with a relatively high frequency. And after the information writing unit 32 enters the soft breakdown state of the MOS structure, it outputs a signal with a relatively low frequency, and after entering the hard breakdown state, it suppresses the output of the signal. Thereby, the electrical energy required to change the MOS structure from the state before dielectric breakdown to the state after dielectric breakdown is supplied without excess or deficiency. Although differences in electrical characteristics may occur between the plurality of anti-fuse elements 311, for example, due to manufacturing variations, according to the present embodiment, the writing of information to each anti-fuse element 311 can be appropriately realized regardless of the differences in the electrical characteristics.

[0046] Consequently, as a step between S4110 and S4200, a signal with a frequency f3 (< f2) may be supplied to the memory unit 31 by the information writing unit 32. At this time, as the signal with the frequency f3, a predetermined number of signal pulses may be supplied to the memory unit 31. Thereby, the hard breakdown state of the MOS structure of the anti-fuse element 311 can be made reliable.

[0047] FIG. 5(b) shows a timing chart when a signal with a frequency f3 is additionally supplied to the memory unit 31, similar to FIG. 5(a). In the figure, the horizontal axis is the time axis, and the vertical axis shows the voltage VHT, the signal SIGwr output by the information writing unit 32, the voltage Vdet corresponding to the current value supplied to the memory unit 31, and the signals ST0 and ST1, respectively.

[0048] With the signals ST0 and ST1 becoming the H level at time t21, in the period T3, signal pulses with a frequency f3 are supplied to the memory unit 31 over a predetermined period as the signal SIGwr. Here, it is assumed that three signal pulses with the frequency f3 are supplied, but the number of the supplied signal pulses is not limited to this example.

[0049] As described above, according to the present embodiment, when writing information to the anti-fuse element 311, electrical energy can be efficiently supplied to the MOS structure without excess or deficiency, and the MOS structure can be changed from the state before dielectric breakdown to the state after dielectric breakdown relatively quickly. Therefore, according to the present embodiment, more appropriate information writing in the memory device 3 can be realized relatively easily.

[0050] FIGS. 6(a) to 6(b) show another configuration example of the memory unit 31.

[0051] 6(a) shows an example in which a clamping transistor is used as the protection element 313c. This transistor is typically used to meet the criteria of evaluation tests that comply with certain ESD standards, such as HBM (Human Body Model) and MM (Machine Model).

[0052] 6(b) shows an example in which the positional relationship between the memory unit 31 and the current detection unit 90 is changed. That is, since the current value supplied to the memory unit 31 and the current value output from the memory unit 31 are substantially the same, the current detection unit 90 may be arranged to detect the current output from the memory unit 31.

[0053] In any of the cases of FIGS. 6(a) and 6(b), a rectifying element may be used as the protective element 313c, in which case the anode may be grounded and the cathode may be connected to the power supply line of the voltage VHT.

[0054] FIG. 7 is a diagram showing the connection relationship between the liquid ejection head 11, the carriage 12, and the head controller 13 in the liquid ejection device 1. As shown in FIG.

[0055] The main function of the control unit 91 (here, arithmetic processing) is provided in the head controller 13, and some functions can be provided in the liquid ejection head 11 as a function control unit 911 and a memory control unit 912. With this configuration, arithmetic processing for the entire system of the liquid ejection head 11 is mainly executed by the head controller 13. Drive control of the function unit 2 and the memory device 3 is performed by the function control unit 911 and the memory control unit 912 in the liquid ejection head 11, respectively, based on signals from the control unit 91.

[0056] The head controller 13 further includes a voltage generation unit 92. The voltage generation unit 92 generates a plurality of voltages VH and the like based on an external voltage. The voltage VH (e.g., 24 V (volts)) can be used mainly for driving and controlling the functional unit 2. The voltage VHT (e.g., 24 V) can be used mainly for driving and controlling the memory device 3. The voltage VDD (e.g., 3.3 V) can be used for arithmetic processing by a logic circuit unit that controls driving and controlling the functional unit 2 and the memory device 3. In addition, a voltage VSS (e.g., 0 V) ​​is generated as a ground voltage corresponding to the voltage VDD, and a voltage GNDH (e.g., 0 V) ​​is generated as a ground voltage corresponding to the voltages VH and VHT.

[0057] Incidentally, among the above-mentioned voltages VH and the like, those with the same potential can be prevented from electrical interference between power supply systems due to potential fluctuations by providing them individually, but they may also be provided in common.

[0058] The carriage 12 includes a plurality of power lines for transmitting the above-mentioned voltage VH and the like generated by the voltage generating unit 92 to the liquid ejection head 11. Capacitors can be provided between the power lines to prevent potential fluctuations therebetween.

[0059] The liquid ejection head 11 receives a voltage VH and the like from a voltage generation unit 92 of the head controller 13 via the carriage 12. The control unit 91 controls the driving of the functional unit 2 of the liquid ejection head 11 and the storage device 3 using the voltage VH and the like based on instructions from an external device. For example, the functional unit 2 can realize a recording function based on the voltage VH, and the storage device 3 can realize writing of information based on the voltage VHT. The control unit 91 may also be expressed as a calculation unit or the like.

[0060] The current detection unit 90 may be connected to the power line of the voltage VHT used to control the drive of the storage device 3, and in the example of FIG. 7 is installed in the liquid ejection head 11, i.e., connected to the power line of the voltage VHT in the liquid ejection head 11. As another example, the current detection unit 90 may be installed in the head controller 13 as shown in FIG. 8, in which case it may be connected to the power line of the voltage VHT in the head controller 13. As yet another example, the current detection unit 90 may be installed in the carriage 12 as shown in FIG. 9, in which case it may be connected to the power line of the voltage VHT in the carriage 12.

[0061] 7 to 9, writing appropriate information to the storage device 3 can be relatively easily achieved. In these examples, signals ST0 and ST1 as the detection results of the current detection unit 90 are output to the control unit 91, and the frequency fm of the signal to be output by the information writing unit 32 is set and changed by the control unit 91. However, various modifications may be made to this configuration without departing from the spirit of the embodiment. For example, signals ST0 and ST1 may be output to the storage control unit 912, and the frequency fm may be set and changed by the storage control unit 912.

[0062] In the above description, for ease of understanding, each element is denoted by a name related to its function. However, each element is not limited to having the content described in the embodiment as its main function, and may have that function auxiliary to the content. Therefore, each element is not strictly limited to the expression, and the expression can be replaced with a similar expression. In the same spirit, the expression "apparatus" may be replaced with "unit," "component," "piece," "member," "structure," "assembly," etc., or may be omitted.

[0063] In addition, for ease of understanding, multiple elements corresponding to the multiple functions described above have been illustrated individually, but they may be configured at least partially as an integrated unit, or some of them may be configured separately.

[0064] (program) The present invention may be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in a computer of the system or device read and execute the program. For example, the present invention may be realized by a circuit (e.g., an ASIC) that realizes one or more functions.

[0065] (others) In the above description, an inkjet recording device has been exemplified as the liquid ejection device 1, but the present invention is not limited to this. That is, the device 1 may be a single-function printer having only a recording function, or a multi-function printer having multiple functions such as a recording function, a fax function, and a scanner function. Furthermore, the device 1 may be, for example, a manufacturing device for manufacturing color filters, electronic devices, optical devices, microstructures, etc. using a predetermined recording method.

[0066] Furthermore, the term "recording" as used in this specification should be interpreted broadly. Therefore, the form of "recording" does not matter whether the object formed on the recording medium is significant information such as characters or figures, or whether it is visible to humans or not.

[0067] Furthermore, the term "recording medium" should be interpreted broadly, just like the above-mentioned "recording." Therefore, the concept of "recording medium" can include not only commonly used paper, but also any material that can accept ink, such as cloth, plastic film, metal plate, glass, ceramics, resin, wood, leather, etc.

[0068] Furthermore, "ink" should be interpreted broadly, just like the above-mentioned "recording." Therefore, the concept of "ink" includes not only a liquid that forms an image, design, pattern, etc. by being applied to a recording medium, but also ancillary liquids that can be used for processing the recording medium, treating the ink (for example, solidifying or insolubilizing the coloring material in the ink applied to the recording medium), etc.

[0069] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0070] 3: memory device, 31: memory unit, 311: anti-fuse element, 313a: protection element (resistance element), 32: information writing section.

Claims

1. a memory unit including an antifuse element and a resistance element connected in parallel to the antifuse element; an information writing unit that writes information into the anti-fuse element by periodically applying a signal to the memory unit; The information writing unit changes the period of a signal applied to the memory unit based on a current value supplied to the memory unit.

1. A storage device comprising:

2. The information writing unit before the current value supplied to the memory unit reaches a first reference value, a signal of a first period is applied to the memory unit; After the current value supplied to the memory unit reaches the first reference value, a signal having a second period greater than the first period is applied to the memory unit.

2. The storage device according to claim 1.

3. The information writing section suppresses the supply of a signal to the memory unit when a value of a current supplied to the memory unit reaches a second reference value that is greater than the first reference value.

3. The storage device according to claim 2.

4. The memory unit further includes a protection element connected in parallel to the protection element.

4. The storage device according to claim 1, wherein the first and second storage units are connected to each other.

5. The resistive element is a first resistive element, The storage device further includes a power supply line for supplying a power supply voltage to the memory unit and a second resistance element disposed between the memory unit and the power supply line.

5. The storage device according to claim 4.

6. The information writing section changes the period of the signal applied to the memory unit based on the current value supplied to the memory unit specified by comparing the voltage generated in the second resistive element with a reference voltage.

6. The storage device according to claim 5.

7. A storage device according to any one of claims 1 to 6; a liquid ejection element for ejecting liquid; A liquid ejection head characterized by:

8. The liquid ejection head according to claim 7, a head controller for controlling the driving of the liquid ejection head; A liquid ejection device characterized by:

9. a current detection unit for detecting a current value supplied to the memory unit; The current detection unit is installed in the liquid ejection head.

9. The liquid ejection device according to claim 8.

10. a current detection unit for detecting a current value supplied to the memory unit; The current detection unit is installed in the head controller.

9. The liquid ejection device according to claim 8.

11. a carriage configured to be able to move the liquid ejection head based on a control signal from the head controller; a current detection unit for detecting a current value supplied to the memory unit; The current detection unit is installed on the carriage.

9. The liquid ejection device according to claim 8.

Images