Semiconductor Devices

Abstract

To provide a highly reliable transistor.SOLUTION: In a bottom-gate transistor in which an oxide semiconductor layer is used as a semiconductor layer in which a channel is formed, after forming an insulating layer containing excess oxygen over the oxide semiconductor layer, an insulating layer through which impurities hardly permeate is formed without being exposed to the atmosphere during the process. An aluminum oxide layer or the like can be used as the insulating layer through which impurities do not easily permeate. Further, by using a conductive layer having a function of absorbing hydrogen for a source electrode and a drain electrode, hydrogen in the oxide semiconductor layer can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method, or the present invention relates to a process, a machine, Manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, a display device ... In particular, one aspect of the present invention relates to a processor, a driving method thereof, or a manufacturing method thereof. The present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of devices, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. may have semiconductor devices. [Background technology]

[0003] Silicon is known as one of the materials used for the semiconductor layer of transistors. Amorphous silicon and polycrystalline silicon are used depending on the application. When silicon is used for the semiconductor layer of the transistor that constitutes the display device, It is preferable to use amorphous silicon, for which the formation technology has been established. When silicon is used for the semiconductor layer of the transistor that constitutes the formed high-performance display device, It is preferable to use polycrystalline silicon, which allows the fabrication of transistors with high field-effect mobility. be.

[0004] On the other hand, oxide semiconductors have recently been attracting attention as a material for the semiconductor layer of transistors. For example, an amorphous oxide semiconductor containing indium, gallium, and zinc is used. A transistor is known (see Patent Document 1).

[0005] Since oxide semiconductors can be formed by sputtering or the like, they can be used to form large display devices. The semiconductor layer of a transistor using amorphous silicon can also be used. It is possible to improve and use some of the transistor production equipment, which reduces capital investment. Furthermore, a transistor including an oxide semiconductor has high field-effect mobility; A highly functional display device with an integrated drive circuit can be realized.

[0006] In addition, a transistor using an oxide semiconductor for a semiconductor layer has extremely low resistance in a non-conducting state. For example, the leakage current of a transistor using an oxide semiconductor is known to be small. A low-power CPU that utilizes the low operating current characteristic has been disclosed (Patent Document See reference 2. ). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-257187 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a transistor having good electrical characteristics. Another object of the present invention is to provide a transistor with a low power consumption. Another object of the present invention is to provide a highly reliable transistor. Another object of the present invention is to provide a novel transistor. Alternatively, a semiconductor device having at least one of these transistors can be provided. This is one of the challenges.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] A bottom-gate transistor that uses an oxide semiconductor layer as the semiconductor layer where the channel is formed. In the case of the oxide semiconductor device, an insulating layer containing excess oxygen is formed over the oxide semiconductor layer, and then the insulating layer is exposed to the air during the formation of the insulating layer. As an insulating layer that is difficult for impurities to penetrate, For example, an aluminum oxide layer can be used. By using a conductive layer having a function of absorbing hydrogen as the electrode, the hydrogen concentration in the oxide semiconductor layer can be reduced. can be reduced.

[0011] Alternatively, a top-gate structure transistor using an oxide semiconductor layer as a semiconductor layer in which a channel is formed may be used. In the transistor, after the gate electrode is formed, the gate electrode is used as a mask to form an oxide semiconductor. Impurities are introduced into the layer, or plasma treatment with inert gas or nitrogen gas is performed. Next, after the heat treatment, the material is left in an insulating state that is difficult for impurities to penetrate, without being exposed to the atmosphere. Forms a border layer.

[0012] One embodiment of the present invention is a semiconductor device including first to third electrodes, first to fifth insulating layers, and first and second insulating layers. an oxide semiconductor layer, a first insulating layer on the first electrode, and a second insulating layer a first oxide semiconductor layer over the first insulating layer, a third insulating layer over the second insulating layer, The semiconductor layer is on the third insulating layer, and the second oxide semiconductor layer is on the first oxide semiconductor layer. a first electrode, a first insulating layer, a second insulating layer, a third insulating layer, a first oxide semiconductor, The first oxide semiconductor layer and the second oxide semiconductor layer have overlapping regions, and the second electrode is a region overlapping with the second oxide semiconductor layer on the second oxide semiconductor layer; a region overlapping the second insulating layer, and the third electrode is formed on the second oxide semiconductor layer by a second oxide semiconductor layer. a region overlapping the nitride semiconductor layer and a region on the second insulating layer overlapping the second insulating layer, The fourth insulating layer has a region overlapping with the second oxide semiconductor layer, and the fifth insulating layer has a region overlapping with the fourth insulating layer. A transistor characterized in that the second oxide semiconductor layer is crystalline and is located on the edge layer. is.

[0013] Alternatively, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of forming a first electrode and forming a first insulating film covering the first electrode. forming a layer, forming a second insulating layer on the first insulating layer, and forming a second insulating layer on the second insulating layer. forming a third insulating layer on the first oxide semiconductor layer; and forming a first oxide semiconductor layer on the third insulating layer. forming a second oxide semiconductor layer on the first oxide semiconductor layer; a step of processing the semiconductor layer and the second oxide semiconductor layer into an island shape; a second electrode overlapping a part of the oxide semiconductor layer and a third electrode overlapping another part of the second oxide semiconductor layer; forming a third electrode; and forming a fourth insulating layer covering the second oxide semiconductor layer. and forming a fifth insulating layer on the fourth insulating layer. The steps from the heat treatment to the formation of the fifth insulating layer are carried out without exposure to the atmosphere. The present invention provides a method for manufacturing a transistor.

[0014] The second insulating layer preferably contains aluminum and oxygen. The fifth insulating layer preferably contains aluminum and oxygen. Preferably, it contains ammonium and oxygen.

[0015] The heat treatment performed after forming the fourth insulating layer is performed at a temperature of 200° C. or higher and 500° C. or lower. It is preferable that:

[0016] The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. The heat treatment may be carried out in an inert atmosphere and then in an oxidizing atmosphere.

[0017] Alternatively, one embodiment of the present invention is a semiconductor device including a first electrode, a second electrode, first to fifth insulating layers, and an oxide film. a first insulating layer on the first electrode and a second insulating layer on the second electrode; a first insulating layer on the first insulating layer, a third insulating layer on the second insulating layer, and an oxide semiconductor layer on the second insulating layer; the third insulating layer is on the oxide semiconductor layer, the fourth insulating layer is on the oxide semiconductor layer, and the second electrode is The first electrode, the second electrode, and the first to fourth insulating layers are disposed on the fourth insulating layer. The fifth insulating layer has a region that covers the second electrode and a region that is in contact with the oxide semiconductor layer. and a region where the gate electrode is formed.

[0018] Alternatively, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of forming a first electrode and forming a first insulating film covering the first electrode. forming a layer, forming a second insulating layer on the first insulating layer, and forming a second insulating layer on the second insulating layer. forming a third insulating layer on the insulating film; and forming an oxide semiconductor layer on the third insulating layer. A step of processing the oxide semiconductor layer into an island shape and a step of forming a fourth insulating layer on the oxide semiconductor layer. a step of forming a second electrode on the fourth insulating layer; and a step of forming a second electrode on the fourth insulating layer using the second electrode as a mask. a step of processing the fourth insulating layer into an island shape; and a step of introducing impurities into a part of the oxide semiconductor layer. and forming a fifth insulating layer covering the second electrode and the oxide semiconductor layer. and a step of forming a fifth insulating layer, wherein the steps from the step of performing the heat treatment to the step of forming the fifth insulating layer are carried out under atmospheric pressure. The present invention relates to a method for manufacturing a transistor, which is characterized in that the method is performed without exposing the transistor to heat. [Effects of the Invention]

[0019] It is possible to provide a transistor with good electrical characteristics. It is possible to provide a transistor with low power consumption. Alternatively, a highly reliable transistor can be provided. Novel transistors can be provided, or at least some of these transistors can be provided. It is possible to provide a semiconductor device having one of the above.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0021] [Figure 1] 1A and 1B are diagrams illustrating a transistor. [Figure 2] 1A and 1B are diagrams illustrating a transistor. [Figure 3] 1A and 1B are diagrams illustrating a transistor. [Figure 4] 1A and 1B are diagrams illustrating a transistor. [Figure 5] 1A and 1B are diagrams illustrating a transistor. [Figure 6] 1A and 1B are diagrams illustrating a transistor. [Figure 7] 1A to 1C illustrate a manufacturing process of a transistor. [Figure 8] 1A to 1C illustrate a manufacturing process of a transistor. [Figure 9] 1A to 1C illustrate a manufacturing process of a transistor. [Figure 10] 1A to 1C illustrate a manufacturing process of a transistor. [Figure 11] 1A and 1B are diagrams illustrating a transistor. [Figure 12] 1A and 1B are diagrams illustrating a transistor. [Figure 13] 1A and 1B are diagrams illustrating a transistor. [Figure 14] 1A and 1B are diagrams illustrating a transistor. [Figure 15] 1A and 1B are diagrams illustrating a transistor. [Figure 16] 1A and 1B are diagrams illustrating a transistor. [Figure 17] 1A and 1B are diagrams illustrating a transistor. [Figure 18] FIG. 2 is a diagram illustrating the range of the atomic ratio of oxides according to the present invention. [Figure 19] 1A and 1B are diagrams illustrating a transistor. [Figure 20] 1A and 1B are diagrams illustrating a transistor. [Figure 21] 1A and 1B are diagrams illustrating a transistor. [Figure 22] 1A and 1B are diagrams illustrating a transistor. [Figure 23] 1A to 1C illustrate a manufacturing process of a transistor. [Figure 24] 1A to 1C illustrate a manufacturing process of a transistor. [Figure 25] 1A to 1C illustrate a manufacturing process of a transistor. [Figure 26]1A to 1C illustrate a manufacturing process of a transistor. [Figure 27] 1A and 1B are diagrams illustrating a transistor. [Figure 28] 1A and 1B are diagrams illustrating a transistor. [Figure 29] 1A and 1B are diagrams illustrating a transistor. [Figure 30] 1A and 1B are diagrams illustrating a transistor. [Figure 31] 1A and 1B are diagrams illustrating a transistor. [Figure 32] 1A and 1B are diagrams illustrating a transistor. [Figure 33] 1A and 1B are diagrams illustrating a transistor. [Figure 34] 1A and 1B illustrate an example of a display device and an example of a circuit configuration of a pixel. [Figure 35] FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel. [Figure 36] FIG. 2 illustrates an example of the configuration of a driver circuit. [Figure 37] 1A and 1B illustrate an example of a display device. [Figure 38] 1A and 1B illustrate an example of a display device. [Figure 39] 1A and 1B illustrate an example of a display device. [Figure 40] FIG. 2 is a diagram illustrating an example of a display module. [Figure 41] 1A to 1C illustrate examples of electronic devices. [Figure 42] FIG. 1 is a perspective view illustrating an example of a display device. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. The repeated explanation may be omitted.

[0023] In addition, the position, size, range, etc. of each component shown in the drawings are for the purpose of facilitating understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, in the actual manufacturing process, layers and resist masks are formed by processes such as etching. Although the number may be reduced unintentionally, it may be omitted to make it easier to understand.

[0024] In addition, in particular, top views (also called "plan views") and perspective views are used to make the invention easier to understand. In order to avoid this, some components may be omitted. may be omitted.

[0025] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are used to indicate the order or priority of the processes or stacking steps. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is used to avoid confusion of the constituent elements. In order to clarify the scope of the invention, ordinal numbers may be used in the claims. Even if a term has an ordinal number in the first place, it may be given a different ordinal number in the claims. In addition, even if a term is given an ordinal number in this specification, etc., it may be used in the patent. Ordinal numbers may be omitted in claims, etc.

[0026] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is installed as an integral part.

[0027] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "electrode on insulating layer A" is not limited to being below and in direct contact with the insulating layer A. If the expression is "B", electrode B does not need to be directly on insulating layer A, The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0028] The source and drain functions may also be different when using transistors with different polarities or when using circuits When the direction of the current changes during circuit operation, they are interchanged depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Let's say.

[0029] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also considered to be described in the drawings or text. do.

[0030] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. Therefore, even when it is expressed as "electrically connecting," in an actual circuit, In some cases, there are no physical connections and only wires running.

[0031] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source voltage) in the region where the The distance between the gate electrode and the drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is any one value, maximum value, The minimum or average value.

[0032] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0033] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter also referred to as the "effective channel width") shown in the top view of the transistor The channel width that is actually used (hereinafter also referred to as the "apparent channel width") may differ from the For example, when the gate electrode covers the side surface of the semiconductor layer, the effective channel width becomes The effect of this may become larger than the channel width of the In a transistor in which the gate electrode covers the side surface of the semiconductor, In this case, the ratio of the channel formation region may be larger than the apparent channel width. , the effective channel width becomes larger.

[0034] In such a case, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known exactly, it is difficult to estimate the effective chip size. Channel width is difficult to measure accurately.

[0035] Therefore, in this specification, the apparent channel width is referred to as the "surrounding channel width (SCW)". In addition, in this specification, So, when we simply write "channel width," it means the enclosed channel width or the apparent channel width. In this specification, when simply referred to as a channel width, it may refer to the actual It may refer to the effective channel width. The width, apparent channel width, and enclosed channel width can be determined by analyzing cross-sectional TEM images. The value can be determined by, for example,

[0036] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0037] The term "impurities" in a semiconductor refers to, for example, anything other than the main component that constitutes the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent can be considered impurities. , the DOS (Density of States) of semiconductors increases, and carrier The mobility and crystallinity may decrease. In the case of a compound semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and main components of oxide semiconductors There are transition metals other than those mentioned above, such as hydrogen, lithium, sodium, silicon, boron, These include phosphorus, carbon, and nitrogen.

[0038] In the case of an oxide semiconductor, water may also function as an impurity. For example, oxygen vacancies may be formed due to the inclusion of impurities. In this case, the impurities that change the properties of the semiconductor are, for example, the first impurities excluding oxygen and hydrogen. Group elements include the elements of Group 1, Group 2, Group 13, and Group 15.

[0039] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" and "orthogonal" mean that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Straight" refers to two straight lines that form an angle of 60° or more and 120° or less.

[0040] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0041] In this specification, the terms "identical," "same," and "equal" are used to refer to counting values ​​and measurement values. " or "uniform" (including their synonyms) unless expressly stated otherwise. The calculations are subject to a margin of error of plus or minus 20%.

[0042] In this specification and the like, a resist mask is formed by photolithography, and the If an etching process (removal process) is performed later, the resist mask is The mask shall be removed after the etching process is completed.

[0043] In this specification and the like, a high power supply potential VDD (also referred to as "VDD" or "H potential") ) indicates a power supply potential higher than the low power supply potential VSS. "VSS" or "L potential" is a power supply with a potential lower than the high power supply potential VDD. The ground potential (also called "GND" or "GND potential") is referred to as VDD or For example, if VDD is at ground potential, VSS can be used as a ground potential. If VSS is at ground potential, VDD is at a potential higher than ground potential. It is ranked 1st.

[0044] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0045] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain Between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode) It has a channel region and allows current to flow between the source and drain through the channel region. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to the area where the fluid flows.

[0046] Furthermore, unless otherwise specified, the transistors shown in this specification are enhancement type (non- The transistors shown in this specification are of the on-off type. Unless otherwise specified, the transistors are n-channel transistors. Unless otherwise specified, the voltage (also referred to as "Vth") is assumed to be greater than 0V.

[0047] In this specification and the like, the Vth of a transistor having a back gate is If there is no back gate, it refers to the Vth when the back gate potential is the same as the source or gate potential. .

[0048] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is in an off-state. The drain current when the device is in the on state (also known as the non-conducting state or cut-off state). , Unless otherwise specified, for n-channel transistors, the voltage between the gate and source, Vg When s is lower than the threshold voltage Vth, in a p-channel transistor, the gate and source This refers to the state in which the voltage Vgs between the gates is higher than the threshold voltage Vth. For example, The off-state current of a transistor is the voltage between the gate and source, Vgs, and the threshold voltage, Vth. It may refer to the drain current when the voltage is lower than

[0049] The off-state current of a transistor may depend on Vgs. The current is I or less if there is a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows in the off state at a given Vgs. Off-state or sufficiently reduced off-current at Vgs within a given range It may refer to the off-state current in the off state at Vgs, etc.

[0050] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -13 A, and the drain current at Vgs = -0.5 V is 1 × 10 -19 A and Vgs The drain current at -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: Or, when Vgs is in the range of -0.5V to -0.8V, 1×10-19 A or below Therefore, the off-state current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 Because there exists a Vgs below A , the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0051] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off voltage is measured at room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of the semiconductor device containing the transistor may be in doubt. or the temperature at which a semiconductor device including the transistor is used (for example, For example, it may refer to the off-state current at any temperature between 5°C and 35°C. The off-state current of the transistor is I or less, which means that the The temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the temperature at which the transistor The temperature at which the semiconductor device containing the stator is used (for example, any one of 5°C to 35°C) This indicates that there exists a value of Vgs at which the off-state current of the transistor is equal to or less than I at This may occur.

[0052] The off-state current of a transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1 V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or It may represent the off-state current at 20 V. Or, the semiconductor including the transistor Vds that guarantees the reliability of devices, etc., or semiconductor devices that include the transistor The off-state current of a transistor is sometimes expressed as the off-state current at Vds used in The current is less than or equal to I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2 .5V, 3V, 3.3V, 10V, 12V, 16V, 20V, including transistors Vds that guarantees the reliability of the semiconductor device in which the transistor is included, or Vds used in devices, etc., Vg at which the off-state current of a transistor is I or less It may refer to the existence of a value of s.

[0053] In the above description of the off-state current, the drain may be read as the source. may also refer to the current that flows through the source when the transistor is in the off state.

[0054] In this specification and the like, the term "leak current" may be used to mean the same thing as "off-state current." In this specification and the like, the off-state current refers to, for example, the current when a transistor is in an off state. It can refer to the current that flows between the source and drain.

[0055] (Embodiment 1) A transistor 100 of one embodiment of the present invention will be described with reference to drawings.

[0056] <Structural example of transistor 100> FIG. 1A is a plan view of a transistor 100. FIG. 1B is a plan view of the transistor 100 shown in FIG. FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed line X1-X2. 2(A) is a cross-sectional view of the portion shown in FIG. 1(B) along the dashed line 1-Y2. 2(B) is an enlarged view of a portion 132 shown in FIG. 1(C).

[0057] The transistor 100 is a type of bottom-gate transistor. The insulating layer 102, the insulating layer 103, the insulating layer 104, the insulating layer 105, the oxide semiconductor layer 106 ( oxide semiconductor layer 106_1 and oxide semiconductor layer 106_2), electrode 107a (electrode 1 07a_1, electrode 107a_2, electrode 107a_3), electrode 107b (electrode 107b_1 , electrode 107b_2, and electrode 107b_3), insulating layer 108, insulating layer 109, and It has an insulating layer 110 .

[0058] The electrode 102 is provided on the substrate 101. The insulating layer 103 is provided to cover the electrode 102. The insulating layer 104 is provided on the insulating layer 103. The insulating layer 105 is an insulating The oxide semiconductor layer 106 is provided on the insulating layer 105. The electrode 102 and the oxide semiconductor layer 106 are formed between the insulating layer 103, the insulating layer 104, and the insulating layer 106. They have an overlapping area with the insulating layer 105 interposed therebetween.

[0059] The electrode 107a and the electrode 107b are provided on the insulating layer 105. The electrode 107b has a region overlapping with a part of the oxide semiconductor layer 106, and the electrode 107b has a region overlapping with a part of the oxide semiconductor layer 106. 106 has an area overlapping with another part of 106.

[0060] The insulating layer 108 is provided to cover the electrode 107a, the electrode 107b, and the oxide semiconductor layer 106. The insulating layer 109 is provided on the insulating layer 108. The insulating layer 110 is an insulating It is provided on the edge layer 109 .

[0061] When the insulating layer 108 and the insulating layer 109 are made of the same material, the insulating layer 108 and the insulating layer 109 Therefore, in this embodiment, the interface between the insulating layer 108 and the insulating layer 108 may not be clearly visible. The interface between the insulating layer 108 and the insulating layer 109 is indicated by a broken line. Although the two-layer structure of the edge layer 109 has been described, one embodiment of the present invention is not limited to this. For example, , a single layer structure of either the insulating layer 108 or the insulating layer 109, or a laminated structure of three or more layers. It may also be constructed as such.

[0062] 3 and 4, an insulating layer 111 may be provided on the insulating layer 110. In the example shown in FIG. FIG. 3A is a plan view of the transistor 100. FIG. 3B is a plan view of the transistor 100 shown in FIG. 3(C) is a cross-sectional view of the portion indicated by the dashed line X1-X2. 4(A) is a cross-sectional view of the portion shown in FIG. 3(B) along the dashed line 1-Y2. 4(B) is an enlarged view of a portion 132 shown in FIG.

[0063] When the transistor 100 is provided with the insulating layer 110 and the insulating layer 111, It is preferable to use an insulating material for one or both of the layers 111 that is difficult for impurities to penetrate. For example, at least one of the insulating layers 110 and 111 may be a silicon nitride layer or an aluminum oxide layer. Alternatively, one of the insulating layers 110 and 111 may be made of silicon nitride. One layer may be a palladium layer, and the other may be an aluminum oxide layer.

[0064] In particular, it is preferable to form an aluminum oxide layer as the insulating layer 110 by a sputtering method. It is particularly preferable to form an aluminum oxide layer as the insulating layer 111 by the ALD method. These effects will be explained later.

[0065] 1B, 1C, 2A, and 2B, the oxide semiconductor layer 1 06 is shown as a stack of two layers of an oxide semiconductor layer 106_1 and an oxide semiconductor layer 106_2. However, one embodiment of the present invention is not limited thereto. The oxide semiconductor layer 106 may be a single layer. 106 is an oxide semiconductor layer 106_1, an oxide semiconductor layer 106_2, and an oxide semiconductor The oxide semiconductor layer 106 may be a stack of four or more layers. 5(A) and 5(B) are cross-sectional views corresponding to FIG. 1(B). .

[0066] The oxide semiconductor layer 106_3 is formed by the oxide semiconductor layer 106_1 or the oxide semiconductor layer 106_ It can be formed using the same materials and methods as in 2.

[0067] An electrode 121 having a region overlapping with the oxide semiconductor layer 106 is provided over the insulating layer 110. (See FIG. 6(A) and FIG. 6(B)). Also, a thin film having a flat surface on the insulating layer 110 may be used. An insulating layer 113 may be provided over the insulating layer 113 (see FIG. 6C). An electrode 121 having a region overlapping with the layer 106 may be provided. It may be provided between the insulating layer 109 and the insulating layer 110 .

[0068] [Gate electrode and back gate electrode] The electrode 102 can function as a gate electrode. When provided on the gate electrode 100, the electrode 121 can also function as a gate electrode. When one of the electrodes 121 is referred to as a "gate electrode," the other is referred to as a "back gate electrode." For example, in the transistor 100 shown in FIG. 6(A) or 6(C), the electrode 102 When referring to a "gate electrode," the electrode 121 is referred to as a "back gate electrode." When the gate electrode is used as the "gate electrode," the transistor 100 is a top-gate transistor. Either the electrode 102 or the electrode 121 can be considered as a type of The first gate electrode is sometimes referred to as the "gate electrode" and the other as the "second gate electrode."

[0069] Generally, the gate electrode and the back gate electrode are formed of a conductive layer. The gate electrodes are arranged to sandwich the channel forming region of the semiconductor layer. The semiconductor layer (oxide semiconductor layer) is surrounded by a gate electrode and a back gate electrode. With such a structure, the oxide semiconductor layer 106 included in the transistor 100 can be The electrode 102 functions as a gate electrode, and the electrode 121 functions as a back gate electrode. The gate and back gate electrodes are electrically surrounded by the electric field. Therefore, the structure of the transistor that electrically surrounds the semiconductor layer where the channel is formed is called Sur This can be called a rounded channel (S-channel) structure.

[0070] The back gate electrode can function in the same way as the gate electrode. The potential may be the same as that of the gate electrode, or may be the ground potential or any other potential. By changing the potential of the back gate electrode independently of the gate electrode, The threshold voltage of the transistor can be changed.

[0071] As mentioned above, the electrode 102 can function as a gate electrode. The edge layer 104 and the insulating layer 105 can function as gate insulating layers. When provided, insulating layer 108 and insulating layer 110 can function as gate insulating layers.

[0072] By providing the electrode 102 and the electrode 121 with the oxide semiconductor layer 106 interposed therebetween, By setting the electrode 102 and the electrode 121 to the same potential, the carrier Since the area in which the carriers flow becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, the on-state current of the transistor increases and the field-effect mobility increases.

[0073] Therefore, the transistor is designed to have a large on-current relative to the area it occupies. In other words, the area occupied by the transistor can be reduced relative to the required on-current. Therefore, a highly integrated semiconductor device can be realized.

[0074] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity In plan view, the back gate electrode is The back gate electrode is formed larger than the semiconductor layer, and the semiconductor layer is covered with the back gate electrode, improving the electric field shielding function. It can be done.

[0075] The electrodes 102 and 121 each have the function of shielding an external electric field. The charges of the charged particles generated above the electrode 121 and below the electrode 102 are transferred to the oxide semiconductor layer As a result, the channel forming region of 106 is not affected. GBT (Gate Bias-Temperature) stress test In addition, the electrode 102 and the electrode 121 are connected to the drain The electric field generated by the electrode can be blocked so that it does not affect the semiconductor layer. Fluctuations in the on-state current rising voltage due to fluctuations in the on-state voltage can be suppressed. This effect is evident when a potential is applied to the electrodes 102 and 121. Occurs spontaneously.

[0076] The GBT stress test is a type of accelerated test that measures the temperature and humidity of the battery during long-term use. It is possible to evaluate the change in characteristics (aging) of a resistor in a short time. The amount of change in the threshold voltage of a transistor before and after testing is an important factor for examining reliability. The smaller the change in threshold voltage before and after the GBT stress test, the higher the signal quality. This means that it is a highly reliable transistor.

[0077] The electrode 102 and the electrode 121 are set to the same potential. This reduces the amount of variation in threshold voltage between multiple transistors. At the same time, the variation in electrical characteristics is reduced.

[0078] A transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0079] In addition, when light is incident from the back gate electrode side, the back gate electrode is By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents light degradation of the semiconductor layer and shifts the threshold voltage of the transistor. This can prevent deterioration of electrical characteristics such as

[0080] One of the electrodes 107a and 107b serves as a source electrode or a drain electrode. The other of the electrodes 107a and 107b can function as a source electrode or a drain electrode. It can function as the other of the two.

[0081] 〔substrate〕 The substrate 101 may be a glass substrate, a ceramic substrate, or any other substrate that can withstand the processing temperature of this manufacturing process. A flexible substrate or the like having sufficient heat resistance can be used. In the case where the substrate does not need to be transparent, an insulating layer is provided on the surface of a metal substrate such as a stainless alloy. The glass substrate may be made of, for example, barium borosilicate glass, aluminum, or the like. Using an alkali-free glass substrate such as lumino-borosilicate glass or alumino-silicate glass Alternatively, a quartz substrate, a sapphire substrate, or the like can be used.

[0082] The substrate 101 is a 3rd generation (550 mm x 650 mm) or 3.5th generation (600 mm x 720 mm, or 620 mm x 750 mm, 4th generation (680 mm x 880 mm) m, or 730mm x 920mm), 5th generation (1100mm x 1300mm), 6th generation Generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th generation Generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm, 245 10th generation (2950mm x 3400mm) and 10th generation (2950mm x 3400mm) glass substrates It can be used.

[0083] When a flexible substrate is used as the substrate 101, transistors and capacitor elements are formed on the flexible substrate. Alternatively, transistors and capacitors may be fabricated on another fabrication substrate. After that, the film may be peeled off and transferred to a flexible substrate. To achieve this, a separation layer may be provided between the formation substrate and the transistor, the capacitor, or the like.

[0084] The flexible substrate may be, for example, a metal, an alloy, a resin, a glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate used for the substrate 101, the more environmentally friendly it is. The flexible substrate used for the substrate 101 has a linear expansion coefficient of, for example, 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less As the resin, for example, polyester, polyolefin, polyamide ( Nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Aramid has a low coefficient of linear expansion and is therefore suitable for flexible substrates.

[0085] The substrate 101 may be a single crystal semiconductor substrate made of silicon, silicon carbide, or the like. A crystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, etc., can be used. Also, strained transistors and FIN type transistors can be formed on SOI substrates and semiconductor substrates. Alternatively, a semiconductor element such as a high electron mobility capacitor may be used. Transistor (HEMT: High Electron Mobility Transistor) Gallium arsenide, aluminum gallium arsenide, and indium gallium arsenide are applicable to ISTRs. Alternatively, silicon nitride, gallium nitride, indium phosphide, silicon germanium, or the like may be used. That is, the substrate 101 is not limited to being a simple support substrate, but is also a substrate on which other devices such as transistors are mounted. In this case, the gate, source, or drain of the transistor may be formed on the substrate. At least one of the inputs may be electrically connected to the other device.

[0086] [Insulating layer] Insulating layers 103 to 105, insulating layer 108, insulating layer 109, insulating layer 110, insulating layer 1 11. The insulating layer 113 is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, Aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide ZrO2, Lanthanum Oxide, Neodymium Oxide, Hafnium Oxide, Tantalum Oxide, Aluminum Oxide Materials selected from silicates and the like are used in a single layer or in a laminated form. A material that is a mixture of multiple materials from among nitride materials, oxynitride materials, and nitride oxide materials is used. It's fine.

[0087] In this specification, the term "nitride oxide" refers to a compound containing more nitrogen than oxygen. Also, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of Measurements can be made using techniques such as kScattering Spectrometry. .

[0088] In particular, the insulating layers 104, 110, and 111 have insulating properties that are difficult for impurities to penetrate. For example, it is preferable to use an insulating material that is difficult for impurities to penetrate. , aluminum oxide, aluminum nitride, aluminum oxide nitride, aluminum oxide nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Examples of suitable oxides include silicon dioxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride. Cut.

[0089] By using an insulating material that is difficult for impurities to penetrate for the insulating layer 104, impurities from the substrate 101 side can be prevented from The diffusion of impurities in the insulating layer 110 can be prevented, thereby improving the reliability of the transistor. By using an insulating material that is difficult for impurities to penetrate, the diffusion of impurities from the upper layer side of the insulating layer 110 can be prevented. This prevents scattering and improves the reliability of the transistor.

[0090] In addition, the insulating layers 104, 110, and 111 are difficult for oxygen to diffuse through. It is preferable to use an insulating material that is resistant to heat and / or absorption. 110 and the insulating layer 111, and the insulating layer 110 is an insulating layer in which oxygen is hardly diffused and / or absorbed. The use of an insulating material can prevent oxygen from diffusing to the outside.

[0091] The insulating layers 104, 110, and 111 are made of these materials. A plurality of insulating layers may be stacked.

[0092] In order to prevent an increase in the hydrogen concentration in the oxide semiconductor layer 106, the hydrogen concentration in the insulating layer is reduced. In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the oxide semiconductor layer 106. In this embodiment, it is preferable to use the insulating layer 105 and the insulating layer 108. It is preferable to reduce the hydrogen concentration in the insulating layer. 2 x 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Below or less, more preferably 1 x 10 19 atoms / cm 3 Less than 5 × 10, more preferably 1 8 atoms / cm 3 In addition, in order to prevent an increase in the nitrogen concentration in the oxide semiconductor layer, In particular, it is preferable to reduce the nitrogen concentration in the insulating layer. , 5 × 10 in SIMS 19 atoms / cm 3 Less than 5 x 10 18 at oms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below are some more preferred Or 5 x 10 17 atoms / cm 3 The following applies.

[0093] At least one of the insulating layers 105, 108, and 109 is heated. The insulating layer is formed by using an insulating layer from which oxygen is released (hereinafter also referred to as an "insulating layer containing excess oxygen"). Specifically, the surface temperature of the layer is preferably 100°C or higher and 700°C or lower, Thermal desorption spectroscopy (TDS) is performed at a temperature between 100°C and 500°C. In normal desorption spectroscopy (DDS), the oxygen atoms are The calculated amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 That's it, 1.0 x 10 19 at oms / cm 3or more than 1.0×10 20 atoms / cm 3 The insulating layer is It is preferable that

[0094] In particular, it is preferable that the insulating layer in contact with the oxide semiconductor layer have a small number of defects. In the ESR measurement, the g value of 2.001, which is due to the dangling bond of silicon, The spin density of the signal is 3×10 17 spins / cm 3 It is preferable that the following is true: If the edge layer has many defects, oxygen may bind to the defects and reduce the excess oxygen.

[0095] In particular, the insulating layer in contact with the oxide semiconductor layer is made of nitrogen oxide (NO X ) due to the level density It is preferable to use an oxide insulating layer with a low degree of nitrogen oxide emission. The silicon layer is a layer that is determined by thermal desorption spectroscopy to determine the amount of ammonia released from nitrogen oxides. This is a layer with a large amount of ammonia, typically 1×10 18 pieces / cm 3 5x1 or more 0 19 pieces / cm 3 The amount of ammonia released is less than that when the surface temperature of the membrane is 50°C or higher. The amount of release is determined by heat treatment at 650°C or less, preferably 50°C to 550°C.

[0096] Nitrogen oxides (typically NO2 or NO) form levels in oxide semiconductor layers and insulating layers. The level is located within the energy gap of the oxide semiconductor. When the level reaches the interface between the insulating layer and the oxide semiconductor layer, it traps electrons on the insulating layer side. As a result, the trapped electrons may move near the interface between the insulating layer and the oxide semiconductor layer. The electrons remain nearby, shifting the threshold voltage of the transistor in the positive direction.

[0097] Note that the density of states due to the nitrogen oxides is determined by the energy level at the top of the valence band of the oxide semiconductor layer. between the energy of the lower edge of the conduction band (Ec_os) of the oxide semiconductor layer and the energy of the lower edge of the conduction band (Ev_os) of the oxide semiconductor layer. As the oxide insulating layer, a nitride film that emits a small amount of nitrogen oxides may be formed. A silicon oxide layer, an aluminum oxynitride layer which emits a small amount of nitrogen oxide, or the like may be used. This can be done.

[0098] Nitrogen oxides also react with ammonia and oxygen during heat treatment. The nitrogen oxides react with the ammonia contained in the insulating layer during the heat treatment, Therefore, the nitrogen oxides contained in the insulating layer are reduced at the interface between the insulating layer and the oxide semiconductor layer. Therefore, electrons are less likely to be trapped.

[0099] In particular, by using the oxide insulating layer as an insulating layer in contact with an oxide semiconductor layer, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0100] The insulating layer containing excess oxygen can also be formed by performing a treatment of adding oxygen to the insulating layer. The process of adding oxygen includes heat treatment under an oxygen atmosphere, ion implantation, ion doping, etc. plasma immersion ion implantation, and plasma treatment or reverse sintering. This can be done by sputtering or the like. Addition of oxygen by reverse sputtering The treatment is also expected to have a cleaning effect on the sample surface. On the other hand, depending on the treatment conditions, damage may occur to the sample surface. The gases used to add oxygen include:16 O2 or 18 O2 Oxygen gas, nitrous oxide gas, ozone gas, etc. can be used. In this specification, the treatment of adding oxygen is also referred to as "oxygen doping treatment."

[0101] The insulating layer 113 also has a function of flattening unevenness caused by transistors and the like. The material used for the insulating layer 113 may be an insulating material. The insulating layer 113 can be formed using an inorganic material or an organic material. As the materials, not only the inorganic materials mentioned above but also polyimide, acrylic, benzocyclobutene, polyimide, Heat-resistant organic materials such as thiamid and epoxy can be used. In addition to the materials, low-k materials, siloxane resins, and PSG (phosphor glass) ), BPSG (borophosphorus glass), etc. can be used. The insulating layer 113 may be formed by stacking a plurality of insulating layers.

[0102] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0103] The method for forming the insulating layer 113 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), printing The insulating layer 113 may be baked by a baking method (screen printing, offset printing, etc.). By combining this process with other heat treatment processes, it becomes possible to efficiently manufacture transistors. .

[0104] 〔electrode〕 Electrode 102, electrode 107a_1, electrode 107a_2, electrode 107a_3, electrode 107b_ 1, a conductive material for forming the electrode 107b_2, the electrode 107b_3, and the electrode 121 The materials include aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), and gold (A u), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum Mo, Tungsten (W), Hafnium (Hf), Vanadium (V), Niobium (N b), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium ( Materials containing one or more metal elements selected from the group consisting of phosphorus, Be, etc. can also be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements, Silicides such as nickel silicide may also be used.

[0105] In addition, as a conductive material, Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, The layer formed of Cu-X alloy can be obtained by wet etching. Since it can be processed using a manufacturing process, manufacturing costs can be reduced.

[0106] Alternatively, a conductive material containing the above-mentioned metal element and oxygen may be used. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Alternatively, a conductive material containing nitrogen, such as indium tin oxide (ITO), may be used. Indium Tin Oxide, Indium Zinc Oxide, Indium containing tungsten oxide Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, silicon-doped indium stannate Alternatively, nitrogen-containing indium gallium zinc oxide may be used.

[0107] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. As a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, In addition, the material containing the metal element, the conductive material containing oxygen, and the conductive material containing nitrogen may be used. A laminated structure combining conductive materials may also be used.

[0108] In this embodiment, each of the electrodes 107a and 107b has a three-layer laminate structure. However, one embodiment of the present invention is not limited to this example. 107b may each have a single layer structure or a double layer structure. It may have a laminated structure of more than one layer.

[0109] In order to reduce the resistance of the electrodes 107a and 107b, When copper is used for the electrode 107b, copper is likely to diffuse between the electrode 107a and the oxide semiconductor layer 106. It is preferable to provide a conductive material between the electrode 107b and the oxide semiconductor layer 106. It is preferable to provide a conductive material between the semiconductor layers that is difficult for copper to diffuse into. This may cause the operation of the semiconductor device to become unstable and significantly reduce the yield. By providing a conductive material that is difficult for copper to diffuse between the wiring or electrode containing copper and the semiconductor layer, This can improve the reliability of the transistor 100.

[0110] Examples of conductive materials into which copper is less likely to diffuse include tungsten, titanium, and tantalum. There are metal materials with higher melting points than copper, and nitride materials of these materials. The copper-containing electrode or wiring may be covered with a material. By covering or encasing the transistor 100 in a highly conductive material, the reliability of the transistor 100 can be further improved. This can be done.

[0111] Furthermore, the regions of the electrodes 107a and 107b in contact with the oxide semiconductor layer 106 are subjected to heat treatment. By using this process, the material becomes conductive and has the ability to absorb hydrogen, which allows the material to absorb the oxygen by subsequent heat treatment. The hydrogen concentration in the oxide semiconductor layer 106 can be reduced. Examples of conductive materials include titanium, indium zinc oxide, and silicon-doped indium. Examples include aluminum tin oxide.

[0112] [Oxide Semiconductor Layer] The oxide semiconductor layer 106 is preferably made of an oxide semiconductor. Since the band gap is 2 eV or more, when an oxide semiconductor is used for the oxide semiconductor layer 106, A transistor with extremely low off-state current can be realized. A transistor using an oxide semiconductor for a semiconductor layer (also called an OS transistor) has a high dielectric strength between the source and drain, providing a highly reliable transistor. It is also possible to provide a transistor with a large output voltage and high breakdown voltage. Furthermore, it is possible to provide a semiconductor device having a large output voltage and a high withstand voltage. It is possible.

[0113] The oxide semiconductor according to the present invention will be described. The oxide semiconductor contains at least indium. It is preferable that the alloy contains indium or zinc. It is particularly preferable that the alloy contains indium and zinc. In addition to these, aluminum, gallium, yttrium, or tin are also included. In addition, boron, silicon, titanium, iron, nickel, germanium, di Zr, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tantalum It may contain one or more selected from the group consisting of gusten, magnesium, etc. stomach.

[0114] Here, a case where the oxide semiconductor contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements M Applicable elements include boron, silicon, titanium, iron, nickel, germanium, and zinc. Zr, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tantalum However, the element M can be a combination of multiple of the above elements. There are cases where it is acceptable to do so.

[0115] First, with reference to FIGS. 18(A), 18(B), and 18(C), the oxide according to the present invention will be described. A preferred range of the atomic ratio of indium, element M, and zinc contained in the semiconductor will be explained. Note that the atomic ratio of oxygen is not shown in FIG. 18. The atomic ratios of indium, element M, and zinc are [In], [M], and Let it be [Zn].

[0116] In Figures 18(A), 18(B), and 18(C), the dashed lines represent the [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2 is n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4 atomic ratio line, and [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):5 is shown. .

[0117] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is :[M]:[Zn]=1:3:β atomic ratio line, [In]:[M]:[Zn] = 1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atoms The line where the atomic ratio is [In]:[M]:[Zn]=5:1:β Represents the

[0118] The dashed double-dashed line indicates the atomic number of [In]:[M]:[Zn]=(1+γ):2:(1-γ). The ratio (-1≦γ≦1) is shown. Oxide semiconductors with an atomic ratio of [n] = 0:2:1 or a value close to that have a spinel-type crystal structure Easy to take.

[0119] 18A and 18B show the indium-ion-containing oxide semiconductor of one embodiment of the present invention. 1 shows an example of a preferred range of the atomic ratio of um, element M, and zinc.

[0120] For example, when forming an oxide semiconductor film using a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the ratio of the target [Zn] of the film may be smaller than [Zn].

[0121] InMZnO is a layer containing indium and oxygen (hereinafter referred to as the In layer) and an element M, zinc. and a layer containing oxygen (hereinafter referred to as the (M,Zn) layer) are stacked. It is noted that indium and element M can be substituted for each other. Therefore, the element M in the (M,Zn) layer is replaced by indium, and the layer can be expressed as an (In,M,Zn) layer. can.

[0122] In addition, multiple phases may coexist in an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, in the atomic ratio [In]:[M]:[Zn]=0:2:1, which is close to the atomic ratio In this case, two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist. At the atomic ratio near the atomic ratio of [M]:[Zn]=1:0:0, Two phases, a cubic crystal structure and a layered crystal structure, tend to coexist. When they coexist, grain boundaries form between the different crystal structures. It may be formed.

[0123] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide semiconductor can be improved. This is because the oxide semiconductor containing indium, element M, and zinc can be In the body, the s orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the concentration, the overlapping area of ​​s orbitals becomes larger, so the indium content Oxide semiconductors with a high indium content have higher carrier mobility than oxide semiconductors with a low indium content. This is because it will be more expensive.

[0124] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0 and its In the atomic ratio having a value close to 0.5 (for example, region C shown in FIG. 18(C)), the insulating property becomes high.

[0125] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio shown in region A in FIG. 18(A) be such that a layered structure is easily formed. stomach.

[0126] Also, in region B shown in Figure 18(B), [In]:[M]:[Zn] = 4:2:3 to 4. 1 and its neighboring values. For example, the atomic ratio [In]:[M] :[Zn]=5:3:4. Oxide semiconductors having the atomic ratio shown in region B include In particular, it is an excellent oxide semiconductor having high crystallinity and high carrier mobility.

[0127] Note that the properties of an oxide semiconductor are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the oxide semiconductor may differ depending on the formation conditions. The region where the oxide semiconductor exhibits the atomic ratio tends to have specific properties. The boundaries between areas A and C are not strict.

[0128] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0129] Note that by using the oxide semiconductor in a transistor, carrier scattering at grain boundaries and the like can be prevented. This allows for the realization of transistors with high field-effect mobility. Furthermore, a highly reliable transistor can be realized.

[0130] In addition, it is preferable to use an oxide semiconductor with low carrier density for the transistor. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0131] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source. In addition, the carrier density can be reduced because the material is intrinsically or substantially pure. Since the density of defect states in an intrinsic oxide semiconductor is low, the density of trap states may also be low. There is a match.

[0132] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel is formed in an oxide semiconductor may have unstable electrical characteristics. do.

[0133] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0134] Here, the influence of each impurity in an oxide semiconductor will be described.

[0135] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in semiconductors. This causes defects in silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0136] In addition, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, it is preferable to use an alkali metal or alkali metal in an oxide semiconductor obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 Do the following:

[0137] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor is likely to be normally on. Therefore, it is preferable that the nitrogen content is reduced as much as possible. It is preferable that the nitrogen concentration in the oxide semiconductor is as low as possible. is 5×10 in SIMS. 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than, more Preferably 5 x 10 17 atoms / cm 3 Less than.

[0138] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, hydrogen in the oxide semiconductor It is preferable that hydrogen in the region where the channel is formed is reduced as much as possible. It is preferable that the hydrogen concentration in the oxide semiconductor is reduced as much as possible. In IMS, 1 x 10 20 atoms / cm 3 Less than 1 x 10 19 ato ms / cm 3 less than 5 × 10 18 atoms / cm 3Less than, even more preferred 1×10 18 atoms / cm 3 Less than.

[0139] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0140] For example, the oxide semiconductor layer 106 may be formed by thermal CVD using InGaZnO X (X>0) Film formation When forming a film, trimethylindium (In(CH3)3), trimethylgallium (G dimethylzinc (Zn(CH3)2) and dimethylzinc (Zn(CH3)2) are used. The combination is not limited to trimethylgallium, but may be replaced with triethylgallium (Ga(C2 H5)3) can also be used, and diethyl zinc (Zn(C2H5) 2) can also be used.

[0141] For example, the oxide semiconductor layer 106 may be formed by an ALD method using InGaZnO X (X>0) Film formation When depositing an InO2 layer, In(CH3)3 gas and O3 gas are introduced repeatedly in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a GaO layer. Then, Zn(CH3)2 gas and O3 gas are introduced repeatedly to form a ZnO layer. The order of these layers is not limited to this example. Mixing of GaO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. Alternatively, an inert gas such as Ar may be used instead of O3 gas to bubble the water. Although H2O gas containing H may be used, it is preferable to use O3 gas containing no H. Instead of In(CH3)3 gas, In(C2H5)3 gas or tris(acetylacetonate) ) indium may be used. Tris(acetylacetonato) indium is In Also called (acac)3. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas Tris(acetylacetonato)gallium or tris(acetylacetonato)gallium may also be used. Gallium nitrate is also called Ga(acac)3. It is also known as Zn(CH3)2 gas and Zinc acetate may also be used. The gas species are not limited to these.

[0142] When the oxide semiconductor layer 106 is formed by a sputtering method, the following steps are required to reduce the number of particles: It is preferable to use a target containing indium. Also, an oxide having a high atomic ratio of element M is preferable. When using a target, the conductivity of the target may be reduced. When a target is used, the conductivity of the target can be increased, and DC discharge and AC discharge can be used. This makes it easier to handle large-area substrates, and therefore improves the productivity of semiconductor devices. can be increased.

[0143] When the oxide semiconductor layer 106 is formed by sputtering, the atomic ratio of the target is I n:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1 :1:2, 1:1:1.2, 1:4:4, 4:2:4.1, 1:3:2, 1:3:4, 5 :1:6, 5:1:8, etc.

[0144] When the oxide semiconductor layer 106 is formed by a sputtering method, the atomic ratio of the target is different. In particular, zinc may form a film with a higher atomic ratio than the target. The atomic ratio of the film may become smaller. Specifically, the number of zinc atoms contained in the target The ratio may be between 40 atomic % and 90 atomic %.

[0145] The oxide semiconductor layer 106_1 is formed using, for example, an oxide semiconductor having a wide energy gap. The energy gap of the oxide semiconductor layer 106_1 is, for example, 2.5 eV or more and 4.2 eV or less. eV or less, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3. It should be 5 eV or less.

[0146] The oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 are It is formed from a material containing one or more of the same metal elements other than oxygen that constitute 1. When such a material is used, the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_4 can be easily formed. The interface with the oxide semiconductor layer 106_1, the oxide semiconductor layer 106_2, and the oxide semiconductor Therefore, the interface state at the interface with the layer 106_1 can be made difficult to occur. This makes it difficult for carriers to be scattered or captured, improving the field-effect mobility of transistors. It is also possible to reduce variations in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics.

[0147] In addition, the oxide semiconductor layer 106_1 is an In-M-Zn oxide (an oxide containing In, element M, and Zn). The oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 are also In-M- When the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 are made of Zn oxide, n:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 106_1 was In:M: If Zn=x2:y2:z2 [atomic ratio], it is preferable that y1 / x1 is greater than y2 / x2. The oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 106_3 are also increased in size. More preferably, y1 / x1 is 1.5 times or more larger than y2 / x2. The oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 106_3 are grown upward. More preferably, y1 / x1 is at least twice as large as y2 / x2. The oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor More preferably, y1 / x1 is three times or more larger than y2 / x2. The oxide semiconductor layer 106_3, the oxide semiconductor layer 106_2, and the oxide semiconductor layer 10 In this case, in the oxide semiconductor layer 106_1, y1 is equal to or greater than x1. It is preferable that y1 is greater than x1 because it can provide stable electrical characteristics to the transistor. If it is more than 5 times larger, the field effect mobility of the transistor will decrease, so y1 should be The thickness of the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2 is preferably less than 5 times. By configuring as above, the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_ The oxide semiconductor layer 106_2 can be a layer in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 106_1.

[0148] When the oxide semiconductor layer 106_3 is an In-M-Zn oxide, the sum of In and M is 1 When the atomic percentage of In is 0.00, it is preferable that In is less than 50 atomic percent and M is 50 atomic percent. more preferably, In is less than 25 atomic % and M is 75 atomic % or more. In addition, the oxide semiconductor layer 106_1 is made of an In-M-Zn oxide. When the sum of In and M is 100 atomic %, it is preferable that In is 25 atomic %. mic%, M is less than 75 atomic %, and more preferably In is 34 atomic % % and M is less than 66 atomic %. In the case of In-M-Zn oxide, when the sum of In and M is 100 atomic %, Preferably, In is less than 50 atomic % and M is higher than 50 atomic %, and more preferably Preferably, In is less than 25 atomic % and M is higher than 75 atomic %. The oxide semiconductor layer 106_2 may be formed using the same type of oxide as the oxide semiconductor layer 106_3. No.

[0149] For example, the oxide semiconductor layer 106_3 containing In or Ga and the oxide semiconductor layer 106_4 containing In or Ga The oxide semiconductor layer 106_2 is made of In:Ga:Zn=1:3:2, 1:3:4, or 1:3 Using targets with atomic ratios such as 1:6, 1:4:5, 1:6:4, or 1:9:6 The atomic ratio of the formed In-Ga-Zn oxides, In:Ga=1:9 or 7:93 In-Ga oxide formed using a target with the same ratio can be used. The semiconductor layer 106_1 may be, for example, In:Ga:Zn=1:1:1 or 3:1:2. In-Ga-Zn oxide formed using a target with any atomic ratio can be used. Note that the oxide semiconductor layer 106_3, the oxide semiconductor layer 106_1, and the oxide semiconductor The atomic ratio of the layer 106_2 is ±20% of the above atomic ratio as an error. Including fluctuations in

[0150] The oxide semiconductor layer 106_1 is formed by the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_ It is preferable to use an oxide having a higher electron affinity than that of the oxide semiconductor layer 1. 106_1, which is a layer having electrons larger than the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106_2. The affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, More preferably, an oxide having a larger value than the above by 0.15 eV or more and 0.4 eV or less may be used. Electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0151] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the oxide semiconductor layer 106_2 preferably contains indium gallium oxide. The gallium atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80%. More preferably, it is 90% or more.

[0152] However, the oxide semiconductor layer 106_3 and / or the oxide semiconductor layer 106_2 is / are not oxide gas. For example, gallium oxide may be used as the oxide semiconductor layer 106_3. When the oxide semiconductor layer 106 is used, leakage current occurring between the electrode 102 and the oxide semiconductor layer 106 can be reduced. That is, the off-state current of the transistor 100 can be reduced.

[0153] At this time, when a gate voltage is applied, the oxide semiconductor layer 106_3 and the oxide semiconductor layer 106 _1, the oxide semiconductor layer 106_1 having a large electron affinity among the oxide semiconductor layers 106_2 A channel is formed in the

[0154] In order to provide stable electrical characteristics to an OS transistor, impurities and and oxygen vacancies are reduced to make at least the oxide semiconductor layer 106_1 highly purified and intrinsic. It is preferable that the oxide semiconductor layer be an oxide semiconductor layer that can be regarded as substantially intrinsic. The channel forming region in the compound semiconductor layer 106_1 is a semiconductor that can be regarded as intrinsic or substantially intrinsic. It is preferable to form the layer.

[0155] [Classification of oxide semiconductor films] Next, the division of the oxide semiconductor film will be described.

[0156] The oxide semiconductor film is classified into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. As a non-single-crystal oxide semiconductor film, CAAC-OS (c-axis-aligned oxide semiconductor) gned crystalline oxide semiconductor) film, Crystalline oxide semiconductor film, nc-OS (nanocrystalline oxide semiconductor) semiconductor film, pseudo-amorphous oxide semiconductor (a-like OS: amor phos-like oxide semiconductor) film and amorphous oxide Semiconductor films and the like.

[0157] From another point of view, the oxide semiconductor film can be classified into an amorphous oxide semiconductor film and a crystalline oxide semiconductor film. Crystalline oxide semiconductor films are classified into single-crystal oxide semiconductor films and Examples of such films include a CAAC-OS film, a polycrystalline oxide semiconductor film, and an nc-OS film.

[0158] Amorphous structures are generally isotropic and have no heterogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and there is short-range order but no long-range order. It is said that...

[0159] That is, a stable oxide semiconductor film is formed into a completely amorphous In addition, the film is not isotropic (for example, in a small area, An oxide semiconductor film having a periodic structure cannot be called a completely amorphous oxide semiconductor film. On the other hand, the a-like OS film is not isotropic but has unstable voids. In terms of instability, the a-like OS film is physically an amorphous acid. It is similar to a compound semiconductor film.

[0160] [CAAC-OS] The CAAC-OS film is an oxide film having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor film.

[0161] The CAAC-OS film is an oxide semiconductor film with high crystallinity. The CAAC-OS film is often deteriorated by impurities or defects. It can also be said that the oxide semiconductor film has few defects (such as oxygen vacancies).

[0162] Note that the impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more likely to be present than metal elements constituting the oxide semiconductor film. An element that has a strong bond to oxygen can remove oxygen from the oxide semiconductor film and become an element of the oxide semiconductor film. In addition, heavy metals such as iron and nickel, and aluminum Carbon dioxide and other carbon-dioxide species have large atomic radii (or molecular radii), so they are difficult to form oxide semiconductor films. This disrupts the atomic arrangement and causes a decrease in crystallinity.

[0163] [nc-OS] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0164] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a higher defect density than the a-like OS film and the amorphous oxide semiconductor film. However, the nc-OS does not show regularity in the crystal orientation between different pellets. Therefore, the nc-OS may have a higher density of defect states than the CAAC-OS. do.

[0165] [a-like OS] The a-like OS film has a structure between the nc-OS film and the amorphous oxide semiconductor film. It is a nitride semiconductor film.

[0166] A-like OS has porosity or low density areas. A-like OS has porosity Therefore, it is an unstable structure.

[0167] In addition, a-like OS has porosity, so compared to nc-OS and CAAC-OS, It is a low-density structure. Specifically, the density of a-like OS is The density of nc-OS and CAAC-O is 78.6% or more and less than 92.3%. The density of S is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a conductivity of less than 78%.

[0168] For example, in an oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 is less than. For example, in an oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1, The densities of nc-OS and CAAC-OS are 5.9 g / cm 3 More than 6.3g / c m 3 is less than.

[0169] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to that of a single crystal with a desired composition. The density corresponding to a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions combined. The density can be estimated using a weighted average. However, the density should be calculated by combining as few types of single crystals as possible. It is preferable to estimate them together.

[0170] As described above, oxide semiconductor films have various structures and each structure has various characteristics. Note that the oxide semiconductor film of one embodiment of the present invention can be formed using an amorphous oxide semiconductor, an a-like OS, Two or more of the nc-OS and CAAC-OS may be mixed.

[0171] [Film formation method] The insulating layer, the conductive layer for forming electrodes and wiring, and the semiconductor layer are formed by sputtering. , spin coating method, CVD (Chemical Vapor Deposition) method (Thermal CVD method, MOCVD (Metal Organic Chemical Vapo r Deposition) method, PECVD (Plasma Enhanced CVD) ) method, high density plasma CVD method, LPCVD method (low pressure CVD), APCVD method (atmosphere ric pressure CVD), ALD (Atomic Layer Deposition) Deposition) method or MBE (Molecular Beam Epitaxial axy) method or PLD (Pulsed Laser Deposition) method, Dip method, spray coating method, droplet ejection method (inkjet method, etc.), printing method (screen The printing method can be used for forming the pattern.

[0172] The plasma CVD method can produce high-quality films at relatively low temperatures. When a film formation method that does not use plasma, such as a thermal CVD method, is used, damage to the surface to be formed is generated. For example, wiring, electrodes, and elements (transistors, Capacitor elements may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge can damage the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage can occur. Since no image is generated, the yield of the semiconductor device can be increased. Since no plasma damage occurs, films with few defects can be obtained.

[0173] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases, this is preferable.

[0174] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having a composition. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by hand, the time required for film formation is shortened by the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0175] When forming a film by the ALD method, a gas containing no chlorine should be used as the source gas. is preferred.

[0176] In addition, when an oxide semiconductor is formed by a sputtering method, The chamber is cryo-treated to remove as much water as possible, which is an impurity for oxide semiconductors. A high vacuum (5 x 10) was created using a vacuum pump of the adsorption type. -7 Pa to 1 x 10 -4 It is preferable to evacuate the air to a pressure of about 100 Pa. The gas molecules equivalent to H2O (gas molecules equivalent to m / z = 18) in the chamber Divide the pressure by 1×10 -4 Pa or less, preferably 5 x 10 -5 It is preferable to set it to Pa or less.

[0177] In addition, the sputtering gas must be highly purified. The oxygen gas or argon gas used has a dew point of -40°C or less, preferably -80°C or less, more preferably Preferably, a gas purified to a temperature of -100°C or less, more preferably -120°C or less, is used. By doing so, moisture and the like can be prevented from being taken into the oxide semiconductor film as much as possible.

[0178] In addition, when forming an insulating layer, a conductive layer, a semiconductor layer, or the like by sputtering, oxygen is By using a sputtering gas containing oxygen, it is possible to supply oxygen to the layer to be formed. The more oxygen contained in the tartering gas, the more oxygen is likely to be supplied to the layer to be formed. .

[0179] <Example of a method for manufacturing the transistor 100> An example of a method for manufacturing the transistor 100 shown in FIGS. 1 and 2 will be described with reference to FIGS. 7A to 7D. ), FIGS. 8(A) to 8(C), FIGS. 9(A) to 9(C), and FIGS. 10(A) to 10(C). 7(A) to 7(D), 8(A) to 8(C), and The X1-X2 cross section in Figs. 9(A) to 9(C) and Figs. 10(A) to 10(C) is This corresponds to the cross section of the region indicated by the dashed line X1-X2 in 1(A).

[0180] [Process 1] First, a conductive layer 181 for forming an electrode 102 is formed on a substrate 101 (FIG. 7(A)). In this embodiment, aluminoborosilicate glass is used as the substrate 101. In this embodiment, the conductive layer 181 is made of a titanium layer having a thickness of 50 nm and a SiO 2 layer having a thickness of 200 nm. The copper layer and the copper layer are formed in this order by sputtering.

[0181] [Process 2] Next, a resist mask is formed (not shown). The resist mask is formed by photolithography. This can be carried out by appropriately using a lithography method, a printing method, an inkjet method, or the like. When a mask is formed by printing or inkjet methods, no photomask is used, reducing manufacturing costs. This can reduce costs.

[0182] The formation of a resist mask by photolithography involves applying a photomask to a photosensitive resist. The exposed area (or the unexposed area) is then resist-deposited using a developer. The light irradiated onto the photosensitive resist is a KrF excimer laser. light, ArF excimer laser light, EUV (Extreme Ultraviolet) light There is also the liquid immersion method, in which exposure is performed by filling the space between the substrate and the projection lens with liquid (for example, water). In addition, instead of the light mentioned above, an electron beam or an ion beam may be used. When an electron beam or an ion beam is used, the photomask becomes unnecessary.

[0183] Using the resist mask as a mask, part of the conductive layer 181 is selectively removed to form an electrode The conductive layer 181 is removed by dry etching or The dry etching method and the wet etching method can be used. Alternatively, both a thermal etching method and a thermal etching method may be used.

[0184] After part of the conductive layer 181 is removed, the resist mask is removed. Dry etching such as ashing or wet etching using a dedicated stripping solution This can be done by both dry and wet etching methods. Good too.

[0185] It is also preferable that the cross-sectional shape of the side surface of the electrode 102 is tapered. The taper angle θ is preferably 20° or more and less than 90°, and more preferably 30° or more and less than 80°. The taper angle θ is preferably 40° or more and less than 70°. When a layer having the above structure is observed from the cross section (a plane perpendicular to the surface of the substrate), the side and bottom of the layer are Indicates the angle between the faces.

[0186] By providing a tapered shape to the side surface of the electrode 102, it is possible to prevent the layer formed thereon from being cut off. In addition, the side surface of the electrode 102 is tapered. This can alleviate the electric field concentration at the upper end of the electrode 102. On the other hand, if the taper angle θ is too small, If the taper angle θ is too small, it may be difficult to miniaturize the transistor. There may be large variations in the size of the openings and the width of the wiring.

[0187] The side surface of the electrode 102 may be formed in a stepped shape. This can prevent the layer from being cut off and improve the coverage. In addition, by making the end of each layer tapered or stepped, the layer coated thereon can be This can prevent the phenomenon in which the coating is broken (step breaks) and improve the coating properties.

[0188] [Process 3] Next, the insulating layer 103, the insulating layer 104, and the insulating layer 105 are formed in this order (see FIG. 7(C)). In this embodiment, a silicon nitride layer having a thickness of 400 nm is formed as the insulating layer 103. Then, an aluminum oxide layer having a thickness of 30 nm is formed as the insulating layer 104, and a SiO 2 layer is formed as the insulating layer 105. A silicon oxynitride layer having a thickness of 50 nm is formed.

[0189] The silicon nitride layer used for the insulating layer 103 is a first silicon nitride layer and a second silicon nitride layer. The three-layer stack structure includes a silicon layer, a third silicon nitride layer, and a third silicon nitride layer. For example, it can be formed as follows.

[0190] The first silicon nitride layer is formed by, for example, silane at a flow rate of 200 sccm, ccm of nitrogen and 100 sccm of ammonia gas were used as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a high frequency of 27.12 MHz was generated. A power of 2000 W is supplied using a microwave power supply, and the thickness is formed to be 50 nm. stomach.

[0191] For the second silicon nitride layer, silane at a flow rate of 200 sccm and Nitrogen and ammonia gas at a flow rate of 2000 sccm were used as source gases for the reaction in the PECVD equipment. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply was used. A power of 2000 W may be supplied using the above method to form a film having a thickness of 300 nm.

[0192] For the third silicon nitride layer, silane at a flow rate of 200 sccm and silane at a flow rate of 5000 sccm m of nitrogen was supplied as a source gas to the reaction chamber of the PECVD device, and the pressure in the reaction chamber was maintained at 100 P a, and a power of 2000 W was supplied using a 27.12 MHz high frequency power supply. It is sufficient to form it so that the thickness is 50 nm.

[0193] The first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are The substrate temperature during the growth can be set to 350° C. or less.

[0194] By forming the silicon nitride layer into the above-mentioned three-layer laminated structure, for example, a conductive material containing copper can be formed in the electrode 102. When the conductive layer is used, the following effects are achieved.

[0195] The first silicon nitride layer can suppress the diffusion of copper elements from the electrode 102. The silicon nitride layer has the function of releasing hydrogen and is an insulating layer that functions as a gate insulating layer. The third silicon nitride layer can improve the breakdown voltage. The hydrogen release is small and the diffusion of the hydrogen released from the second silicon nitride layer can be prevented. can.

[0196] As described above, the insulating layer 104 is formed using an insulating material that is difficult for impurities to penetrate. It is also preferable that the insulating layer 104 be formed using an insulating material through which oxygen does not easily diffuse. The aluminum oxide layer used for the insulating layer 104 is preferably formed by depositing an aluminum target. It may be formed by DC sputtering using an aluminum oxide target. It may be formed by AC sputtering or ALD.

[0197] The insulating layer 105 is preferably an insulating layer containing excess oxygen. Alternatively, a heat treatment may be performed after the formation of the insulating layer 105 to remove the insulating layer 105. It is preferable to reduce the hydrogen and moisture contained in the SiO2. The oxygen doping process may be performed by, for example, heating the substrate to 400° C. and This can be done by exciting oxygen-containing gas at a frequency of 2.45 GHz. The process may be repeated multiple times.

[0198] In addition, the insulating layer 105 is exposed to a plasma atmosphere of nitrogen or an inert gas. Impurities such as hydrogen and carbon on the surface and near the surface can be reduced. The plasma was heated to 400°C and excited at a frequency of 2.45 GHz in a gas containing argon and nitrogen. This can be achieved by exposing the insulating layer 105 to the turbulent atmosphere.

[0199] The heat treatment may be carried out, for example, in an inert atmosphere containing nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-high pressure atmosphere. Dry air (measured using a CRDS (cavity ring-down laser spectroscopy) type dew point meter) When measured, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less The oxidation is preferably carried out in an atmosphere of 10 ppb or less of air. An atmosphere containing 10 ppm or more of oxidizing gases such as oxygen, ozone, or nitrogen dioxide. In addition, "inert atmosphere" means an atmosphere in which the above-mentioned oxidizing gases are less than 10 ppm, and other There are no particular restrictions on the pressure during the heat treatment, but The treatment is preferably carried out under reduced pressure.

[0200] The heat treatment is carried out at a temperature of 150°C or higher but lower than the strain point of the substrate, preferably 200°C or higher but 500°C or lower, more preferably More preferably, the treatment is carried out at a temperature of 250° C. to 400° C. The treatment time is within 24 hours. Heat treatment for more than 24 hours is not preferable because it reduces productivity.

[0201] The heat treatment can be carried out using an electric furnace, an RTA device, or the like. By using this method, it is possible to perform heat treatment at a temperature above the distortion point of the substrate for a short period of time. Therefore, it is possible to shorten the heating time. It is preferable that the rare gas does not contain hydrogen, water, or the like.

[0202] [Step 4] Next, the oxide semiconductor layer 182 and the oxide semiconductor layer 183 are formed in this order (see FIG. 7D). Before the oxide semiconductor layer 182 is formed, oxygen gas is supplied to generate plasma. As a result, the oxide semiconductor layer 182 may be formed on the insulating layer 105. Oxygen can be added.

[0203] The oxide semiconductor layer 182 may be made of indium zinc oxide or a material having a composition of In:Ga:Zn=5. Indium gallium zinc oxide formed using a target with an atomic ratio of 1:6, Insulators formed using a target with a composition of In:Ga:Zn=4:2:3 [atomic ratio] It is preferable to use gallium zinc oxide or the like.

[0204] In this embodiment, the oxide semiconductor layer 182 is made of indium gallium zinc oxide. was deposited by sputtering using a target with an atomic ratio of In:Ga:Zn=5:1:6. In addition, oxygen or a mixture of oxygen and rare gas is used as the sputtering gas. In this embodiment, a mixture of oxygen and aluminum with a flow rate ratio of 10% is used as the sputtering gas. It uses a mixture of gon gases.

[0205] The flow rate ratio of oxygen contained in the sputtering gas is set to 0% or more and 30% or less, preferably 5% or more. When the concentration is 20% or less, an oxygen-deficient oxide semiconductor layer is formed. A transistor including an oxide semiconductor layer can have relatively high field-effect mobility.

[0206] In addition, when the oxide semiconductor layer 182 is formed, part of the oxygen contained in the sputtering gas is insulated. The more oxygen contained in the sputtering gas, the better the insulating layer 105 will be. The oxygen supplied to the insulating layer 105 also increases. The hydrogen reacts with the hydrogen remaining in the insulating layer 105 to form water, which is then removed from the insulating layer 105 by a subsequent heat treatment. In this way, the hydrogen concentration in the insulating layer 105 can be reduced. By increasing the excess oxygen in the insulating layer 105, the oxide semiconductor layer 18 Oxygen can also be supplied to the oxide semiconductor layer 106_1 (later formed oxide semiconductor layer 106_1).

[0207] The oxide semiconductor layer 183 has a composition of In:Ga:Zn=5:1:6 [atomic ratio]. ], In:Ga:Zn=4:2:3 [atomic ratio], or In:Ga:Zn=1:1:1 [Atomic ratio] and other targets were used. It is preferable that

[0208] The oxide semiconductor layer 183 is preferably an oxide semiconductor layer with high crystallinity. For example, it is preferable to use CAAC-OS for the oxide semiconductor layer 183. For example, the etching process for forming the electrodes 107a and 107b to be performed later During this process, the exposed oxide semiconductor layer is etched, causing damage to the oxide semiconductor layer. An oxide semiconductor layer with high crystallinity may be etched in the etching step. By using an oxide semiconductor layer with high crystallinity as the oxide semiconductor layer 183, Damage to the oxide semiconductor layer in the etching process can be reduced. This can improve the reliability of the system.

[0209] In this embodiment, CAAC-OS is used for the oxide semiconductor layer 183. Specifically, Indium gallium zinc oxide has a composition of In:Ga:Zn=1:1:1 [atomic ratio] The film is formed by sputtering using a target. In this embodiment, a sputtering gas is used as the sputtering gas. The sputtering for forming the oxide semiconductor layer 183 is carried out using 100% oxygen. The flow rate ratio of oxygen contained in the heating gas is preferably 70% or more, and more preferably 80% or more. The ratio of oxygen contained in the sputtering gas (flow rate ratio) is preferably high. By doing so, the crystallinity of the oxide semiconductor layer can be improved.

[0210] Note that by introducing an impurity element after the formation of the oxide semiconductor layer 183, The threshold voltage of 0 can be changed. The introduction of impurity elements can be performed by ion implantation, ion implantation, doping method, or plasma immersion ion implantation method, or gas containing impurity elements This can be done by plasma treatment using a gas.

[0211] After the oxide semiconductor layer 183 is formed, heat treatment may be performed or oxygen doping treatment may be performed. The heat treatment and oxygen doping treatment may be repeated multiple times.

[0212] In addition, after heat treatment in a nitrogen or rare gas atmosphere, the material is dried in an oxygen or ultra-dry air atmosphere. Heat treatment may be performed. As a result, hydrogen, water, and the like contained in the oxide semiconductor layer are released. At the same time, oxygen can be supplied to the oxide semiconductor layer. The oxygen vacancies contained therein can be reduced.

[0213] [Step 5] Next, a resist mask is formed by photolithography (not shown). The oxide semiconductor layer 182 and the oxide semiconductor layer 183 were formed by using a mask as a mask. The oxide semiconductor layer 106_1 and the oxide semiconductor layer 106_2 are selectively removed. 106_2 is formed (see FIG. 8(A)).

[0214] After the oxide semiconductor layer 106_1 and the oxide semiconductor layer 106_2 are formed, heat treatment is performed. Alternatively, the heat treatment and the oxygen doping treatment may be repeated. good.

[0215] [Step 6] Next, a conductive layer 184 and a conductive layer 185 are formed in this order (see FIG. 8(B)). The oxide semiconductor layer 84 is in contact with the oxide semiconductor layer 106 and has a function of absorbing hydrogen by heat treatment. By using such a material for the conductive layer 184, The hydrogen concentration in the oxide semiconductor layer 106 can be reduced by the subsequent heat treatment. Examples of conductive materials that have the function of absorbing oxygen include titanium, indium zinc oxide, silicon dioxide, and silicon dioxide. Examples include silicon-doped indium tin oxide.

[0216] In this embodiment, a titanium layer having a thickness of 30 nm is formed as the conductive layer 184, and a conductive layer 185 is formed as the conductive layer 185. A copper layer having a thickness of 200 nm is formed as the insulating layer by sputtering.

[0217] [Step 7] Next, a resist mask is formed by photolithography (not shown). Using the mask as a mask, a portion of the conductive layer 185 is selectively removed to form the electrode 107. a_2 and an electrode 107b_2 are formed (see FIG. 8(C)).

[0218] The conductive layer 185 is removed by dry etching or wet etching. Both dry etching and wet etching may be used.

[0219] [Step 8] Next, the conductive layer 186 is formed (see FIG. 9A). In this embodiment, the conductive layer 186 A titanium layer having a thickness of 10 nm is formed as a result.

[0220] [Step 9] Next, a resist mask is formed by photolithography (not shown). Using the mask as a mask, a portion of the conductive layer 184 and the conductive layer 186 are selectively removed. Remove the electrodes 107a_1, 107a_3, 107b_1, and 107b_2. In this way, the electrode 107a and the electrode 107b are formed (see FIG. 9(B)). is formed.

[0221] The conductive layer 184 and the conductive layer 185 can be removed by dry etching or wet etching. Both dry etching and wet etching methods can be used. may also be used.

[0222] When a part of the conductive layer 184 and the conductive layer 185 is removed by dry etching, the exposed The oxide semiconductor layer 106_2 and the insulating layer 105 are free of impurities such as residual components of the etching gas. For example, if a chlorine-based gas is used as the etching gas, salt elements may adhere to the surface. In addition, if a hydrocarbon gas is used as the etching gas, Carbon, hydrogen, etc. may adhere.

[0223] Therefore, impurities attached to the exposed surfaces of the oxide semiconductor layer 106_2 and the insulating layer 105 are It is preferable to reduce the amount of pure elements. The reduction of impurities can be achieved by, for example, using diluted hydrofluoric acid. Cleaning treatment using ozone, ultraviolet light, etc. Alternatively, plasma treatment using an oxidizing gas may be performed. For example, nitrous oxide gas may be used. By performing the plasma treatment, the exposed surface It can reduce fluorine and other substances adhering to the surface. It also has the effect of removing organic matter. It is also possible to combine multiple cleaning processes. That's fine.

[0224] [Step 10] Next, the insulating layer 108 and the insulating layer 109 are formed in this order (see FIG. 9(C)). The insulating layer 109 is preferably formed continuously without being exposed to the air midway.

[0225] The insulating layer 108 is preferably an insulating layer containing excess oxygen. The thickness of the insulating layer 108 is 5n The thickness of the insulating layer may be from 100 nm to 150 nm, preferably from 5 nm to 50 nm. By using an insulating layer that can transmit oxygen as 108, the insulating layer 1 Oxygen contained in O9 can be moved to the oxide semiconductor layer 106.

[0226] For example, a silicon oxynitride layer formed by PECVD may be used as the insulating layer 108. In this case, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of silicon-containing deposition gases include silane, disilane, Examples of oxidizing gases include nitrous oxide and nitrogen dioxide. In addition, the flow rate of the oxidizing gas is set to 20 times or more, 5000 times, the flow rate of the deposition gas. times or less, preferably 40 times or more and 100 times or less.

[0227] In this embodiment, a silicon oxynitride layer having a thickness of 30 nm is formed as the insulating layer 108. Specifically, the substrate temperature was set to 350°C, and silane with a flow rate of 20 sccm and 3000 The source gas was dinitrogen monoxide at a flow rate of 100 sccm, the pressure in the processing chamber was set to 200 Pa, and a parallel plate The PECVD method was used with a high frequency power of 13.56 MHz and 100 W supplied to the electrode. A silicon nitride layer is formed.

[0228] The insulating layer 109 is preferably an insulating layer containing excess oxygen. The thickness may be set to 500 nm or more, and preferably 400 nm or more.

[0229] Furthermore, it is preferable that the insulating layer 109 has a small number of defects. , the spin density of the signal at g=2.001 originating from silicon dangling bonds is 1.5×10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 Below Note that the insulating layer 109 is preferably made of an oxide semiconductor, as compared with the insulating layer 108. Because it is further away from layer 106 , it may have a higher defect density than insulating layer 108 .

[0230] The insulating layer 109 can be a silicon oxynitride layer formed by PECVD. For example, a substrate placed in a vacuum-evacuated processing chamber of a PECVD device is heated to 180°C or higher for 4 The temperature is kept at 00°C or lower, and the raw material gas is introduced into the processing chamber to reduce the pressure in the processing chamber to 100 Pa or lower. The pressure in the processing chamber is set to 250 Pa or less, and more preferably 100 Pa or more and 200 Pa or less. 0.17W / cm 2 More than 0.5W / cm 2 or less, more preferably 0.2 5W / cm 2 More than 0.35W / cm 2 Under the following conditions for supplying high frequency power, silicon oxide A silicon layer or silicon oxynitride layer is formed.

[0231] In forming the insulating layer 109, high frequency power with the above power density is supplied in a reaction chamber with the above pressure. By doing so, the decomposition efficiency of the source gas in the plasma is increased. As a result, the oxygen content in the insulating layer 109 increases. The amount is greater than the stoichiometric composition.

[0232] In addition, in the insulating layer formed at the above substrate temperature, the bonding strength between silicon and oxygen is weak, so The heat treatment in this step causes some of the oxygen in the insulating layer to be released. It contains more oxygen than the oxygen that fills the space, and forms an oxide insulating layer in which some of the oxygen is released when heated. It can be achieved.

[0233] In this embodiment, a silicon oxynitride layer having a thickness of 100 nm is formed as the insulating layer 109. Specifically, the substrate temperature was set to 220° C., and silane was used at a flow rate of 160 sccm and 40 The source gas was nitrous oxide at 0.00 sccm, the pressure in the processing chamber was 200 Pa, and the parallel parallel The PECVD method was used, with the high frequency power supplied to the plate electrode being 13.56 MHz and 1500 W. A silicon oxynitride layer is formed.

[0234] In the step of forming the insulating layer 109, the insulating layer 108 is a protective layer for the oxide semiconductor layer 106. Therefore, it is possible to reduce damage to the oxide semiconductor layer 106 while achieving a high power density. The insulating layer 109 can be formed using low high frequency power.

[0235] In the formation conditions of the insulating layer 109, the deposition gas containing silicon is used in place of the oxidizing gas. By increasing the flow rate, it is possible to reduce the number of defects in the insulating layer 109. appears at g=2.001 due to the dangling bond of silicon by ESR measurement. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 s pins / cm 3 Less than or equal to 1.5 × 10 17 spins / cm 3 Defects that are less than As a result, the reliability of the transistor can be improved. It can be done.

[0236] [Step 11] Next, a heat treatment is carried out in an inert atmosphere to remove the oxides contained in the insulating layers 108 and 109. This reduces impurities such as hydrogen and moisture that are present in the gas. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment is carried out (see FIG. 10(A)).

[0237] [Step 12] Subsequently, a heat treatment is performed in an oxidizing atmosphere. In this embodiment, the heat treatment is performed in an oxygen atmosphere at 400 ℃ for 1 hour (see Figure 10 (B)). In this case, part of the oxygen contained in the insulating layer 108 and / or the insulating layer 109 is converted into an oxide semiconductor layer. By moving the oxygen atoms to the oxide semiconductor layer 106, oxygen vacancies in the oxide semiconductor layer 106 can be reduced. Either step 11 or step 12 may be omitted.

[0238] [Step 13] Next, the insulating layer 110 is formed (see FIG. 10(C)). As described above, the insulating layer 110 It is preferable to form the insulating layer 11 using an insulating material that is difficult for impurities to penetrate. The insulating layer 110 is preferably formed using an insulating material that does not easily diffuse oxygen. The thickness may be between 5 nm and 40 nm.

[0239] In this embodiment, an aluminum oxide layer having a thickness of 30 nm is formed as the insulating layer 110 by sputtering. The sputtering gas is oxygen or a mixture of oxygen and rare gas. The flow rate ratio of oxygen contained in the sputtering gas is preferably 70% or more. The oxygen content is preferably 80% or more, and more preferably 100%. By using the sputtering method, oxygen can be supplied to the layer to be formed (the insulating layer 109). The more oxygen contained in the gas, the more oxygen is likely to be supplied to the layer to be formed. In this embodiment, 100% oxygen is used as the sputtering gas.

[0240] The aluminum oxide layer used for the insulating layer 110 is formed by DC spat using an aluminum target. It may be formed by a sputtering method, or by AC sputtering using an aluminum oxide target. Alternatively, the film may be formed by a coating method.

[0241] The insulating layer 110 may be a silicon nitride layer that does not contain or contains little hydrogen. Such a silicon nitride layer may be formed by, for example, a sputtering method. It is possible.

[0242] When the insulating layer 111 is formed on the insulating layer 110, the insulating layer 111 is made of aluminum oxide. The thickness of the insulating layer 111 is preferably 5 nm to 40 nm. By forming an aluminum oxide layer using the ALD method, an oxide layer with good coating properties can be obtained. Therefore, the reliability of the transistor can be improved. Alternatively, the insulating layer 111 may be a silicon nitride layer.

[0243] Steps 11 to 13 are carried out consecutively without exposing the material to the atmosphere. This prevents the adsorption of hydrogen, moisture, and the like, thereby improving the reliability of the transistor. Furthermore, by covering the oxide semiconductor layer 106 with the insulating layer 110, it is possible to prevent infiltration of hydrogen, moisture, etc. from the outside. In addition, oxygen can be prevented from diffusing to the outside.

[0244] <Modifications of the Transistor 100> Modifications of the transistor 100 will be described with reference to the drawings.

[0245] [Variation 1] 11A is a plan view of the transistor 100A. 11(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 1 is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG.

[0246] In the transistor 100A, when viewed in a plan view, the region surrounding the oxide semiconductor layer 106 is The transistor 100 differs from the transistor 100 in that it has an insulating layer 105 and an insulating layer 123. Layer 108 and insulating layer 109 have been removed, leaving insulating layer 104 and insulating layer 110 in contact.

[0247] By providing the region 123, it is possible to improve the effect of preventing the intrusion of hydrogen, moisture, etc. from the outside. In addition, the effect of preventing oxygen from diffusing to the outside can be improved.

[0248] [Variation 2] 12(A) is a plan view of the transistor 100B. 12(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 12(A) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. FIG. 13(B) is an enlarged view of the area 131B shown in FIG. 12(C). 132B is an enlarged view.

[0249] The transistor 100B has the same stacking order of the insulating layer 108 and the insulating layer 110 as the transistor 10 The transistor 100B is formed by sputtering using a sputtering gas containing oxygen. When the insulating layer 110 is formed by the deposition method, oxygen can be supplied to the insulating layer 105. In addition, oxygen can be supplied to part of the oxide semiconductor layer 106.

[0250] [Variation 3] FIG. 14A is a plan view of the transistor 100C. FIG. 14B is a plan view of the transistor 100C. 14(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 14(A) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. FIG. 15(B) is an enlarged view of the area 131C shown in FIG. 14(C). This is an enlarged view of 132C.

[0251] The transistor 100C differs from the transistor 100A in the shape of the insulating layer 105. The transistor 100C has an island-shaped insulating layer 105 overlapping with the oxide semiconductor layer 106. The insulating layer 105 is formed by removing the exposed insulating layer 105 when the oxide semiconductor layer 106 is formed in step 5. can be formed by successively removing portions of

[0252] In the transistor 100C, the insulating layer 110 and the insulating layer 104 are formed on the oxide semiconductor layer 106. The insulating layer 105 has an end portion and an area extending beyond the end portion of the insulating layer 105 where the insulating layer 105 and the insulating layer 105 are in contact with each other. This configuration can enhance the effect of preventing the intrusion of hydrogen, moisture, etc. from the outside. In addition, the effect of preventing oxygen from diffusing to the outside can be enhanced.

[0253] The insulating layer 110 is made of an insulating material that is difficult for impurities to penetrate, such as aluminum oxide. By using this, even if a conductive layer containing copper is used for the electrode 107a_2, the electrode 107a_3 Therefore, the manufacturing cost can be reduced.

[0254] [Variation 4] FIG. 16A is a plan view of the transistor 100D. FIG. 16B is a plan view of the transistor 100D. FIG. 16(C) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 16(A) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. FIG. 17(B) is an enlarged view of the area 131D shown in FIG. 16(C). This is an enlarged view of 132D.

[0255] The transistor 100D differs from the transistor 100B in the shape of the insulating layer 110. In the transistor 100D, a part of the insulating layer 110 is removed, and the oxide semiconductor layer 106 and the insulating layer 10 With this structure, excess oxygen in the insulating layer 108 is oxidized. The oxide semiconductor layer 106 can be efficiently supplied with the oxygen.

[0256] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0257] (Embodiment 2) A transistor 200 of one embodiment of the present invention will be described with reference to drawings.

[0258] <Structural example of transistor 200> FIG. 19(A) is a plan view of a transistor 200. FIG. 19(B) is a plan view of the transistor 200 shown in FIG. 19(C) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 20 is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. 2 is an enlarged view of the portion 231.

[0259] The transistor 200 is a type of top-gate transistor. , an electrode 102, an insulating layer 103, an insulating layer 104, an insulating layer 105, an oxide semiconductor layer 106, Insulating layer 108, insulating layer 109, electrode 112, insulating layer 110, insulating layer 113, electrode 114a (electrodes 114a_1 and 114a_2), and electrodes 114b (electrodes 114b_1 and electrode 114b_2).

[0260] The electrode 102 is provided on the substrate 101. The insulating layer 103 is provided to cover the electrode 102. The insulating layer 104 is provided on the insulating layer 103. The insulating layer 105 is an insulating The oxide semiconductor layer 106 is provided on the insulating layer 105. The electrode 102 and the oxide semiconductor layer 106 are formed between the insulating layer 103, the insulating layer 104, and the insulating layer 106. They have an overlapping area with the insulating layer 105 interposed therebetween.

[0261] The insulating layer 108 is provided on the oxide semiconductor layer 106. The insulating layer 109 is an insulating The electrode 112 is disposed on the insulating layer 109. The layer 108, the insulating layer 109, and the electrode 112 have an area overlapping with the oxide semiconductor layer 106. The insulating layer 110 is formed by stacking the insulating layer 105, the oxide semiconductor layer 106, the insulating layer 108, and the insulating layer 110. The insulating layer 113 is provided on the insulating layer 110. It is being done.

[0262] The electrodes 114a (electrodes 114a_1 and 114a_2) are provided on the insulating layer 113. The electrode 114a is formed through an opening provided in the insulating layer 113 and the insulating layer 110. The electrode 114b is electrically connected to a part of the oxide semiconductor layer 106. The electrodes 114b_1 and 114b_2 are provided on the insulating layer 113. 4b is an oxide semiconductor film formed in the openings in the insulating layer 113 and the insulating layer 110. It is electrically connected to another part of the conductor layer 106 .

[0263] When the insulating layer 108 and the insulating layer 109 are made of the same material, the insulating layer 108 and the insulating layer 109 Therefore, in this embodiment, the interface between the insulating layer 108 and the insulating layer 108 may not be clearly visible. The interface between the insulating layer 108 and the insulating layer 109 is indicated by a broken line. Although the two-layer structure of the edge layer 109 has been described, one embodiment of the present invention is not limited to this. For example, , a single layer structure of either the insulating layer 108 or the insulating layer 109, or a laminated structure of three or more layers. It may also be constructed as such.

[0264] As shown in FIG. 21, an insulating layer 111 may be provided on the insulating layer 110. FIG. 21(A) is a plan view of the transistor 200. FIG. 21(B) shows the X 21(C) is a cross-sectional view of the portion indicated by the dashed line 1-X2 in FIG. 1 is a cross-sectional view of a portion indicated by a dashed line along Y1-Y2.

[0265] When the transistor 200 is provided with the insulating layer 110 and the insulating layer 111, It is preferable to use an insulating material for one or both of the layers 111 that is difficult for impurities to penetrate. For example, at least one of the insulating layers 110 and 111 may be a silicon nitride layer or an aluminum oxide layer. Alternatively, one of the insulating layers 110 and 111 may be made of silicon nitride. One layer may be a palladium layer, and the other may be an aluminum oxide layer.

[0266] In particular, it is preferable to form an aluminum oxide layer as the insulating layer 110 by a sputtering method. It is particularly preferable to form an aluminum oxide layer as the insulating layer 111 by the ALD method. These effects will be explained later.

[0267] The oxide semiconductor layer 106 is not limited to a single layer and may be a stack of multiple layers. As shown in FIG. 1, the oxide semiconductor layer 106 is divided into an oxide semiconductor layer 106_1 and an oxide semiconductor layer 22(B), for example, an oxide The semiconductor layer 106 is divided into an oxide semiconductor layer 106_1, an oxide semiconductor layer 106_2, and an oxide semiconductor layer 106_3. Of course, the oxide semiconductor layer 106 may be formed as a three-layer stack. 22(A) and 22(B) are the same as those in FIG. 19(B). ) is a cross-sectional view corresponding to FIG.

[0268] In transistor 200, electrode 102 and electrode 112 can function as gate electrodes. When one of the electrodes 102 and 112 is referred to as a "gate electrode," the other is referred to as a "transistor." For example, in transistor 200, electrode 102 is called a "gate electrode." When referring to the "back gate electrode," the electrode 112 is referred to as the "back gate electrode." When used as a "polar electrode," transistor 200 is considered a type of bottom-gate transistor. Either the electrode 102 or the electrode 112 can be considered as a "first gate electrode." The first electrode is sometimes called the "electrode" and the other is sometimes called the "second gate electrode."

[0269] In the transistor 200, the insulating layer 108 and the insulating layer 109 are gate insulating layers. In addition, the insulating layer 103, the insulating layer 104, and the insulating layer 105 can also function as a gate It can function as an insulating layer.

[0270] By providing the electrode 102 and the electrode 112 with the oxide semiconductor layer 106 interposed therebetween, By setting the electrode 102 and the electrode 112 to the same potential, the carrier Since the area in which the carriers flow becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, the on-state current of the transistor increases and the field-effect mobility increases.

[0271] Therefore, the transistor is designed to have a large on-current relative to the area it occupies. In other words, the area occupied by the transistor can be reduced relative to the required on-current. Therefore, a highly integrated semiconductor device can be realized.

[0272] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity In plan view, the back gate electrode is The back gate electrode is formed larger than the semiconductor layer, and the semiconductor layer is covered with the back gate electrode, improving the electric field shielding function. It can be done.

[0273] The electrodes 102 and 112 each have the function of shielding an external electric field. The charges of the charged particles generated above the electrode 112 and below the electrode 102 are transferred to the oxide semiconductor layer This does not affect the channel formation region of 106. As a result, the deterioration of electrical characteristics during stress testing is minimized. In addition, the electrodes 102 and 112 are semiconductors that are protected from the electric field generated by the drain electrode. Therefore, the voltage fluctuation caused by the drain voltage fluctuation can be prevented from affecting the body layer. This effect can be suppressed by the electrode 1. This is particularly noticeable when a potential is applied to electrode 02 and electrode 112.

[0274] The electrode 102 and the electrode 112 are set to the same potential. This reduces the amount of variation in threshold voltage between multiple transistors. At the same time, the variation in electrical characteristics is reduced.

[0275] One of the electrodes 114a and 114b serves as a source electrode or a drain electrode. The other of the electrodes 114a and 114b can function as a source electrode or a drain electrode. It can function as the other of the two.

[0276] Electrode 114a_1, electrode 114a_2, electrode 114b_1, electrode 114b_2, and electrode The conductive material for forming the electrode 112 may be the same as that for the electrode 102. This can be done.

[0277] In this embodiment, each of the electrodes 114a and 114b has a two-layer laminated structure. However, one embodiment of the present invention is not limited to this example. 114b may each have a single layer structure or a three layer structure. It may have a laminated structure of more than one layer.

[0278] In order to reduce the resistance of the electrodes 114a and 114b, When copper is used for the electrode 114b, copper is likely to diffuse between the electrode 114a and the oxide semiconductor layer 106. It is preferable to provide a conductive material between the electrode 114b and the oxide semiconductor layer 106. It is preferable to provide a conductive material between the semiconductor layers that is difficult for copper to diffuse into. This may cause the operation of the semiconductor device to become unstable and significantly reduce the yield. By providing a conductive material that is difficult for copper to diffuse between the wiring or electrode containing copper and the semiconductor layer, This can improve the reliability of the transistor 200.

[0279] In addition, by covering or wrapping copper-containing wiring or electrodes with a conductive material that makes it difficult for copper to diffuse, The reliability of the transistor 200 can be further improved.

[0280] Furthermore, the regions of the electrodes 114a and 114b in contact with the oxide semiconductor layer 106 are subjected to a heat treatment. By using this process, the material becomes conductive and has the ability to absorb hydrogen, which allows the material to absorb the oxygen by subsequent heat treatment. The hydrogen concentration in the compound semiconductor layer 106 can be reduced.

[0281] <Example of a method for manufacturing the transistor 200> An example of a method for manufacturing the transistor 200 will be described with reference to FIGS. The X1-X2 cross section in Figures 23(A) to 26(C) is the same as that of Figure 19(A) taken along the line X1-X2. This corresponds to the cross section of the portion indicated by the dashed dotted line.

[0282] [Process 1] First, a conductive layer 181 for forming an electrode 102 is formed on a substrate 101 (FIG. 23(A) ) In this embodiment, aluminoborosilicate glass is used as the substrate 101. In this embodiment, the conductive layer 181 is a titanium layer having a thickness of 50 nm and a SiO 2 layer having a thickness of 200 nm. The copper layer m is formed in this order by sputtering.

[0283] [Process 2] Next, a resist mask is formed (not shown). The resist mask is formed by photolithography. This can be carried out by appropriately using a lithography method, a printing method, an inkjet method, or the like. When a mask is formed by printing or inkjet methods, no photomask is used, reducing manufacturing costs. This can reduce costs.

[0284] The formation of a resist mask by photolithography involves applying a photomask to a photosensitive resist. The exposed area (or the unexposed area) is then resist-deposited using a developer. The light irradiated onto the photosensitive resist is a KrF excimer laser. light, ArF excimer laser light, EUV (Extreme Ultraviolet) light There is also the liquid immersion method, in which exposure is performed by filling the space between the substrate and the projection lens with liquid (for example, water). In addition, instead of the light mentioned above, an electron beam or an ion beam may be used. When an electron beam or an ion beam is used, the photomask becomes unnecessary.

[0285] Using the resist mask as a mask, part of the conductive layer 181 is selectively removed to form an electrode The conductive layer 181 is removed by dry etching. The etching can be performed by dry etching or wet etching. Both hot and hot etching methods may be used.

[0286] After part of the conductive layer 181 is removed, the resist mask is removed. Dry etching such as ashing or wet etching using a dedicated stripping solution This can be done by both dry and wet etching methods. Good too.

[0287] It is also preferable that the cross-sectional shape of the side surface of the electrode 102 is tapered. The taper angle θ is preferably 20° or more and less than 90°, and more preferably 30° or more and less than 80°. The taper angle θ is preferably 40° or more and less than 70°. When a layer having the above structure is observed from the cross section (a plane perpendicular to the surface of the substrate), the side and bottom of the layer are Indicates the angle between the faces.

[0288] By providing a tapered shape to the side surface of the electrode 102, it is possible to prevent the layer formed thereon from being cut off. In addition, the side surface of the electrode 102 is tapered. This can alleviate the electric field concentration at the upper end of the electrode 102. On the other hand, if the taper angle θ is too small, If the taper angle θ is too small, it may be difficult to miniaturize the transistor. There may be large variations in the size of the openings and the width of the wiring.

[0289] The side surface of the electrode 102 may be formed in a stepped shape. This can prevent the layer from being cut off and improve the coverage. In addition, by making the end of each layer tapered or stepped, the layer coated thereon can be This can prevent the phenomenon in which the coating is broken (step breaks) and improve the coating properties.

[0290] [Process 3] Next, insulating layer 103, insulating layer 104, and insulating layer 105 are formed in this order (FIG. 23(C) In this embodiment, a silicon nitride layer having a thickness of 400 nm is formed as the insulating layer 103. An aluminum oxide layer having a thickness of 30 nm is formed as the insulating layer 104, and an insulating layer 105 is formed as the insulating layer 105. A silicon oxynitride layer having a thickness of 50 nm is formed.

[0291] The silicon nitride layer used for the insulating layer 103 is a first silicon nitride layer and a second silicon nitride layer. The three-layer stack structure includes a silicon layer, a third silicon nitride layer, and a third silicon nitride layer. For example, it can be formed as follows.

[0292] The first silicon nitride layer is formed by, for example, silane at a flow rate of 200 sccm, ccm of nitrogen and 100 sccm of ammonia gas were used as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a high frequency of 27.12 MHz was generated. A power of 2000 W is supplied using a microwave power supply, and the thickness is formed to be 50 nm. stomach.

[0293] For the second silicon nitride layer, silane at a flow rate of 200 sccm and Nitrogen and ammonia gas at a flow rate of 2000 sccm were used as source gases for the reaction in the PECVD equipment. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply was used. A power of 2000 W may be supplied using the above method to form a film having a thickness of 300 nm.

[0294] For the third silicon nitride layer, silane at a flow rate of 200 sccm and silane at a flow rate of 5000 sccm m of nitrogen was supplied as a source gas to the reaction chamber of the PECVD device, and the pressure in the reaction chamber was maintained at 100 P a, and a power of 2000 W was supplied using a 27.12 MHz high frequency power supply. It is sufficient to form it so that the thickness is 50 nm.

[0295] The first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer are The substrate temperature during the growth can be set to 350° C. or less.

[0296] By forming the silicon nitride layer into the above-mentioned three-layer laminated structure, for example, a conductive material containing copper can be formed in the electrode 102. When the conductive layer is used, the following effects are achieved.

[0297] The first silicon nitride layer can suppress the diffusion of copper elements from the electrode 102. The silicon nitride layer has the function of releasing hydrogen and is an insulating layer that functions as a gate insulating layer. The third silicon nitride layer can improve the breakdown voltage. The hydrogen release is small and the diffusion of the hydrogen released from the second silicon nitride layer can be prevented. can.

[0298] As described above, the insulating layer 104 is formed using an insulating material that is difficult for impurities to penetrate. It is also preferable that the insulating layer 104 be formed using an insulating material through which oxygen does not easily diffuse. The aluminum oxide layer used for the insulating layer 104 is preferably formed by depositing an aluminum target. It may be formed by DC sputtering using an aluminum oxide target. It may be formed by AC sputtering or ALD.

[0299] The insulating layer 105 is preferably an insulating layer containing excess oxygen. Alternatively, a heat treatment may be performed after the formation of the insulating layer 105 to remove the insulating layer 105. It is preferable to reduce the hydrogen and moisture contained in the SiO2. The oxygen doping process may be performed by, for example, heating the substrate to 400° C. and This can be done by exciting oxygen-containing gas at a frequency of 2.45 GHz. The process may be repeated multiple times.

[0300] In addition, the insulating layer 105 is exposed to a plasma atmosphere of nitrogen or an inert gas. Impurities such as hydrogen and carbon on the surface and near the surface can be reduced. The plasma was heated to 400°C and excited at a frequency of 2.45 GHz in a gas containing argon and nitrogen. This can be achieved by exposing the insulating layer 105 to the turbulent atmosphere.

[0301] The heat treatment may be carried out, for example, in an inert atmosphere containing nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-high pressure atmosphere. Dry air (measured using a CRDS (cavity ring-down laser spectroscopy) type dew point meter) When measured, the moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less The oxidation is preferably carried out in an atmosphere of 10 ppb or less of air. An atmosphere containing 10 ppm or more of oxidizing gases such as oxygen, ozone, or nitrogen dioxide. In addition, "inert atmosphere" means an atmosphere in which the above-mentioned oxidizing gases are less than 10 ppm, and other There are no particular restrictions on the pressure during the heat treatment, but The treatment is preferably carried out under reduced pressure.

[0302] The heat treatment is carried out at a temperature of 150°C or higher but lower than the strain point of the substrate, preferably 200°C or higher but 500°C or lower, more preferably More preferably, the treatment is carried out at a temperature of 250° C. to 400° C. The treatment time is within 24 hours. Heat treatment for more than 24 hours is not preferable because it reduces productivity.

[0303] The heat treatment can be carried out using an electric furnace, an RTA device, or the like. By using this method, it is possible to perform heat treatment at a temperature above the distortion point of the substrate for a short period of time. This allows for a reduction in heating time. Heat treatment can be carried out using nitrogen, oxygen, or ultra-dry air. (Water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less) The reaction may be carried out under an atmosphere of nitrogen (air) or rare gas (argon, helium, etc.). It is preferable that the oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc.

[0304] [Step 4] Next, the oxide semiconductor layer 182 is formed (see FIG. 23D). Before forming 182, oxygen gas may be supplied to generate plasma. This allows oxygen to be added to the insulating layer 105, which is a surface where the oxide semiconductor layer 182 is to be formed.

[0305] The oxide semiconductor layer 182 may be made of indium zinc oxide or a material having a composition of In:Ga:Zn=5. Indium gallium zinc oxide formed using a target with an atomic ratio of 1:6, Insulators formed using a target with a composition of In:Ga:Zn=4:2:3 [atomic ratio] It is preferable to use gallium zinc oxide or the like.

[0306] In this embodiment, the oxide semiconductor layer 182 is made of indium gallium zinc oxide. was deposited by sputtering using a target with an atomic ratio of In:Ga:Zn=5:1:6. In addition, oxygen or a mixture of oxygen and rare gas is used as the sputtering gas. In this embodiment, a mixture of oxygen and aluminum with a flow rate ratio of 10% is used as the sputtering gas. It uses a mixture of gon gases.

[0307] The flow rate ratio of oxygen contained in the sputtering gas is set to 0% or more and 30% or less, preferably 5% or more. When the concentration is 20% or less, an oxygen-deficient oxide semiconductor layer is formed. A transistor including an oxide semiconductor layer can have relatively high field-effect mobility.

[0308] In addition, when the oxide semiconductor layer 182 is formed, part of the oxygen contained in the sputtering gas is insulated. The more oxygen contained in the sputtering gas, the better the insulating layer 105 will be. The oxygen supplied to the insulating layer 105 also increases. The hydrogen reacts with the hydrogen remaining in the insulating layer 105 to form water, which is then removed from the insulating layer 105 by a subsequent heat treatment. In this way, the hydrogen concentration in the insulating layer 105 can be reduced. By increasing the excess oxygen in the insulating layer 105, the oxide semiconductor layer 18 Oxygen can also be supplied to 2 (the oxide semiconductor layer 106 to be formed later).

[0309] As shown in FIG. 22(A) and FIG. 22(B), the oxide semiconductor layer 106 is formed into a two-layer or three-layer structure. In the case of stacking layers, the oxide semiconductor layer for forming the oxide semiconductor layer 106_1 is It is formed by the method described above.

[0310] In addition, in order to form the oxide semiconductor layer 106_2 and / or the oxide semiconductor layer 106_3, For this purpose, it is preferable to use an oxide semiconductor layer with high crystallinity. It is preferable to use CAAC-OS. For example, the insulating layer 108 and the insulating layer The oxide semiconductor exposed during the etching process for forming 109 and electrode 112 The oxide semiconductor layer may be damaged by etching. The oxide semiconductor layer is difficult to be etched in the etching process. By using an oxide semiconductor layer with high thermal conductivity, damage to the oxide semiconductor layer during the etching process can be reduced. Therefore, the reliability of the transistor can be improved.

[0311] The oxide semiconductor layer 106_2 and / or the oxide semiconductor layer 106_3 may be formed by an acid. As the compound semiconductor layer, for example, indium gallium zinc oxide having a composition of In:Ga:Zn The sputtering method is performed using a target with an atomic ratio of 1:1:1. Oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. The evaporating gas is oxygen at a ratio of 100%. The flow rate ratio of oxygen contained in the sputtering gas is preferably 70% or more, and more preferably 80% or more. The proportion of oxygen contained in the sputtering gas (flow) is more preferably 100%. By increasing the amount ratio, the crystallinity of the oxide semiconductor layer can be improved.

[0312] Note that by introducing an impurity element after the formation of the oxide semiconductor layer 182, the transistor 20 The threshold voltage of 0 can be changed. The introduction of impurity elements can be performed by ion implantation, ion implantation, doping method, or plasma immersion ion implantation method, or gas containing impurity elements This can be done by plasma treatment using a gas.

[0313] After the oxide semiconductor layer 182 is formed, heat treatment may be performed or oxygen doping treatment may be performed. The heat treatment and oxygen doping treatment may be repeated multiple times.

[0314] In addition, after heat treatment in a nitrogen or rare gas atmosphere, the material is dried in an oxygen or ultra-dry air atmosphere. Heat treatment may be performed. As a result, hydrogen, water, and the like contained in the oxide semiconductor layer are released. At the same time, oxygen can be supplied to the oxide semiconductor layer. The oxygen vacancies contained therein can be reduced.

[0315] [Step 5] Next, a resist mask is formed by photolithography (not shown). Part of the oxide semiconductor layer 182 is selectively removed using the mask as a mask to form an island. Then, a crystalline oxide semiconductor layer 106 is formed (see FIG. 24A).

[0316] The oxide semiconductor layer 182 is removed by dry etching, wet etching, or the like. Both dry etching and wet etching can be used. good.

[0317] After the oxide semiconductor layer 106 is formed, heat treatment may be performed or oxygen doping treatment may be performed. The heat treatment and the oxygen doping treatment may be repeated.

[0318] [Step 6] Next, the insulating layer 108 and the insulating layer 109 are formed in this order (see FIG. 24(B)). It is preferable that the insulating layer 8 and the insulating layer 109 are formed successively without exposing them to the air in between.

[0319] The insulating layer 108 is preferably an insulating layer containing excess oxygen. The thickness of the insulating layer 108 is 5n The thickness of the insulating layer may be from 100 nm to 150 nm, preferably from 5 nm to 50 nm. By using an insulating layer that can transmit oxygen as 108, the insulating layer 1 Oxygen contained in O9 can be moved to the oxide semiconductor layer 106.

[0320] For example, a silicon oxynitride layer formed by PECVD may be used as the insulating layer 108. In this case, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of silicon-containing deposition gases include silane, disilane, Examples of oxidizing gases include nitrous oxide and nitrogen dioxide. In addition, the flow rate of the oxidizing gas is set to 20 times or more, 5000 times, the flow rate of the deposition gas. times or less, preferably 40 times or more and 100 times or less.

[0321] In this embodiment, a silicon oxynitride layer having a thickness of 30 nm is formed as the insulating layer 108. Specifically, the substrate temperature was set to 350°C, and silane with a flow rate of 20 sccm and 3000 The source gas was dinitrogen monoxide at a flow rate of 100 sccm, the pressure in the processing chamber was set to 200 Pa, and a parallel plate The PECVD method was used with a high frequency power of 13.56 MHz and 100 W supplied to the electrode. A silicon nitride layer is formed.

[0322] The insulating layer 109 is preferably an insulating layer containing excess oxygen. The thickness may be set to 500 nm or more, and preferably 400 nm or more.

[0323] Furthermore, it is preferable that the insulating layer 109 has a small number of defects. , the spin density of the signal at g=2.001 originating from silicon dangling bonds is 1.5×10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 Below Note that the insulating layer 109 is preferably made of an oxide semiconductor, as compared with the insulating layer 108. Because it is further away from layer 106 , it may have a higher defect density than insulating layer 108 .

[0324] The insulating layer 109 can be a silicon oxynitride layer formed by PECVD. For example, a substrate placed in a vacuum-evacuated processing chamber of a PECVD device is heated to 180°C or higher for 4 The temperature is kept at 00°C or lower, and the raw material gas is introduced into the processing chamber to reduce the pressure in the processing chamber to 100 Pa or lower. The pressure in the processing chamber is set to 250 Pa or less, and more preferably 100 Pa or more and 200 Pa or less. 0.17W / cm 2 More than 0.5W / cm 2 or less, more preferably 0.2 5W / cm 2 More than 0.35W / cm 2 Under the following conditions for supplying high frequency power, silicon oxide A silicon layer or silicon oxynitride layer is formed.

[0325] In forming the insulating layer 109, high frequency power with the above power density is supplied in a reaction chamber with the above pressure. By doing so, the decomposition efficiency of the source gas in the plasma is increased. As a result, the oxygen content in the insulating layer 109 increases. The amount is greater than the stoichiometric composition.

[0326] In addition, in the insulating layer formed at the above substrate temperature, the bonding strength between silicon and oxygen is weak, so The heat treatment in this step causes some of the oxygen in the insulating layer to be released. It contains more oxygen than the oxygen that fills the space, and forms an oxide insulating layer in which some of the oxygen is released when heated. It can be achieved.

[0327] In this embodiment, a silicon oxynitride layer having a thickness of 100 nm is formed as the insulating layer 109. Specifically, the substrate temperature was set to 220° C., and silane was used at a flow rate of 160 sccm and 40 The source gas was nitrous oxide at 0.00 sccm, the pressure in the processing chamber was 200 Pa, and the parallel parallel The PECVD method was used, with the high frequency power supplied to the plate electrode being 13.56 MHz and 1500 W. A silicon oxynitride layer is formed.

[0328] In the step of forming the insulating layer 109, the insulating layer 108 is a protective layer for the oxide semiconductor layer 106. Therefore, it is possible to reduce damage to the oxide semiconductor layer 106 while achieving a high power density. The insulating layer 109 can be formed using low high frequency power.

[0329] In the formation conditions of the insulating layer 109, the deposition gas containing silicon is used in place of the oxidizing gas. By increasing the flow rate, it is possible to reduce the number of defects in the insulating layer 109. appears at g=2.001 due to the dangling bond of silicon by ESR measurement. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 s pins / cm 3 Less than or equal to 1.5 × 10 17 spins / cm 3 Defects that are less than As a result, the reliability of the transistor can be improved. It can be done.

[0330] [Step 7] A conductive layer 185 for forming the electrode 112 is formed on the insulating layer 109 (see FIG. 24(C)). In this embodiment, indium gallium zinc oxide is used as the conductive layer 185. More specifically, a two-layer stack of indium gallium zinc oxide is used as the conductive layer 185. do.

[0331] First, a target with a composition of In:Ga:Zn=4:2:3 [atomic ratio] and a target with 100% oxygen % sputtering gas and a 10 nm thick indium gallium zinc oxide layer Next, a target having a composition of In:Ga:Zn=4:2:3 [atomic ratio] is formed. The sputtering gas was 10% oxygen and 90% argon, and the thickness was A 90 nm indium gallium zinc oxide layer is formed.

[0332] [Step 8] Next, a resist mask is formed by photolithography (not shown). Using the mask as a mask, a portion of the conductive layer 185 is selectively removed to form the electrode 112. At this time, the electrode 112 is used as a mask to form the insulating layer 108 and the insulating layer 109. A part of the oxide semiconductor layer 106 is selectively removed (see FIG. 24D). A part of it is exposed.

[0333] The conductive layer 185, the insulating layer 108, and the insulating layer 109 can be removed by dry etching or This can be done by using a dry etching method or a wet etching method. Both etching and etching methods may be used.

[0334] [Step 9] Next, impurities are introduced into the region of the oxide semiconductor layer 106 exposed in step 8 (FIG. 25(A) The introduction of impurities can be achieved by ion implantation, ion doping, plasma immersion, This can be done by ion implantation or the like. By introducing impurities such as nitrogen into the region, This can reduce the resistance value of the region.

[0335] Alternatively, the region may be exposed to a plasma atmosphere of nitrogen or an inert gas. By exposing the area to the atmosphere, defects are generated in the area, and the resistance value of the area is reduced. It is possible.

[0336] A region of the oxide semiconductor layer 106 into which an impurity is introduced or a region exposed to a plasma atmosphere can function as the source or drain region of a transistor. The region of the layer 106 that overlaps with the electrode 112 can function as a channel forming region. The source and drain regions of the transistor are formed in a self-aligned manner. It is possible.

[0337] [Step 10] Next, heat treatment is performed in an inert atmosphere to form the oxide semiconductor layer 106, the insulating layer 108, and This reduces hydrogen and moisture contained in the insulating layer 109. In addition, a heat treatment is performed after step 9. As a result, the resistance of the source and drain regions of the oxide semiconductor layer 106 may be reduced. The heat treatment may be carried out under reduced pressure without supplying an inert gas or other gas. In this embodiment mode, heat treatment is performed in a nitrogen atmosphere at 400° C. for one hour.

[0338] [Step 11] Subsequently, heat treatment may be performed in an oxidizing atmosphere. For example, in step 8, the oxide semiconductor layer 106 is heated to 400° C. for 1 hour. When an element is introduced, the source and drain regions are heated in an oxygen atmosphere. Area No. X In some cases, the resistance value may decrease due to an increase in the temperature. The other option may be omitted.

[0339] [Step 12] Next, the insulating layer 110 is formed (see FIG. 25(B)). As described above, the insulating layer 110 It is preferable to form the insulating layer 11 using an insulating material that is difficult for impurities to penetrate. The insulating layer 110 is preferably formed using an insulating material that does not easily diffuse oxygen. The thickness may be between 5 nm and 40 nm.

[0340] In this embodiment, an aluminum oxide layer having a thickness of 30 nm is formed as the insulating layer 110 by sputtering. The sputtering gas is oxygen or a mixture of oxygen and rare gas. The flow rate ratio of oxygen contained in the sputtering gas is preferably 70% or more. The oxygen content is preferably 80% or more, and more preferably 100%. By using the sputtering method, oxygen can be supplied to the layer to be formed (the insulating layer 109). The more oxygen contained in the gas, the more oxygen is likely to be supplied to the layer to be formed. In this embodiment, 100% oxygen is used as the sputtering gas.

[0341] The aluminum oxide layer used for the insulating layer 110 is formed by DC spat using an aluminum target. It may be formed by a sputtering method, or by AC sputtering using an aluminum oxide target. Alternatively, the film may be formed by a coating method.

[0342] The insulating layer 110 may be a silicon nitride layer that does not contain or contains little hydrogen. Such a silicon nitride layer may be formed by, for example, a sputtering method. It is possible.

[0343] When the insulating layer 111 is formed on the insulating layer 110, the insulating layer 111 is made of aluminum oxide. The thickness of the insulating layer 111 is preferably 5 nm to 40 nm. By forming an aluminum oxide layer using the ALD method, an oxide layer with good coating properties can be obtained. Therefore, the reliability of the transistor can be improved. Alternatively, the insulating layer 111 may be a silicon nitride layer.

[0344] Steps 10 to 12 are carried out continuously without exposing the material to the atmosphere. This prevents hydrogen, moisture, and the like from being adsorbed to the oxide semiconductor layer 106, thereby improving the reliability of the transistor. In addition, by covering the oxide semiconductor layer 106 with the insulating layer 110, It is possible to prevent hydrogen and moisture from entering through the inside of the housing. In addition, it is possible to prevent oxygen from diffusing to the outside. This can be done.

[0345] [Step 13] Next, the insulating layer 113 is formed (see FIG. 25(C)). In this embodiment, the insulating layer 11 As 3, an acrylic resin layer having a thickness of 1.5 μm is formed.

[0346] [Step 14] Next, a resist mask is formed by photolithography (not shown). A part of each of the insulating layer 113 and the insulating layer 110 is selected using a photomask as a mask. The oxide semiconductor is selectively removed to form an opening 188 (see FIG. 26A). A portion of layer 106 is exposed.

[0347] [Step 15] Next, a conductive layer 186 and a conductive layer 187 are formed in this order (see FIG. 26(B)). The oxide semiconductor layer 186 is in contact with the oxide semiconductor layer 106 and has a function of absorbing hydrogen by heat treatment. It is preferable to use a conductive material that can achieve this. By subsequent heat treatment, the hydrogen concentration in the oxide semiconductor layer 106 can be reduced. Examples of conductive materials that have the function of absorbing hydrogen include titanium, indium zinc oxide, Examples include silicon-doped indium tin oxide.

[0348] In this embodiment, a titanium layer having a thickness of 30 nm is formed as the conductive layer 186, and a conductive layer 187 is formed as the conductive layer 187. A copper layer having a thickness of 200 nm is formed as the insulating layer by sputtering.

[0349] [Step 16] Next, a resist mask is formed by photolithography (not shown). Using the mask as a mask, portions of the conductive layer 186 are selectively removed to form the electrode 114. a_1 and an electrode 114b_1 are formed (see FIG. 26(C)). At the same time, a conductive layer 187 A portion of the insulating film is selectively removed to form an electrode 114a_2 and an electrode 114b_2.

[0350] The conductive layer 186 and the insulating layer 187 can be removed by dry etching or wet etching. Both dry etching and wet etching methods can be used. may also be used.

[0351] After removing the resist mask, a heat treatment may be performed. For example, the heat treatment may be performed in a nitrogen atmosphere at 250 Heat treatment was carried out at ℃ for 1 hour.

[0352] <Modifications of the Transistor 200> A modification of the transistor 200 will be described with reference to the drawings.

[0353] [Variation 1] 27(A) is a plan view of the transistor 200A. 27(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 1 is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG.

[0354] The transistor 200A includes an electrode 114c (electrode 114c_1 and electrode The electrode 114c is different from the transistor 200 in that it has an electrode 114c_2. a and electrode 114b can be provided in the same process using the same materials and methods. The electrode 114c is formed in an opening in each of the insulating layer 113 and the insulating layer 110. , and is electrically connected to the electrode 112.

[0355] In addition, in the transistor 200A, when viewed in a plan view, the oxide semiconductor layer 106 is surrounded by a The transistor 200 differs from the transistor 200 in that it has a region 123 containing an insulating layer 105. is removed, and insulating layer 104 and insulating layer 110 are in contact with each other.

[0356] By providing the region 123, it is possible to improve the effect of preventing the intrusion of hydrogen, moisture, etc. from the outside. In addition, the effect of preventing oxygen from diffusing to the outside can be improved.

[0357] [Variation 2] FIG. 28(A) is a plan view of the transistor 200B. FIG. 28(B) is a plan view of the transistor 200B. 28(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 29(A) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. FIG. 29(B) is an enlarged view of the area 231B shown in FIG. 28(C). 232B is an enlarged view.

[0358] The transistor 200B differs from the transistor 200 in the shape of the insulating layer 105. The gate 200B has an island-shaped insulating layer 105 overlapping the oxide semiconductor layer 106. The edge layer 105 is formed by removing the exposed insulating layer 105 when the oxide semiconductor layer 106 is formed in step 5. It can be formed by successively removing portions.

[0359] In the transistor 200B, the insulating layer 110 and the insulating layer 104 are formed on the oxide semiconductor layer 1. The insulating layer 105 and the insulating layer 106 are connected to each other. By adopting such a configuration, it is possible to improve the effectiveness of preventing the intrusion of hydrogen, moisture, etc. from the outside. In addition, the effect of preventing oxygen from diffusing to the outside can be improved.

[0360] [Variation 3] FIG. 30(A) is a plan view of the transistor 200C. FIG. 30(B) is a plan view of the transistor 200C. 30(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 1 is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG.

[0361] The transistor 200C is a transistor 200 having a structure in which the insulating layer 108 and the insulating layer 109 are formed. In the transistor 200C, the insulating layer 108 and the insulating layer 109 are made of an oxide semiconductor. The transistor 200C has a structure covering the electrode 112 in step 8. During the formation, the insulating layer 108 and the insulating layer 109 are left unetched.

[0362] By covering the oxide semiconductor layer 106 with the insulating layer 108 and the insulating layer 109, In addition, the amount of oxygen supplied from the insulating layer 109 to the oxide semiconductor layer 106 can be increased.

[0363] [Variation 4] FIG. 31(A) is a plan view of the transistor 200D. FIG. 31(B) is a plan view of the transistor 200D. 31(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 1 is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG.

[0364] The transistor 200D has a configuration in which the electrode 102 is removed from the transistor 200. Depending on the performance and purpose required of the transistor, the electrode 102 may not be provided. By not providing the electrode 102, the number of manufacturing steps for the transistor is reduced, thereby reducing the manufacturing cost. Furthermore, the manufacturing yield of transistors can be increased.

[0365] [Variation 5] 32(A) is a plan view of the transistor 200E. 32(A) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 32(B) is a cross-sectional view of the portion indicated by the dashed line Y1-Y2 in FIG. 2 is an enlarged view of the indicated portion 231E.

[0366] The transistor 200E has an insulating layer 118 between the insulating layer 109 and the electrode 112. The insulating layer 118 is different from the transistor 200. It may be formed by any material and method.

[0367] For example, a silicon oxynitride layer having a thickness of 20 nm is formed as the insulating layer 118. The substrate temperature was set to 350°C, and the flow rate of silane was 20 sccm and the flow rate of silane was 3000 sccm. Nitrous oxide was used as the raw material gas, and the pressure in the processing chamber was set to 200 Pa. The gas was supplied to the parallel plate electrodes. The silicon oxynitride was deposited using the PECVD method with a high frequency power of 13.56 MHz and 100 W. Form a corn layer.

[0368] In addition, by using an insulating layer containing excess oxygen as the insulating layer 118, the oxide semiconductor layer 106 This allows for an increased amount of oxygen to be supplied to the

[0369] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0370] (Embodiment 3) In this embodiment, as an example of a semiconductor device using a transistor disclosed in this specification, A display device and a display module are described.

[0371] <Display device> An example of a display device in which the above-described transistor can be used will be described. 1 is a block diagram illustrating an example of the configuration of a display device 500. FIG.

[0372] The display device 500 shown in FIG. 34(A) includes a drive circuit 511, a drive circuit 521a, and a drive circuit 5 21b, and a display area 531. and the drive circuit 521b are sometimes collectively referred to as the "drive circuit" or the "peripheral drive circuit." be.

[0373] The driving circuits 521a and 521b can function as, for example, scanning line driving circuits. The driver circuit 511 can function as, for example, a signal line driver circuit. The display area 531 may be formed by the driving circuit 521b. A circuit of some kind may be provided at a position facing the driving circuit 511 across the substrate.

[0374] In addition, the display device 500 shown in FIG. 34(A) is arranged substantially parallel to each other and is driven by p wirings 5 ​​whose potentials are controlled by the circuit 521a and / or the drive circuit 521b 35 and q electrodes which are arranged approximately parallel to each other and whose potentials are controlled by a driving circuit 511. (p and q are both natural numbers equal to or greater than 1.) The pixel circuit 531 has a plurality of pixels 532 arranged in a matrix. 34 and a display element.

[0375] In addition, by making the three pixels 532 function as one pixel, a full color display can be realized. The three pixels 532 can be transparent, each emitting red, green, or blue light. The transmittance, reflectance, or emitted light amount is controlled by the three pixels 532. The colors are not limited to a combination of red, green, and blue, but may also be yellow, cyan, and magenta.

[0376] In addition to the pixels that control red, green, and blue light, a pixel 532 that controls white light is added. In this case, four pixels 532 may be grouped together to function as one pixel. By adding the pixel 532, the brightness of the display area can be increased. The number of pixels 532 that function as a function of the red, green, blue, yellow, cyan, and magenta is increased. By using them together, the reproducible color gamut can be expanded.

[0377] When pixels are arranged in a 1920 x 1080 matrix, it becomes what is known as full high definition (" Also known as "2K resolution," "2K1K," or "2K." The device 500 can be realized. For example, the pixels can be arranged in a matrix of 3840 x 2160. When arranged in a grid, it becomes what is known as ultra high definition ("4K resolution", "4K2K", It is possible to realize a display device 500 capable of displaying at a resolution of 1080p (also called "4K"). For example, if pixels are arranged in a 7680 x 4320 matrix, Super Hi-Vision (also called "8K resolution," "8K4K," or "8K") By increasing the number of pixels, it is possible to realize a display device 500 capable of displaying at a resolution of 1 It is also possible to realize a display device 500 capable of displaying at a resolution of 6K or 32K.

[0378] The wiring 535_g (g is a natural number between 1 and p) in the gth row is p in the display area 531. Among the pixels 532 arranged in rows and columns q, q pixels 532 arranged in rows g are electrically connected to Also, the wiring 536_h (h is a natural number between 1 and q) in the h-th column is Of the pixels 532 arranged in rows and columns q, p pixels 532 arranged in columns h are electrically connected. To be continued.

[0379] [Display element] The display device 500 can take a variety of forms or have a variety of display elements. An example of a display element is an EL (electroluminescence) element (organic EL element, Inorganic EL elements, or EL elements containing organic and inorganic materials), LEDs (white LEDs, red LED, green LED, blue LED, etc.), transistor (transistor that emits light according to the current) Electron emission element, liquid crystal element, electronic ink, electrophoretic element, grating light bar GLV (Glass Liquid Crystal Display), MEMS (Micro-Electro-Mechanical Systems) Display element, Digital Micromirror Device (DMD), DMS (Digital Micromirror Scatter), MIRASOL (registered trademark), IMOD (Interferometric Module) MEMS display elements, shutter-type MEMS display elements, optical interference-type MEMS display elements electrons, electrowetting elements, piezoelectric ceramic displays, carbon nanotubes Display elements using a magnetic field, etc., which use electrical or magnetic effects to improve contrast, brightness, and reflectivity. Some display devices have display media that change their reflectivity, transmittance, etc. A marker may also be used.

[0380] An example of a display device using an EL element is an EL display. An example of a display device using the above is a field emission display (FED) or SED type flat panel display (SED: Surface-conduction El Quantum dot displays An example of such a device is a quantum dot display. An example is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). , reflective LCD displays, direct-view LCD displays, projection LCD displays, etc. An example of a display device using electronic ink, electronic liquid powder (registered trademark), or electrophoretic elements Examples include electronic paper. The display device is a plasma display panel (PDP). The display device may be a retinal scanning projection device.

[0381] When realizing a semi-transmissive or reflective LCD display, the pixel voltage A part or all of the electrodes may be made to function as a reflective electrode. For example, A part or all of the pixel electrodes may be made of aluminum, silver, or the like. Furthermore, in this case, it is also possible to provide a memory circuit such as an SRAM below the reflective electrode. This further reduces power consumption.

[0382] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form a nitride layer on the graphene or graphite. Semiconductors, such as n-type GaN semiconductor layers having crystallinity, can be easily formed. Furthermore, a p-type GaN semiconductor layer having crystals is formed on top of that to form an LED. It is possible to combine graphene or graphite with a crystalline n-type GaN semiconductor layer. An AlN layer may be provided between the GaN layer and the LED. However, by providing graphene, the GaN semiconductor of the LED The layer can also be deposited by sputtering.

[0383] 34(B), 34(C), 35(A), and 35(B) show the structure used for pixel 532. 1 shows an example of a circuit configuration that can be implemented.

[0384] [Example of a pixel circuit for a light-emitting display device] The pixel circuit 534 shown in FIG. 34B includes a transistor 461, a capacitor 463, and a transistor 34B. The path 534 is electrically connected to a light emitting element 469 that can function as a display element.

[0385] Transistor 461, transistor 468, and transistor 464 are connected to an OS transistor. In particular, an OS transistor can be used as the transistor 461. preferable.

[0386] One of the source electrode and the drain electrode of the transistor 461 is electrically connected to the wiring 536_h. Furthermore, the gate electrode of the transistor 461 is electrically connected to the wiring 535_g. A video signal is supplied from the wiring 536_h.

[0387] The transistor 461 has a function of controlling writing of a video signal to a node 465. .

[0388] One of a pair of electrodes of the capacitor 463 is electrically connected to the node 465, and the other is The source electrode and the drain electrode of the transistor 461 are electrically connected to the The other of the electrodes is electrically connected to node 465 .

[0389] The capacitor 463 functions as a storage capacitor for storing data written to the node 465. It has.

[0390] One of the source electrode and the drain electrode of the transistor 468 is connected to the potential supply line VL_a. The other end is electrically connected to node 467. The gate electrode of 8 is electrically connected to node 465 .

[0391] One of the source electrode and the drain electrode of the transistor 464 is electrically connected to the potential supply line V0. and the other is electrically connected to a node 467. The gate electrode is electrically connected to a wiring 535_g.

[0392] One of the anode and cathode of the light emitting element 469 is electrically connected to the potential supply line VL_b. and the other is electrically connected to node 467.

[0393] The light emitting element 469 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 469 is not limited to this. For example, an inorganic EL element made of an inorganic material may be used.

[0394] For example, a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0395] In the display device 500 having the pixel circuit 534 of FIG. 34(B), the driver circuit 521a and / or the driver circuit 521b sequentially selects the pixels 532 in each row, and the transistors 461, Then, the transistor 464 is turned on to write the video signal to the node 465 .

[0396] The pixel 532 in which data is written to the node 465 is connected to the transistor 461 and the transistor The register 464 is turned off, which puts the node 465 into a holding state. A current flows between the source and drain electrodes of the transistor 468 according to the potential of the input data. The amount of current is controlled, and the light emitting element 469 emits light with a brightness according to the amount of current flowing. By performing this step sequentially, an image can be displayed.

[0397] As shown in FIG. 35A, the transistor 461, the transistor 464, and the transistor 465 are connected to each other. A transistor having a back gate may be used as the transistor 468. The transistor 461 and the transistor 464 shown in A) have a back gate and a gate electrode. They are electrically connected. Therefore, the gate and back gate are always at the same potential. The back gate of the transistor 468 is electrically connected to the node 467. The back gate is always at the same potential as the node 467 .

[0398] At least one of the transistor 461, the transistor 468, and the transistor 464 The transistor of one embodiment of the present invention can be used for the semiconductor device.

[0399] [An example of a pixel circuit for a liquid crystal display device] The pixel circuit 534 shown in FIG. 34C includes a transistor 461 and a capacitor 463. The pixel circuit 534 shown in FIG. 34(C) is a liquid crystal element that can function as a display element. The transistor 461 is electrically connected to the transistor 462. is preferred.

[0400] The potential of one of the pair of electrodes of the liquid crystal element 462 is set appropriately according to the specifications of the pixel circuit 534. For example, a common potential is applied to one of the pair of electrodes of the liquid crystal element 462. Alternatively, one of the pair of electrodes of the liquid crystal element 462 may be set to the same potential as the capacitance line CL. On the other hand, different potentials may be applied to the pixels 532. The liquid crystal element 462 is electrically connected to the node 466. The alignment state is set by the data.

[0401] As a driving method of the display device including the liquid crystal element 462, for example, TN (Twisted Nematic) Nematic mode, STN (Super Twisted Nematic) mode mode, VA (Vertical Alignment) mode, ASM (Axially Symmetric Aligned Micro-cell mode, OCB (Opt Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC(A AntiFerroelectric Liquid Crystal) mode, MVA ( Multi-Domain Vertical Alignment) mode, PVA( Patterned Vertical Alignment mode, IPS (In- Plane Switching) mode, FFS (Fringe Field Switching) tching) mode or TBA (Transverse Bend Alignment The display device may be driven in the above-described driving mode. In addition to the above method, ECB (Electrically Controlled Birefrigeration) ngence mode, PDLC (Polymer Dispersed Liquid Crystal Crystal mode, PNLC (Polymer Network Liquid Crystal mode, guest host mode, etc., but are not limited to these. Various liquid crystal elements and driving methods thereof can be used.

[0402] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0403] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the crystalline phase to the isotropic phase. Therefore, a liquid crystal composition containing 5% by weight or more of a chiral agent is used to improve the temperature range. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of It is short (less than 1 msec), has optical isotropy so alignment processing is not required, and is not dependent on viewing angle. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. This prevents electrostatic damage caused by the soldering process, and prevents the LCD display from being damaged during the manufacturing process. This reduces the number of defects and damages to the device, thereby improving the productivity of liquid crystal display devices. This makes it possible to:

[0404] In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. It is called multi-domain or multi-domain design, which is designed to defeat molecules. The method can be used.

[0405] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0406] In the pixel circuit 534 in the gth row and the hth column, the source electrode and the drain electrode of the transistor 461 One of the electrodes is electrically connected to the wiring 536_h, and the other is electrically connected to the node 466. A gate electrode of the transistor 461 is electrically connected to a wiring 535_g. The line 536_h provides the video signal. The transistor 461 provides a It has the function of controlling the writing of video signals.

[0407] One of the pair of electrodes of the capacitor 463 is connected to a wiring to which a specific potential is supplied (hereinafter, referred to as a capacitor line CL ), and the other is electrically connected to a node 466. The value of the potential is set as appropriate according to the specifications of the pixel circuit 534. It functions as a storage capacitor that stores data written in the memory card 466 .

[0408] For example, in a display device 500 having a pixel circuit 534 shown in FIG. 34(C), a driver circuit 521a and / or the pixel circuits 534 in each row are sequentially selected by the driving circuit 521b, and the transistors The starter 461 is turned on to write the video signal to the node 466.

[0409] In the pixel circuit 534 in which the video signal is written to the node 466, the transistor 461 is turned off. By doing this for each row, the display area 531 You can display images.

[0410] In addition, as shown in FIG. 35B, the transistor 461 may have a back gate. The transistor 461 shown in FIG. 35B has a back gate. Therefore, the gate and back gate are always at the same potential.

[0411] [Example of peripheral circuit configuration] 36A shows a configuration example of the driver circuit 511. The driver circuit 511 includes a shift register 51 2, a latch circuit 513, and a buffer 514. Also, in FIG. 36(B), a driving circuit The driver circuit 521a includes a shift register 522 and a buffer The driving circuit 521b can have the same configuration as the driving circuit 521a. .

[0412] The shift register 512 and the shift register 522 receive a start pulse SP and a clock signal. The signal CLK etc. is input.

[0413] [Example of display device configuration] A part of a driver circuit including a shift register can be formed using the transistor described in the above embodiment. Alternatively, the entire display can be formed on the same substrate as the pixel section to form a system-on-panel. Cut.

[0414] In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using an EL element are described. A configuration example will be described. In FIG. 37A, a pixel formed on a first substrate 4001 A sealing material 4005 is provided so as to surround the element portion 4002, and a second substrate 4006 is provided. In FIG. 37A, the sealing material 400 on the first substrate 4001 is In a region different from the region surrounded by 5, a single crystal semiconductor or or a signal line driver circuit 4003 and a scanning line driver circuit 4004 formed of a polycrystalline semiconductor. Also, a signal line driver circuit 4003, a scanning line driver circuit 4004, or a display driver circuit 4006 is mounted. Various signals and potentials are applied to the element part 4002 through an FPC 4018a (FPC: Flexible Printed Circuit). ible printed circuit), supplied by FPC4018b.

[0415] In FIG. 37(B) and FIG. 37(C), the pixel portion 4 provided on the first substrate 4001 A sealant 4005 is provided so as to surround the gate electrode 4002 and the scanning line driver circuit 4004. In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are connected to the first substrate 400. The display element is sealed with a sealing material 4005 and a second substrate 4006. In FIG. 37(B) and FIG. 37(C), the sealant 400 on the first substrate 4001 In a region different from the region surrounded by 5, a single crystal semiconductor or A signal line driver circuit 4003 formed of a polycrystalline semiconductor is mounted on the substrate. In FIG. 37(C), a signal line driver circuit 4003, a scanning line driver circuit 4004, Various signals and potentials applied to the pixel portion 4002 are supplied from the FPC 4018. There are.

[0416] In addition, in FIG. 37(B) and FIG. 37(C), a signal line driver circuit 4003 is separately formed. 10, an example in which the scanning element 4001 is mounted on the first substrate 4001 is shown, but the present invention is not limited to this configuration. A signal line driver circuit may be formed separately and mounted, or a part of the signal line driver circuit or the scanning line driver circuit may be mounted. Only a part of the path may be formed separately and mounted.

[0417] The method of connecting the separately formed drive circuit is not particularly limited, and may be a wire bond. ing, COG (Chip On Glass), TCP (Tape Carrier) Package), COF (Chip On Film), etc. can be used. 37(A) is a circuit board in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are mounted by COG. FIG. 37(B) is an example in which a signal line driver circuit 4003 is mounted by COG. FIG. 37C shows an example in which the signal line driver circuit 4003 is implemented using TCP.

[0418] The display device also includes a panel in which a display element is sealed, and a controller for the panel. This may also include a module in which an IC or the like including the above is mounted.

[0419] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be applied to this.

[0420] 38(A), 38(B), 39(A), and 39(B) are the same as those in FIG. 37(B). 38(A) and 38(B) are cross-sectional views showing the cross-sectional configuration of the portion indicated by the chain line N1-N2. The display devices shown in FIGS. 39(A) and 39(B) have an electrode 4015. The electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. In addition, in FIG. 38(A) and FIG. 38(B), the electrode 4015 is connected to the insulating layer 4112, the insulating layer 4111, and the wiring 401 in the opening formed in the insulating layer 4110. 39(A) and 39(B), the electrode 401 5 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112. .

[0421] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The same conductive layer is used.

[0422] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 provided on a first substrate 4001 are It has a plurality of transistors, and is shown in Figs. 38(A), 38(B), 39(A), and 39(B), a transistor 4010 included in a pixel portion 4002 and a scanning line driving circuit The transistor 4011 included in the circuit 4004 is illustrated.

[0423] In FIG. 38(A) and FIG. 38(B), the transistor 4010 and the transistor 401 39(A) and 39(B) show an example of a bottom gate transistor. ) transistors 4010 and 4011 are top-gate transistors. The figure shows an example of a transistor.

[0424] In FIG. 38(A) and FIG. 38(B), the transistor 4010 and the transistor 401 38(B), an insulating layer 4112 is provided on the insulating layer 4112. A partition wall 4510 is formed. In FIG. 39(A) and FIG. 39(B), the transistor 4 An insulating layer 4113 is provided over the transistor 4010 and the transistor 4011. An insulating layer 4112 is provided. In FIG. 39(B), a partition wall 4 510 is formed.

[0425] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. In addition, in FIG. 38(A) and FIG. 38(B), the transistor 4010 and The transistor 4011 has an electrode 4017 formed over the insulating layer 4111. 39(A) and 39(B), the transistor 4010 and the transistor 4011 has an electrode 4017 formed on an insulating layer 4102. The electrode 4017 is The gate electrode can function as a gate electrode.

[0426] The transistors 4010 and 4011 are the same as those described in the above embodiment modes. The transistors 4010 and 4011 can be O. It is preferable to use an OS transistor. Therefore, the present embodiment shown in Fig. 38(A) and Fig. 38(B) is The display device of this embodiment can be a highly reliable display device.

[0427] In addition, the OS transistor can reduce the current in an off state (off-state current). Therefore, the retention time of the electric signals such as the image signals can be extended, and the writing of the image signals etc. can be easily performed. The write interval can also be set longer, which reduces the frequency of refresh operations. This has the effect of reducing power consumption.

[0428] Furthermore, OS transistors can have relatively high field-effect mobility. Therefore, when the above transistor is used in a driver circuit portion or a pixel portion of a display device, By doing so, it is possible to provide high quality images. The number of parts in a display device can be reduced because the pixel section can be manufactured separately. can be done.

[0429] In addition, the display devices shown in FIGS. 38(A), 38(B), 39(A), and 39(B) The capacitor 4020 shown in FIGS. 400 is an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and a source and an electrode formed in the same process as the source electrode and the drain electrode. 39(A) and 39(B), the capacitor element 4102 is overlapped with the insulating layer 4103 interposed therebetween. The electrode 4020 is formed in the same process as the gate electrode of the transistor 4010. The electrode 4021 is formed in the same process as the electrode 4017. Overlapping via 4103.

[0430] Generally, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set to be able to hold charge for a predetermined period, taking into consideration factors such as leakage current of the capacitor. The capacitance of the capacitor may be set in consideration of the off-state current of the transistor.

[0431] For example, by using an OS transistor in a pixel portion of a liquid crystal display device, the capacitance of a capacitor element can be reduced. The volume of the liquid crystal can be reduced to 1 / 3 or even 1 / 5. By using a resistor, the formation of a capacitive element can be omitted.

[0432] The transistor 4010 provided in the pixel portion 4002 is electrically connected to the display element. 8(A) and 39(A) are examples of liquid crystal display devices using liquid crystal elements as display elements. In FIG. 38(A) and FIG. 39(A), a liquid crystal element 4013 which is a display element is The liquid crystal layer 4008 includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. The crystal layer 4008 is sandwiched between insulating layers 4032 and 4033, which function as alignment films. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode The layer 4030 and the second electrode layer 4031 overlap with each other with a liquid crystal layer 4008 interposed therebetween.

[0433] The spacers 4035 are columnar spacers obtained by selectively etching the insulating layer. and the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0434] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, For example, a polarizing substrate and an optical member (optical substrate) such as a polarizing member may be provided. Circularly polarized light produced by a retardation substrate may also be used. etc. may also be used.

[0435] In addition, the display devices shown in FIGS. 38(A), 38(B), 39(A), and 39(B) The insulating layer 4111 and the insulating layer 4104 are The insulating layer 4111 and the insulating layer 4104 are used as insulating layers that are difficult for impurity elements to penetrate. By sandwiching the semiconductor layer of the transistor, it is possible to prevent impurities from entering from the outside. The insulating layer 4111 and the insulating layer 4104 are in contact with each other outside the element part 4002, so that impurities from the outside are prevented from entering the insulating layer 4111. This can improve the effectiveness of preventing objects from entering.

[0436] The insulating layer 4104 may be formed using, for example, a material and method similar to those of the insulating layer 104. The edge layer 4111 may be formed, for example, using the same material and method as the insulating layer 110 .

[0437] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. An EL element is a device that is disposed between a pair of electrodes. The EL element has a layer containing a light-emitting compound (also called an "EL layer") between a pair of electrodes. When a potential difference greater than the threshold voltage is generated, holes are injected into the EL layer from the anode side, and the cathode Electrons are injected from the electrode side. The injected electrons and holes recombine in the EL layer, forming a The luminescent material contained therein emits light.

[0438] EL elements are also classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0439] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer, and then the carriers (electrons and holes) recombine. By this, the light-emitting organic compound forms an excited state, and the excited state returns to the ground state. Due to this mechanism, such a light-emitting element is called a current-excited light-emitting element. It is called a child.

[0440] In addition to the light-emitting compound, the EL layer may contain a material having a high hole injection property and a material having a high hole transport property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The layer may contain a highly functional substance (a substance having high electron-transporting and hole-transporting properties).

[0441] The EL layer can be formed by a variety of methods, including vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0442] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0443] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. The transistor and the light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. Top emission structure, which emits light from the top surface, and bottom emission structure, which emits light from the surface of the substrate. (bottom emission) structure and double-sided emission (dual emission) structure There are light emitting elements with a light-emitting structure, and any light emitting element with an emission structure can be applied.

[0444] 38(B) and 39(B) show a light-emitting display device (" The light-emitting element 4513, which is a display element, is an example of a pixel portion. The light-emitting element 45 is electrically connected to the transistor 4010 provided in the light-emitting element 4002. The structure of the device 13 is a laminated structure of a first electrode layer 4030, a light emitting layer 4511, and a second electrode layer 4031. However, it is not limited to this structure. In addition, the structure of the light-emitting element 4513 can be changed as appropriate.

[0445] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is It is preferable to form the inclined surface with a curvature.

[0446] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers stacked. Either way is fine.

[0447] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be formed of silicon nitride. silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (laminating film) with high airtightness and low outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. I wish.

[0448] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or Ethylene vinyl acetate (EVA) can also be used. may contain a desiccant.

[0449] The sealing material 4005 is made of glass materials such as glass frit, or ordinary materials such as two-component mixed resin. Resin materials such as heat-curable resin, photo-curable resin, and thermosetting resin can be used. The sealing material 4005 may also contain a desiccant.

[0450] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0451] In addition, by using a microcavity structure for the light-emitting element, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves the visibility of the displayed image.

[0452] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0453] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, may be used. This can be done.

[0454] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or its alloy, or metal nitride thereof. .

[0455] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene, or Its derivatives are also included.

[0456] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0457] By using the transistor described in the above embodiment, a highly reliable display device can be provided. In addition, by using the transistor described in the above embodiment, high definition and This makes it possible to provide a display device with a large area and good display quality. It is possible to provide a display device in which the above-mentioned problem is reduced.

[0458] <Display module> A display module will be described as an example of a semiconductor device using the above-described transistor. The display module 6000 shown in FIG. Between the two, touch sensor 6004 connected to FPC6003 and FPC6005 a display panel 6006, a backlight unit 6007, a frame 6009, a printer The backlight unit 6007 has a backlight substrate 6010 and a battery 6011. The battery 6011, the touch sensor 6004, etc. may not be provided.

[0459] The semiconductor device of one embodiment of the present invention includes, for example, a touch sensor 6004, a display panel 6006, It can be used for an integrated circuit mounted on a printed circuit board 6010. For example, The display device described above can be used for the panel 6006.

[0460] The upper cover 6001 and the lower cover 6002 are connected to the touch sensor 6004 and the display panel 6006. The shape and dimensions can be changed as needed to fit sizes such as 006.

[0461] The touch sensor 6004 is a resistive or capacitive touch sensor connected to the display panel 6 The display panel 6006 can be used by being superimposed on the display panel 6006. For example, it is possible to provide a touch sensor electrode in each pixel of the display panel 6006. It is also possible to add a capacitive touch panel function. By providing an optical sensor in each pixel of the panel 6006 and adding the function of an optical touch sensor, Also, if there is no need to provide the touch sensor 6004, Sensor 6004 can be omitted.

[0462] The backlight unit 6007 includes a light source 6008. It may be configured to be provided at the end of the unit 6007 and to use a light diffusion plate. When a light-emitting display device or the like is used for 6006, the backlight unit 6007 is omitted. It is possible.

[0463] The frame 6009 not only protects the display panel 6006 but also protects the printed circuit board 6010 from the side. It also functions as an electromagnetic shield to block the electromagnetic waves generated. 009 may also function as a heat sink.

[0464] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply for the power supply circuit is a battery 6011. If a commercial power source is used as the power source, , the battery 6011 can be omitted.

[0465] In addition, components such as polarizing plates, retardation plates, and prism sheets have been added to the Display Module 6000. It may also be provided as follows.

[0466] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0467] (Fourth embodiment) The transistor and / or semiconductor device according to one embodiment of the present invention can be used in various electronic devices. 41 and 42 show transistors and / or Examples of electronic devices using semiconductor devices will be shown.

[0468] Examples of electronic devices using a semiconductor device according to one embodiment of the present invention include display devices such as televisions and monitors. , lighting equipment, desktop or notebook personal computers, word processors stored on recording media such as DVD (Digital Versatile Disc) Image playback devices that play still or moving images, portable CD players, radios, tapes Recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets , transceivers, mobile phones, car phones, portable game consoles, tablet terminals, pachinko machines large game consoles such as PCs, calculators, personal digital assistants, electronic organizers, e-book readers, electronic translators, High frequency devices such as voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. Wave heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air Air conditioning equipment such as conditioners, humidifiers, dehumidifiers, dishwashers, dish dryers, and clothes dryers electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, pocket refrigerators Examples include electric lights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Furthermore, guide lights, traffic lights, conveyor belts, elevators, escalators, and industrial robots , energy storage systems, industrial equipment such as energy storage devices for power leveling and smart grids Examples include:

[0469] In addition, moving objects propelled by electric motors using power from a power storage device are also included in the category of electronic devices. The above-mentioned mobile units include, for example, electric vehicles (EVs), vehicles with internal combustion engines and electric vehicles (EVs), and Hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), These tires and wheels are converted into tracks, and motorized vehicles including electrically assisted bicycles are also available. Bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters Examples include aircraft, rockets, satellites, space probes, planetary probes, and spacecraft. .

[0470] The electronic device shown in FIGS. 41A to 41G includes a housing 9000, a display portion 9001, a speaker 9002, and a touch panel 9003. 9003, operation keys 9005 (including power switch or operation switch), connection terminal 9006, Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light , liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow (including functions to measure volume, humidity, gradient, vibration, odor or infrared), microphone 9008, etc.

[0471] The electronic devices shown in FIGS. 41A to 41G have various functions. Functions for displaying information (still images, videos, text images, etc.) on the display, touch panel function, Functions that display calendars, dates, or times, etc., and various software (programs) Therefore, it has the functions of controlling processing, wireless communication, and various computer networks using wireless communication functions. Functions for connecting to networks and transmitting or receiving various data using wireless communication functions Function: Reads out programs or data recorded on a recording medium and displays them on the display. The electronic devices shown in FIGS. The functions that can be provided are not limited to these, and various other functions can be provided. Although not shown in FIGS. 41A to 41G, the electronic device may have a plurality of display units. The electronic device may be provided with a camera or the like to take still images. A function to record video and save the captured images to a recording medium (external or built-in to the camera) The image capturing device may have a function of capturing an image on a display unit, a function of displaying a captured image on a display unit, etc.

[0472] FIG. 41(A) is a perspective view showing a television device 9100. 00 is a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more. A display unit 9001 can be incorporated.

[0473] 41(B) is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 is For example, it has one or more functions selected from a telephone, a notebook, an information viewing device, etc. In practice, it can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple screens. The operation buttons 9050 (also referred to as operation icons or simply icons) are displayed on the display unit 9001. In addition, information 9051 shown in a dashed rectangle can be displayed on one side of the display unit 9001. It should be noted that an example of the information 9051 is an email or S Displays to notify you of incoming calls, such as NS (social networking services), and Subjects of e-mails and SNS, sender names of e-mails and SNS, date and time, time, battery The remaining battery capacity, antenna reception strength, etc. Or, the location where information 9051 is displayed Instead of the information 9051, operation buttons 9050 or the like may be displayed.

[0474] 41(C) is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 is The display unit 9001 has a function of displaying information on three or more surfaces. 9053 and 9054 are displayed on different sides. The user of the information terminal 9102 has the mobile information terminal 9102 stored in the breast pocket of his / her clothes. You can check the display (information 9053 in this case) by A position where the caller's telephone number or name can be observed from above the mobile information terminal 9102 The user can view the display without taking the mobile information terminal 9102 out of his pocket. You can check and decide whether to accept the call or not.

[0475] FIG. 41(D) is a perspective view showing a wristwatch-type mobile information terminal 9200. 200 is for mobile phone calls, e-mail, document viewing and creation, music playback, internet communication, It can run various applications such as computer games. The display surface of the unit 9001 is curved, and the display can be performed along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 has a connection terminal 9006. It is also possible to exchange data directly with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Alternatively, power may be supplied wirelessly without going through a power supply.

[0476] 41(E), (F), and (G) are perspective views showing a foldable mobile information terminal 9201. 41(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG. F) The mobile information terminal 9201 changes from one of the unfolded state and the folded state to the other. 41(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded, and is unfolded. In this state, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 1 is attached to three housings 9000 connected by hinges 9055. The hinge 9055 allows the two housings 9000 to bend. , and the mobile information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm or more and 150 mm or less. It is possible.

[0477] Next, an example of an electronic device different from the electronic devices shown in FIGS. 41(A) to 41(G) is shown in FIG. 42(A) and (B) are perspective views of a display device having a plurality of display panels. FIG. 42(A) is a perspective view of a state in which a plurality of display panels are rolled up. FIG. 42(B) is a perspective view of a state in which a plurality of display panels are unfolded.

[0478] The display device 9500 shown in FIGS. 42(A) and 42(B) includes a plurality of display panels 9501 and a shaft portion 95 11 and a bearing portion 9512. The plurality of display panels 9501 have a display area 9 502 and a light-transmitting region 9503.

[0479] The display panels 9501 are flexible. 9501 are provided so that they partially overlap each other. For example, two adjacent tables The light-transmitting regions 9503 of the display panels 9501 can be overlapped. By using the display panel 9501, a large screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. The device may be a device.

[0480] In addition, in FIGS. 42(A) and 42(B), the adjacent display panels 9501 are Although the display areas 9502 do not overlap, this is not limitative. For example, By overlapping the display areas 9502 of the display panels 9501 without any gaps, a continuous display can be achieved. It may also be area 9502.

[0481] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is not limited to an electronic device that does not have a display portion. It can also be applied to [Explanation of symbols]

[0482] 100 transistors 101 Substrate 102 electrode 103 Insulating layer 104 Insulating layer 105 Insulating layer 106 Oxide semiconductor layer 108 Insulating layer 109 Insulating Layer 110 Insulating layer 113 Insulating layer 121 Electrode 131 parts 132 parts 181 Conductive layer 182 Oxide semiconductor layer 183 Oxide semiconductor layer 184 Conductive Layer 185 Conductive Layer 186 Conductive Layer 200 transistors 461 Transistor 462 Liquid crystal element 463 Capacitor 464 transistors 465 nodes 466 nodes 467 nodes 468 transistors 469 Light-emitting element 500 display device 511 Drive circuit

Claims

1. a first electrode; a first insulating layer having a region disposed on the first electrode; a second insulating layer having a region disposed on the first insulating layer; a semiconductor layer having a region provided on the second insulating layer; a third insulating layer having a region provided on the semiconductor layer; a second electrode having a region disposed on the third insulating layer; a fourth insulating layer having a region disposed on the second electrode; the first insulating layer has a region in contact with the fourth insulating layer in a channel width direction of the semiconductor layer, the third insulating layer has a region covering an end portion of the semiconductor layer in a channel width direction of the semiconductor layer and a region in contact with the second insulating layer, The semiconductor device, wherein the first electrode and the second electrode are supplied with the same potential.

2. a first electrode; a first insulating layer having a region disposed on the first electrode; a second insulating layer having a region disposed on the first insulating layer; an oxide semiconductor layer having a region provided on the second insulating layer; a third insulating layer having a region provided on the oxide semiconductor layer; a second electrode having a region disposed on the third insulating layer; a fourth insulating layer having a region disposed on the second electrode; the first insulating layer has a region in contact with the fourth insulating layer in a channel width direction of the oxide semiconductor layer, the third insulating layer has a region covering an end portion of the oxide semiconductor layer in a channel width direction of the oxide semiconductor layer and a region in contact with the second insulating layer; The semiconductor device, wherein the first electrode and the second electrode are supplied with the same potential.

3. In claim 1 or claim 2, The semiconductor device, wherein the first insulating layer has a region in contact with the fourth insulating layer in a region where the second insulating layer and the third insulating layer have been removed.

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